ADRDY

Bit 0: ADC ready.

Allowed values:
0: NotReady: ADC not yet ready to start conversion
1: Ready: ADC ready to start conversion

EOSMP

Bit 1: End of sampling flag.

Allowed values:
0: NotAtEnd: Not at the end of the samplings phase
1: AtEnd: End of sampling phase reached

EOC

Bit 2: End of conversion flag.

Allowed values:
0: NotComplete: Channel conversion is not complete
1: Complete: Channel conversion complete

EOS

Bit 3: End of sequence flag.

Allowed values:
0: NotComplete: Conversion sequence is not complete
1: Complete: Conversion sequence complete

OVR

Bit 4: ADC overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

AWD

Bit 7: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOCAL

Bit 11: End Of Calibration flag.

Allowed values:
0: NotComplete: Calibration is not complete
1: Complete: Calibration complete

ADRDYIE

Bit 0: ADC ready interrupt enable.

Allowed values:
0: Disabled: ADRDY interrupt disabled
1: Enabled: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

EOSMPIE

Bit 1: End of sampling flag interrupt enable.

Allowed values:
0: Disabled: EOSMP interrupt disabled
1: Enabled: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

EOCIE

Bit 2: End of conversion interrupt enable.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

EOSIE

Bit 3: End of conversion sequence interrupt enable.

Allowed values:
0: Disabled: EOS interrupt disabled
1: Enabled: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

OVRIE

Bit 4: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

AWDIE

Bit 7: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

EOCALIE

Bit 11: End of calibration interrupt enable.

Allowed values:
0: Disabled: End of calibration interrupt disabled
1: Enabled: End of calibration interrupt enabled

ADEN

Bit 0: ADC enable command.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADC disable command.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADC start conversion command.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADC stop conversion command.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADC Voltage Regulator Enable.

Allowed values:
0: Disabled: ADC voltage regulator disabled
1: Enabled: ADC voltage regulator enabled

ADCAL

Bit 31: ADC calibration.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

DMAEN

Bit 0: Direct memory access enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: Direct memery access configuration.

Allowed values:
0: OneShot: DMA one shot mode selected
1: Circular: DMA circular mode selected

SCANDIR

Bit 2: Scan sequence direction.

Allowed values:
0: Upward: Upward scan (from CHSEL0 to CHSEL18)
1: Backward: Backward scan (from CHSEL18 to CHSEL0)

RES

Bits 3-4: Data resolution.

Allowed values:
0: TwelveBit: 12 bits
1: TenBit: 10 bits
2: EightBit: 8 bits
3: SixBit: 6 bits

ALIGN

Bit 5: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-8: External trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM21_CH2: Timer 21 CH2 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CH4: Timer 2 CH4 event
4: TIM22_TRGO: Timer 22 TRGO, Timer 21 TRGO event
5: TIM2_CH3: Timer 2 CH3 event
6: TIM3_TRGO: Timer 3 TRGO event
7: EXTI_LINE11: EXTI line 11 event

EXTEN

Bits 10-11: External trigger enable and polarity selection.

Allowed values:
0: Disabled: Hardware trigger detection disabled
1: RisingEdge: Hardware trigger detection on the rising edge
2: FallingEdge: Hardware trigger detection on the falling edge
3: BothEdges: Hardware trigger detection on both the rising and falling edges

OVRMOD

Bit 12: Overrun management mode.

Allowed values:
0: Preserve: ADC_DR register is preserved with the old data when an overrun is detected
1: Overwrite: ADC_DR register is overwritten with the last conversion result when an overrun is detected

CONT

Bit 13: Single / continuous conversion mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

WAIT

Bit 14: Auto-delayed conversion mode.

Allowed values:
0: Disabled: Wait conversion mode off
1: Enabled: Wait conversion mode on

AUTOFF

Bit 15: Auto-off mode.

Allowed values:
0: Disabled: Auto-off mode disabled
1: Enabled: Auto-off mode enabled

DISCEN

Bit 16: Discontinuous mode.

Allowed values:
0: Disabled: Discontinuous mode disabled
1: Enabled: Discontinuous mode enabled

AWDSGL

Bit 22: Enable the watchdog on a single channel or on all channels.

Allowed values:
0: AllChannels: Analog watchdog enabled on all channels
1: SingleChannel: Analog watchdog enabled on a single channel

AWDEN

Bit 23: Analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled
1: Enabled: Analog watchdog enabled

AWDCH

Bits 26-30: Analog watchdog channel selection.

Allowed values: 0x0-0x12

OVSE

Bit 0: Oversampler Enable.

Allowed values:
0: Disabled: Oversampler disabled
1: Enabled: Oversampler enabled

OVSR

Bits 2-4: Oversampling ratio.

Allowed values:
0: Mul2: 2x
1: Mul4: 4x
2: Mul8: 8x
3: Mul16: 16x
4: Mul32: 32x
5: Mul64: 64x
6: Mul128: 128x
7: Mul256: 256x

OVSS

Bits 5-8: Oversampling shift.

Allowed values: 0x0-0x8

TOVS

Bit 9: Triggered Oversampling.

Allowed values:
0: TriggerAll: All oversampled conversions for a channel are done consecutively after a trigger
1: TriggerEach: Each oversampled conversion for a channel needs a trigger

CKMODE

Bits 30-31: ADC clock mode.

Allowed values:
0: ADCLK: ADCCLK (Asynchronous clock mode)
1: PCLK_Div2: PCLK/2 (Synchronous clock mode)
2: PCLK_Div4: PCLK/4 (Synchronous clock mode)
3: PCLK: PCLK (Synchronous clock mode)

SMP

Bits 0-2: Sampling time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles3_5: 3.5 ADC clock cycles
2: Cycles7_5: 7.5 ADC clock cycles
3: Cycles12_5: 12.5 ADC clock cycles
4: Cycles19_5: 19.5 ADC clock cycles
5: Cycles39_5: 39.5 ADC clock cycles
6: Cycles79_5: 79.5 ADC clock cycles
7: Cycles160_5: 160.5 ADC clock cycles

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0x0-0x7ff

HT

Bits 16-27: Analog watchdog higher threshold.

Allowed values: 0x0-0x7ff

CHSEL0

Bit 0: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL1

Bit 1: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL2

Bit 2: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL3

Bit 3: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL4

Bit 4: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL5

Bit 5: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL6

Bit 6: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL7

Bit 7: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL8

Bit 8: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL9

Bit 9: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL10

Bit 10: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL11

Bit 11: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL12

Bit 12: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL13

Bit 13: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL14

Bit 14: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL15

Bit 15: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL16

Bit 16: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL17

Bit 17: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

CHSEL18

Bit 18: Channel-x selection.

Allowed values:
0: NotSelected: Input Channel is not selected for conversion
1: Selected: Input Channel is selected for conversion

DATA

Bits 0-15: Converted data.

Allowed values: 0x0-0xffff

CALFACT

Bits 0-6: Calibration factor.

Allowed values: 0x0-0x7f

PRESC

Bits 18-21: ADC prescaler.

Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256

VREFEN

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: VREFINT disabled
1: Enabled: VREFINT enabled

TSEN

Bit 23: Temperature sensor enable.

Allowed values:
0: Disabled: Temperature sensor disabled
1: Enabled: Temperature sensor enabled

LFMEN

Bit 25: Low Frequency Mode enable.

Allowed values:
0: Disabled: Low Frequency Mode disabled
1: Enabled: Low Frequency Mode enabled

EN

Bit 0: AES enable.

Allowed values:
0: Disabled: Disable AES
1: Enabled: Enable AES

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

Allowed values:
0: None: Word
1: HalfWord: Half-word (16-bit)
2: Byte: Byte (8-bit)
3: Bit: Bit

MODE

Bits 3-4: AES operating mode.

Allowed values:
0: Mode1: Mode 1: encryption
1: Mode2: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
2: Mode3: Mode 3: decryption
3: Mode4: Mode 4: key derivation then single decryption

CHMOD

Bits 5-6: AES chaining mode.

Allowed values:
0: ECB: Electronic codebook (ECB)
1: CBC: Cipher-Block Chaining (CBC)
2: CTR: Counter Mode (CTR)

CCFC

Bit 7: Computation Complete Flag Clear.

Allowed values:
1: Clear: Clear computation complete flag

ERRC

Bit 8: Error clear.

Allowed values:
1: Clear: Clear RDERR and WRERR flags

CCFIE

Bit 9: CCF flag interrupt enable.

Allowed values:
0: Disabled: Disable (mask) CCF interrupt
1: Enabled: Enable CCF interrupt

ERRIE

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Disable (mask) error interrupt
1: Enabled: Enable error interrupt

DMAINEN

Bit 11: Enable DMA management of data input phase.

Allowed values:
0: Disabled: Disable DMA Input
1: Enabled: Enable DMA Input

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

Allowed values:
0: Disabled: Disable DMA Output
1: Enabled: Enabled DMA Output

CCF

Bit 0: Computation complete flag.

Allowed values:
0: Complete: Computation complete
1: NotComplete: Computation not complete

RDERR

Bit 1: Read error flag.

Allowed values:
0: NoError: Read error not detected
1: Error: Read error detected

WRERR

Bit 2: Write error flag.

Allowed values:
0: NoError: Write error not detected
1: Error: Write error detected

DIN

Bits 0-31: Data Input Register..

Allowed values: 0x0-0xffffffff

DOUT

Bits 0-31: Data output register.

Allowed values: 0x0-0xffffffff

KEY0

Bits 0-31: Data Output Register (LSB key [31:0]).

Allowed values: 0x0-0xffffffff

KEY1

Bits 0-31: AES key register (key [63:32]).

Allowed values: 0x0-0xffffffff

KEY2

Bits 0-31: AES key register (key [95:64]).

Allowed values: 0x0-0xffffffff

KEY3

Bits 0-31: AES key register (MSB key [127:96]).

Allowed values: 0x0-0xffffffff

IV0

Bits 0-31: initialization vector register (LSB IVR [31:0]).

Allowed values: 0x0-0xffffffff

IV1

Bits 0-31: Initialization Vector Register (IVR [63:32]).

Allowed values: 0x0-0xffffffff

IV2

Bits 0-31: Initialization Vector Register (IVR [95:64]).

Allowed values: 0x0-0xffffffff

IV3

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

Allowed values: 0x0-0xffffffff

DR

Bits 0-31: Data register bits.

Allowed values: 0x0-0xffffffff

DR16

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

DR8

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

IDR

Bits 0-7: General-purpose 8-bit data register bits.

Allowed values: 0x0-0xff

RESET

Bit 0: RESET bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

POLYSIZE

Bits 3-4: Polynomial size.

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

REV_IN

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

INIT

Bits 0-31: Programmable initial CRC value.

Allowed values: 0x0-0xffffffff

POL

Bits 0-31: Programmable polynomial.

Allowed values: 0x0-0xffffffff

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-13: HSI48 oscillator smooth trimming.

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

EN1

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF1

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN1

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL1

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM3_TRGO: Timer 3 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM15_TRGO: Timer 15 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

DMAEN1

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

SWTRIG1

Bit 0: DAC channel1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC1DOR

Bits 0-11: DAC channel1 data output.

DACC2DOR

Bits 0-11: DAC channel2 data output.

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DEV_ID

Bits 0-11: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

DBG_SLEEP

Bit 0: Debug Sleep Mode.

Allowed values:
0: Disabled: Debug Sleep Mode Disabled
1: Enabled: Debug Sleep Mode Enabled

DBG_STOP

Bit 1: Debug Stop Mode.

Allowed values:
0: Disabled: Debug Stop Mode Disabled
1: Enabled: Debug Stop Mode Enabled

DBG_STANDBY

Bit 2: Debug Standby Mode.

Allowed values:
0: Disabled: Debug Standby Mode Disabled
1: Enabled: Debug Standby Mode Enabled

DBG_TIMER2_STOP

Bit 0: Debug Timer 2 stopped when Core is halted.

Allowed values:
0: Continue: The counter clock of TIMx is fed even if the core is halted
1: Stop: The counter clock of TIMx is stopped when the core is halted

DBG_TIMER6_STOP

Bit 4: Debug Timer 6 stopped when Core is halted.

Allowed values:
0: Continue: The counter clock of TIMx is fed even if the core is halted
1: Stop: The counter clock of TIMx is stopped when the core is halted

DBG_RTC_STOP

Bit 10: Debug RTC stopped when Core is halted.

Allowed values:
0: Continue: The clock of the RTC counter is fed even if the core is halted
1: Stop: The clock of the RTC counter is stopped when the core is halted

DBG_WWDG_STOP

Bit 11: Debug Window Wachdog stopped when Core is halted.

Allowed values:
0: Continue: The window watchdog counter clock continues even if the core is halted
1: Stop: The window watchdog counter clock is stopped when the core is halted

DBG_IWDG_STOP

Bit 12: Debug Independent Wachdog stopped when Core is halted.

Allowed values:
0: Continue: The independent watchdog counter clock continues even if the core is halted
1: Stop: The independent watchdog counter clock is stopped when the core is halted

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout mode stopped when core is halted.

Allowed values:
0: NormalMode: Same behavior as in normal mode
1: SMBusTimeoutFrozen: I2C3 SMBUS timeout is frozen

DBG_I2C2_STOP

Bit 22: I2C2 SMBUS timeout mode stopped when core is halted.

Allowed values:
0: NormalMode: Same behavior as in normal mode
1: SMBusTimeoutFrozen: I2C3 SMBUS timeout is frozen

DBG_LPTIMER_STOP

Bit 31: LPTIM1 counter stopped when core is halted.

Allowed values:
0: Continue: LPTIM1 counter clock is fed even if the core is halted
1: Stop: LPTIM1 counter clock is stopped when the core is halted

DBG_TIMER21_STOP

Bit 2: Debug Timer 21 stopped when Core is halted.

Allowed values:
0: Continue: The counter clock of TIMx is fed even if the core is halted
1: Stop: The counter clock of TIMx is stopped when the core is halted

DBG_TIMER22_STO

Bit 6: Debug Timer 22 stopped when Core is halted.

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled