Overall: 2195/3959 fields covered

ADC

0x40012400: Analog-to-digital converter

15/125 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 CR1
0x8 CR2
0xc SMPR1
0x10 SMPR2
0x14 SMPR3
0x18 JOFR1
0x1c JOFR2
0x20 JOFR3
0x24 JOFR4
0x28 HTR
0x2c LTR
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 SQR5
0x44 JSQR
0x48 JDR1
0x4c JDR2
0x50 JDR3
0x54 JDR4
0x58 DR
0x5c SMPR0
0x300 CSR
0x304 CCR
Toggle registers

SR

status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

3/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCNR
r 		RCNR
r 		ADONS
r 		OVR
rw 		STRT
rw 		JSTRT
rw 		JEOC
rw 		EOC
rw 		AWD
rw
Toggle fields

AWD

Bit 0: Analog watchdog flag.

EOC

Bit 1: Regular channel end of conversion.

JEOC

Bit 2: Injected channel end of conversion.

JSTRT

Bit 3: Injected channel start flag.

STRT

Bit 4: Regular channel start flag.

OVR

Bit 5: Overrun.

ADONS

Bit 6: ADC ON status.

RCNR

Bit 8: Regular channel not ready.

JCNR

Bit 9: Injected channel not ready.

CR1

control register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVRIE
rw 		RES
rw 		AWDEN
rw 		JAWDEN
rw 		PDI
rw 		PDD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw 		JDISCEN
rw 		DISCEN
rw 		JAUTO
rw 		AWDSGL
rw 		SCAN
rw 		JEOCIE
rw 		AWDIE
rw 		EOCIE
rw 		AWDCH
rw
Toggle fields

AWDCH

Bits 0-4: Analog watchdog channel select bits.

EOCIE

Bit 5: Interrupt enable for EOC.

AWDIE

Bit 6: Analog watchdog interrupt enable.

JEOCIE

Bit 7: Interrupt enable for injected channels.

SCAN

Bit 8: Scan mode.

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

JAUTO

Bit 10: Automatic injected group conversion.

DISCEN

Bit 11: Discontinuous mode on regular channels.

JDISCEN

Bit 12: Discontinuous mode on injected channels.

DISCNUM

Bits 13-15: Discontinuous mode channel count.

PDD

Bit 16: Power down during the delay phase.

PDI

Bit 17: Power down during the idle phase.

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

AWDEN

Bit 23: Analog watchdog enable on regular channels.

RES

Bits 24-25: Resolution.

OVRIE

Bit 26: Overrun interrupt enable.

CR2

control register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWSTART
rw 		EXTEN
rw 		EXTSEL
rw 		JSWSTART
rw 		JEXTEN
rw 		JEXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALIGN
rw 		EOCS
rw 		DDS
rw 		DMA
rw 		DELS
rw 		ADC_CFG
rw 		CONT
rw 		ADON
rw
Toggle fields

ADON

Bit 0: A/D Converter ON / OFF.

CONT

Bit 1: Continuous conversion.

ADC_CFG

Bit 2: ADC configuration.

DELS

Bits 4-6: Delay selection.

DMA

Bit 8: Direct memory access mode.

DDS

Bit 9: DMA disable selection.

EOCS

Bit 10: End of conversion selection.

ALIGN

Bit 11: Data alignment.

JEXTSEL

Bits 16-19: External event select for injected group.

JEXTEN

Bits 20-21: External trigger enable for injected channels.

JSWSTART

Bit 22: Start conversion of injected channels.

EXTSEL

Bits 24-27: External event select for regular group.

EXTEN

Bits 28-29: External trigger enable for regular channels.

SWSTART

Bit 30: Start conversion of regular channels.

SMPR1

sample time register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP29
rw 		SMP28
rw 		SMP27
rw 		SMP26
rw 		SMP25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP25
rw 		SMP24
rw 		SMP23
rw 		SMP22
rw 		SMP21
rw 		SMP20
rw
Toggle fields

SMP20

Bits 0-2: Channel 20 sampling time selection.

SMP21

Bits 3-5: Channel 21 sampling time selection.

SMP22

Bits 6-8: Channel 22 sampling time selection.

SMP23

Bits 9-11: Channel 23 sampling time selection.

SMP24

Bits 12-14: Channel 24 sampling time selection.

SMP25

Bits 15-17: Channel 25 sampling time selection.

SMP26

Bits 18-20: Channel 26 sampling time selection.

SMP27

Bits 21-23: Channel 27 sampling time selection.

SMP28

Bits 24-26: Channel 28 sampling time selection.

SMP29

Bits 27-29: Channel 29 sampling time selection.

SMPR2

sample time register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP19
rw 		SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: Channel 10 sampling time selection.

SMP11

Bits 3-5: Channel 11 sampling time selection.

SMP12

Bits 6-8: Channel 12 sampling time selection.

SMP13

Bits 9-11: Channel 13 sampling time selection.

SMP14

Bits 12-14: Channel 14 sampling time selection.

SMP15

Bits 15-17: Channel 15 sampling time selection.

SMP16

Bits 18-20: Channel 16 sampling time selection.

SMP17

Bits 21-23: Channel 17 sampling time selection.

SMP18

Bits 24-26: Channel 18 sampling time selection.

SMP19

Bits 27-29: Channel 19 sampling time selection.

SMPR3

sample time register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle fields

SMP0

Bits 0-2: Channel 0 sampling time selection.

SMP1

Bits 3-5: Channel 1 sampling time selection.

SMP2

Bits 6-8: Channel 2 sampling time selection.

SMP3

Bits 9-11: Channel 3 sampling time selection.

SMP4

Bits 12-14: Channel 4 sampling time selection.

SMP5

Bits 15-17: Channel 5 sampling time selection.

SMP6

Bits 18-20: Channel 6 sampling time selection.

SMP7

Bits 21-23: Channel 7 sampling time selection.

SMP8

Bits 24-26: Channel 8 sampling time selection.

SMP9

Bits 27-29: Channel 9 sampling time selection.

JOFR1

injected channel data offset register x

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET1
rw
Toggle fields

JOFFSET1

Bits 0-11: Data offset for injected channel x.

JOFR2

injected channel data offset register x

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET2
rw
Toggle fields

JOFFSET2

Bits 0-11: Data offset for injected channel x.

JOFR3

injected channel data offset register x

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET3
rw
Toggle fields

JOFFSET3

Bits 0-11: Data offset for injected channel x.

JOFR4

injected channel data offset register x

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET4
rw
Toggle fields

JOFFSET4

Bits 0-11: Data offset for injected channel x.

HTR

watchdog higher threshold register

Offset: 0x28, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle fields

HT

Bits 0-11: Analog watchdog higher threshold.

LTR

watchdog lower threshold register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle fields

LT

Bits 0-11: Analog watchdog lower threshold.

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw 		SQ28
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ28
rw 		SQ27
rw 		SQ26
rw 		SQ25
rw
Toggle fields

SQ25

Bits 0-4: 25th conversion in regular sequence.

SQ26

Bits 5-9: 26th conversion in regular sequence.

SQ27

Bits 10-14: 27th conversion in regular sequence.

SQ28

Bits 15-19: 28th conversion in regular sequence.

L

Bits 20-23: Regular channel sequence length.

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ24
rw 		SQ23
rw 		SQ22
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ22
rw 		SQ21
rw 		SQ20
rw 		SQ19
rw
Toggle fields

SQ19

Bits 0-4: 19th conversion in regular sequence.

SQ20

Bits 5-9: 20th conversion in regular sequence.

SQ21

Bits 10-14: 21st conversion in regular sequence.

SQ22

Bits 15-19: 22nd conversion in regular sequence.

SQ23

Bits 20-24: 23rd conversion in regular sequence.

SQ24

Bits 25-29: 24th conversion in regular sequence.

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ18
rw 		SQ17
rw 		SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw 		SQ14
rw 		SQ13
rw
Toggle fields

SQ13

Bits 0-4: 13th conversion in regular sequence.

SQ14

Bits 5-9: 14th conversion in regular sequence.

SQ15

Bits 10-14: 15th conversion in regular sequence.

SQ16

Bits 15-19: 16th conversion in regular sequence.

SQ17

Bits 20-24: 17th conversion in regular sequence.

SQ18

Bits 25-29: 18th conversion in regular sequence.

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw 		SQ11
rw 		SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw 		SQ9
rw 		SQ8
rw 		SQ7
rw
Toggle fields

SQ7

Bits 0-4: 7th conversion in regular sequence.

SQ8

Bits 5-9: 8th conversion in regular sequence.

SQ9

Bits 10-14: 9th conversion in regular sequence.

SQ10

Bits 15-19: 10th conversion in regular sequence.

SQ11

Bits 20-24: 11th conversion in regular sequence.

SQ12

Bits 25-29: 12th conversion in regular sequence.

SQR5

regular sequence register 5

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw 		SQ5
rw 		SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw 		SQ3
rw 		SQ2
rw 		SQ1
rw
Toggle fields

SQ1

Bits 0-4: 1st conversion in regular sequence.

SQ2

Bits 5-9: 2nd conversion in regular sequence.

SQ3

Bits 10-14: 3rd conversion in regular sequence.

SQ4

Bits 15-19: 4th conversion in regular sequence.

SQ5

Bits 20-24: 5th conversion in regular sequence.

SQ6

Bits 25-29: 6th conversion in regular sequence.

JSQR

injected sequence register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw 		JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw 		JSQ3
rw 		JSQ2
rw 		JSQ1
rw
Toggle fields

JSQ1

Bits 0-4: 1st conversion in injected sequence.

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

JSQ4

Bits 15-19: 4th conversion in injected sequence.

JL

Bits 20-21: Injected sequence length.

JDR1

injected data register x

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR2

injected data register x

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR3

injected data register x

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

JDR4

injected data register x

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RegularDATA
r
Toggle fields

RegularDATA

Bits 0-15: Regular data.

SMPR0

sample time register 0

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP31
rw 		SMP30
rw
Toggle fields

SMP30

Bits 0-2: Channel 30 sampling time selection.

SMP31

Bits 3-5: Channel 31 sampling time selection.

CSR

ADC common status register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADONS1
r 		OVR1
r 		STRT1
r 		JSTRT1
r 		JEOC1
r 		EOC1
r 		AWD1
r
Toggle fields

AWD1

Bit 0: Analog watchdog flag of the ADC.

EOC1

Bit 1: End of conversion of the ADC.

JEOC1

Bit 2: Injected channel end of conversion of the ADC.

JSTRT1

Bit 3: Injected channel Start flag of the ADC.

STRT1

Bit 4: Regular channel Start flag of the ADC.

OVR1

Bit 5: Overrun flag of the ADC.

ADONS1

Bit 6: ADON Status of ADC1.

CCR

ADC common control register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw 		ADCPRE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

ADCPRE

Bits 16-17: ADC prescaler.

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

AES

0x50060000: Advanced encrytion standard hardware accelerator

4/23 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DINR
0xc DOUTR
0x10 KEYR0
0x14 KEYR1
0x18 KEYR2
0x1c KEYR3
0x20 IVR0
0x24 IVR1
0x28 IVR2
0x2c IVR3
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAOUTEN
rw 		DMAINEN
rw 		ERRIE
rw 		CCFIE
rw 		ERRC
rw 		CCFC
rw 		CHMOD
rw 		MODE
rw 		DATATYPE
rw 		EN
rw
Toggle fields

EN

Bit 0: AES enable.

DATATYPE

Bits 1-2: Data type selection.

MODE

Bits 3-4: AES operating mode.

CHMOD

Bits 5-6: AES chaining mode.

CCFC

Bit 7: Computation Complete Flag Clear.

ERRC

Bit 8: Error clear.

CCFIE

Bit 9: CCF flag interrupt enable.

ERRIE

Bit 10: Error interrupt enable.

DMAINEN

Bit 11: Enable DMA management of data input phase.

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

SR

Status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRERR
r 		RDERR
r 		CCF
r
Toggle fields

CCF

Bit 0: Computation complete flag.

RDERR

Bit 1: Read error flag.

WRERR

Bit 2: Write error flag.

DINR

Data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DINR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DINR
rw
Toggle fields

DINR

Bits 0-31: Data input.

DOUTR

Data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOUTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUTR
r
Toggle fields

DOUTR

Bits 0-31: Data output.

KEYR0

AES Key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEYR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYR0
rw
Toggle fields

KEYR0

Bits 0-31: AES key.

KEYR1

AES Key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEYR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYR1
rw
Toggle fields

KEYR1

Bits 0-31: AES key.

KEYR2

AES Key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEYR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYR2
rw
Toggle fields

KEYR2

Bits 0-31: AES key.

KEYR3

AES Key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEYR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYR3
rw
Toggle fields

KEYR3

Bits 0-31: AES key.

IVR0

Initialization Vector Register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVR0
rw
Toggle fields

IVR0

Bits 0-31: Initialization Vector Register.

IVR1

Initialization Vector Register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVR1
rw
Toggle fields

IVR1

Bits 0-31: Initialization Vector Register.

IVR2

Initialization Vector Register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVR2
rw
Toggle fields

IVR2

Bits 0-31: Initialization Vector Register.

IVR3

Initialization Vector Register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVR3
rw
Toggle fields

IVR3

Bits 0-31: Initialization Vector Register.

COMP

0x40007c00: Comparators

3/19 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
Toggle registers

CSR

comparator control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

3/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSUSP
rw 		CAIF
r 		CAIE
rw 		RCH13
rw 		FCH8
rw 		FCH3
rw 		OUTSEL
rw 		INSEL
rw 		WNDWE
rw 		VREFOUTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP2OUT
r 		SPEED
rw 		CMP1OUT
r 		SW1
rw 		CMP1EN
rw 		PD400K
rw 		PD10K
rw 		PU400K
rw 		PU10K
rw
Toggle fields

PU10K

Bit 0: 10 kO pull-up resistor.

PU400K

Bit 1: 400 kO pull-up resistor.

PD10K

Bit 2: 10 kO pull-down resistor.

PD400K

Bit 3: 400 kO pull-down resistor.

CMP1EN

Bit 4: Comparator 1 enable.

SW1

Bit 5: SW1 analog switch enable.

CMP1OUT

Bit 7: Comparator 1 output.

SPEED

Bit 12: Comparator 2 speed mode.

CMP2OUT

Bit 13: Comparator 2 output.

VREFOUTEN

Bit 16: VREFINT output enable.

WNDWE

Bit 17: Window mode enable.

INSEL

Bits 18-20: Inverted input selection.

OUTSEL

Bits 21-23: Comparator 2 output selection.

FCH3

Bit 26: Select GPIO port PA3 as fast ADC input channel CH3..

FCH8

Bit 27: Select GPIO port PB0 as fast ADC input channel CH8..

RCH13

Bit 28: Select GPIO port PC3 as re-routed ADC input channel CH13..

CAIE

Bit 29: Channel Acquisition Interrupt Enable / Clear.

CAIF

Bit 30: Channel acquisition interrupt flag.

TSUSP

Bit 31: Suspend Timer Mode.

CRC

0x40023000: CRC calculation unit

3/3 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data Register.

Allowed values: 0x0-0xffffffff

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-7: Independent data register.

Allowed values: 0x0-0xff

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
w
Toggle fields

RESET

Bit 0: RESET.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

DAC

0x40007400: Digital-to-analog converter

34/34 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRIGR
0x8 DHR12R1
0xc DHR12L1
0x10 DHR8R1
0x14 DHR12R2
0x18 DHR12L2
0x1c DHR8R2
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR1
0x30 DOR2
0x34 SR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDRIE2
rw 		DMAEN2
rw 		MAMP2
rw 		WAVE2
rw 		TSEL2
rw 		TEN2
rw 		BOFF2
rw 		EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL1
rw 		TEN1
rw 		BOFF1
rw 		EN1
rw
Toggle fields

EN1

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF1

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN1

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL1

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM3_TRGO: Timer 3 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM15_TRGO: Timer 15 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values: 0x0-0xf

DMAEN1

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

EN2

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF2

Bit 17: DAC channel2 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN2

Bit 18: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL2

Bits 19-21: DAC channel2 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values: 0x0-0xf

DMAEN2

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

SWTRIGR

software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w 		SWTRIG1
w
Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

SWTRIG2

Bit 1: DAC channel2 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

DHR12R1

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12L1

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8R1

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DHR12R2

channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12L2

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8R2

channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw 		DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR1

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output.

SR

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDR1
rw
Toggle fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DBGMCU

0xe0042000: debug support

2/21 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IDCODE
0x4 CR
0x8 APB1_FZ
0xc APB2_FZ
Toggle registers

IDCODE

DBGMCU_IDCODE

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle fields

DEV_ID

Bits 0-11: Device identifier.

REV_ID

Bits 16-31: Revision identifie.

CR

Debug MCU configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw 		TRACE_IOEN
rw 		DBG_STANDBY
rw 		DBG_STOP
rw 		DBG_SLEEP
rw
Toggle fields

DBG_SLEEP

Bit 0: Debug Sleep mode.

DBG_STOP

Bit 1: Debug Stop mode.

DBG_STANDBY

Bit 2: Debug Standby mode.

TRACE_IOEN

Bit 5: Trace pin assignment control.

TRACE_MODE

Bits 6-7: Trace pin assignment control.

APB1_FZ

Debug MCU APB1 freeze register1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_I2C2_SMBUS_TIMEOUT
rw 		DBG_I2C1_SMBUS_TIMEOUT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw 		DBG_WWDG_STOP
rw 		DBG_RTC_STOP
rw 		DBG_TIM7_STOP
rw 		DBG_TIM6_STOP
rw 		DBG_TIM5_STOP
rw 		DBG_TIM4_STOP
rw 		DBG_TIM3_STOP
rw 		DBG_TIM2_STOP
rw
Toggle fields

DBG_TIM2_STOP

Bit 0: TIM2 counter stopped when core is halted.

DBG_TIM3_STOP

Bit 1: TIM3 counter stopped when core is halted.

DBG_TIM4_STOP

Bit 2: TIM4 counter stopped when core is halted.

DBG_TIM5_STOP

Bit 3: TIM5 counter stopped when core is halted.

DBG_TIM6_STOP

Bit 4: TIM6 counter stopped when core is halted.

DBG_TIM7_STOP

Bit 5: TIM7 counter stopped when core is halted.

DBG_RTC_STOP

Bit 10: Debug RTC stopped when core is halted.

DBG_WWDG_STOP

Bit 11: Debug window watchdog stopped when core is halted.

DBG_IWDG_STOP

Bit 12: Debug independent watchdog stopped when core is halted.

DBG_I2C1_SMBUS_TIMEOUT

Bit 21: SMBUS timeout mode stopped when core is halted.

DBG_I2C2_SMBUS_TIMEOUT

Bit 22: SMBUS timeout mode stopped when core is halted.

APB2_FZ

Debug MCU APB1 freeze register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM11_STOP
rw 		DBG_TIM10_STOP
rw 		DBG_TIM9_STOP
rw
Toggle fields

DBG_TIM9_STOP

Bit 2: TIM counter stopped when core is halted.

DBG_TIM10_STOP

Bit 3: TIM counter stopped when core is halted.

DBG_TIM11_STOP

Bit 4: TIM counter stopped when core is halted.

DMA1

0x40026000: Direct memory access controller

28/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CCR1
0xc CNDTR1
0x10 CPAR1
0x14 CMAR1
0x1c CCR2
0x20 CNDTR2
0x24 CPAR2
0x28 CMAR2
0x30 CCR3
0x34 CNDTR3
0x38 CPAR3
0x3c CMAR3
0x44 CCR4
0x48 CNDTR4
0x4c CPAR4
0x50 CMAR4
0x58 CCR5
0x5c CNDTR5
0x60 CPAR5
0x64 CMAR5
0x6c CCR6
0x70 CNDTR6
0x74 CPAR6
0x78 CMAR6
0x80 CCR7
0x84 CNDTR7
0x88 CPAR7
0x8c CMAR7
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle fields

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF7
w 		CHTIF7
w 		CTCIF7
w 		CGIF7
w 		CTEIF6
w 		CHTIF6
w 		CTCIF6
w 		CGIF6
w 		CTEIF5
w 		CHTIF5
w 		CTCIF5
w 		CGIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4
w 		CHTIF4
w 		CTCIF4
w 		CGIF4
w 		CTEIF3
w 		CHTIF3
w 		CTCIF3
w 		CGIF3
w 		CTEIF2
w 		CHTIF2
w 		CTCIF2
w 		CGIF2
w 		CTEIF1
w 		CHTIF1
w 		CTCIF1
w 		CGIF1
w
Toggle fields

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CCR1

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR1

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR1

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR2

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR2

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR2

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR3

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR3

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR3

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR3

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR4

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR4

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR4

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR5

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR5

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR5

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR6

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR6

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR6

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR7

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR7

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR7

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR7

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

DMA2

0x40026400: Direct memory access controller

28/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CCR1
0xc CNDTR1
0x10 CPAR1
0x14 CMAR1
0x1c CCR2
0x20 CNDTR2
0x24 CPAR2
0x28 CMAR2
0x30 CCR3
0x34 CNDTR3
0x38 CPAR3
0x3c CMAR3
0x44 CCR4
0x48 CNDTR4
0x4c CPAR4
0x50 CMAR4
0x58 CCR5
0x5c CNDTR5
0x60 CPAR5
0x64 CMAR5
0x6c CCR6
0x70 CNDTR6
0x74 CPAR6
0x78 CMAR6
0x80 CCR7
0x84 CNDTR7
0x88 CPAR7
0x8c CMAR7
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle fields

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF7
w 		CHTIF7
w 		CTCIF7
w 		CGIF7
w 		CTEIF6
w 		CHTIF6
w 		CTCIF6
w 		CGIF6
w 		CTEIF5
w 		CHTIF5
w 		CTCIF5
w 		CGIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4
w 		CHTIF4
w 		CTCIF4
w 		CGIF4
w 		CTEIF3
w 		CHTIF3
w 		CTCIF3
w 		CGIF3
w 		CTEIF2
w 		CHTIF2
w 		CTCIF2
w 		CGIF2
w 		CTEIF1
w 		CHTIF1
w 		CTCIF1
w 		CGIF1
w
Toggle fields

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CCR1

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR1

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR1

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR2

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR2

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR2

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR3

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR3

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR3

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR3

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR4

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR4

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR4

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR5

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR5

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR5

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR6

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR6

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR6

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CCR7

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR7

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

CPAR7

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

CMAR7

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

EXTI

0x40010400: External interrupt/event controller

138/138 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IMR
0x4 EMR
0x8 RTSR
0xc FTSR
0x10 SWIER
0x14 PR
Toggle registers

IMR

IMR

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR22
rw 		MR21
rw 		MR20
rw 		MR19
rw 		MR18
rw 		MR17
rw 		MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw 		MR14
rw 		MR13
rw 		MR12
rw 		MR11
rw 		MR10
rw 		MR9
rw 		MR8
rw 		MR7
rw 		MR6
rw 		MR5
rw 		MR4
rw 		MR3
rw 		MR2
rw 		MR1
rw 		MR0
rw
Toggle fields

MR0

Bit 0: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Interrupt mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR

EMR

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR22
rw 		MR21
rw 		MR20
rw 		MR19
rw 		MR18
rw 		MR17
rw 		MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw 		MR14
rw 		MR13
rw 		MR12
rw 		MR11
rw 		MR10
rw 		MR9
rw 		MR8
rw 		MR7
rw 		MR6
rw 		MR5
rw 		MR4
rw 		MR3
rw 		MR2
rw 		MR1
rw 		MR0
rw
Toggle fields

MR0

Bit 0: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Event mask on line x.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR

RTSR

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw 		TR21
rw 		TR20
rw 		TR19
rw 		TR18
rw 		TR17
rw 		TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw 		TR14
rw 		TR13
rw 		TR12
rw 		TR11
rw 		TR10
rw 		TR9
rw 		TR8
rw 		TR7
rw 		TR6
rw 		TR5
rw 		TR4
rw 		TR3
rw 		TR2
rw 		TR1
rw 		TR0
rw
Toggle fields

TR0

Bit 0: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR17

Bit 17: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR19

Bit 19: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR20

Bit 20: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR21

Bit 21: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR22

Bit 22: Rising edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR

FTSR

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw 		TR21
rw 		TR20
rw 		TR19
rw 		TR18
rw 		TR17
rw 		TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw 		TR14
rw 		TR13
rw 		TR12
rw 		TR11
rw 		TR10
rw 		TR9
rw 		TR8
rw 		TR7
rw 		TR6
rw 		TR5
rw 		TR4
rw 		TR3
rw 		TR2
rw 		TR1
rw 		TR0
rw
Toggle fields

TR0

Bit 0: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR17

Bit 17: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR19

Bit 19: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR20

Bit 20: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR21

Bit 21: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR22

Bit 22: Falling edge trigger event configuration bit of line x.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER

SWIER

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER22
rw 		SWIER21
rw 		SWIER20
rw 		SWIER19
rw 		SWIER18
rw 		SWIER17
rw 		SWIER16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER15
rw 		SWIER14
rw 		SWIER13
rw 		SWIER12
rw 		SWIER11
rw 		SWIER10
rw 		SWIER9
rw 		SWIER8
rw 		SWIER7
rw 		SWIER6
rw 		SWIER5
rw 		SWIER4
rw 		SWIER3
rw 		SWIER2
rw 		SWIER1
rw 		SWIER0
rw
Toggle fields

SWIER0

Bit 0: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER17

Bit 17: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER19

Bit 19: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER20

Bit 20: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER21

Bit 21: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

SWIER22

Bit 22: Software interrupt on line x.

Allowed values:
1: Pend: Generates an interrupt request

PR

PR

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR22
rw 		PR21
rw 		PR20
rw 		PR19
rw 		PR18
rw 		PR17
rw 		PR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15
rw 		PR14
rw 		PR13
rw 		PR12
rw 		PR11
rw 		PR10
rw 		PR9
rw 		PR8
rw 		PR7
rw 		PR6
rw 		PR5
rw 		PR4
rw 		PR3
rw 		PR2
rw 		PR1
rw 		PR0
rw
Toggle fields

PR0

Bit 0: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR17

Bit 17: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR18

Bit 18: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR19

Bit 19: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR20

Bit 20: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR21

Bit 21: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR22

Bit 22: Pending bit.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

Flash

0x40023c00: Flash

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 PECR
0x8 PDKEYR
0xc PEKEYR
0x10 PRGKEYR
0x14 OPTKEYR
0x18 SR
0x1c OBR
0x20 WRPR1
0x80 WRPR2
0x84 WRPR3
Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUN_PD
rw 		SLEEP_PD
rw 		ACC64
rw 		PRFTEN
rw 		LATENCY
rw
Toggle fields

LATENCY

Bit 0: Latency.

PRFTEN

Bit 1: Prefetch enable.

ACC64

Bit 2: 64-bit access.

SLEEP_PD

Bit 3: Flash mode during Sleep.

RUN_PD

Bit 4: Flash mode during Run.

PECR

Program/erase control register

Offset: 0x4, size: 32, reset: 0x00000007, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OBL_LAUNCH
rw 		ERRIE
rw 		EOPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PARALLELBANK
rw 		FPRG
rw 		ERASE
rw 		FTDW
rw 		DATA
rw 		PROG
rw 		OPTLOCK
rw 		PRGLOCK
rw 		PELOCK
rw
Toggle fields

PELOCK

Bit 0: FLASH_PECR and data EEPROM lock.

PRGLOCK

Bit 1: Program memory lock.

OPTLOCK

Bit 2: Option bytes block lock.

PROG

Bit 3: Program memory selection.

DATA

Bit 4: Data EEPROM selection.

FTDW

Bit 8: Fixed time data write for Byte, Half Word and Word programming.

ERASE

Bit 9: Page or Double Word erase mode.

FPRG

Bit 10: Half Page/Double Word programming mode.

PARALLELBANK

Bit 15: Parallel bank mode.

EOPIE

Bit 16: End of programming interrupt enable.

ERRIE

Bit 17: Error interrupt enable.

OBL_LAUNCH

Bit 18: Launch the option byte loading.

PDKEYR

Power down key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR
w
Toggle fields

PDKEYR

Bits 0-31: RUN_PD in FLASH_ACR key.

PEKEYR

Program/erase key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PEKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEKEYR
w
Toggle fields

PEKEYR

Bits 0-31: FLASH_PEC and data EEPROM key.

PRGKEYR

Program memory key register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRGKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRGKEYR
w
Toggle fields

PRGKEYR

Bits 0-31: Program memory key.

OPTKEYR

Option byte key register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle fields

OPTKEYR

Bits 0-31: Option byte key.

SR

Status register

Offset: 0x18, size: 32, reset: 0x00000004, access: Unspecified

4/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERRUSR
rw 		OPTVERR
rw 		SIZERR
rw 		PGAERR
rw 		WRPERR
rw 		READY
r 		ENDHV
r 		EOP
r 		BSY
r
Toggle fields

BSY

Bit 0: Write/erase operations in progress.

EOP

Bit 1: End of operation.

ENDHV

Bit 2: End of high voltage.

READY

Bit 3: Flash memory module ready after low power mode.

WRPERR

Bit 8: Write protected error.

PGAERR

Bit 9: Programming alignment error.

SIZERR

Bit 10: Size error.

OPTVERR

Bit 11: Option validity error.

OPTVERRUSR

Bit 12: Option UserValidity Error.

OBR

Option byte register

Offset: 0x1c, size: 32, reset: 0x00F80000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BFB2
r 		nRST_STDBY
r 		nRTS_STOP
r 		IWDG_SW
r 		BOR_LEV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDPRT
r
Toggle fields

RDPRT

Bits 0-7: Read protection.

BOR_LEV

Bits 16-19: BOR_LEV.

IWDG_SW

Bit 20: IWDG_SW.

nRTS_STOP

Bit 21: nRTS_STOP.

nRST_STDBY

Bit 22: nRST_STDBY.

BFB2

Bit 23: Boot From Bank 2.

WRPR1

Write protection register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1
rw
Toggle fields

WRP1

Bits 0-31: Write protection.

WRPR2

Write protection register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2
rw
Toggle fields

WRP2

Bits 0-31: WRP2.

WRPR3

Write protection register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP3
rw
Toggle fields

WRP3

Bits 0-31: WRP3.

FSMC

0xa0000000: Flexible static memory controller

104/116 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BCR1
0x4 BTR[1]
0x8 BCR[2]
0xc BTR[2]
0x10 BCR[3]
0x14 BTR[3]
0x18 BCR[4]
0x1c BTR[4]
0x104 BWTR[1]
0x10c BWTR[2]
0x114 BWTR[3]
0x11c BWTR[4]
Toggle registers

BCR1

BCR1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[1]

BTR1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[2]

BCR2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[2]

BTR2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[3]

BCR3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[3]

BTR3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR[4]

BCR4

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

BTR[4]

BTR4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[1]

BWTR1

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[2]

BWTR2

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[3]

BWTR3

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[4]

BWTR4

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 0x1-0xf

DATAST

Bits 8-15: DATAST.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

GPIOA

0x40020000: General-purpose I/Os

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xA8000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

AFRL

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOB

0x40020400: General-purpose I/Os

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000280, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

AFRL

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOC

0x40020800: General-purpose I/Os

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

AFRL

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOD

0x40020c00: General-purpose I/Os

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

AFRL

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOH

0x40021400: General-purpose I/Os

161/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

AFRL

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

I2C1

0x40005400: Inter-integrated circuit

51/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 DR
0x14 SR1
0x18 SR2
0x1c CCR
0x20 TRISE
Toggle registers

CR1

CR1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		ALERT
rw 		PEC
rw 		POS
rw 		ACK
rw 		STOP
rw 		START
rw 		NOSTRETCH
rw 		ENGC
rw 		ENPEC
rw 		ENARP
rw 		SMBTYPE
rw 		SMBUS
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

CR2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw 		DMAEN
rw 		ITBUFEN
rw 		ITEVTEN
rw 		ITERREN
rw 		FREQ
rw
Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 0x2-0x32

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

OAR1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw 		ADD
rw
Toggle fields

ADD

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

ADDMODE

Bit 15: ADDMODE.

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

OAR2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw 		ENDUAL
rw
Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

DR

DR

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: -bit data register.

Allowed values: 0x0-0xff

SR1

SR1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw 		TIMEOUT
rw 		PECERR
rw 		OVR
rw 		AF
rw 		ARLO
rw 		BERR
rw 		TxE
r 		RxNE
r 		STOPF
r 		ADD10
r 		BTF
r 		ADDR
r 		SB
r
Toggle fields

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

SR2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r 		DUALF
r 		SMBHOST
r 		SMBDEFAULT
r 		GENCALL
r 		TRA
r 		BUSY
r 		MSL
r
Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

CCR

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw 		DUTY
rw 		CCR
rw
Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0x1-0xfff

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0x0-0x3f

I2C2

0x40005800: Inter-integrated circuit

51/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 DR
0x14 SR1
0x18 SR2
0x1c CCR
0x20 TRISE
Toggle registers

CR1

CR1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		ALERT
rw 		PEC
rw 		POS
rw 		ACK
rw 		STOP
rw 		START
rw 		NOSTRETCH
rw 		ENGC
rw 		ENPEC
rw 		ENARP
rw 		SMBTYPE
rw 		SMBUS
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

CR2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw 		DMAEN
rw 		ITBUFEN
rw 		ITEVTEN
rw 		ITERREN
rw 		FREQ
rw
Toggle fields

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 0x2-0x32

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

OAR1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw 		ADD
rw
Toggle fields

ADD

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

ADDMODE

Bit 15: ADDMODE.

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

OAR2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw 		ENDUAL
rw
Toggle fields

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

DR

DR

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: -bit data register.

Allowed values: 0x0-0xff

SR1

SR1

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw 		TIMEOUT
rw 		PECERR
rw 		OVR
rw 		AF
rw 		ARLO
rw 		BERR
rw 		TxE
r 		RxNE
r 		STOPF
r 		ADD10
r 		BTF
r 		ADDR
r 		SB
r
Toggle fields

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

SR2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r 		DUALF
r 		SMBHOST
r 		SMBDEFAULT
r 		GENCALL
r 		TRA
r 		BUSY
r 		MSL
r
Toggle fields

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

CCR

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw 		DUTY
rw 		CCR
rw
Toggle fields

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0x1-0xfff

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE

Offset: 0x20, size: 32, reset: 0x00000002, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle fields

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0x0-0x3f

IWDG

0x40003000: Independent watchdog

5/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 KR
0x4 PR
0x8 RLR
0xc SR
Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0000h).

Allowed values:
21845: Unlock: Enable access to PR, RLR and WINR registers
43690: Feed: Feed watchdog with RLR register value
52428: Start: Start the watchdog

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0x0-0xfff

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

LCD

0x40002400: Liquid crystal display controller

5/279 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 FCR
0x8 SR
0xc CLR
0x14 RAM_COM0
0x1c RAM_COM1
0x24 RAM_COM2
0x2c RAM_COM3
0x34 RAM_COM4
0x3c RAM_COM5
0x44 RAM_COM6
0x4c RAM_COM7
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_SEG
rw 		BIAS
rw 		DUTY
rw 		VSEL
rw 		LCDEN
rw
Toggle fields

LCDEN

Bit 0: LCD controller enable.

VSEL

Bit 1: Voltage source selection.

DUTY

Bits 2-4: Duty selection.

BIAS

Bits 5-6: Bias selector.

MUX_SEG

Bit 7: Mux segment enable.

FCR

frame control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PS
rw 		DIV
rw 		BLINK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLINKF
rw 		CC
rw 		DEAD
rw 		PON
rw 		UDDIE
rw 		SOFIE
rw 		HD
rw
Toggle fields

HD

Bit 0: High drive enable.

SOFIE

Bit 1: Start of frame interrupt enable.

UDDIE

Bit 3: Update display done interrupt enable.

PON

Bits 4-6: Pulse ON duration.

DEAD

Bits 7-9: Dead time duration.

CC

Bits 10-12: Contrast control.

BLINKF

Bits 13-15: Blink frequency selection.

Bits 16-17: Blink mode selection.

DIV

Bits 18-21: DIV clock divider.

PS

Bits 22-25: PS 16-bit prescaler.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000020, access: Unspecified

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FCRSF
r 		RDY
r 		UDD
r 		UDR
rw 		SOF
r 		ENS
r
Toggle fields

ENS

Bit 0: LCD enabled status.

SOF

Bit 1: Start of frame flag.

UDR

Bit 2: Update display request.

UDD

Bit 3: Update Display Done.

RDY

Bit 4: Ready flag.

FCRSF

Bit 5: LCD Frame Control Register Synchronization flag.

CLR

clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDDC
w 		SOFC
w
Toggle fields

SOFC

Bit 1: Start of frame flag clear.

UDDC

Bit 3: Update display done clear.

RAM_COM0

display memory

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw 		S30
rw 		S29
rw 		S28
rw 		S27
rw 		S26
rw 		S25
rw 		S24
rw 		S23
rw 		S22
rw 		S21
rw 		S20
rw 		S19
rw 		S18
rw 		S17
rw 		S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw 		S14
rw 		S13
rw 		S12
rw 		S11
rw 		S10
rw 		S09
rw 		S08
rw 		S07
rw 		S06
rw 		S05
rw 		S04
rw 		S03
rw 		S02
rw 		S01
rw 		S00
rw
Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM1

display memory

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw 		S30
rw 		S29
rw 		S28
rw 		S27
rw 		S26
rw 		S25
rw 		S24
rw 		S23
rw 		S22
rw 		S21
rw 		S20
rw 		S19
rw 		S18
rw 		S17
rw 		S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw 		S14
rw 		S13
rw 		S12
rw 		S11
rw 		S10
rw 		S09
rw 		S08
rw 		S07
rw 		S06
rw 		S05
rw 		S04
rw 		S03
rw 		S02
rw 		S01
rw 		S00
rw
Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM2

display memory

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw 		S30
rw 		S29
rw 		S28
rw 		S27
rw 		S26
rw 		S25
rw 		S24
rw 		S23
rw 		S22
rw 		S21
rw 		S20
rw 		S19
rw 		S18
rw 		S17
rw 		S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw 		S14
rw 		S13
rw 		S12
rw 		S11
rw 		S10
rw 		S09
rw 		S08
rw 		S07
rw 		S06
rw 		S05
rw 		S04
rw 		S03
rw 		S02
rw 		S01
rw 		S00
rw
Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM3

display memory

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw 		S30
rw 		S29
rw 		S28
rw 		S27
rw 		S26
rw 		S25
rw 		S24
rw 		S23
rw 		S22
rw 		S21
rw 		S20
rw 		S19
rw 		S18
rw 		S17
rw 		S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw 		S14
rw 		S13
rw 		S12
rw 		S11
rw 		S10
rw 		S09
rw 		S08
rw 		S07
rw 		S06
rw 		S05
rw 		S04
rw 		S03
rw 		S02
rw 		S01
rw 		S00
rw
Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM4

display memory

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw 		S30
rw 		S29
rw 		S28
rw 		S27
rw 		S26
rw 		S25
rw 		S24
rw 		S23
rw 		S22
rw 		S21
rw 		S20
rw 		S19
rw 		S18
rw 		S17
rw 		S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw 		S14
rw 		S13
rw 		S12
rw 		S11
rw 		S10
rw 		S09
rw 		S08
rw 		S07
rw 		S06
rw 		S05
rw 		S04
rw 		S03
rw 		S02
rw 		S01
rw 		S00
rw
Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM5

display memory

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw 		S30
rw 		S29
rw 		S28
rw 		S27
rw 		S26
rw 		S25
rw 		S24
rw 		S23
rw 		S22
rw 		S21
rw 		S20
rw 		S19
rw 		S18
rw 		S17
rw 		S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw 		S14
rw 		S13
rw 		S12
rw 		S11
rw 		S10
rw 		S09
rw 		S08
rw 		S07
rw 		S06
rw 		S05
rw 		S04
rw 		S03
rw 		S02
rw 		S01
rw 		S00
rw
Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM6

display memory

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw 		S30
rw 		S29
rw 		S28
rw 		S27
rw 		S26
rw 		S25
rw 		S24
rw 		S23
rw 		S22
rw 		S21
rw 		S20
rw 		S19
rw 		S18
rw 		S17
rw 		S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw 		S14
rw 		S13
rw 		S12
rw 		S11
rw 		S10
rw 		S09
rw 		S08
rw 		S07
rw 		S06
rw 		S05
rw 		S04
rw 		S03
rw 		S02
rw 		S01
rw 		S00
rw
Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM7

display memory

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw 		S30
rw 		S29
rw 		S28
rw 		S27
rw 		S26
rw 		S25
rw 		S24
rw 		S23
rw 		S22
rw 		S21
rw 		S20
rw 		S19
rw 		S18
rw 		S17
rw 		S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw 		S14
rw 		S13
rw 		S12
rw 		S11
rw 		S10
rw 		S09
rw 		S08
rw 		S07
rw 		S06
rw 		S05
rw 		S04
rw 		S03
rw 		S02
rw 		S01
rw 		S00
rw
Toggle fields

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

MPU

0xe000ed90: Memory protection unit

6/19 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TYPER
0x4 CTRL
0x8 RNR
0xc RBAR
0x10 RASR
Toggle registers

TYPER

MPU type register

Offset: 0x0, size: 32, reset: 0x00000800, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREGION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DREGION
r 		SEPARATE
r
Toggle fields

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

CTRL

MPU control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIVDEFENA
r 		HFNMIENA
r 		ENABLE
r
Toggle fields

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

RNR

MPU region number register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGION
rw
Toggle fields

REGION

Bits 0-7: MPU region.

RBAR

MPU region base address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw 		VALID
rw 		REGION
rw
Toggle fields

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

RASR

MPU region attribute and size register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XN
rw 		AP
rw 		TEX
rw 		S
rw 		C
rw 		B
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD
rw 		SIZE
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xe000e100: Nested Vectored Interrupt Controller

2/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISER0
0x4 ISER1
0x80 ICER0
0x84 ICER1
0x100 ISPR0
0x104 ISPR1
0x180 ICPR0
0x184 ICPR1
0x200 IABR0
0x204 IABR1
0x300 IPR0
0x304 IPR1
0x308 IPR2
0x30c IPR3
0x310 IPR4
0x314 IPR5
0x318 IPR6
0x31c IPR7
0x320 IPR8
0x324 IPR9
0x328 IPR10
0x32c IPR11
0x330 IPR12
0x334 IPR13
Toggle registers

ISER0

Interrupt Set-Enable Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xe000ef00: Nested vectored interrupt controller

0/1 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 STIR
Toggle registers

STIR

Software trigger interrupt register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
rw
Toggle fields

INTID

Bits 0-8: Software generated interrupt ID.

OPAMP

0x40007c5c: Operational amplifiers

0/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 OTR
0x8 LPOTR
Toggle registers

CSR

control/status register

Offset: 0x0, size: 32, reset: 0x00010101, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA3CALOUT
rw 		OPA2CALOUT
rw 		OPA1CALOUT
rw 		AOP_RANGE
rw 		S7SEL2
rw 		ANAWSEL3
rw 		ANAWSEL2
rw 		ANAWSEL1
rw 		OPA3LPM
rw 		OPA3CAL_H
rw 		OPA3CAL_L
rw 		S6SEL3
rw 		S5SEL3
rw 		S4SEL3
rw 		S3SEL3
rw 		OPA3PD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPA2LPM
rw 		OPA2CAL_H
rw 		OPA2CAL_L
rw 		S6SEL2
rw 		S5SEL2
rw 		S4SEL2
rw 		S3SEL2
rw 		OPA2PD
rw 		OPA1LPM
rw 		OPA1CAL_H
rw 		OPA1CAL_L
rw 		S6SEL1
rw 		S5SEL1
rw 		S4SEL1
rw 		S3SEL1
rw 		OPA1PD
rw
Toggle fields

OPA1PD

Bit 0: OPAMP1 power down.

S3SEL1

Bit 1: Switch 3 for OPAMP1 enable.

S4SEL1

Bit 2: Switch 4 for OPAMP1 enable.

S5SEL1

Bit 3: Switch 5 for OPAMP1 enable.

S6SEL1

Bit 4: Switch 6 for OPAMP1 enable.

OPA1CAL_L

Bit 5: OPAMP1 offset calibration for P differential pair.

OPA1CAL_H

Bit 6: OPAMP1 offset calibration for N differential pair.

OPA1LPM

Bit 7: OPAMP1 low power mode.

OPA2PD

Bit 8: OPAMP2 power down.

S3SEL2

Bit 9: Switch 3 for OPAMP2 enable.

S4SEL2

Bit 10: Switch 4 for OPAMP2 enable.

S5SEL2

Bit 11: Switch 5 for OPAMP2 enable.

S6SEL2

Bit 12: Switch 6 for OPAMP2 enable.

OPA2CAL_L

Bit 13: OPAMP2 offset Calibration for P differential pair.

OPA2CAL_H

Bit 14: OPAMP2 offset calibration for N differential pair.

OPA2LPM

Bit 15: OPAMP2 low power mode.

OPA3PD

Bit 16: OPAMP3 power down.

S3SEL3

Bit 17: Switch 3 for OPAMP3 Enable.

S4SEL3

Bit 18: Switch 4 for OPAMP3 enable.

S5SEL3

Bit 19: Switch 5 for OPAMP3 enable.

S6SEL3

Bit 20: Switch 6 for OPAMP3 enable.

OPA3CAL_L

Bit 21: OPAMP3 offset Calibration for P differential pair.

OPA3CAL_H

Bit 22: OPAMP3 offset calibration for N differential pair.

OPA3LPM

Bit 23: OPAMP3 low power mode.

ANAWSEL1

Bit 24: Switch SanA enable for OPAMP1.

ANAWSEL2

Bit 25: Switch SanA enable for OPAMP2.

ANAWSEL3

Bit 26: Switch SanA enable for OPAMP3.

S7SEL2

Bit 27: Switch 7 for OPAMP2 enable.

AOP_RANGE

Bit 28: Power range selection.

OPA1CALOUT

Bit 29: OPAMP1 calibration output.

OPA2CALOUT

Bit 30: OPAMP2 calibration output.

OPA3CALOUT

Bit 31: OPAMP3 calibration output.

OTR

offset trimming register for normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OT_USER
rw 		AO3_OPT_OFFSET_TRIM
rw 		AO2_OPT_OFFSET_TRIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AO2_OPT_OFFSET_TRIM
rw 		AO1_OPT_OFFSET_TRIM
rw
Toggle fields

AO1_OPT_OFFSET_TRIM

Bits 0-9: OPAMP1, 10-bit offset trim value for normal mode.

AO2_OPT_OFFSET_TRIM

Bits 10-19: OPAMP2, 10-bit offset trim value for normal mode.

AO3_OPT_OFFSET_TRIM

Bits 20-29: OPAMP3, 10-bit offset trim value for normal mode.

OT_USER

Bit 31: Select user or factory trimming value.

LPOTR

OPAMP offset trimming register for low power mode

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AO3_OPT_OFFSET_TRIM_LP
rw 		AO2_OPT_OFFSET_TRIM_LP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AO2_OPT_OFFSET_TRIM_LP
rw 		AO1_OPT_OFFSET_TRIM_LP
rw
Toggle fields

AO1_OPT_OFFSET_TRIM_LP

Bits 0-9: OPAMP1, 10-bit offset trim value for low power mode.

AO2_OPT_OFFSET_TRIM_LP

Bits 10-19: OPAMP2, 10-bit offset trim value for low power mode.

AO3_OPT_OFFSET_TRIM_LP

Bits 20-29: OPAMP3, 10-bit offset trim value for low power mode.

PWR

0x40007000: Power control

7/20 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CSR
Toggle registers

CR

power control register

Offset: 0x0, size: 32, reset: 0x00001000, access: read-write

1/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPRUN
rw 		VOS
rw 		FWU
rw 		ULP
rw 		DBP
rw 		PLS
rw 		PVDE
rw 		CSBF
rw 		CWUF
rw 		PDDS
rw 		LPSDSR
rw
Toggle fields

LPSDSR

Bit 0: Low-power deep sleep.

PDDS

Bit 1: Power down deepsleep.

Allowed values:
0: STOP_MODE: Enter Stop mode when the CPU enters deepsleep
1: STANDBY_MODE: Enter Standby mode when the CPU enters deepsleep

CWUF

Bit 2: Clear wakeup flag.

CSBF

Bit 3: Clear standby flag.

PVDE

Bit 4: Power voltage detector enable.

PLS

Bits 5-7: PVD level selection.

DBP

Bit 8: Disable backup domain write protection.

ULP

Bit 9: Ultralow power mode.

FWU

Bit 10: Fast wakeup.

VOS

Bits 11-12: Voltage scaling range selection.

LPRUN

Bit 14: Low power run mode.

CSR

power control/status register

Offset: 0x4, size: 32, reset: 0x00000008, access: Unspecified

6/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWUP3
rw 		EWUP2
rw 		EWUP1
rw 		REGLPF
r 		VOSF
r 		VREFINTRDYF
r 		PVDO
r 		SBF
r 		WUF
r
Toggle fields

WUF

Bit 0: Wakeup flag.

SBF

Bit 1: Standby flag.

PVDO

Bit 2: PVD output.

VREFINTRDYF

Bit 3: Internal voltage reference (VREFINT) ready flag.

VOSF

Bit 4: Voltage Scaling select flag.

REGLPF

Bit 5: Regulator LP flag.

EWUP1

Bit 8: Enable WKUP pin 1.

EWUP2

Bit 9: Enable WKUP pin 2.

EWUP3

Bit 10: Enable WKUP pin 3.

RCC

0x40023800: Reset and clock control

182/192 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ICSCR
0x8 CFGR
0xc CIR
0x10 AHBRSTR
0x14 APB2RSTR
0x18 APB1RSTR
0x1c AHBENR
0x20 APB2ENR
0x24 APB1ENR
0x28 AHBLPENR
0x2c APB2LPENR
0x30 APB1LPENR
0x34 CSR
Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000300, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTCPRE
N/A 		CSSON
rw 		PLLRDY
r 		PLLON
rw 		HSEBYP
rw 		HSERDY
r 		HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSIRDY
r 		MSION
rw 		HSIRDY
r 		HSION
rw
Toggle fields

HSION

Bit 0: Internal high-speed clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

HSIRDY

Bit 1: Internal high-speed clock ready flag.

Allowed values:
0: NotReady: Oscillator is not stable
1: Ready: Oscillator is stable

MSION

Bit 8: MSI clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

MSIRDY

Bit 9: MSI clock ready flag.

Allowed values:
0: NotReady: Oscillator is not stable
1: Ready: Oscillator is stable

HSEON

Bit 16: HSE clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

HSERDY

Bit 17: HSE clock ready flag.

Allowed values:
0: NotReady: Oscillator is not stable
1: Ready: Oscillator is stable

HSEBYP

Bit 18: HSE clock bypass.

Allowed values:
0: NotBypassed: HSE oscillator not bypassed
1: Bypassed: HSE oscillator bypassed

PLLON

Bit 24: PLL enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

PLLRDY

Bit 25: PLL clock ready flag.

Allowed values:
0: Unlocked: PLL unlocked
1: Locked: PLL locked

CSSON

Bit 28: Clock security system enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

RTCPRE

Bits 29-30: TC/LCD prescaler.

Allowed values:
0: Div2: HSE divided by 2
1: Div4: HSE divided by 4
2: Div8: HSE divided by 8
3: Div16: HSE divided by 16

ICSCR

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x0000B000, access: Unspecified

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSITRIM
rw 		MSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSIRANGE
rw 		HSITRIM
rw 		HSICAL
r
Toggle fields

HSICAL

Bits 0-7: nternal high speed clock calibration.

HSITRIM

Bits 8-12: High speed internal clock trimming.

MSIRANGE

Bits 13-15: MSI clock ranges.

MSICAL

Bits 16-23: MSI clock calibration.

MSITRIM

Bits 24-31: MSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
rw 		MCOSEL
rw 		PLLDIV
rw 		PLLMUL
rw 		PLLSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPRE2
rw 		PPRE1
rw 		HPRE
rw 		SWS
r 		SW
rw
Toggle fields

SW

Bits 0-1: System clock switch.

Allowed values:
0: HSI: MSI oscillator used as system clock
1: MSI: HSI oscillator used as system clock
2: HSE: HSE oscillator used as system clock
3: PLL: PLL used as system clock

SWS

Bits 2-3: System clock switch status.

Allowed values:
0: HSI: MSI oscillator used as system clock
1: MSI: HSI oscillator used as system clock
2: HSE: HSE oscillator used as system clock
3: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
8: Div2: system clock divided by 2
9: Div4: system clock divided by 4
10: Div8: system clock divided by 8
11: Div16: system clock divided by 16
12: Div64: system clock divided by 64
13: Div128: system clock divided by 128
14: Div256: system clock divided by 256
15: Div512: system clock divided by 512
0 (+): Div1: system clock not divided

PPRE1

Bits 8-10: APB low-speed prescaler (APB1).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PLLSRC

Bit 16: PLL entry clock source.

Allowed values:
0: HSI: HSI selected as PLL input clock
1: HSE: HSE selected as PLL input clock

PLLMUL

Bits 18-21: PLL multiplication factor.

Allowed values:
0: Mul3: PLL clock entry x 3
1: Mul4: PLL clock entry x 4
2: Mul6: PLL clock entry x 6
3: Mul8: PLL clock entry x 8
4: Mul12: PLL clock entry x 12
5: Mul16: PLL clock entry x 16
6: Mul24: PLL clock entry x 24
7: Mul32: PLL clock entry x 32
8: Mul48: PLL clock entry x 48

PLLDIV

Bits 22-23: PLL output division.

Allowed values:
1: Div2: PLLVCO / 2
2: Div3: PLLVCO / 3
3: Div4: PLLVCO / 4

MCOSEL

Bits 24-26: Microcontroller clock output selection.

Allowed values:
0: NoClock: No clock
1: SYSCLK: SYSCLK clock selected
2: HSI: HSI oscillator clock selected
3: MSI: MSI oscillator clock selected
4: HSE: HSE oscillator clock selected
5: PLL: PLL clock selected
6: LSI: LSI oscillator clock selected
7: LSE: LSE oscillator clock selected

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

Allowed values:
0: Div1: No division
1: Div2: Division by 2
2: Div4: Division by 4
3: Div8: Division by 8
4: Div16: Division by 16

CIR

Clock interrupt register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSSC
w 		LSECSSC
w 		MSIRDYC
w 		PLLRDYC
w 		HSERDYC
w 		HSIRDYC
w 		LSERDYC
w 		LSIRDYC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSIE
N/A 		MSIRDYIE
rw 		PLLRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw 		CSSF
r 		LSECSSF
N/A 		MSIRDYF
r 		PLLRDYF
r 		HSERDYF
r 		HSIRDYF
r 		LSERDYF
r 		LSIRDYF
r
Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

Allowed values:
0: NotStable: Clock is not stable
1: Stable: Clock is stable

LSERDYF

Bit 1: LSE ready interrupt flag.

Allowed values:
0: NotStable: Clock is not stable
1: Stable: Clock is stable

HSIRDYF

Bit 2: HSI ready interrupt flag.

Allowed values:
0: NotStable: Clock is not stable
1: Stable: Clock is stable

HSERDYF

Bit 3: HSE ready interrupt flag.

Allowed values:
0: NotStable: Clock is not stable
1: Stable: Clock is stable

PLLRDYF

Bit 4: PLL ready interrupt flag.

Allowed values:
0: NotStable: Clock is not stable
1: Stable: Clock is stable

MSIRDYF

Bit 5: MSI ready interrupt flag.

Allowed values:
0: NotStable: Clock is not stable
1: Stable: Clock is stable

LSECSSF

Bit 6: LSE Clock security system interrupt flag.

Allowed values:
0: NoFailure: No failure detected on the external 32 KHz oscillator
1: Failure: A failure is detected on the external 32 kHz oscillator

CSSF

Bit 7: Clock security system interrupt flag.

Allowed values:
0: NotInterupted: No clock security interrupt caused by HSE clock failure
1: Interupted: Clock security interrupt caused by HSE clock failure

LSIRDYIE

Bit 8: LSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSERDYIE

Bit 9: LSE ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSIRDYIE

Bit 10: HSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSERDYIE

Bit 11: HSE ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLRDYIE

Bit 12: PLL ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

MSIRDYIE

Bit 13: MSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSECSSIE

Bit 14: LSE clock security system interrupt enable.

Allowed values:
0: Disabled: LSE CSS interrupt disabled
1: Enabled: LSE CSS interrupt enabled

LSIRDYC

Bit 16: LSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt

LSERDYC

Bit 17: LSE ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt

HSIRDYC

Bit 18: HSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt

HSERDYC

Bit 19: HSE ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt

PLLRDYC

Bit 20: PLL ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt

MSIRDYC

Bit 21: MSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt

LSECSSC

Bit 22: LSE Clock security system interrupt clear.

Allowed values:
1: Clear: Clear interrupt

CSSC

Bit 23: Clock security system interrupt clear.

Allowed values:
1: Clear: Clear interrupt

AHBRSTR

AHB peripheral reset register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSMCRST
rw 		DMA2RST
rw 		DMA1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLITFRST
rw 		CRCRST
rw 		GPIOGRST
rw 		GPIOFRST
rw 		GPIOHRST
rw 		GPIOERST
rw 		GPIODRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: IO port A reset.

Allowed values:
1: Reset: Reset the module

GPIOBRST

Bit 1: IO port B reset.

Allowed values:
1: Reset: Reset the module

GPIOCRST

Bit 2: IO port C reset.

Allowed values:
1: Reset: Reset the module

GPIODRST

Bit 3: IO port D reset.

Allowed values:
1: Reset: Reset the module

GPIOERST

Bit 4: IO port E reset.

Allowed values:
1: Reset: Reset the module

GPIOHRST

Bit 5: IO port H reset.

Allowed values:
1: Reset: Reset the module

GPIOFRST

Bit 6: IO port F reset.

Allowed values:
1: Reset: Reset the module

GPIOGRST

Bit 7: IO port G reset.

Allowed values:
1: Reset: Reset the module

CRCRST

Bit 12: CRC reset.

Allowed values:
1: Reset: Reset the module

FLITFRST

Bit 15: FLITF reset.

Allowed values:
1: Reset: Reset the module

DMA1RST

Bit 24: DMA1 reset.

Allowed values:
1: Reset: Reset the module

DMA2RST

Bit 25: DMA2 reset.

Allowed values:
1: Reset: Reset the module

FSMCRST

Bit 30: FSMC reset.

Allowed values:
1: Reset: Reset the module

APB2RSTR

APB2 peripheral reset register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		SPI1RST
rw 		SDIORST
rw 		ADC1RST
rw 		TM11RST
rw 		TM10RST
rw 		TIM9RST
rw 		SYSCFGRST
rw
Toggle fields

SYSCFGRST

Bit 0: SYSCFGRST.

Allowed values:
1: Reset: Reset the module

TIM9RST

Bit 2: TIM9RST.

Allowed values:
1: Reset: Reset the module

TM10RST

Bit 3: TM10RST.

Allowed values:
1: Reset: Reset the module

TM11RST

Bit 4: TM11RST.

Allowed values:
1: Reset: Reset the module

ADC1RST

Bit 9: ADC1RST.

Allowed values:
1: Reset: Reset the module

SDIORST

Bit 11: SDIORST.

Allowed values:
1: Reset: Reset the module

SPI1RST

Bit 12: SPI1RST.

Allowed values:
1: Reset: Reset the module

USART1RST

Bit 14: USART1RST.

Allowed values:
1: Reset: Reset the module

APB1RSTR

APB1 peripheral reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMPRST
rw 		DACRST
rw 		PWRRST
rw 		USBRST
rw 		I2C2RST
rw 		I2C1RST
rw 		UART5RST
rw 		UART4RST
rw 		USART3RST
rw 		USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw 		SPI2RST
rw 		WWDRST
rw 		LCDRST
rw 		TIM7RST
rw 		TIM6RST
rw 		TIM5RST
rw 		TIM4RST
rw 		TIM3RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: Timer 2 reset.

Allowed values:
1: Reset: Reset the module

TIM3RST

Bit 1: Timer 3 reset.

Allowed values:
1: Reset: Reset the module

TIM4RST

Bit 2: Timer 4 reset.

Allowed values:
1: Reset: Reset the module

TIM5RST

Bit 3: Timer 5 reset.

Allowed values:
1: Reset: Reset the module

TIM6RST

Bit 4: Timer 6reset.

Allowed values:
1: Reset: Reset the module

TIM7RST

Bit 5: Timer 7 reset.

Allowed values:
1: Reset: Reset the module

LCDRST

Bit 9: LCD reset.

Allowed values:
1: Reset: Reset the module

WWDRST

Bit 11: Window watchdog reset.

Allowed values:
1: Reset: Reset the module

SPI2RST

Bit 14: SPI 2 reset.

Allowed values:
1: Reset: Reset the module

SPI3RST

Bit 15: SPI 3 reset.

Allowed values:
1: Reset: Reset the module

USART2RST

Bit 17: USART 2 reset.

Allowed values:
1: Reset: Reset the module

USART3RST

Bit 18: USART 3 reset.

Allowed values:
1: Reset: Reset the module

UART4RST

Bit 19: UART 4 reset.

Allowed values:
1: Reset: Reset the module

UART5RST

Bit 20: UART 5 reset.

Allowed values:
1: Reset: Reset the module

I2C1RST

Bit 21: I2C 1 reset.

Allowed values:
1: Reset: Reset the module

I2C2RST

Bit 22: I2C 2 reset.

Allowed values:
1: Reset: Reset the module

USBRST

Bit 23: USB reset.

Allowed values:
1: Reset: Reset the module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the module

DACRST

Bit 29: DAC interface reset.

Allowed values:
1: Reset: Reset the module

COMPRST

Bit 31: COMP interface reset.

Allowed values:
1: Reset: Reset the module

AHBENR

AHB peripheral clock enable register

Offset: 0x1c, size: 32, reset: 0x00008000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSMCEN
rw 		DMA2EN
rw 		DMA1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLITFEN
rw 		CRCEN
rw 		GPIOPGEN
rw 		GPIOPFEN
rw 		GPIOPHEN
rw 		GPIOPEEN
rw 		GPIOPDEN
rw 		GPIOPCEN
rw 		GPIOPBEN
rw 		GPIOPAEN
rw
Toggle fields

GPIOPAEN

Bit 0: IO port A clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOPBEN

Bit 1: IO port B clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOPCEN

Bit 2: IO port C clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOPDEN

Bit 3: IO port D clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOPEEN

Bit 4: IO port E clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOPHEN

Bit 5: IO port H clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOPFEN

Bit 6: IO port F clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOPGEN

Bit 7: IO port G clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CRCEN

Bit 12: CRC clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

FLITFEN

Bit 15: FLITF clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DMA1EN

Bit 24: DMA1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DMA2EN

Bit 25: DMA2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

FSMCEN

Bit 30: FSMCEN.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB2ENR

APB2 peripheral clock enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw 		SPI1EN
rw 		SDIOEN
rw 		ADC1EN
rw 		TIM11EN
rw 		TIM10EN
rw 		TIM9EN
rw 		SYSCFGEN
rw
Toggle fields

SYSCFGEN

Bit 0: System configuration controller clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM9EN

Bit 2: TIM9 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM10EN

Bit 3: TIM10 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM11EN

Bit 4: TIM11 timer clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

ADC1EN

Bit 9: ADC1 interface clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SDIOEN

Bit 11: SDIO clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI1EN

Bit 12: SPI 1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART1EN

Bit 14: USART1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB1ENR

APB1 peripheral clock enable register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMPEN
rw 		DACEN
rw 		PWREN
rw 		USBEN
rw 		I2C2EN
rw 		I2C1EN
rw 		USART5EN
rw 		USART4EN
rw 		USART3EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3EN
rw 		SPI2EN
rw 		WWDGEN
rw 		LCDEN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: Timer 2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM3EN

Bit 1: Timer 3 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM4EN

Bit 2: Timer 4 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM5EN

Bit 3: Timer 5 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM6EN

Bit 4: Timer 6 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM7EN

Bit 5: Timer 7 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

LCDEN

Bit 9: LCD clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI2EN

Bit 14: SPI 2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI3EN

Bit 15: SPI 3 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART2EN

Bit 17: USART 2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART3EN

Bit 18: USART 3 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART4EN

Bit 19: UART 4 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART5EN

Bit 20: UART 5 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C1EN

Bit 21: I2C 1 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C2EN

Bit 22: I2C 2 clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USBEN

Bit 23: USB clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DACEN

Bit 29: DAC interface clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

COMPEN

Bit 31: COMP interface clock enable.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AHBLPENR

AHB peripheral clock enable in low power mode register

Offset: 0x28, size: 32, reset: 0x0101903F, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSMCLPEN
rw 		AESLPEN
rw 		DMA2LPEN
rw 		DMA1LPEN
rw 		SRAMLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLITFLPEN
rw 		CRCLPEN
rw 		GPIOGLPEN
rw 		GPIOFLPEN
rw 		GPIOHLPEN
rw 		GPIOELPEN
rw 		GPIODLPEN
rw 		GPIOCLPEN
rw 		GPIOBLPEN
rw 		GPIOALPEN
rw
Toggle fields

GPIOALPEN

Bit 0: IO port A clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOBLPEN

Bit 1: IO port B clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOCLPEN

Bit 2: IO port C clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIODLPEN

Bit 3: IO port D clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOELPEN

Bit 4: IO port E clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOHLPEN

Bit 5: IO port H clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOFLPEN

Bit 6: IO port F clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

GPIOGLPEN

Bit 7: IO port G clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CRCLPEN

Bit 12: CRC clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

FLITFLPEN

Bit 15: FLITF clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SRAMLPEN

Bit 16: SRAM clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DMA1LPEN

Bit 24: DMA1 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DMA2LPEN

Bit 25: DMA2 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

AESLPEN

Bit 27: AES clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

FSMCLPEN

Bit 30: FSMC clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB2LPENR

APB2 peripheral clock enable in low power mode register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1LPEN
rw 		SPI1LPEN
rw 		SDIOLPEN
rw 		ADC1LPEN
rw 		TIM11LPEN
rw 		TIM10LPEN
rw 		TIM9LPEN
rw 		SYSCFGLPEN
rw
Toggle fields

SYSCFGLPEN

Bit 0: System configuration controller clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM9LPEN

Bit 2: TIM9 timer clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM10LPEN

Bit 3: TIM10 timer clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM11LPEN

Bit 4: TIM11 timer clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

ADC1LPEN

Bit 9: ADC1 interface clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SDIOLPEN

Bit 11: SDIO clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI1LPEN

Bit 12: SPI 1 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART1LPEN

Bit 14: USART1 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

APB1LPENR

APB1 peripheral clock enable in low power mode register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMPLPEN
rw 		DACLPEN
rw 		PWRLPEN
rw 		USBLPEN
rw 		I2C2LPEN
rw 		I2C1LPEN
rw 		UART5LPEN
rw 		UART4LPEN
rw 		USART3LPEN
rw 		USART2LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3LPEN
rw 		SPI2LPEN
rw 		WWDGLPEN
rw 		LCDLPEN
rw 		TIM7LPEN
rw 		TIM6LPEN
rw 		TIM5LPEN
rw 		TIM4LPEN
rw 		TIM3LPEN
rw 		TIM2LPEN
rw
Toggle fields

TIM2LPEN

Bit 0: Timer 2 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM3LPEN

Bit 1: Timer 3 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM4LPEN

Bit 2: Timer 4 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM5LPEN

Bit 3: Timer 5 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM6LPEN

Bit 4: Timer 6 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

TIM7LPEN

Bit 5: Timer 7 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

LCDLPEN

Bit 9: LCD clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

WWDGLPEN

Bit 11: Window watchdog clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI2LPEN

Bit 14: SPI 2 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

SPI3LPEN

Bit 15: SPI 3 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART2LPEN

Bit 17: USART 2 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USART3LPEN

Bit 18: USART 3 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

UART4LPEN

Bit 19: USART 4 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

UART5LPEN

Bit 20: USART 5 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C1LPEN

Bit 21: I2C 1 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

I2C2LPEN

Bit 22: I2C 2 clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

USBLPEN

Bit 23: USB clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

PWRLPEN

Bit 28: Power interface clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

DACLPEN

Bit 29: DAC interface clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

COMPLPEN

Bit 31: COMP interface clock enable during Sleep mode.

Allowed values:
0: Disabled: Clock disabled
1: Enabled: Clock enabled

CSR

Control/status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

11/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRSTF
rw 		WWDGRSTF
rw 		IWDGRSTF
rw 		SFTRSTF
rw 		PORRSTF
rw 		PINRSTF
rw 		OBLRSTF
N/A 		RMVF
rw 		RTCRST
rw 		RTCEN
rw 		RTCSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSD
N/A 		LSECSSON
N/A 		LSEBYP
rw 		LSERDY
r 		LSEON
rw 		LSIRDY
r 		LSION
rw
Toggle fields

LSION

Bit 0: Internal low-speed oscillator enable.

LSIRDY

Bit 1: Internal low-speed oscillator ready.

LSEON

Bit 8: External low-speed oscillator enable.

LSERDY

Bit 9: External low-speed oscillator ready.

LSEBYP

Bit 10: External low-speed oscillator bypass.

LSECSSON

Bit 11: CSS on LSE enable.

LSECSSD

Bit 12: CSS on LSE failure Detection.

RTCSEL

Bits 16-17: RTC and LCD clock source selection.

RTCEN

Bit 22: RTC clock enable.

RTCRST

Bit 23: RTC software reset.

Allowed values:
1: Reset: Resets the RTC peripheral

RMVF

Bit 24: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

OBLRSTF

Bit 25: Options bytes loading reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PINRSTF

Bit 26: PIN reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PORRSTF

Bit 27: POR/PDR reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

IWDGRSTF

Bit 29: Independent watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

RI

0x40007c04: Routing interface

0/73 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4 ICR
0x8 ASCR1
0xc ASCR2
0x10 HYSCR1
0x14 HYSCR2
0x18 HYSCR3
0x1c HYSCR4
Toggle registers

ICR

RI input capture register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IC4
rw 		IC3
rw 		IC2
rw 		IC1
rw 		TIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4IOS
rw 		IC3IOS
rw 		IC2IOS
rw 		IC1IOS
rw
Toggle fields

IC1IOS

Bits 0-3: Input capture 1 select bits.

IC2IOS

Bits 4-7: Input capture 2 select bits.

IC3IOS

Bits 8-11: Input capture 3 select bits.

IC4IOS

Bits 12-15: Input capture 4 select bits.

TIM

Bits 16-17: Timer select bits.

IC1

Bit 18: IC1.

IC2

Bit 19: IC2.

IC3

Bit 20: IC3.

IC4

Bit 21: IC4.

ASCR1

RI analog switches control register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/31 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCM
rw 		CH30GR11_4
rw 		CH29GR11_3
rw 		CH28GR11_2
rw 		CH27GR11_1
rw 		VCOMP
rw 		CH25
rw 		CH24
rw 		CH23
rw 		CH22
rw 		CH21GR7_4
rw 		CH20GR7_3
rw 		CH19GR7_2
rw 		CH18GR7_1
rw 		CH31GR7_1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15GR9_2
rw 		CH14GR9_1
rw 		CH13GR8_4
rw 		CH12GR8_3
rw 		CH11GR8_2
rw 		CH10GR8_1
rw 		CH9GR3_2
rw 		CH8GR3_1
rw 		CH7GR2_2
rw 		CH6GR2_1
rw 		COMP1_SW1
rw 		CH31GR11_5
rw 		CH3GR1_4
rw 		CH2GR1_3
rw 		CH1GR1_2
rw 		CH0GR1_1
rw
Toggle fields

CH0GR1_1

Bit 0: Analog switch control.

CH1GR1_2

Bit 1: Analog switch control.

CH2GR1_3

Bit 2: Analog switch control.

CH3GR1_4

Bit 3: Analog switch control.

CH31GR11_5

Bit 4: Analog switch control.

COMP1_SW1

Bit 5: Comparator 1 analog switch.

CH6GR2_1

Bit 6: Analog switch control.

CH7GR2_2

Bit 7: Analog switch control.

CH8GR3_1

Bit 8: Analog switch control.

CH9GR3_2

Bit 9: Analog switch control.

CH10GR8_1

Bit 10: Analog switch control.

CH11GR8_2

Bit 11: Analog switch control.

CH12GR8_3

Bit 12: Analog switch control.

CH13GR8_4

Bit 13: Analog switch control.

CH14GR9_1

Bit 14: Analog switch control.

CH15GR9_2

Bit 15: Analog switch control.

CH31GR7_1

Bit 16: Analog switch control.

CH18GR7_1

Bit 18: Analog switch control.

CH19GR7_2

Bit 19: Analog switch control.

CH20GR7_3

Bit 20: Analog switch control.

CH21GR7_4

Bit 21: Analog switch control.

CH22

Bit 22: Analog I/O switch control of channel CH22.

CH23

Bit 23: Analog I/O switch control of channel CH23.

CH24

Bit 24: Analog I/O switch control of channel CH24.

CH25

Bit 25: Analog I/O switch control of channel CH25.

VCOMP

Bit 26: ADC analog switch selection for internal node to comparator 1.

CH27GR11_1

Bit 27: Analog switch control.

CH28GR11_2

Bit 28: Analog switch control.

CH29GR11_3

Bit 29: Analog switch control.

CH30GR11_4

Bit 30: Analog switch control.

SCM

Bit 31: Switch control mode.

ASCR2

RI analog switches control register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GR5_4
rw 		GR6_4
rw 		GR6_3
rw 		GR7_7
rw 		GR7_6
rw 		GR7_5
rw 		GR2_5
rw 		GR2_4
rw 		GR2_3
rw 		GR9_4
rw 		GR9_3
rw 		GR3_5
rw 		GR3_4
rw 		GR3_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GR4_3
rw 		GR4_2
rw 		GR4_1
rw 		GR5_3
rw 		GR5_2
rw 		GR5_1
rw 		GR6_2
rw 		GR6_1
rw 		GR10_4
rw 		GR10_3
rw 		GR10_2
rw 		GR10_1
rw
Toggle fields

GR10_1

Bit 0: GR10_1 analog switch control.

GR10_2

Bit 1: GR10_2 analog switch control.

GR10_3

Bit 2: GR10_3 analog switch control.

GR10_4

Bit 3: GR10_4 analog switch control.

GR6_1

Bit 4: GR6_1 analog switch control.

GR6_2

Bit 5: GR6_2 analog switch control.

GR5_1

Bit 6: GR5_1 analog switch control.

GR5_2

Bit 7: GR5_2 analog switch control.

GR5_3

Bit 8: GR5_3 analog switch control.

GR4_1

Bit 9: GR4_1 analog switch control.

GR4_2

Bit 10: GR4_2 analog switch control.

GR4_3

Bit 11: GR4_3 analog switch control.

GR3_3

Bit 16: GR3_3 analog switch control.

GR3_4

Bit 17: GR3_4 analog switch control.

GR3_5

Bit 18: GR3_5 analog switch control.

GR9_3

Bit 19: GR9_3 analog switch control.

GR9_4

Bit 20: GR9_4 analog switch control.

GR2_3

Bit 21: GR2_3 analog switch control.

GR2_4

Bit 22: GR2_4 analog switch control.

GR2_5

Bit 23: GR2_5 analog switch control.

GR7_5

Bit 24: GR7_5 analog switch control.

GR7_6

Bit 25: GR7_6 analog switch control.

GR7_7

Bit 26: GR7_7 analog switch control.

GR6_3

Bit 27: GR6_3 analog switch control.

GR6_4

Bit 28: GR6_4 analog switch control.

GR5_4

Bit 29: GR5_4 analog switch control.

HYSCR1

RI hysteresis control register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-15: Port A hysteresis control on/off.

PB

Bits 16-31: Port B hysteresis control on/off.

HYSCR2

RI hysteresis control register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC
rw
Toggle fields

PC

Bits 0-15: Port C hysteresis control on/off.

PD

Bits 16-31: Port D hysteresis control on/off.

HYSCR3

RI hysteresis control register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PE
rw
Toggle fields

PE

Bits 0-15: Port E hysteresis control on/off.

PF

Bits 16-31: Port F hysteresis control on/off.

HYSCR4

Hysteresis control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG
rw
Toggle fields

PG

Bits 0-15: Port G hysteresis control on/off.

RTC

0x40002800: Real-time clock

7/157 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 CR
0xc ISR
0x10 PRER
0x14 WUTR
0x18 CALIBR
0x1c ALRM[A]R
0x20 ALRM[B]R
0x24 WPR
0x28 SSR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x3c CALR
0x40 TAFCR
0x44 ALRM[A]SSR
0x48 ALRM[B]SSR
0x50 BKP[0]R
0x54 BKP[1]R
0x58 BKP[2]R
0x5c BKP[3]R
0x60 BKP[4]R
0x64 BKP[5]R
0x68 BKP[6]R
0x6c BKP[7]R
0x70 BKP[8]R
0x74 BKP[9]R
0x78 BKP[10]R
0x7c BKP[11]R
0x80 BKP[12]R
0x84 BKP[13]R
0x88 BKP[14]R
0x8c BKP[15]R
0x90 BKP[16]R
0x94 BKP[17]R
0x98 BKP[18]R
0x9c BKP[19]R
0xa0 BKP[20]R
0xa4 BKP[21]R
0xa8 BKP[22]R
0xac BKP[23]R
0xb0 BKP[24]R
0xb4 BKP[25]R
0xb8 BKP[26]R
0xbc BKP[27]R
0xc0 BKP[28]R
0xc4 BKP[29]R
0xc8 BKP[30]R
0xcc BKP[31]R
Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COE
rw 		OSEL
rw 		POL
rw 		COSEL
rw 		BKP
rw 		SUB1H
rw 		ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALRBIE
rw 		ALRAIE
rw 		TSE
rw 		WUTE
rw 		ALRBE
rw 		ALRAE
rw 		DCE
rw 		FMT
rw 		BYPSHAD
rw 		REFCKON
rw 		TSEDGE
rw 		WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection.

TSEDGE

Bit 3: Time-stamp event active edge.

REFCKON

Bit 4: Reference clock detection enable.

BYPSHAD

Bit 5: Bypass the shadow registers.

FMT

Bit 6: Hour format.

DCE

Bit 7: Coarse digital calibration enable.

ALRAE

Bit 8: Alarm A enable.

ALRBE

Bit 9: Alarm B enable.

WUTE

Bit 10: Wakeup timer enable.

TSE

Bit 11: Time stamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

ALRBIE

Bit 13: Alarm B interrupt enable.

WUTIE

Bit 14: Wakeup timer interrupt enable.

TSIE

Bit 15: Time-stamp interrupt enable.

ADD1H

Bit 16: Add 1 hour.

SUB1H

Bit 17: Subtract 1 hour.

BKP

Bit 18: Backup.

COSEL

Bit 19: Calibration output selection.

POL

Bit 20: Output polarity.

OSEL

Bits 21-22: Output selection.

COE

Bit 23: Calibration output enable.

ISR

initialization and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

5/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3F
rw 		TAMP2F
rw 		TAMP1F
rw 		TSOVF
rw 		TSF
rw 		WUTF
rw 		ALRBF
rw 		ALRAF
rw 		INIT
rw 		INITF
rw 		RSF
rw 		INITS
r 		SHPF
rw 		WUTWF
r 		ALRBWF
r 		ALRAWF
r
Toggle fields

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

ALRAF

Bit 8: Alarm A flag.

ALRBF

Bit 9: Alarm B flag.

WUTF

Bit 10: Wakeup timer flag.

TSF

Bit 11: Timestamp flag.

TSOVF

Bit 12: Timestamp overflow flag.

TAMP1F

Bit 13: Tamper detection flag.

TAMP2F

Bit 14: TAMPER2 detection flag.

TAMP3F

Bit 15: TAMPER3 detection flag.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

CALIBR

calibration register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCS
rw 		DC
rw
Toggle fields

DC

Bits 0-4: Digital calibration.

DCS

Bit 7: Digital calibration sign.

ALRM[A]R

Alarm A register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

ALRM[B]R

Alarm B register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

SSR

sub second register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value.

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: ADD1S.

TSTR

TSTR

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value.

CALR

calibration register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

CALW16

Bit 13: CALW16.

CALW8

Bit 14: Use a 16-second calibration cycle period.

CALP

Bit 15: Use an 8-second calibration cycle period.

TAFCR

tamper and alternate function configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALARMOUTTYPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw 		TAMPTS
rw 		TAMP3TRG
rw 		TAMP3E
rw 		TAMP2TRG
rw 		TAMP2E
rw 		TAMPIE
rw 		TAMP1ETRG
rw 		TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1ETRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP2E

Bit 3: Tamper 2 detection enable.

TAMP2TRG

Bit 4: Active level for tamper 2.

TAMP3E

Bit 5: TIMESTAMP mapping.

TAMP3TRG

Bit 6: TAMPER1 mapping.

TAMPTS

Bit 7: Activate timestamp on tamper detection event.

TAMPFREQ

Bits 8-10: Tamper sampling frequency.

TAMPFLT

Bits 11-12: Tamper filter count.

TAMPPRCH

Bits 13-14: Tamper precharge duration.

TAMPPUDIS

Bit 15: TAMPER pull-up disable.

ALARMOUTTYPE

Bit 18: AFO_ALARM output type.

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

BKP[0]R

backup register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[1]R

backup register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[2]R

backup register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[3]R

backup register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[4]R

backup register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[5]R

backup register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[6]R

backup register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[7]R

backup register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[8]R

backup register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[9]R

backup register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[10]R

backup register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[11]R

backup register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[12]R

backup register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[13]R

backup register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[14]R

backup register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[15]R

backup register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[16]R

backup register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[17]R

backup register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[18]R

backup register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[19]R

backup register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[20]R

backup register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[21]R

backup register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[22]R

backup register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[23]R

backup register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[24]R

backup register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[25]R

backup register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[26]R

backup register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[27]R

backup register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[28]R

backup register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[29]R

backup register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[30]R

backup register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[31]R

backup register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

SCB

0xe000ed00: System control block

5/74 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CPUID
0x4 ICSR
0x8 VTOR
0xc AIRCR
0x10 SCR
0x14 CCR
0x18 SHPR1
0x1c SHPR2
0x20 SHPR3
0x24 SHCRS
0x28 CFSR_UFSR_BFSR_MMFSR
0x2c HFSR
0x34 MMFAR
0x38 BFAR
Toggle registers

CPUID

CPUID base register

Offset: 0x0, size: 32, reset: 0x410FC241, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Implementer
r 		Variant
r 		Constant
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PartNo
r 		Revision
r
Toggle fields

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIPENDSET
rw 		PENDSVSET
rw 		PENDSVCLR
rw 		PENDSTSET
rw 		PENDSTCLR
rw 		ISRPENDING
rw 		VECTPENDING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTPENDING
rw 		RETTOBASE
rw 		VECTACTIVE
rw
Toggle fields

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBLOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBLOFF
rw
Toggle fields

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEYSTAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIANESS
rw 		PRIGROUP
rw 		SYSRESETREQ
rw 		VECTCLRACTIVE
rw 		VECTRESET
rw
Toggle fields

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEVEONPEND
rw 		SLEEPDEEP
rw 		SLEEPONEXIT
rw
Toggle fields

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKALIGN
rw 		BFHFNMIGN
rw 		DIV_0_TRP
rw 		UNALIGN__TRP
rw 		USERSETMPEND
rw 		NONBASETHRDENA
rw
Toggle fields

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_5
rw 		PRI_4
rw
Toggle fields

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_15
rw 		PRI_14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USGFAULTENA
rw 		BUSFAULTENA
rw 		MEMFAULTENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVCALLPENDED
rw 		BUSFAULTPENDED
rw 		MEMFAULTPENDED
rw 		USGFAULTPENDED
rw 		SYSTICKACT
rw 		PENDSVACT
rw 		MONITORACT
rw 		SVCALLACT
rw 		USGFAULTACT
rw 		BUSFAULTACT
rw 		MEMFAULTACT
rw
Toggle fields

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVBYZERO
rw 		UNALIGNED
rw 		NOCP
rw 		INVPC
rw 		INVSTATE
rw 		UNDEFINSTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFARVALID
rw 		LSPERR
rw 		STKERR
rw 		UNSTKERR
rw 		IMPRECISERR
rw 		PRECISERR
rw 		IBUSERR
rw 		MMARVALID
rw 		MLSPERR
rw 		MSTKERR
rw 		MUNSTKERR
rw 		DACCVIOL
rw 		IACCVIOL
rw
Toggle fields

IACCVIOL

Bit 0: IACCVIOL.

DACCVIOL

Bit 1: DACCVIOL.

MUNSTKERR

Bit 3: MUNSTKERR.

MSTKERR

Bit 4: MSTKERR.

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: MMARVALID.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUG_VT
rw 		FORCED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTTBL
rw
Toggle fields

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMFAR
rw
Toggle fields

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFAR
rw
Toggle fields

BFAR

Bits 0-31: Bus fault address.

SCB_ACTRL

0xe000e008: System control block ACTLR

0/4 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACTRL
Toggle registers

ACTRL

Auxiliary control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISITMATBFLUSH
rw 		DISRAMODE
rw 		FPEXCODIS
rw 		DISFOLD
rw
Toggle fields

DISFOLD

Bit 2: DISFOLD.

FPEXCODIS

Bit 10: FPEXCODIS.

DISRAMODE

Bit 11: DISRAMODE.

DISITMATBFLUSH

Bit 12: DISITMATBFLUSH.

SDIO

0x40012c00: Secure digital input/output interface

31/98 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARG
0xc CMD
0x10 RESPCMD
0x14 RESP1
0x18 RESP2
0x1c RESP3
0x20 RESP4
0x24 DTIMER
0x28 DLEN
0x2c DCTRL
0x30 DCOUNT
0x34 STA
0x38 ICR
0x3c MASK
0x48 FIFOCNT
0x80 FIFO
Toggle registers

POWER

power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: Power supply control bits..

CLKCR

SDI clock control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWFC_EN
rw 		NEGEDGE
rw 		WIDBUS
rw 		BYPASS
rw 		PWRSAV
rw 		CLKEN
rw 		CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-7: Clock divide factor.

CLKEN

Bit 8: Clock enable bit.

PWRSAV

Bit 9: Power saving configuration bit.

BYPASS

Bit 10: Clock divider bypass enable bit.

WIDBUS

Bits 11-12: Wide bus mode enable bit.

NEGEDGE

Bit 13: SDIO_CK dephasing selection bit.

HWFC_EN

Bit 14: HW Flow Control enable.

ARG

argument register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument.

CMD

command register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CE_ATACMD
rw 		nIEN
rw 		ENCMDcompl
rw 		SDIOSuspend
rw 		CPSMEN
rw 		WAITPEND
rw 		WAITINT
rw 		WAITRESP
rw 		CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: Command index.

WAITRESP

Bits 6-7: Wait for response bits.

WAITINT

Bit 8: CPSM waits for interrupt request.

WAITPEND

Bit 9: CPSM Waits for ends of data transfer (CmdPend internal signal)..

CPSMEN

Bit 10: Command path state machine (CPSM) Enable bit.

SDIOSuspend

Bit 11: SD I/O suspend command.

ENCMDcompl

Bit 12: Enable CMD completion.

nIEN

Bit 13: not Interrupt Enable.

CE_ATACMD

Bit 14: CE-ATA command.

RESPCMD

command response register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1

response 1..4 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: see Table 133..

RESP2

response 1..4 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: see Table 133..

RESP3

response 1..4 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: see Table 133..

RESP4

response 1..4 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: see Table 133..

DTIMER

data timer register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: Data timeout period.

DLEN

data length register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: Data length value.

DCTRL

data control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw 		RWMOD
rw 		RWSTOP
rw 		RWSTART
rw 		DBLOCKSIZE
rw 		DMAEN
rw 		DTMODE
rw 		DTDIR
rw 		DTEN
rw
Toggle fields

DTEN

Bit 0: Data transfer enabled bit.

DTDIR

Bit 1: Data transfer direction selection.

DTMODE

Bit 2: Data transfer mode selection 1: Stream or SDIO multibyte data transfer..

DMAEN

Bit 3: DMA enable bit.

DBLOCKSIZE

Bits 4-7: Data block size.

RWSTART

Bit 8: Read wait start.

RWSTOP

Bit 9: Read wait stop.

RWMOD

Bit 10: Read wait mode.

SDIOEN

Bit 11: SD I/O enable functions.

DCOUNT

data counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: Data count value.

STA

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAEND
r 		SDIOIT
r 		RXDAVL
r 		TXDAVL
r 		RXFIFOE
r 		TXFIFOE
r 		RXFIFOF
r 		TXFIFOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHF
r 		TXFIFOHE
r 		RXACT
r 		TXACT
r 		CMDACT
r 		DBCKEND
r 		STBITERR
r 		DATAEND
r 		CMDSENT
r 		CMDREND
r 		RXOVERR
r 		TXUNDERR
r 		DTIMEOUT
r 		CTIMEOUT
r 		DCRCFAIL
r 		CCRCFAIL
r
Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed).

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed).

CTIMEOUT

Bit 2: Command response timeout.

DTIMEOUT

Bit 3: Data timeout.

TXUNDERR

Bit 4: Transmit FIFO underrun error.

RXOVERR

Bit 5: Received FIFO overrun error.

CMDREND

Bit 6: Command response received (CRC check passed).

CMDSENT

Bit 7: Command sent (no response required).

DATAEND

Bit 8: Data end (data counter, SDIDCOUNT, is zero).

STBITERR

Bit 9: Start bit not detected on all data signals in wide bus mode.

DBCKEND

Bit 10: Data block sent/received (CRC check passed).

CMDACT

Bit 11: Command transfer in progress.

TXACT

Bit 12: Data transmit in progress.

RXACT

Bit 13: Data receive in progress.

TXFIFOHE

Bit 14: Transmit FIFO half empty: at least 8 words can be written into the FIFO.

RXFIFOHF

Bit 15: Receive FIFO half full: there are at least 8 words in the FIFO.

TXFIFOF

Bit 16: Transmit FIFO full.

RXFIFOF

Bit 17: Receive FIFO full.

TXFIFOE

Bit 18: Transmit FIFO empty.

RXFIFOE

Bit 19: Receive FIFO empty.

TXDAVL

Bit 20: Data available in transmit FIFO.

RXDAVL

Bit 21: Data available in receive FIFO.

SDIOIT

Bit 22: SDIO interrupt received.

CEATAEND

Bit 23: CE-ATA command completion signal received for CMD61.

ICR

interrupt clear register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDC
rw 		SDIOITC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBCKENDC
rw 		STBITERRC
rw 		DATAENDC
rw 		CMDSENTC
rw 		CMDRENDC
rw 		RXOVERRC
rw 		TXUNDERRC
rw 		DTIMEOUTC
rw 		CTIMEOUTC
rw 		DCRCFAILC
rw 		CCRCFAILC
rw
Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit.

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit.

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit.

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit.

TXUNDERRC

Bit 4: TXUNDERR flag clear bit.

RXOVERRC

Bit 5: RXOVERR flag clear bit.

CMDRENDC

Bit 6: CMDREND flag clear bit.

CMDSENTC

Bit 7: CMDSENT flag clear bit.

DATAENDC

Bit 8: DATAEND flag clear bit.

STBITERRC

Bit 9: STBITERR flag clear bit.

DBCKENDC

Bit 10: DBCKEND flag clear bit.

SDIOITC

Bit 22: SDIOIT flag clear bit.

CEATAENDC

Bit 23: CEATAEND flag clear bit.

MASK

mask register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDIE
rw 		SDIOITIE
rw 		RXDAVLIE
rw 		TXDAVLIE
rw 		RXFIFOEIE
rw 		TXFIFOEIE
rw 		RXFIFOFIE
rw 		TXFIFOFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHFIE
rw 		TXFIFOHEIE
rw 		RXACTIE
rw 		TXACTIE
rw 		CMDACTIE
rw 		DBCKENDIE
rw 		STBITERRIE
rw 		DATAENDIE
rw 		CMDSENTIE
rw 		CMDRENDIE
rw 		RXOVERRIE
rw 		TXUNDERRIE
rw 		DTIMEOUTIE
rw 		CTIMEOUTIE
rw 		DCRCFAILIE
rw 		CCRCFAILIE
rw
Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable.

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable.

CTIMEOUTIE

Bit 2: Command timeout interrupt enable.

DTIMEOUTIE

Bit 3: Data timeout interrupt enable.

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable.

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable.

CMDRENDIE

Bit 6: Command response received interrupt enable.

CMDSENTIE

Bit 7: Command sent interrupt enable.

DATAENDIE

Bit 8: Data end interrupt enable.

STBITERRIE

Bit 9: Start bit error interrupt enable.

DBCKENDIE

Bit 10: Data block end interrupt enable.

CMDACTIE

Bit 11: Command acting interrupt enable.

TXACTIE

Bit 12: Data transmit acting interrupt enable.

RXACTIE

Bit 13: Data receive acting interrupt enable.

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable.

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable.

TXFIFOFIE

Bit 16: Tx FIFO full interrupt enable.

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable.

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable.

RXFIFOEIE

Bit 19: Rx FIFO empty interrupt enable.

TXDAVLIE

Bit 20: Data available in Tx FIFO interrupt enable.

RXDAVLIE

Bit 21: Data available in Rx FIFO interrupt enable.

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable.

CEATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCOUNT
r
Toggle fields

FIFOCOUNT

Bits 0-23: Remaining number of words to be written to or read from the FIFO..

FIFO

data FIFO register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIF0Data
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIF0Data
rw
Toggle fields

FIF0Data

Bits 0-31: FIF0Data.

SPI1

0x40013000: Serial peripheral interface

46/46 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame Error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000002, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI2

0x40003800: Serial peripheral interface

46/46 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame Error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000002, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI3

0x40003c00: Serial peripheral interface

46/46 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
0x1c (16-bit) I2SCFGR
0x20 (16-bit) I2SPR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		UDR
r 		CHSIDE
r 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

FRE

Bit 8: Frame Error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

I2SCFGR

I2S configuration register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw 		I2SE
rw 		I2SCFG
rw 		PCMSYNC
rw 		I2SSTD
rw 		CKPOL
rw 		DATLEN
rw 		CHLEN
rw
Toggle fields

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, size: 16, reset: 0x00000002, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw 		ODD
rw 		I2SDIV
rw
Toggle fields

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 0x2-0xff

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

STK

0xe000e010: SysTick timer

0/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTRL
0x4 LOAD_
0x8 VAL
0xc CALIB
Toggle registers

CTRL

SysTick control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNTFLAG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSOURCE
rw 		TICKINT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD_

SysTick reload value register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOAD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT
rw
Toggle fields

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TENMS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TENMS
rw
Toggle fields

TENMS

Bits 0-23: Calibration value.

SYSCFG

0x40010000: System configuration controller

1/19 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MEMRMP
0x4 PMC
0x8 EXTICR1
0xc EXTICR2
0x10 EXTICR3
0x14 EXTICR4
Toggle registers

MEMRMP

memory remap register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_MODE
r 		MEM_MODE
rw
Toggle fields

MEM_MODE

Bits 0-1: MEM_MODE.

BOOT_MODE

Bits 8-9: BOOT_MODE.

PMC

peripheral mode configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USB_PU
rw
Toggle fields

USB_PU

Bit 0: USB pull-up.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw 		EXTI2
rw 		EXTI1
rw 		EXTI0
rw
Toggle fields

EXTI0

Bits 0-3: EXTI x configuration (x = 0 to 3).

EXTI1

Bits 4-7: EXTI x configuration (x = 0 to 3).

EXTI2

Bits 8-11: EXTI x configuration (x = 0 to 3).

EXTI3

Bits 12-15: EXTI x configuration (x = 0 to 3).

EXTICR2

external interrupt configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw 		EXTI6
rw 		EXTI5
rw 		EXTI4
rw
Toggle fields

EXTI4

Bits 0-3: EXTI x configuration (x = 4 to 7).

EXTI5

Bits 4-7: EXTI x configuration (x = 4 to 7).

EXTI6

Bits 8-11: EXTI x configuration (x = 4 to 7).

EXTI7

Bits 12-15: EXTI x configuration (x = 4 to 7).

EXTICR3

external interrupt configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw 		EXTI10
rw 		EXTI9
rw 		EXTI8
rw
Toggle fields

EXTI8

Bits 0-3: EXTI x configuration (x = 8 to 11).

EXTI9

Bits 4-7: EXTI x configuration (x = 8 to 11).

EXTI10

Bits 8-11: EXTI10.

EXTI11

Bits 12-15: EXTI x configuration (x = 8 to 11).

EXTICR4

external interrupt configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw 		EXTI14
rw 		EXTI13
rw 		EXTI12
rw
Toggle fields

EXTI12

Bits 0-3: EXTI12.

EXTI13

Bits 4-7: EXTI13.

EXTI14

Bits 8-11: EXTI14.

EXTI15

Bits 12-15: EXTI x configuration (x = 12 to 15).

TIM10

0x40010c00: General-purpose timers

11/28 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]G
rw 		UG
rw
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: TIM10 counter.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: TIM9 prescaler.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

OR

option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: TIM11 Input 1 remapping capability.

TIM11

0x40011000: General-purpose timers

11/28 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]G
rw 		UG
rw
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: TIM10 counter.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: TIM9 prescaler.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

OR

option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: TIM11 Input 1 remapping capability.

TIM2

0x40000000: General-purpose timers

77/101 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw 		CC[4]G
rw 		CC[3]G
rw 		CC[2]G
rw 		CC[1]G
rw 		UG
rw
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: TIM2 counter.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: TIM2 prescaler.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM3

0x40000400: General-purpose timers

77/101 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw 		CC[4]G
rw 		CC[3]G
rw 		CC[2]G
rw 		CC[1]G
rw 		UG
rw
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: TIM2 counter.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: TIM2 prescaler.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM4

0x40000800: General-purpose timers

77/101 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw 		CC[4]G
rw 		CC[3]G
rw 		CC[2]G
rw 		CC[1]G
rw 		UG
rw
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: TIM2 counter.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: TIM2 prescaler.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM5

0x40000c00: General-purpose timers

77/101 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		OCCS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw 		CC[4]G
rw 		CC[3]G
rw 		CC[2]G
rw 		CC[1]G
rw 		UG
rw
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: TIM2 counter.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: TIM2 prescaler.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM6

0x40001000: Basic timers

13/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

TIM6 control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

TIM6 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

TIM6 DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

TIM6 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

TIM6 event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

TIM6 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

PSC

TIM6 prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1)..

Allowed values: 0x0-0xffff

ARR

TIM6 auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

TIM7

0x40001400: Basic timers

13/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

TIM6 control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

TIM6 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

TIM6 DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

TIM6 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

TIM6 event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

TIM6 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

PSC

TIM6 prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1)..

Allowed values: 0x0-0xffff

ARR

TIM6 auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

TIM9

0x40010800: General-purpose timers

12/52 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw 		CC[2]G
rw 		CC[1]G
rw 		UG
rw
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

CC[2]G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

2/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: TIM9 counter.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: TIM9 prescaler.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

OR

option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: TIM9 Input 1 remapping capability.

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART4

0x40004c00: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART5

0x40005000: Universal synchronous asynchronous receiver transmitter

6/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SR
0x4 DR
0x8 BRR
0xc CR1
0x10 CR2
0x14 CR3
0x18 GTPR
Toggle registers

SR

Status register

Offset: 0x0, size: 32, reset: 0x00C00000, access: Unspecified

6/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw 		LBD
rw 		TXE
r 		TC
rw 		RXNE
rw 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-8: Data value.

BRR

Baud rate register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw 		DIV_Fraction
rw
Toggle fields

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

CR1

Control register 1

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		UE
rw 		M
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		RWU
rw 		SBK
rw
Toggle fields

SBK

Bit 0: Send break.

RWU

Bit 1: Receiver wakeup.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: TXE interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Wakeup method.

M

Bit 12: Word length.

UE

Bit 13: USART enable.

OVER8

Bit 15: Oversampling mode.

CR2

Control register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADD
rw
Toggle fields

ADD

Bits 0-3: Address of the USART node.

LBDL

Bit 5: lin break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

CR3

Control register 3

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

GTPR

Guard time and prescaler register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USB

0x40005c00: Universal serial bus full-speed device interface

63/111 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 EP0R
0x4 EP1R
0x8 EP2R
0xc EP3R
0x10 EP4R
0x14 EP5R
0x18 EP6R
0x1c EP7R
0x40 CNTR
0x44 ISTR
0x48 FNR
0x4c DADDR
0x50 BTABLE
Toggle registers

EP0R

endpoint 0 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP1R

endpoint 1 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP2R

endpoint 2 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP3R

endpoint 3 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP4R

endpoint 4 register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP5R

endpoint 5 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP6R

endpoint 6 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP7R

endpoint 7 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, size: 32, reset: 0x00000003, access: read-write

13/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRM
rw 		PMAOVRM
rw 		ERRM
rw 		WKUPM
rw 		SUSPM
rw 		RESETM
rw 		SOFM
rw 		ESOFM
rw 		RESUME
rw 		FSUSP
rw 		LPMODE
rw 		PDWN
rw 		FRES
rw
Toggle fields

FRES

Bit 0: Force USB Reset.

Allowed values:
0: NoReset: Clear USB reset
1: Reset: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB

PDWN

Bit 1: Power down.

Allowed values:
0: Disabled: No power down
1: Enabled: Enter power down mode

LPMODE

Bit 2: Low-power mode.

Allowed values:
0: Disabled: No low-power mode
1: Enabled: Enter low-power mode

FSUSP

Bit 3: Force suspend.

Allowed values:
0: NoEffect: No effect
1: Suspend: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected

RESUME

Bit 4: Resume request.

Allowed values:
1: Requested: Resume requested

ESOFM

Bit 8: Expected start of frame interrupt mask.

Allowed values:
0: Disabled: ESOF Interrupt disabled
1: Enabled: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

SOFM

Bit 9: Start of frame interrupt mask.

Allowed values:
0: Disabled: SOF Interrupt disabled
1: Enabled: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

RESETM

Bit 10: USB reset interrupt mask.

Allowed values:
0: Disabled: RESET Interrupt disabled
1: Enabled: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

SUSPM

Bit 11: Suspend mode interrupt mask.

Allowed values:
0: Disabled: Suspend Mode Request SUSP Interrupt disabled
1: Enabled: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

WKUPM

Bit 12: Wakeup interrupt mask.

Allowed values:
0: Disabled: WKUP Interrupt disabled
1: Enabled: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ERRM

Bit 13: Error interrupt mask.

Allowed values:
0: Disabled: ERR Interrupt disabled
1: Enabled: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

Allowed values:
0: Disabled: PMAOVR Interrupt disabled
1: Enabled: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

CTRM

Bit 15: Correct transfer interrupt mask.

Allowed values:
0: Disabled: Correct Transfer (CTR) Interrupt disabled
1: Enabled: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ISTR

interrupt status register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR
rw 		PMAOVR
rw 		ERR
rw 		WKUP
rw 		SUSP
rw 		RESET
rw 		SOF
rw 		ESOF
rw 		DIR
rw 		EP_ID
rw
Toggle fields

EP_ID

Bits 0-3: Endpoint Identifier.

Allowed values: 0x0-0xf

DIR

Bit 4: Direction of transaction.

Allowed values:
0: To: data transmitted by the USB peripheral to the host PC
1: From: data received by the USB peripheral from the host PC

ESOF

Bit 8: Expected start frame.

Allowed values:
0: NotExpectedStartOfFrame: NotExpectedStartOfFrame
1: ExpectedStartOfFrame: an SOF packet is expected but not received

SOF

Bit 9: start of frame.

Allowed values:
0: NotStartOfFrame: NotStartOfFrame
1: StartOfFrame: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus

RESET

Bit 10: reset request.

Allowed values:
0: NotReset: NotReset
1: Reset: peripheral detects an active USB RESET signal at its inputs

SUSP

Bit 11: Suspend mode request.

Allowed values:
0: NotSuspend: NotSuspend
1: Suspend: no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus

WKUP

Bit 12: Wakeup.

Allowed values:
0: NotWakeup: NotWakeup
1: Wakeup: activity is detected that wakes up the USB peripheral

ERR

Bit 13: Error.

Allowed values:
0: NotOverrun: Errors are not occurred
1: Error: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred

PMAOVR

Bit 14: Packet memory area over / underrun.

Allowed values:
0: NotOverrun: Overrun is not occurred
1: Overrun: microcontroller has not been able to respond in time to an USB memory request

CTR

Bit 15: Correct transfer.

Allowed values:
1: Completed: endpoint has successfully completed a transaction

FNR

frame number register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP
r 		RXDM
r 		LCK
r 		LSOF
r 		FN
r
Toggle fields

FN

Bits 0-10: Frame number.

Allowed values: 0x0-0x7ff

LSOF

Bits 11-12: Lost SOF.

Allowed values: 0x0-0x3

LCK

Bit 13: Locked.

Allowed values:
1: Locked: the frame timer remains in this state until an USB reset or USB suspend event occurs

RXDM

Bit 14: Receive data - line status.

Allowed values:
1: Received: received data minus upstream port data line

RXDP

Bit 15: Receive data + line status.

Allowed values:
1: Received: received data plus upstream port data line

DADDR

device address

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
rw 		ADD
rw
Toggle fields

ADD

Bits 0-6: Device address.

Allowed values: 0x0-0x7f

EF

Bit 7: Enable function.

Allowed values:
0: Disabled: USB device disabled
1: Enabled: USB device enabled

BTABLE

Buffer table address

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTABLE
rw
Toggle fields

BTABLE

Bits 3-15: Buffer table.

Allowed values: 0x0-0x1fff

USB_SRAM

0x40006000: Universal serial bus full-speed device interface

63/111 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 EP0R
0x4 EP1R
0x8 EP2R
0xc EP3R
0x10 EP4R
0x14 EP5R
0x18 EP6R
0x1c EP7R
0x40 CNTR
0x44 ISTR
0x48 FNR
0x4c DADDR
0x50 BTABLE
Toggle registers

EP0R

endpoint 0 register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP1R

endpoint 1 register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP2R

endpoint 2 register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP3R

endpoint 3 register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP4R

endpoint 4 register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP5R

endpoint 5 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP6R

endpoint 6 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP7R

endpoint 7 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

Allowed values: 0x0-0xf

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, size: 32, reset: 0x00000003, access: read-write

13/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRM
rw 		PMAOVRM
rw 		ERRM
rw 		WKUPM
rw 		SUSPM
rw 		RESETM
rw 		SOFM
rw 		ESOFM
rw 		RESUME
rw 		FSUSP
rw 		LPMODE
rw 		PDWN
rw 		FRES
rw
Toggle fields

FRES

Bit 0: Force USB Reset.

Allowed values:
0: NoReset: Clear USB reset
1: Reset: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB

PDWN

Bit 1: Power down.

Allowed values:
0: Disabled: No power down
1: Enabled: Enter power down mode

LPMODE

Bit 2: Low-power mode.

Allowed values:
0: Disabled: No low-power mode
1: Enabled: Enter low-power mode

FSUSP

Bit 3: Force suspend.

Allowed values:
0: NoEffect: No effect
1: Suspend: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected

RESUME

Bit 4: Resume request.

Allowed values:
1: Requested: Resume requested

ESOFM

Bit 8: Expected start of frame interrupt mask.

Allowed values:
0: Disabled: ESOF Interrupt disabled
1: Enabled: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

SOFM

Bit 9: Start of frame interrupt mask.

Allowed values:
0: Disabled: SOF Interrupt disabled
1: Enabled: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

RESETM

Bit 10: USB reset interrupt mask.

Allowed values:
0: Disabled: RESET Interrupt disabled
1: Enabled: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

SUSPM

Bit 11: Suspend mode interrupt mask.

Allowed values:
0: Disabled: Suspend Mode Request SUSP Interrupt disabled
1: Enabled: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

WKUPM

Bit 12: Wakeup interrupt mask.

Allowed values:
0: Disabled: WKUP Interrupt disabled
1: Enabled: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ERRM

Bit 13: Error interrupt mask.

Allowed values:
0: Disabled: ERR Interrupt disabled
1: Enabled: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

Allowed values:
0: Disabled: PMAOVR Interrupt disabled
1: Enabled: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

CTRM

Bit 15: Correct transfer interrupt mask.

Allowed values:
0: Disabled: Correct Transfer (CTR) Interrupt disabled
1: Enabled: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ISTR

interrupt status register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR
rw 		PMAOVR
rw 		ERR
rw 		WKUP
rw 		SUSP
rw 		RESET
rw 		SOF
rw 		ESOF
rw 		DIR
rw 		EP_ID
rw
Toggle fields

EP_ID

Bits 0-3: Endpoint Identifier.

Allowed values: 0x0-0xf

DIR

Bit 4: Direction of transaction.

Allowed values:
0: To: data transmitted by the USB peripheral to the host PC
1: From: data received by the USB peripheral from the host PC

ESOF

Bit 8: Expected start frame.

Allowed values:
0: NotExpectedStartOfFrame: NotExpectedStartOfFrame
1: ExpectedStartOfFrame: an SOF packet is expected but not received

SOF

Bit 9: start of frame.

Allowed values:
0: NotStartOfFrame: NotStartOfFrame
1: StartOfFrame: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus

RESET

Bit 10: reset request.

Allowed values:
0: NotReset: NotReset
1: Reset: peripheral detects an active USB RESET signal at its inputs

SUSP

Bit 11: Suspend mode request.

Allowed values:
0: NotSuspend: NotSuspend
1: Suspend: no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus

WKUP

Bit 12: Wakeup.

Allowed values:
0: NotWakeup: NotWakeup
1: Wakeup: activity is detected that wakes up the USB peripheral

ERR

Bit 13: Error.

Allowed values:
0: NotOverrun: Errors are not occurred
1: Error: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred

PMAOVR

Bit 14: Packet memory area over / underrun.

Allowed values:
0: NotOverrun: Overrun is not occurred
1: Overrun: microcontroller has not been able to respond in time to an USB memory request

CTR

Bit 15: Correct transfer.

Allowed values:
1: Completed: endpoint has successfully completed a transaction

FNR

frame number register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP
r 		RXDM
r 		LCK
r 		LSOF
r 		FN
r
Toggle fields

FN

Bits 0-10: Frame number.

Allowed values: 0x0-0x7ff

LSOF

Bits 11-12: Lost SOF.

Allowed values: 0x0-0x3

LCK

Bit 13: Locked.

Allowed values:
1: Locked: the frame timer remains in this state until an USB reset or USB suspend event occurs

RXDM

Bit 14: Receive data - line status.

Allowed values:
1: Received: received data minus upstream port data line

RXDP

Bit 15: Receive data + line status.

Allowed values:
1: Received: received data plus upstream port data line

DADDR

device address

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
rw 		ADD
rw
Toggle fields

ADD

Bits 0-6: Device address.

Allowed values: 0x0-0x7f

EF

Bit 7: Enable function.

Allowed values:
0: Disabled: USB device disabled
1: Enabled: USB device enabled

BTABLE

Buffer table address

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTABLE
rw
Toggle fields

BTABLE

Bits 3-15: Buffer table.

Allowed values: 0x0-0x1fff

WWDG

0x40002c00: Window watchdog

6/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFR
0x8 SR
Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: Unspecified

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
w 		T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

Allowed values: 0x0-0x7f

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: Unspecified

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
w 		WDGTB
N/A 		W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

Allowed values: 0x0-0x7f

WDGTB

Bits 7-8: Timer base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWI

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

SR

SR

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle fields

EWIF

Bit 0: EWIF.

Allowed values:
0: Finished: The EWI Interrupt Service Routine has been serviced
1: Pending: The EWI Interrupt Service Routine has been triggered