ADRDY

Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase..

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it..

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it..

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it..

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to Section 16.4.21: Queue of context for injected conversions for more information..

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDYIE

Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

ADEN

Bit 0: ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator).

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion starts immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) Note: In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN[1:0], a conversion starts immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). Note: In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)..

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) Note: In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to Section 16.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

DEEPPWD

Bit 29: Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

ADCALDIF

Bit 30: Differential mode for calibration This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. Note: The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing).

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

DMAEN

Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to Section : Managing conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the ADCx_CCR register..

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing conversions using the DMA Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the ADCx_CCR register..

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

DFSDMCFG

Bit 2: DFSDM mode configuration This bit is set and cleared by software to enable the DFSDM mode. It is effective only when DMAEN = 0. Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0..

RES

Bits 3-4: Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

ALIGN

Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN) Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-9: External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

EXTEN

Bits 10-11: External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC..

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC..

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. Note: It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC..

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC..

Allowed values: 0x0-0x7

JDISCEN

Bit 20: Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Note: When dual mode is enabled (bits DUAL of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC..

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to Section 16.4.21: Queue of context for injected conversions for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC..

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC..

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0x13

JQDIS

Bit 31: Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). Note: A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared..

ROVSE

Bit 0: Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

JOVSE

Bit 1: Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

OVSR

Bits 2-4: Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

OVSS

Bits 5-8: Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

TROVS

Bit 9: Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[4]

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[5]

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[6]

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[7]

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[8]

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[9]

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMPPLUS

Bit 31: Addition of one clock cycle to the sampling time To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0..

Allowed values:
0: KeepCycles: The sampling time remains set to 2.5 ADC clock cycles remains
1: Add1Cycle: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers

SMP[10]

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[11]

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[12]

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[13]

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[14]

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[15]

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[16]

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[17]

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[18]

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

LT1

Bits 0-11: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to Section 16.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0xfff

HT1

Bits 16-27: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to Section 16.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0xfff

LT2

Bits 0-7: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to Section 16.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0xff

HT2

Bits 16-23: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to Section 16.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0xff

LT3

Bits 0-7: Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0xff

HT3

Bits 16-23: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to Section 16.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0xff

L

Bits 0-3: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values: 0x0-0xf

SQ[1]

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[2]

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[3]

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[4]

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[5]

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[6]

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[7]

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[8]

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[9]

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[10]

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[11]

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[12]

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[13]

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[14]

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[15]

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[16]

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

RDATA

Bits 0-15: Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in Section 16.4.26: Data management..

Allowed values: 0x0-0xffff

JL

Bits 0-1: Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-5: External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

JEXTEN

Bits 6-7: External Trigger Enable and Polarity Selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Section 16.4.21: Queue of context for injected conversions).

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ[1]

Bits 8-12: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[2]

Bits 14-18: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[3]

Bits 20-24: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[4]

Bits 26-30: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

OFFSET

Bits 0-11: Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Note: Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is subtracted when converting channel 4..

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the data offset y..

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFFSET

Bits 0-11: Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Note: Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is subtracted when converting channel 4..

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the data offset y..

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFFSET

Bits 0-11: Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Note: Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is subtracted when converting channel 4..

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the data offset y..

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFFSET

Bits 0-11: Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Note: Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is subtracted when converting channel 4..

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the data offset y..

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

JDATA

Bits 0-15: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 16.4.26: Data management..

Allowed values: 0x0-0xffff

JDATA

Bits 0-15: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 16.4.26: Data management..

Allowed values: 0x0-0xffff

JDATA

Bits 0-15: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 16.4.26: Data management..

Allowed values: 0x0-0xffff

JDATA

Bits 0-15: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in Section 16.4.26: Data management..

Allowed values: 0x0-0xffff

AWD2CH[0]

Bit 0: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[1]

Bit 1: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[2]

Bit 2: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[3]

Bit 3: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[4]

Bit 4: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[5]

Bit 5: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[6]

Bit 6: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[7]

Bit 7: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[8]

Bit 8: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[9]

Bit 9: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[10]

Bit 10: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[11]

Bit 11: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[12]

Bit 12: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[13]

Bit 13: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[14]

Bit 14: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[15]

Bit 15: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[16]

Bit 16: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[17]

Bit 17: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[18]

Bit 18: Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[0]

Bit 0: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[1]

Bit 1: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[2]

Bit 2: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[3]

Bit 3: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[4]

Bit 4: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[5]

Bit 5: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[6]

Bit 6: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[7]

Bit 7: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[8]

Bit 8: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[9]

Bit 9: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[10]

Bit 10: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[11]

Bit 11: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[12]

Bit 12: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[13]

Bit 13: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[14]

Bit 14: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[15]

Bit 15: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[16]

Bit 16: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[17]

Bit 17: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[18]

Bit 18: Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: Some channels are not connected physically and must not be selected for the analog watchdog..

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

DIFSEL[0]

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[1]

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[2]

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[3]

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[4]

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[5]

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[6]

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[7]

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[8]

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[9]

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[10]

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[11]

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[12]

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[13]

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[14]

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[15]

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[16]

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[17]

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[18]

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT_S

Bits 0-6: Calibration Factors In single-ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)..

Allowed values: 0x0-0x7f

CALFACT_D

Bits 16-22: Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)..

Allowed values: 0x0-0x7f

ADRDY_MST

Bit 0: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register..

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_MST

Bit 1: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register..

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_MST

Bit 2: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register..

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_MST

Bit 3: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register..

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_MST

Bit 4: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register..

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_MST

Bit 5: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register..

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_MST

Bit 6: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register..

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_MST

Bit 7: Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register..

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_MST

Bit 8: Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register..

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_MST

Bit 9: Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register..

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_MST

Bit 10: Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register..

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDY_SLV

Bit 16: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register..

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_SLV

Bit 17: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register..

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_SLV

Bit 18: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register..

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_SLV

Bit 19: End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register..

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_SLV

Bit 20: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register..

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_SLV

Bit 21: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register..

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_SLV

Bit 22: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register..

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_SLV

Bit 23: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register..

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_SLV

Bit 24: Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register..

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_SLV

Bit 25: Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register..

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_SLV

Bit 26: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register..

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

DUAL

Bits 0-4: Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs independent: 00001 to 01001: Dual mode, master and slave ADCs working together All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

DELAY

Bits 8-11: Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 112 for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values: 0x0-0xf

DMACFG

Bit 13: DMA configuration (for dual ADC mode) This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing conversions using the DMA Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

MDMA

Bits 14-15: Direct memory access mode for dual ADC mode This bitfield is set and cleared by software. Refer to the DMA controller section for more details. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

CKMODE

Bits 16-17: ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

PRESC

Bits 18-21: ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 00..

VREFEN

Bit 22: V_REFINT enable This bit is set and cleared by software to enable/disable the V_REFINT channel..

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

CH17SEL

Bit 23: CH17 selection This bit is set and cleared by software to control channel 17..

CH18SEL

Bit 24: CH18 selection This bit is set and cleared by software to control channel 18..

RDATA_MST

Bits 0-15: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to Section 16.4.32: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)) In MDMA = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]..

RDATA_SLV

Bits 16-31: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 16.4.32: Dual ADC modes. The data alignment is applied as described in Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)).

ADRDY

Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase..

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it..

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it..

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it..

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to Section 16.4.21: Queue of context for injected conversions for more information..

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDYIE

Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

ADEN

Bit 0: ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator).

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion starts immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) Note: In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN[1:0], a conversion starts immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). Note: In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)..

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) Note: In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to Section 16.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

DEEPPWD

Bit 29: Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

ADCALDIF

Bit 30: Differential mode for calibration This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)..

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. Note: The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing).

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

DMAEN

Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to Section : Managing conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the ADCx_CCR register..

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing conversions using the DMA Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the ADCx_CCR register..

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

DFSDMCFG

Bit 2: DFSDM mode configuration This bit is set and cleared by software to enable the DFSDM mode. It is effective only when DMAEN = 0. Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0..

RES

Bits 3-4: Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

ALIGN

Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN) Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-9: External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

EXTEN

Bits 10-11: External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC..

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC..

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. Note: It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC..

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC..

Allowed values: 0x0-0x7

JDISCEN

Bit 20: Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Note: When dual mode is enabled (bits DUAL of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC..

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to Section 16.4.21: Queue of context for injected conversions for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC..

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)..

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC..

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values: 0x0-0x13

JQDIS

Bit 31: Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). Note: A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared..

ROVSE

Bit 0: Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

JOVSE

Bit 1: Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

OVSR

Bits 2-4: Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

OVSS

Bits 5-8: Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

TROVS

Bit 9: Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)..

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles