0x50040000: Analog-to-Digital Converter
179/180 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ISR | ||||||||||||||||||||||||||||||||
0x4 | IER | ||||||||||||||||||||||||||||||||
0x8 | CR | ||||||||||||||||||||||||||||||||
0xc | CFGR | ||||||||||||||||||||||||||||||||
0x10 | CFGR2 | ||||||||||||||||||||||||||||||||
0x14 | SMPR1 | ||||||||||||||||||||||||||||||||
0x18 | SMPR2 | ||||||||||||||||||||||||||||||||
0x20 | TR1 | ||||||||||||||||||||||||||||||||
0x24 | TR2 | ||||||||||||||||||||||||||||||||
0x28 | TR3 | ||||||||||||||||||||||||||||||||
0x30 | SQR1 | ||||||||||||||||||||||||||||||||
0x34 | SQR2 | ||||||||||||||||||||||||||||||||
0x38 | SQR3 | ||||||||||||||||||||||||||||||||
0x3c | SQR4 | ||||||||||||||||||||||||||||||||
0x40 | DR | ||||||||||||||||||||||||||||||||
0x4c | JSQR | ||||||||||||||||||||||||||||||||
0x60 | OFR[1] | ||||||||||||||||||||||||||||||||
0x64 | OFR[2] | ||||||||||||||||||||||||||||||||
0x68 | OFR[3] | ||||||||||||||||||||||||||||||||
0x6c | OFR[4] | ||||||||||||||||||||||||||||||||
0x80 | JDR[1] | ||||||||||||||||||||||||||||||||
0x84 | JDR[2] | ||||||||||||||||||||||||||||||||
0x88 | JDR[3] | ||||||||||||||||||||||||||||||||
0x8c | JDR[4] | ||||||||||||||||||||||||||||||||
0xa0 | AWD2CR | ||||||||||||||||||||||||||||||||
0xa4 | AWD3CR | ||||||||||||||||||||||||||||||||
0xb0 | DIFSEL | ||||||||||||||||||||||||||||||||
0xb4 | CALFACT |
interrupt and status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JQOVF
r/w1c |
AWD[3]
r/w1c |
AWD[2]
r/w1c |
AWD[1]
r/w1c |
JEOS
r/w1c |
JEOC
r/w1c |
OVR
r/w1c |
EOS
r/w1c |
EOC
r/w1c |
EOSMP
r/w1c |
ADRDY
r/w1c |
Bit 0: ADRDY.
Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion
Bit 1: EOSMP.
Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached
Bit 2: EOC.
Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete
Bit 3: EOS.
Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete
Bit 4: OVR.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 5: JEOC.
Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete
Bit 6: JEOS.
Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete
Bit 7: Analog watchdog 1 flag.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 8: Analog watchdog 2 flag.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 9: Analog watchdog 3 flag.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 10: JQOVF.
Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred
interrupt enable register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JQOVFIE
rw |
AWD[3]IE
rw |
AWD[2]IE
rw |
AWD[1]IE
rw |
JEOSIE
rw |
JEOCIE
rw |
OVRIE
rw |
EOSIE
rw |
EOCIE
rw |
EOSMPIE
rw |
ADRDYIE
rw |
Bit 0: ADRDYIE.
Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled
Bit 1: EOSMPIE.
Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled
Bit 2: EOCIE.
Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled
Bit 3: EOSIE.
Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled
Bit 4: OVRIE.
Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled
Bit 5: JEOCIE.
Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled
Bit 6: JEOSIE.
Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled
Bit 7: Analog watchdog 1 interrupt enable.
Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled
Bit 8: Analog watchdog 2 interrupt enable.
Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled
Bit 9: Analog watchdog 3 interrupt enable.
Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled
Bit 10: JQOVFIE.
Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled
control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADCAL
r/w1s |
ADCALDIF
rw |
DEEPPWD
rw |
ADVREGEN
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JADSTP
r/w1s |
ADSTP
r/w1s |
JADSTART
r/w1s |
ADSTART
r/w1s |
ADDIS
r/w1s |
ADEN
r/w1s |
Bit 0: ADEN.
Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled
Bit 1: ADDIS.
Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling
Bit 2: ADSTART.
Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting
Bit 3: JADSTART.
Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting
Bit 4: ADSTP.
Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion
Bit 5: JADSTP.
Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion
Bit 28: ADVREGEN.
Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled
Bit 29: DEEPPWD.
Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)
Bit 30: ADCALDIF.
Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode
Bit 31: ADCAL.
Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress
configuration register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
18/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JQDIS
rw |
AWD1CH
rw |
JAUTO
rw |
JAWD1EN
rw |
AWD1EN
rw |
AWD1SGL
rw |
JQM
rw |
JDISCEN
rw |
DISCNUM
rw |
DISCEN
rw |
||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTDLY
rw |
CONT
rw |
OVRMOD
rw |
EXTEN
rw |
EXTSEL
rw |
ALIGN
rw |
RES
rw |
DMACFG
rw |
DMAEN
rw |
Bit 0: DMAEN.
Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled
Bit 1: DMACFG.
Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected
Bits 3-4: RES.
Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit
Bit 5: ALIGN.
Allowed values:
0: Right: Right alignment
1: Left: Left alignment
Bits 6-9: EXTSEL.
Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event
Bits 10-11: EXTEN.
Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges
Bit 12: OVRMOD.
Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected
Bit 13: CONT.
Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode
Bit 14: AUTDLY.
Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on
Bit 16: DISCEN.
Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled
Bits 17-19: DISCNUM.
Allowed values: 0x0-0x7
Bit 20: JDISCEN.
Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled
Bit 21: JQM.
Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence
Bit 22: AWD1SGL.
Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH
Bit 23: AWD1EN.
Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels
Bit 24: JAWD1EN.
Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels
Bit 25: JAUTO.
Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled
Bits 26-30: AWDCH1CH.
Allowed values: 0x0-0x12
Bit 31: Injected Queue disable.
configuration register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
Bit 0: DMAEN.
Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled
Bit 1: DMACFG.
Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled
Bits 2-4: RES.
Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x
Bits 5-8: ALIGN.
Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit
Bit 9: Triggered Regular Oversampling.
Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger
Bit 10: EXTEN.
Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)
sample time register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SMPPLUS
rw |
SMP[9]
rw |
SMP[8]
rw |
SMP[7]
rw |
SMP[6]
rw |
SMP[5]
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SMP[5]
rw |
SMP[4]
rw |
SMP[3]
rw |
SMP[2]
rw |
SMP[1]
rw |
SMP[0]
rw |
Bits 0-2: Channel 0 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 3-5: Channel 1 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 6-8: Channel 2 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 9-11: Channel 3 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 12-14: Channel 4 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 15-17: Channel 5 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 18-20: Channel 6 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 21-23: Channel 7 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 24-26: Channel 8 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 27-29: Channel 9 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bit 31: Addition of one clock cycle to the sampling time.
Allowed values:
0: KeepCycles: The sampling time remains set to 2.5 ADC clock cycles remains
1: Add1Cycle: 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers
sample time register 2
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SMP[18]
rw |
SMP[17]
rw |
SMP[16]
rw |
SMP[15]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SMP[15]
rw |
SMP[14]
rw |
SMP[13]
rw |
SMP[12]
rw |
SMP[11]
rw |
SMP[10]
rw |
Bits 0-2: Channel 10 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 3-5: Channel 11 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 6-8: Channel 12 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 9-11: Channel 13 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 12-14: Channel 14 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 15-17: Channel 15 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 18-20: Channel 16 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 21-23: Channel 17 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
Bits 24-26: Channel 18 sample time selection.
Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles
watchdog threshold register 1
Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
watchdog threshold register
Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
watchdog threshold register 3
Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write
2/2 fields covered.
regular sequence register 1
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SQ[4]
rw |
SQ[3]
rw |
SQ[2]
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SQ[2]
rw |
SQ[1]
rw |
L
rw |
Bits 0-3: Regular channel sequence length.
Allowed values: 0x0-0xf
Bits 6-10: 1 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 12-16: 2 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 18-22: 3 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 24-28: 4 conversion in regular sequence.
Allowed values: 0x0-0x12
regular sequence register 2
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SQ[9]
rw |
SQ[8]
rw |
SQ[7]
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SQ[7]
rw |
SQ[6]
rw |
SQ[5]
rw |
Bits 0-4: 5 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 6-10: 6 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 12-16: 7 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 18-22: 8 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 24-28: 9 conversion in regular sequence.
Allowed values: 0x0-0x12
regular sequence register 3
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SQ[14]
rw |
SQ[13]
rw |
SQ[12]
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SQ[12]
rw |
SQ[11]
rw |
SQ[10]
rw |
Bits 0-4: 10 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 6-10: 11 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 12-16: 12 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 18-22: 13 conversion in regular sequence.
Allowed values: 0x0-0x12
Bits 24-28: 14 conversion in regular sequence.
Allowed values: 0x0-0x12
regular sequence register 4
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
regular Data Register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDATA
r |
injected sequence register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JSQ[4]
rw |
JSQ[3]
rw |
JSQ[2]
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JSQ[2]
rw |
JSQ[1]
rw |
JEXTEN
rw |
JEXTSEL
rw |
JL
rw |
Bits 0-1: JL.
Allowed values: 0x0-0x3
Bits 2-5: JEXTSEL.
Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event
Bits 6-7: JEXTEN.
Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges
Bits 8-12: 1 conversion in injected sequence.
Allowed values: 0x0-0x13
Bits 14-18: 2 conversion in injected sequence.
Allowed values: 0x0-0x13
Bits 20-24: 3 conversion in injected sequence.
Allowed values: 0x0-0x13
Bits 26-30: 4 conversion in injected sequence.
Allowed values: 0x0-0x13
offset register 1
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OFFSET_EN
rw |
OFFSET_CH
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET
rw |
Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.
Allowed values: 0x0-0xfff
Bits 26-30: Channel selection for the data offset X.
Allowed values: 0x0-0x1f
Bit 31: Offset X Enable.
Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
offset register 2
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OFFSET_EN
rw |
OFFSET_CH
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET
rw |
Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.
Allowed values: 0x0-0xfff
Bits 26-30: Channel selection for the data offset X.
Allowed values: 0x0-0x1f
Bit 31: Offset X Enable.
Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
offset register 3
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OFFSET_EN
rw |
OFFSET_CH
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET
rw |
Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.
Allowed values: 0x0-0xfff
Bits 26-30: Channel selection for the data offset X.
Allowed values: 0x0-0x1f
Bit 31: Offset X Enable.
Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
offset register 4
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OFFSET_EN
rw |
OFFSET_CH
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET
rw |
Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.
Allowed values: 0x0-0xfff
Bits 26-30: Channel selection for the data offset X.
Allowed values: 0x0-0x1f
Bit 31: Offset X Enable.
Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
injected data register 1
Offset: 0x80, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JDATA
r |
injected data register 2
Offset: 0x84, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JDATA
r |
injected data register 3
Offset: 0x88, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JDATA
r |
injected data register 4
Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JDATA
r |
Analog Watchdog 2 Configuration Register
Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write
18/18 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWD2CH[17]
rw |
AWD2CH[16]
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AWD2CH[15]
rw |
AWD2CH[14]
rw |
AWD2CH[13]
rw |
AWD2CH[12]
rw |
AWD2CH[11]
rw |
AWD2CH[10]
rw |
AWD2CH[9]
rw |
AWD2CH[8]
rw |
AWD2CH[7]
rw |
AWD2CH[6]
rw |
AWD2CH[5]
rw |
AWD2CH[4]
rw |
AWD2CH[3]
rw |
AWD2CH[2]
rw |
AWD2CH[1]
rw |
AWD2CH[0]
rw |
Bit 0: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 1: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 2: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 3: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 4: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 5: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 6: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 7: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 8: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 9: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 10: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 11: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 12: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 13: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 14: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 15: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 16: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 17: AWD2CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Analog Watchdog 3 Configuration Register
Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write
18/18 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWD3CH[17]
rw |
AWD3CH[16]
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AWD3CH[15]
rw |
AWD3CH[14]
rw |
AWD3CH[13]
rw |
AWD3CH[12]
rw |
AWD3CH[11]
rw |
AWD3CH[10]
rw |
AWD3CH[9]
rw |
AWD3CH[8]
rw |
AWD3CH[7]
rw |
AWD3CH[6]
rw |
AWD3CH[5]
rw |
AWD3CH[4]
rw |
AWD3CH[3]
rw |
AWD3CH[2]
rw |
AWD3CH[1]
rw |
AWD3CH[0]
rw |
Bit 0: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 1: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 2: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 3: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 4: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 5: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 6: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 7: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 8: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 9: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 10: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 11: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 12: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 13: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 14: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 15: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 16: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Bit 17: AWD3CH.
Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx
Differential Mode Selection Register 2
Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified
18/18 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIFSEL[17]
N/A |
DIFSEL[16]
N/A |
DIFSEL[15]
N/A |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFSEL[14]
N/A |
DIFSEL[13]
N/A |
DIFSEL[12]
N/A |
DIFSEL[11]
N/A |
DIFSEL[10]
N/A |
DIFSEL[9]
N/A |
DIFSEL[8]
N/A |
DIFSEL[7]
N/A |
DIFSEL[6]
N/A |
DIFSEL[5]
N/A |
DIFSEL[4]
N/A |
DIFSEL[3]
N/A |
DIFSEL[2]
N/A |
DIFSEL[1]
N/A |
DIFSEL[0]
N/A |
Bit 1: Differential mode for channel 0.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 2: Differential mode for channel 1.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 3: Differential mode for channel 2.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 4: Differential mode for channel 3.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 5: Differential mode for channel 4.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 6: Differential mode for channel 5.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 7: Differential mode for channel 6.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 8: Differential mode for channel 7.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 9: Differential mode for channel 8.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 10: Differential mode for channel 9.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 11: Differential mode for channel 10.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 12: Differential mode for channel 11.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 13: Differential mode for channel 12.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 14: Differential mode for channel 13.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 15: Differential mode for channel 14.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 16: Differential mode for channel 15.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 17: Differential mode for channel 16.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
Bit 18: Differential mode for channel 17.
Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode
0x50040300: Analog-to-Digital Converter
33/33 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CSR | ||||||||||||||||||||||||||||||||
0x8 | CCR | ||||||||||||||||||||||||||||||||
0xc | CDR |
ADC Common status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
22/22 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JQOVF_SLV
r |
AWD3_SLV
r |
AWD2_SLV
r |
AWD1_SLV
r |
JEOS_SLV
r |
JEOC_SLV
r |
OVR_SLV
r |
EOS_SLV
r |
EOC_SLV
r |
EOSMP_SLV
r |
ADRDY_SLV
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JQOVF_MST
r |
AWD3_MST
r |
AWD2_MST
r |
AWD1_MST
r |
JEOS_MST
r |
JEOC_MST
r |
OVR_MST
r |
EOS_MST
r |
EOC_MST
r |
EOSMP_MST
r |
ADRDY_MST
r |
Bit 0: ADDRDY_MST.
Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion
Bit 1: EOSMP_MST.
Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached
Bit 2: EOC_MST.
Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete
Bit 3: EOS_MST.
Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete
Bit 4: OVR_MST.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 5: JEOC_MST.
Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete
Bit 6: JEOS_MST.
Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete
Bit 7: AWD1_MST.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 8: AWD2_MST.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 9: AWD3_MST.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 10: JQOVF_MST.
Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred
Bit 16: ADRDY_SLV.
Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion
Bit 17: EOSMP_SLV.
Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached
Bit 18: End of regular conversion of the slave ADC.
Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete
Bit 19: End of regular sequence flag of the slave ADC.
Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete
Bit 20: Overrun flag of the slave ADC.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 21: End of injected conversion flag of the slave ADC.
Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete
Bit 22: End of injected sequence flag of the slave ADC.
Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete
Bit 23: Analog watchdog 1 flag of the slave ADC.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 24: Analog watchdog 2 flag of the slave ADC.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 25: Analog watchdog 3 flag of the slave ADC.
Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred
Bit 26: Injected Context Queue Overflow flag of the slave ADC.
Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred
ADC common control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VBATEN
rw |
VSENSEEN
rw |
VREFEN
rw |
PRESC
rw |
CKMODE
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDMA
rw |
DMACFG
rw |
DELAY
rw |
DUAL
rw |
Bits 0-4: Dual ADC mode selection.
Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only
Bits 8-11: Delay between 2 sampling phases.
Allowed values: 0x0-0xf
Bit 13: DMA configuration (for multi-ADC mode).
Allowed values:
0: OneShotMode: DMA One Shot mode selected
1: CircularMode: DMA Circular mode selected
Bits 14-15: Direct memory access mode for multi ADC mode.
Allowed values:
0: Disabled: MDMA mode disabled
1: Interleaved: Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width)
2: Bits12_10: MDMA mode enabled for 12 and 10-bit resolution
3: Bits8_6: MDMA mode enabled for 8 and 6-bit resolution
Bits 16-17: ADC clock mode.
Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4
Bits 18-21: ADC prescaler.
Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256
Bit 22: VREFINT enable.
Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled
Bit 23: Temperature sensor selection.
Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled
Bit 24: VBAT selection.
Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled
0x50060000: Advanced encryption standard hardware accelerator
40/40 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | SR | ||||||||||||||||||||||||||||||||
0x8 | DINR | ||||||||||||||||||||||||||||||||
0xc | DOUTR | ||||||||||||||||||||||||||||||||
0x10 | KEYR0 | ||||||||||||||||||||||||||||||||
0x14 | KEYR1 | ||||||||||||||||||||||||||||||||
0x18 | KEYR2 | ||||||||||||||||||||||||||||||||
0x1c | KEYR3 | ||||||||||||||||||||||||||||||||
0x20 | IVR0 | ||||||||||||||||||||||||||||||||
0x24 | IVR1 | ||||||||||||||||||||||||||||||||
0x28 | IVR2 | ||||||||||||||||||||||||||||||||
0x2c | IVR3 | ||||||||||||||||||||||||||||||||
0x30 | KEYR4 | ||||||||||||||||||||||||||||||||
0x34 | KEYR5 | ||||||||||||||||||||||||||||||||
0x38 | KEYR6 | ||||||||||||||||||||||||||||||||
0x3c | KEYR7 | ||||||||||||||||||||||||||||||||
0x40 | SUSP0R | ||||||||||||||||||||||||||||||||
0x44 | SUSP1R | ||||||||||||||||||||||||||||||||
0x48 | SUSP2R | ||||||||||||||||||||||||||||||||
0x4c | SUSP3R | ||||||||||||||||||||||||||||||||
0x50 | SUSP4R | ||||||||||||||||||||||||||||||||
0x54 | SUSP5R | ||||||||||||||||||||||||||||||||
0x58 | SUSP6R | ||||||||||||||||||||||||||||||||
0x5c | SUSP7R |
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
14/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NPBLB
rw |
KEYSIZE
rw |
CHMOD2
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GCMPH
rw |
DMAOUTEN
rw |
DMAINEN
rw |
ERRIE
rw |
CCFIE
rw |
ERRC
rw |
CCFC
rw |
CHMOD
rw |
MODE
rw |
DATATYPE
rw |
EN
rw |
Bit 0: AES enable.
Allowed values:
0: Disabled: Disable AES
1: Enabled: Enable AES
Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).
Allowed values:
0: None: Word
1: HalfWord: Half-word (16-bit)
2: Byte: Byte (8-bit)
3: Bit: Bit
Bits 3-4: AES operating mode.
Allowed values:
0: Mode1: Mode 1: encryption
1: Mode2: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
2: Mode3: Mode 3: decryption
3: Mode4: Mode 4: key derivation then single decryption
Bits 5-6: AES chaining mode.
Allowed values:
0: ECB: Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1
1: CBC: Cipher-block chaining (CBC)
2: CTR: Counter mode (CTR)
3: GCM: Galois counter mode (GCM) and Galois message authentication code (GMAC)
Bit 7: Computation Complete Flag Clear.
Allowed values:
1: Clear: Clear computation complete flag
Bit 8: Error clear.
Allowed values:
1: Clear: Clear RDERR and WRERR flags
Bit 9: CCF flag interrupt enable.
Allowed values:
0: Disabled: Disable (mask) CCF interrupt
1: Enabled: Enable CCF interrupt
Bit 10: Error interrupt enable.
Allowed values:
0: Disabled: Disable (mask) error interrupt
1: Enabled: Enable error interrupt
Bit 11: Enable DMA management of data input phase.
Allowed values:
0: Disabled: Disable DMA Input
1: Enabled: Enable DMA Input
Bit 12: Enable DMA management of data output phase.
Allowed values:
0: Disabled: Disable DMA Output
1: Enabled: Enabled DMA Output
Bits 13-14: GCM or CCM phase selection.
Allowed values:
0: Init: Init phase
1: Header: Header phase
2: Payload: Payload phase
3: Final: Final Phase
Bit 16: Chaining mode selection, bit [2].
Allowed values:
0: CHMOD: Mode as per CHMOD (ECB, CBC, CTR, GCM)
1: CCM: Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)
Bit 18: Key size selection.
Allowed values:
0: AES128: 128
1: AES256: 256
Bits 20-23: Number of padding bytes in last block.
Allowed values: 0x0-0xf
status register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
Bit 0: Computation complete flag.
Allowed values:
0: Complete: Computation complete
1: NotComplete: Computation not complete
Bit 1: Read error flag.
Allowed values:
0: NoError: Read error not detected
1: Error: Read error detected
Bit 2: Write error flag.
Allowed values:
0: NoError: Write error not detected
1: Error: Write error detected
Bit 3: Busy.
Allowed values:
0: Idle: Idle
1: Busy: Busy
data input register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
data output register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
key register 0
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
key register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
key register 2
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
key register 3
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
initialization vector register 0
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
initialization vector register 1
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
initialization vector register 2
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
initialization vector register 3
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
key register 4
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
key register 5
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
key register 6
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
key register 7
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
suspend registers
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
suspend registers
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
suspend registers
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
suspend registers
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
suspend registers
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
suspend registers
Offset: 0x54, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
0x40006400: Controller area network
82/323 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MCR | ||||||||||||||||||||||||||||||||
0x4 | MSR | ||||||||||||||||||||||||||||||||
0x8 | TSR | ||||||||||||||||||||||||||||||||
0xc | RF[0]R | ||||||||||||||||||||||||||||||||
0x10 | RF[1]R | ||||||||||||||||||||||||||||||||
0x14 | IER | ||||||||||||||||||||||||||||||||
0x18 | ESR | ||||||||||||||||||||||||||||||||
0x1c | BTR | ||||||||||||||||||||||||||||||||
0x180 | TIR [0] | ||||||||||||||||||||||||||||||||
0x184 | TDTR [0] | ||||||||||||||||||||||||||||||||
0x188 | TDLR [0] | ||||||||||||||||||||||||||||||||
0x18c | TDHR [0] | ||||||||||||||||||||||||||||||||
0x190 | TIR [1] | ||||||||||||||||||||||||||||||||
0x194 | TDTR [1] | ||||||||||||||||||||||||||||||||
0x198 | TDLR [1] | ||||||||||||||||||||||||||||||||
0x19c | TDHR [1] | ||||||||||||||||||||||||||||||||
0x1a0 | TIR [2] | ||||||||||||||||||||||||||||||||
0x1a4 | TDTR [2] | ||||||||||||||||||||||||||||||||
0x1a8 | TDLR [2] | ||||||||||||||||||||||||||||||||
0x1ac | TDHR [2] | ||||||||||||||||||||||||||||||||
0x1b0 | RIR [0] | ||||||||||||||||||||||||||||||||
0x1b4 | RDTR [0] | ||||||||||||||||||||||||||||||||
0x1b8 | RDLR [0] | ||||||||||||||||||||||||||||||||
0x1bc | RDHR [0] | ||||||||||||||||||||||||||||||||
0x1c0 | RIR [1] | ||||||||||||||||||||||||||||||||
0x1c4 | RDTR [1] | ||||||||||||||||||||||||||||||||
0x1c8 | RDLR [1] | ||||||||||||||||||||||||||||||||
0x1cc | RDHR [1] | ||||||||||||||||||||||||||||||||
0x200 | FMR | ||||||||||||||||||||||||||||||||
0x204 | FM1R | ||||||||||||||||||||||||||||||||
0x20c | FS1R | ||||||||||||||||||||||||||||||||
0x214 | FFA1R | ||||||||||||||||||||||||||||||||
0x21c | FA1R | ||||||||||||||||||||||||||||||||
0x240 | FR1 [0] | ||||||||||||||||||||||||||||||||
0x244 | FR2 [0] | ||||||||||||||||||||||||||||||||
0x248 | FR1 [1] | ||||||||||||||||||||||||||||||||
0x24c | FR2 [1] | ||||||||||||||||||||||||||||||||
0x250 | FR1 [2] | ||||||||||||||||||||||||||||||||
0x254 | FR2 [2] | ||||||||||||||||||||||||||||||||
0x258 | FR1 [3] | ||||||||||||||||||||||||||||||||
0x25c | FR2 [3] | ||||||||||||||||||||||||||||||||
0x260 | FR1 [4] | ||||||||||||||||||||||||||||||||
0x264 | FR2 [4] | ||||||||||||||||||||||||||||||||
0x268 | FR1 [5] | ||||||||||||||||||||||||||||||||
0x26c | FR2 [5] | ||||||||||||||||||||||||||||||||
0x270 | FR1 [6] | ||||||||||||||||||||||||||||||||
0x274 | FR2 [6] | ||||||||||||||||||||||||||||||||
0x278 | FR1 [7] | ||||||||||||||||||||||||||||||||
0x27c | FR2 [7] | ||||||||||||||||||||||||||||||||
0x280 | FR1 [8] | ||||||||||||||||||||||||||||||||
0x284 | FR2 [8] | ||||||||||||||||||||||||||||||||
0x288 | FR1 [9] | ||||||||||||||||||||||||||||||||
0x28c | FR2 [9] | ||||||||||||||||||||||||||||||||
0x290 | FR1 [10] | ||||||||||||||||||||||||||||||||
0x294 | FR2 [10] | ||||||||||||||||||||||||||||||||
0x298 | FR1 [11] | ||||||||||||||||||||||||||||||||
0x29c | FR2 [11] | ||||||||||||||||||||||||||||||||
0x2a0 | FR1 [12] | ||||||||||||||||||||||||||||||||
0x2a4 | FR2 [12] | ||||||||||||||||||||||||||||||||
0x2a8 | FR1 [13] | ||||||||||||||||||||||||||||||||
0x2ac | FR2 [13] | ||||||||||||||||||||||||||||||||
0x2b0 | FR1 [14] | ||||||||||||||||||||||||||||||||
0x2b4 | FR2 [14] | ||||||||||||||||||||||||||||||||
0x2b8 | FR1 [15] | ||||||||||||||||||||||||||||||||
0x2bc | FR2 [15] | ||||||||||||||||||||||||||||||||
0x2c0 | FR1 [16] | ||||||||||||||||||||||||||||||||
0x2c4 | FR2 [16] | ||||||||||||||||||||||||||||||||
0x2c8 | FR1 [17] | ||||||||||||||||||||||||||||||||
0x2cc | FR2 [17] | ||||||||||||||||||||||||||||||||
0x2d0 | FR1 [18] | ||||||||||||||||||||||||||||||||
0x2d4 | FR2 [18] | ||||||||||||||||||||||||||||||||
0x2d8 | FR1 [19] | ||||||||||||||||||||||||||||||||
0x2dc | FR2 [19] | ||||||||||||||||||||||||||||||||
0x2e0 | FR1 [20] | ||||||||||||||||||||||||||||||||
0x2e4 | FR2 [20] | ||||||||||||||||||||||||||||||||
0x2e8 | FR1 [21] | ||||||||||||||||||||||||||||||||
0x2ec | FR2 [21] | ||||||||||||||||||||||||||||||||
0x2f0 | FR1 [22] | ||||||||||||||||||||||||||||||||
0x2f4 | FR2 [22] | ||||||||||||||||||||||||||||||||
0x2f8 | FR1 [23] | ||||||||||||||||||||||||||||||||
0x2fc | FR2 [23] | ||||||||||||||||||||||||||||||||
0x300 | FR1 [24] | ||||||||||||||||||||||||||||||||
0x304 | FR2 [24] | ||||||||||||||||||||||||||||||||
0x308 | FR1 [25] | ||||||||||||||||||||||||||||||||
0x30c | FR2 [25] | ||||||||||||||||||||||||||||||||
0x310 | FR1 [26] | ||||||||||||||||||||||||||||||||
0x314 | FR2 [26] | ||||||||||||||||||||||||||||||||
0x318 | FR1 [27] | ||||||||||||||||||||||||||||||||
0x31c | FR2 [27] |
master control register
Offset: 0x0, size: 32, reset: 0x00010002, access: read-write
0/10 fields covered.
master status register
Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified
6/9 fields covered.
transmit status register
Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified
7/22 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LOW[2]
r |
LOW[1]
r |
LOW[0]
r |
TME[2]
r |
TME[1]
r |
TME[0]
r |
CODE
r |
ABRQ2
rw |
TERR2
rw |
ALST2
rw |
TXOK2
rw |
RQCP2
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABRQ1
rw |
TERR1
rw |
ALST1
rw |
TXOK1
rw |
RQCP1
rw |
ABRQ0
rw |
TERR0
rw |
ALST0
rw |
TXOK0
rw |
RQCP0
rw |
Bit 0: RQCP0.
Bit 1: TXOK0.
Bit 2: ALST0.
Bit 3: TERR0.
Bit 7: ABRQ0.
Bit 8: RQCP1.
Bit 9: TXOK1.
Bit 10: ALST1.
Bit 11: TERR1.
Bit 15: ABRQ1.
Bit 16: RQCP2.
Bit 17: TXOK2.
Bit 18: ALST2.
Bit 19: TERR2.
Bit 23: ABRQ2.
Bits 24-25: CODE.
Bit 26: Lowest priority flag for mailbox 0.
Bit 27: Lowest priority flag for mailbox 1.
Bit 28: Lowest priority flag for mailbox 2.
Bit 29: Lowest priority flag for mailbox 0.
Bit 30: Lowest priority flag for mailbox 1.
Bit 31: Lowest priority flag for mailbox 2.
receive FIFO 0 register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bits 0-1: FMP0.
Bit 3: FULL0.
Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full
Bit 4: FOVR0.
Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun
Bit 5: RFOM0.
Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO
receive FIFO 1 register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bits 0-1: FMP0.
Bit 3: FULL0.
Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full
Bit 4: FOVR0.
Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun
Bit 5: RFOM0.
Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO
interrupt enable register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
14/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SLKIE
rw |
WKUIE
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERRIE
rw |
LECIE
rw |
BOFIE
rw |
EPVIE
rw |
EWGIE
rw |
FOVIE1
rw |
FFIE1
rw |
FMPIE1
rw |
FOVIE0
rw |
FFIE0
rw |
FMPIE0
rw |
TMEIE
rw |
Bit 0: TMEIE.
Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set
Bit 1: FMPIE0.
Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b
Bit 2: FFIE0.
Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set
Bit 3: FOVIE0.
Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set
Bit 4: FMPIE1.
Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b
Bit 5: FFIE1.
Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set
Bit 6: FOVIE1.
Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set
Bit 8: EWGIE.
Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set
Bit 9: EPVIE.
Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set
Bit 10: BOFIE.
Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set
Bit 11: LECIE.
Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection
Bit 15: ERRIE.
Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR
Bit 16: WKUIE.
Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set
Bit 17: SLKIE.
Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set
interrupt enable register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REC
r |
TEC
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEC
rw |
BOFF
r |
EPVF
r |
EWGF
r |
Bit 0: EWGF.
Bit 1: EPVF.
Bit 2: BOFF.
Bits 4-6: LEC.
Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software
Bits 16-23: TEC.
Bits 24-31: REC.
bit timing register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
2/6 fields covered.
TX mailbox identifier register
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
2/5 fields covered.
mailbox data length control and time stamp register
Offset: 0x184, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
mailbox data low register
Offset: 0x188, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
mailbox data high register
Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
TX mailbox identifier register
Offset: 0x190, size: 32, reset: 0x00000000, access: read-write
2/5 fields covered.
mailbox data length control and time stamp register
Offset: 0x194, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
mailbox data low register
Offset: 0x198, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
mailbox data high register
Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
TX mailbox identifier register
Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write
2/5 fields covered.
mailbox data length control and time stamp register
Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
mailbox data low register
Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
mailbox data high register
Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
receive FIFO mailbox identifier register
Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
mailbox data high register
Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
mailbox data high register
Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
receive FIFO mailbox data high register
Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
receive FIFO mailbox identifier register
Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
mailbox data high register
Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
mailbox data high register
Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
receive FIFO mailbox data high register
Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
filter master register
Offset: 0x200, size: 32, reset: 0x2A1C0E01, access: read-write
0/2 fields covered.
filter mode register
Offset: 0x204, size: 32, reset: 0x00000000, access: read-write
0/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FBM[27]
rw |
FBM[26]
rw |
FBM[25]
rw |
FBM[24]
rw |
FBM[23]
rw |
FBM[22]
rw |
FBM[21]
rw |
FBM[20]
rw |
FBM[19]
rw |
FBM[18]
rw |
FBM[17]
rw |
FBM[16]
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FBM[15]
rw |
FBM[14]
rw |
FBM[13]
rw |
FBM[12]
rw |
FBM[11]
rw |
FBM[10]
rw |
FBM[9]
rw |
FBM[8]
rw |
FBM[7]
rw |
FBM[6]
rw |
FBM[5]
rw |
FBM[4]
rw |
FBM[3]
rw |
FBM[2]
rw |
FBM[1]
rw |
FBM[0]
rw |
Bit 0: Filter mode.
Bit 1: Filter mode.
Bit 2: Filter mode.
Bit 3: Filter mode.
Bit 4: Filter mode.
Bit 5: Filter mode.
Bit 6: Filter mode.
Bit 7: Filter mode.
Bit 8: Filter mode.
Bit 9: Filter mode.
Bit 10: Filter mode.
Bit 11: Filter mode.
Bit 12: Filter mode.
Bit 13: Filter mode.
Bit 14: Filter mode.
Bit 15: Filter mode.
Bit 16: Filter mode.
Bit 17: Filter mode.
Bit 18: Filter mode.
Bit 19: Filter mode.
Bit 20: Filter mode.
Bit 21: Filter mode.
Bit 22: Filter mode.
Bit 23: Filter mode.
Bit 24: Filter mode.
Bit 25: Filter mode.
Bit 26: Filter mode.
Bit 27: Filter mode.
filter scale register
Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write
0/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FSC[27]
rw |
FSC[26]
rw |
FSC[25]
rw |
FSC[24]
rw |
FSC[23]
rw |
FSC[22]
rw |
FSC[21]
rw |
FSC[20]
rw |
FSC[19]
rw |
FSC[18]
rw |
FSC[17]
rw |
FSC[16]
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSC[15]
rw |
FSC[14]
rw |
FSC[13]
rw |
FSC[12]
rw |
FSC[11]
rw |
FSC[10]
rw |
FSC[9]
rw |
FSC[8]
rw |
FSC[7]
rw |
FSC[6]
rw |
FSC[5]
rw |
FSC[4]
rw |
FSC[3]
rw |
FSC[2]
rw |
FSC[1]
rw |
FSC[0]
rw |
Bit 0: Filter scale configuration.
Bit 1: Filter scale configuration.
Bit 2: Filter scale configuration.
Bit 3: Filter scale configuration.
Bit 4: Filter scale configuration.
Bit 5: Filter scale configuration.
Bit 6: Filter scale configuration.
Bit 7: Filter scale configuration.
Bit 8: Filter scale configuration.
Bit 9: Filter scale configuration.
Bit 10: Filter scale configuration.
Bit 11: Filter scale configuration.
Bit 12: Filter scale configuration.
Bit 13: Filter scale configuration.
Bit 14: Filter scale configuration.
Bit 15: Filter scale configuration.
Bit 16: Filter scale configuration.
Bit 17: Filter scale configuration.
Bit 18: Filter scale configuration.
Bit 19: Filter scale configuration.
Bit 20: Filter scale configuration.
Bit 21: Filter scale configuration.
Bit 22: Filter scale configuration.
Bit 23: Filter scale configuration.
Bit 24: Filter scale configuration.
Bit 25: Filter scale configuration.
Bit 26: Filter scale configuration.
Bit 27: Filter scale configuration.
filter FIFO assignment register
Offset: 0x214, size: 32, reset: 0x00000000, access: read-write
0/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FFA[27]
rw |
FFA[26]
rw |
FFA[25]
rw |
FFA[24]
rw |
FFA[23]
rw |
FFA[22]
rw |
FFA[21]
rw |
FFA[20]
rw |
FFA[19]
rw |
FFA[18]
rw |
FFA[17]
rw |
FFA[16]
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FFA[15]
rw |
FFA[14]
rw |
FFA[13]
rw |
FFA[12]
rw |
FFA[11]
rw |
FFA[10]
rw |
FFA[9]
rw |
FFA[8]
rw |
FFA[7]
rw |
FFA[6]
rw |
FFA[5]
rw |
FFA[4]
rw |
FFA[3]
rw |
FFA[2]
rw |
FFA[1]
rw |
FFA[0]
rw |
Bit 0: Filter FIFO assignment for filter 0.
Bit 1: Filter FIFO assignment for filter 1.
Bit 2: Filter FIFO assignment for filter 2.
Bit 3: Filter FIFO assignment for filter 3.
Bit 4: Filter FIFO assignment for filter 4.
Bit 5: Filter FIFO assignment for filter 5.
Bit 6: Filter FIFO assignment for filter 6.
Bit 7: Filter FIFO assignment for filter 7.
Bit 8: Filter FIFO assignment for filter 8.
Bit 9: Filter FIFO assignment for filter 9.
Bit 10: Filter FIFO assignment for filter 10.
Bit 11: Filter FIFO assignment for filter 11.
Bit 12: Filter FIFO assignment for filter 12.
Bit 13: Filter FIFO assignment for filter 13.
Bit 14: Filter FIFO assignment for filter 14.
Bit 15: Filter FIFO assignment for filter 15.
Bit 16: Filter FIFO assignment for filter 16.
Bit 17: Filter FIFO assignment for filter 17.
Bit 18: Filter FIFO assignment for filter 18.
Bit 19: Filter FIFO assignment for filter 19.
Bit 20: Filter FIFO assignment for filter 20.
Bit 21: Filter FIFO assignment for filter 21.
Bit 22: Filter FIFO assignment for filter 22.
Bit 23: Filter FIFO assignment for filter 23.
Bit 24: Filter FIFO assignment for filter 24.
Bit 25: Filter FIFO assignment for filter 25.
Bit 26: Filter FIFO assignment for filter 26.
Bit 27: Filter FIFO assignment for filter 27.
filter activation register
Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write
0/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FACT[27]
rw |
FACT[26]
rw |
FACT[25]
rw |
FACT[24]
rw |
FACT[23]
rw |
FACT[22]
rw |
FACT[21]
rw |
FACT[20]
rw |
FACT[19]
rw |
FACT[18]
rw |
FACT[17]
rw |
FACT[16]
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FACT[15]
rw |
FACT[14]
rw |
FACT[13]
rw |
FACT[12]
rw |
FACT[11]
rw |
FACT[10]
rw |
FACT[9]
rw |
FACT[8]
rw |
FACT[7]
rw |
FACT[6]
rw |
FACT[5]
rw |
FACT[4]
rw |
FACT[3]
rw |
FACT[2]
rw |
FACT[1]
rw |
FACT[0]
rw |
Bit 0: Filter active.
Bit 1: Filter active.
Bit 2: Filter active.
Bit 3: Filter active.
Bit 4: Filter active.
Bit 5: Filter active.
Bit 6: Filter active.
Bit 7: Filter active.
Bit 8: Filter active.
Bit 9: Filter active.
Bit 10: Filter active.
Bit 11: Filter active.
Bit 12: Filter active.
Bit 13: Filter active.
Bit 14: Filter active.
Bit 15: Filter active.
Bit 16: Filter active.
Bit 17: Filter active.
Bit 18: Filter active.
Bit 19: Filter active.
Bit 20: Filter active.
Bit 21: Filter active.
Bit 22: Filter active.
Bit 23: Filter active.
Bit 24: Filter active.
Bit 25: Filter active.
Bit 26: Filter active.
Bit 27: Filter active.
Filter bank x register 1
Offset: 0x240, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x244, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x248, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x250, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x254, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x258, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x260, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x264, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x268, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x270, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x274, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x278, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x27c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x280, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x284, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x288, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x290, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x294, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x298, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x2f8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x2fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x300, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x304, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x308, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 1
Offset: 0x310, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Filter bank x register 2
Offset: 0x314, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
0x40010200: Comparator
2/23 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | COMP1_CSR | ||||||||||||||||||||||||||||||||
0x4 | COMP2_CSR |
Comparator 1 control and status register
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
1/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMP1_LOCK
w |
COMP1_VALUE
r |
COMP1_SCALEN
rw |
COMP1_BRGEN
rw |
COMP1_BLANKING
rw |
COMP1_HYST
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP1_POLARITY
rw |
COMP1_INPSEL
rw |
COMP1_INMSEL
rw |
COMP1_PWRMODE
rw |
COMP1_EN
rw |
Bit 0: Comparator 1 enable bit.
Bits 2-3: Power Mode of the comparator 1.
Bits 4-6: Comparator 1 Input Minus connection configuration bit.
Bit 7: Comparator1 input plus selection bit.
Bit 15: Comparator 1 polarity selection bit.
Bits 16-17: Comparator 1 hysteresis selection bits.
Bits 18-20: Comparator 1 blanking source selection bits.
Bit 22: Scaler bridge enable.
Bit 23: Voltage scaler enable bit.
Bit 30: Comparator 1 output status bit.
Bit 31: COMP1_CSR register lock bit.
Comparator 2 control and status register
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
1/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMP2_LOCK
w |
COMP2_VALUE
r |
COMP2_SCALEN
rw |
COMP2_BRGEN
rw |
COMP2_BLANKING
rw |
COMP2_HYST
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP2_POLARITY
rw |
COMP2_WINMODE
rw |
COMP2_INPSEL
rw |
COMP2_INMSEL
rw |
COMP2_PWRMODE
rw |
COMP2_EN
rw |
Bit 0: Comparator 2 enable bit.
Bits 2-3: Power Mode of the comparator 2.
Bits 4-6: Comparator 2 Input Minus connection configuration bit.
Bit 7: Comparator 2 Input Plus connection configuration bit.
Bit 9: Windows mode selection bit.
Bit 15: Comparator 2 polarity selection bit.
Bits 16-17: Comparator 2 hysteresis selection bits.
Bits 18-20: Comparator 2 blanking source selection bits.
Bit 22: Scaler bridge enable.
Bit 23: Voltage scaler enable bit.
Bit 30: Comparator 2 output status bit.
Bit 31: COMP2_CSR register lock bit.
0x40023000: Cyclic redundancy check calculation unit
10/10 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | DR | ||||||||||||||||||||||||||||||||
0x0 (16-bit) | DR16 | ||||||||||||||||||||||||||||||||
0x0 (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
0x4 | IDR | ||||||||||||||||||||||||||||||||
0x8 | CR | ||||||||||||||||||||||||||||||||
0x10 | INIT | ||||||||||||||||||||||||||||||||
0x14 | POL |
Data register - half-word sized
Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DR16
rw |
Data register - byte sized
Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DR8
rw |
Independent data register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR
rw |
Control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bit 0: RESET bit.
Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF
Bits 3-4: Polynomial size.
Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial
Bits 5-6: Reverse input data.
Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word
Bit 7: Reverse output data.
Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output
0x40006000: Clock recovery system
9/26 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | CFGR | ||||||||||||||||||||||||||||||||
0x8 | ISR | ||||||||||||||||||||||||||||||||
0xc | ICR |
control register
Offset: 0x0, size: 32, reset: 0x00002000, access: read-write
0/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRIM
rw |
SWSYNC
rw |
AUTOTRIMEN
rw |
CEN
rw |
ESYNCIE
rw |
ERRIE
rw |
SYNCWARNIE
rw |
SYNCOKIE
rw |
Bit 0: SYNC event OK interrupt enable.
Bit 1: SYNC warning interrupt enable.
Bit 2: Synchronization or trimming error interrupt enable.
Bit 3: Expected SYNC interrupt enable.
Bit 5: Frequency error counter enable.
Bit 6: Automatic trimming enable.
Bit 7: Generate software SYNC event.
Bits 8-13: HSI48 oscillator smooth trimming.
configuration register
Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write
0/5 fields covered.
interrupt and status register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FECAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FEDIR
r |
TRIMOVF
r |
SYNCMISS
r |
SYNCERR
r |
ESYNCF
r |
ERRF
r |
SYNCWARNF
r |
SYNCOKF
r |
Bit 0: SYNC event OK flag.
Bit 1: SYNC warning flag.
Bit 2: Error flag.
Bit 3: Expected SYNC flag.
Bit 8: SYNC error.
Bit 9: SYNC missed.
Bit 10: Trimming overflow or underflow.
Bit 15: Frequency error direction.
Bits 16-31: Frequency error capture.
0x40007400: Digital-to-analog converter
49/49 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | SWTRIGR | ||||||||||||||||||||||||||||||||
0x8 | DHR12R[1] | ||||||||||||||||||||||||||||||||
0xc | DHR12L[1] | ||||||||||||||||||||||||||||||||
0x10 | DHR8R[1] | ||||||||||||||||||||||||||||||||
0x14 | DHR12R[2] | ||||||||||||||||||||||||||||||||
0x18 | DHR12L[2] | ||||||||||||||||||||||||||||||||
0x1c | DHR8R[2] | ||||||||||||||||||||||||||||||||
0x20 | DHR12RD | ||||||||||||||||||||||||||||||||
0x24 | DHR12LD | ||||||||||||||||||||||||||||||||
0x28 | DHR8RD | ||||||||||||||||||||||||||||||||
0x2c | DOR[1] | ||||||||||||||||||||||||||||||||
0x30 | DOR[2] | ||||||||||||||||||||||||||||||||
0x34 | SR | ||||||||||||||||||||||||||||||||
0x38 | CCR | ||||||||||||||||||||||||||||||||
0x3c | MCR | ||||||||||||||||||||||||||||||||
0x40 | SHSR[1] | ||||||||||||||||||||||||||||||||
0x44 | SHSR[2] | ||||||||||||||||||||||||||||||||
0x48 | SHHR | ||||||||||||||||||||||||||||||||
0x4c | SHRR |
DAC control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CEN[2]
rw |
DMAUDRIE[2]
rw |
DMAEN[2]
rw |
MAMP[2]
rw |
WAVE[2]
rw |
TSEL2
rw |
TEN[2]
rw |
EN[2]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HFSEL
rw |
CEN[1]
rw |
DMAUDRIE[1]
rw |
DMAEN[1]
rw |
MAMP[1]
rw |
WAVE[1]
rw |
TSEL1
rw |
TEN[1]
rw |
EN[1]
rw |
Bit 0: DAC channel1 enable.
Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled
Bit 1: DAC channel1 trigger enable.
Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled
Bits 2-5: DAC channel1 trigger selection.
Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: External pin
Bits 6-7: DAC channel1 noise/triangle wave generation enable.
Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled
Bits 8-11: DAC channel1 mask/amplitude selector.
Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bit 12: DAC channel1 DMA enable.
Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled
Bit 13: DAC channel1 DMA Underrun Interrupt enable.
Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled
Bit 14: DAC channel1 calibration enable.
Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode
Bit 15: High frequency interface mode enable.
Allowed values:
0: Disabled: High frequency interface mode disabled
1: Enabled: High frequency interface mode enabled
Bit 16: DAC channel2 enable.
Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled
Bit 17: DAC channel2 trigger enable.
Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled
Bits 18-21: DAC channel2 trigger selection.
Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: External pin
Bits 22-23: DAC channel2 noise/triangle wave generation enable.
Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled
Bits 24-27: DAC channel2 mask/amplitude selector.
Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bit 28: DAC channel2 DMA enable.
Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled
Bit 29: DAC channel2 DMA Underrun Interrupt enable.
Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled
Bit 30: DAC channel2 calibration enable.
Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode
software trigger register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
2/2 fields covered.
channel1 12-bit right-aligned data holding register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCDHR
rw |
channel1 12-bit left aligned data holding register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCDHR
rw |
channel1 8-bit right aligned data holding register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCDHR
rw |
channel2 12-bit right-aligned data holding register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCDHR
rw |
channel2 12-bit left aligned data holding register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCDHR
rw |
channel2 8-bit right aligned data holding register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCDHR
rw |
Dual DAC 12-bit right-aligned data holding register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACC[2]DHR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DACC[1]DHR
rw |
DUAL DAC 12-bit left aligned data holding register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACC[2]DHR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DACC[1]DHR
rw |
DUAL DAC 8-bit right aligned data holding register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACC[2]DHR
rw |
DACC[1]DHR
rw |
channel1 data output register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCDOR
r |
channel2 data output register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACCDOR
r |
status register
Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BWST[2]
r |
CAL_FLAG[2]
r |
DMAUDR[2]
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BWST[1]
r |
CAL_FLAG[1]
r |
DMAUDR[1]
rw |
Bit 13: DAC channel1 DMA underrun flag.
Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bit 14: DAC channel1 calibration offset status.
Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value
Bit 15: DAC channel1 busy writing sample time flag.
Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
Bit 29: DAC channel2 DMA underrun flag.
Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bit 30: DAC channel2 calibration offset status.
Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value
Bit 31: DAC channel2 busy writing sample time flag.
Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
calibration control register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
mode control register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODE[2]
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE[1]
rw |
Bits 0-2: DAC channel1 mode.
Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
Bits 16-18: DAC channel2 mode.
Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
DAC channel1 sample and hold sample time register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TSAMPLE
rw |
DAC channel2 sample and hold sample time register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TSAMPLE
rw |
Sample and Hold hold time register
Offset: 0x48, size: 32, reset: 0x00010001, access: read-write
2/2 fields covered.
Sample and Hold refresh time register
Offset: 0x4c, size: 32, reset: 0x00000001, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TREFRESH[2]
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TREFRESH[1]
rw |
0xe0042000: Debug support
2/27 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | IDCODE | ||||||||||||||||||||||||||||||||
0x4 | CR | ||||||||||||||||||||||||||||||||
0x8 | APB1FZR1 | ||||||||||||||||||||||||||||||||
0xc | APB1FZR2 | ||||||||||||||||||||||||||||||||
0x10 | APB2FZR |
MCU Device ID Code Register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
Debug MCU Configuration Register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRACE_MODE
rw |
TRACE_IOEN
rw |
DBG_STANDBY
rw |
DBG_STOP
rw |
DBG_SLEEP
rw |
APB Low Freeze Register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DBG_LPTIMER_STOP
rw |
DBG_CAN_STOP
rw |
DBG_I2C3_STOP
rw |
DBG_I2C2_STOP
rw |
DBG_I2C1_STOP
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG_IWDG_STOP
rw |
DBG_WWDG_STOP
rw |
DBG_RTC_STOP
rw |
DBG_TIM7_STOP
rw |
DBG_TIMER6_STOP
rw |
DBG_TIM5_STOP
rw |
DBG_TIM4_STOP
rw |
DBG_TIM3_STOP
rw |
DBG_TIMER2_STOP
rw |
Bit 0: Debug Timer 2 stopped when Core is halted.
Bit 1: TIM3 counter stopped when core is halted.
Bit 2: TIM4 counter stopped when core is halted.
Bit 3: TIM5 counter stopped when core is halted.
Bit 4: Debug Timer 6 stopped when Core is halted.
Bit 5: TIM7 counter stopped when core is halted.
Bit 10: Debug RTC stopped when Core is halted.
Bit 11: Debug Window Wachdog stopped when Core is halted.
Bit 12: Debug Independent Wachdog stopped when Core is halted.
Bit 21: I2C1 SMBUS timeout mode stopped when core is halted.
Bit 22: I2C2 SMBUS timeout mode stopped when core is halted.
Bit 23: I2C3 SMBUS timeout counter stopped when core is halted.
Bit 25: bxCAN stopped when core is halted.
Bit 31: LPTIM1 counter stopped when core is halted.
APB Low Freeze Register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DBG_LPTIM2_STOP
rw |
APB High Freeze Register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DBG_TIM17_STOP
rw |
DBG_TIM16_STOP
rw |
DBG_TIM15_STOP
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG_TIM8_STOP
rw |
DBG_TIM1_STOP
rw |
Bit 11: TIM1 counter stopped when core is halted.
Bit 13: TIM8 counter stopped when core is halted.
Bit 16: TIM15 counter stopped when core is halted.
Bit 17: TIM16 counter stopped when core is halted.
Bit 18: TIM17 counter stopped when core is halted.
0x50050000: Digital camera interface
17/54 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | SR | ||||||||||||||||||||||||||||||||
0x8 | RIS | ||||||||||||||||||||||||||||||||
0xc | IER | ||||||||||||||||||||||||||||||||
0x10 | MIS | ||||||||||||||||||||||||||||||||
0x14 | ICR | ||||||||||||||||||||||||||||||||
0x18 | ESCR | ||||||||||||||||||||||||||||||||
0x1c | ESUR | ||||||||||||||||||||||||||||||||
0x20 | CWSTRT | ||||||||||||||||||||||||||||||||
0x24 | CWSIZE | ||||||||||||||||||||||||||||||||
0x28 | DR |
control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OELS
rw |
LSM
rw |
OEBS
rw |
BSM
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE
rw |
EDM
rw |
FCRC
rw |
VSPOL
rw |
HSPOL
rw |
PCKPOL
rw |
ESS
rw |
JPEG
rw |
CROP
rw |
CM
rw |
CAPTURE
rw |
Bit 0: Capture enable.
Bit 1: Capture mode.
Bit 2: Crop feature.
Bit 3: JPEG format.
Bit 4: Embedded synchronization select.
Bit 5: Pixel clock polarity.
Bit 6: Horizontal synchronization polarity.
Bit 7: Vertical synchronization polarity.
Bits 8-9: Frame capture rate control.
Bits 10-11: Extended data mode.
Bit 14: DCMI enable.
Bits 16-17: Byte Select mode.
Bit 18: Odd/Even Byte Select (Byte Select Start).
Bit 19: Line Select mode.
Bit 20: Odd/Even Line Select (Line Select Start).
raw interrupt status register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-only
5/5 fields covered.
interrupt enable register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
masked interrupt status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
5/5 fields covered.
interrupt clear register
Offset: 0x14, size: 32, reset: 0x00000000, access: write-only
0/5 fields covered.
embedded synchronization code register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
embedded synchronization unmask register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
crop window start
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
crop window size
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
0x40016000: Digital filter for sigma delta modulators
84/379 fields covered.
channel configuration y register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/11 fields covered.
channel configuration y register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog and short-circuit detector register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
channel watchdog filter data register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WDATA
rw |
channel data input register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel y delay register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLSSKP
rw |
CH1CFGR1
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
CH1CFGR2
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
CH1AWSCDR
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
CH1WDATR
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WDATA
rw |
CH1DATINR
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel y delay register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLSSKP
rw |
CH2CFGR1
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
CH2CFGR2
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
CH2AWSCDR
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
CH2WDATR
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WDATA
rw |
CH2DATINR
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel y delay register
Offset: 0x54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLSSKP
rw |
CH3CFGR1
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
CH3CFGR2
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
CH3AWSCDR
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
CH3WDATR
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WDATA
rw |
CH3DATINR
Offset: 0x70, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel y delay register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLSSKP
rw |
CH4CFGR1
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
CH4CFGR2
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
CH4AWSCDR
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
CH4WDATR
Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WDATA
rw |
CH4DATINR
Offset: 0x90, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel y delay register
Offset: 0x94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLSSKP
rw |
CH5CFGR1
Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
CH5CFGR2
Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
CH5AWSCDR
Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
CH5WDATR
Offset: 0xac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WDATA
rw |
CH5DATINR
Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel y delay register
Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLSSKP
rw |
CH6CFGR1
Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
CH6CFGR2
Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
CH6AWSCDR
Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
CH6WDATR
Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WDATA
rw |
CH6DATINR
Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel y delay register
Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLSSKP
rw |
CH7CFGR1
Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
CH7CFGR2
Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
CH7AWSCDR
Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
CH7WDATR
Offset: 0xec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WDATA
rw |
CH7DATINR
Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
channel y delay register
Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLSSKP
rw |
control register 1
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWFSEL
rw |
FAST
rw |
RCH
rw |
RDMAEN
rw |
RSYNC
rw |
RCONT
rw |
RSWSTART
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JEXTEN
rw |
JEXTSEL
rw |
JDMAEN
rw |
JSCAN
rw |
JSYNC
rw |
JSWSTART
rw |
DFEN
rw |
Bit 0: DFSDM enable.
Bit 1: Start a conversion of the injected group of channels.
Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.
Bit 4: Scanning conversion mode for injected conversions.
Bit 5: DMA channel enabled to read data for the injected channel group.
Bits 8-10: Trigger signal selection for launching injected conversions.
Bits 13-14: Trigger enable and trigger edge selection for injected conversions.
Bit 17: Software start of a conversion on the regular channel.
Bit 18: Continuous mode selection for regular conversions.
Bit 19: Launch regular conversion synchronously with DFSDM0.
Bit 21: DMA channel enabled to read data for the regular conversion.
Bits 24-26: Regular channel selection.
Bit 29: Fast conversion mode selection for regular conversions.
Bit 30: Analog watchdog fast mode select.
control register 2
Offset: 0x104, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWDCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXCH
rw |
CKABIE
rw |
SCDIE
rw |
AWDIE
rw |
ROVRIE
rw |
JOVRIE
rw |
REOCIE
rw |
JEOCIE
rw |
Bit 0: Injected end of conversion interrupt enable.
Bit 1: Regular end of conversion interrupt enable.
Bit 2: Injected data overrun interrupt enable.
Bit 3: Regular data overrun interrupt enable.
Bit 4: Analog watchdog interrupt enable.
Bit 5: Short-circuit detector interrupt enable.
Bit 6: Clock absence interrupt enable.
Bits 8-15: Extremes detector channel selection.
Bits 16-23: Analog watchdog channel selection.
interrupt and status register
Offset: 0x108, size: 32, reset: 0x00FF0000, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCDF
r |
CKABF
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCIP
r |
JCIP
r |
AWDF
r |
ROVRF
r |
JOVRF
r |
REOCF
r |
JEOCF
r |
Bit 0: End of injected conversion flag.
Bit 1: End of regular conversion flag.
Bit 2: Injected conversion overrun flag.
Bit 3: Regular conversion overrun flag.
Bit 4: Analog watchdog.
Bit 13: Injected conversion in progress status.
Bit 14: Regular conversion in progress status.
Bits 16-23: Clock absence flag.
Bits 24-31: short-circuit detector flag.
interrupt flag clear register
Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
injected channel group selection register
Offset: 0x110, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JCHG
rw |
filter control register
Offset: 0x114, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
data register for injected group
Offset: 0x118, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
data register for the regular channel
Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
analog watchdog high threshold register
Offset: 0x120, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog low threshold register
Offset: 0x124, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog status register
Offset: 0x128, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
analog watchdog clear flag register
Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Extremes detector maximum register
Offset: 0x130, size: 32, reset: 0x80000000, access: read-only
2/2 fields covered.
Extremes detector minimum register
Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: read-only
2/2 fields covered.
conversion timer register
Offset: 0x138, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
control register 1
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWFSEL
rw |
FAST
rw |
RCH
rw |
RDMAEN
rw |
RSYNC
rw |
RCONT
rw |
RSWSTART
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JEXTEN
rw |
JEXTSEL
rw |
JDMAEN
rw |
JSCAN
rw |
JSYNC
rw |
JSWSTART
rw |
DFEN
rw |
Bit 0: DFSDM enable.
Bit 1: Start a conversion of the injected group of channels.
Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.
Bit 4: Scanning conversion mode for injected conversions.
Bit 5: DMA channel enabled to read data for the injected channel group.
Bits 8-10: Trigger signal selection for launching injected conversions.
Bits 13-14: Trigger enable and trigger edge selection for injected conversions.
Bit 17: Software start of a conversion on the regular channel.
Bit 18: Continuous mode selection for regular conversions.
Bit 19: Launch regular conversion synchronously with DFSDM0.
Bit 21: DMA channel enabled to read data for the regular conversion.
Bits 24-26: Regular channel selection.
Bit 29: Fast conversion mode selection for regular conversions.
Bit 30: Analog watchdog fast mode select.
control register 2
Offset: 0x184, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWDCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXCH
rw |
CKABIE
rw |
SCDIE
rw |
AWDIE
rw |
ROVRIE
rw |
JOVRIE
rw |
REOCIE
rw |
JEOCIE
rw |
Bit 0: Injected end of conversion interrupt enable.
Bit 1: Regular end of conversion interrupt enable.
Bit 2: Injected data overrun interrupt enable.
Bit 3: Regular data overrun interrupt enable.
Bit 4: Analog watchdog interrupt enable.
Bit 5: Short-circuit detector interrupt enable.
Bit 6: Clock absence interrupt enable.
Bits 8-15: Extremes detector channel selection.
Bits 16-23: Analog watchdog channel selection.
interrupt and status register
Offset: 0x188, size: 32, reset: 0x00FF0000, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCDF
r |
CKABF
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCIP
r |
JCIP
r |
AWDF
r |
ROVRF
r |
JOVRF
r |
REOCF
r |
JEOCF
r |
Bit 0: End of injected conversion flag.
Bit 1: End of regular conversion flag.
Bit 2: Injected conversion overrun flag.
Bit 3: Regular conversion overrun flag.
Bit 4: Analog watchdog.
Bit 13: Injected conversion in progress status.
Bit 14: Regular conversion in progress status.
Bits 16-23: Clock absence flag.
Bits 24-31: short-circuit detector flag.
interrupt flag clear register
Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
injected channel group selection register
Offset: 0x190, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JCHG
rw |
filter control register
Offset: 0x194, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
data register for injected group
Offset: 0x198, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
data register for the regular channel
Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
analog watchdog high threshold register
Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog low threshold register
Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog status register
Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
analog watchdog clear flag register
Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Extremes detector maximum register
Offset: 0x1b0, size: 32, reset: 0x80000000, access: read-only
2/2 fields covered.
Extremes detector minimum register
Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: read-only
2/2 fields covered.
conversion timer register
Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
control register 1
Offset: 0x200, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWFSEL
rw |
FAST
rw |
RCH
rw |
RDMAEN
rw |
RSYNC
rw |
RCONT
rw |
RSWSTART
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JEXTEN
rw |
JEXTSEL
rw |
JDMAEN
rw |
JSCAN
rw |
JSYNC
rw |
JSWSTART
rw |
DFEN
rw |
Bit 0: DFSDM enable.
Bit 1: Start a conversion of the injected group of channels.
Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.
Bit 4: Scanning conversion mode for injected conversions.
Bit 5: DMA channel enabled to read data for the injected channel group.
Bits 8-10: Trigger signal selection for launching injected conversions.
Bits 13-14: Trigger enable and trigger edge selection for injected conversions.
Bit 17: Software start of a conversion on the regular channel.
Bit 18: Continuous mode selection for regular conversions.
Bit 19: Launch regular conversion synchronously with DFSDM0.
Bit 21: DMA channel enabled to read data for the regular conversion.
Bits 24-26: Regular channel selection.
Bit 29: Fast conversion mode selection for regular conversions.
Bit 30: Analog watchdog fast mode select.
control register 2
Offset: 0x204, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWDCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXCH
rw |
CKABIE
rw |
SCDIE
rw |
AWDIE
rw |
ROVRIE
rw |
JOVRIE
rw |
REOCIE
rw |
JEOCIE
rw |
Bit 0: Injected end of conversion interrupt enable.
Bit 1: Regular end of conversion interrupt enable.
Bit 2: Injected data overrun interrupt enable.
Bit 3: Regular data overrun interrupt enable.
Bit 4: Analog watchdog interrupt enable.
Bit 5: Short-circuit detector interrupt enable.
Bit 6: Clock absence interrupt enable.
Bits 8-15: Extremes detector channel selection.
Bits 16-23: Analog watchdog channel selection.
interrupt and status register
Offset: 0x208, size: 32, reset: 0x00FF0000, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCDF
r |
CKABF
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCIP
r |
JCIP
r |
AWDF
r |
ROVRF
r |
JOVRF
r |
REOCF
r |
JEOCF
r |
Bit 0: End of injected conversion flag.
Bit 1: End of regular conversion flag.
Bit 2: Injected conversion overrun flag.
Bit 3: Regular conversion overrun flag.
Bit 4: Analog watchdog.
Bit 13: Injected conversion in progress status.
Bit 14: Regular conversion in progress status.
Bits 16-23: Clock absence flag.
Bits 24-31: short-circuit detector flag.
interrupt flag clear register
Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
injected channel group selection register
Offset: 0x210, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JCHG
rw |
filter control register
Offset: 0x214, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
data register for injected group
Offset: 0x218, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
data register for the regular channel
Offset: 0x21c, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
analog watchdog high threshold register
Offset: 0x220, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog low threshold register
Offset: 0x224, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog status register
Offset: 0x228, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
analog watchdog clear flag register
Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Extremes detector maximum register
Offset: 0x230, size: 32, reset: 0x80000000, access: read-only
2/2 fields covered.
Extremes detector minimum register
Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: read-only
2/2 fields covered.
conversion timer register
Offset: 0x238, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
control register 1
Offset: 0x280, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWFSEL
rw |
FAST
rw |
RCH
rw |
RDMAEN
rw |
RSYNC
rw |
RCONT
rw |
RSWSTART
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
JEXTEN
rw |
JEXTSEL
rw |
JDMAEN
rw |
JSCAN
rw |
JSYNC
rw |
JSWSTART
rw |
DFEN
rw |
Bit 0: DFSDM enable.
Bit 1: Start a conversion of the injected group of channels.
Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.
Bit 4: Scanning conversion mode for injected conversions.
Bit 5: DMA channel enabled to read data for the injected channel group.
Bits 8-10: Trigger signal selection for launching injected conversions.
Bits 13-14: Trigger enable and trigger edge selection for injected conversions.
Bit 17: Software start of a conversion on the regular channel.
Bit 18: Continuous mode selection for regular conversions.
Bit 19: Launch regular conversion synchronously with DFSDM0.
Bit 21: DMA channel enabled to read data for the regular conversion.
Bits 24-26: Regular channel selection.
Bit 29: Fast conversion mode selection for regular conversions.
Bit 30: Analog watchdog fast mode select.
control register 2
Offset: 0x284, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AWDCH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXCH
rw |
CKABIE
rw |
SCDIE
rw |
AWDIE
rw |
ROVRIE
rw |
JOVRIE
rw |
REOCIE
rw |
JEOCIE
rw |
Bit 0: Injected end of conversion interrupt enable.
Bit 1: Regular end of conversion interrupt enable.
Bit 2: Injected data overrun interrupt enable.
Bit 3: Regular data overrun interrupt enable.
Bit 4: Analog watchdog interrupt enable.
Bit 5: Short-circuit detector interrupt enable.
Bit 6: Clock absence interrupt enable.
Bits 8-15: Extremes detector channel selection.
Bits 16-23: Analog watchdog channel selection.
interrupt and status register
Offset: 0x288, size: 32, reset: 0x00FF0000, access: read-only
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCDF
r |
CKABF
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCIP
r |
JCIP
r |
AWDF
r |
ROVRF
r |
JOVRF
r |
REOCF
r |
JEOCF
r |
Bit 0: End of injected conversion flag.
Bit 1: End of regular conversion flag.
Bit 2: Injected conversion overrun flag.
Bit 3: Regular conversion overrun flag.
Bit 4: Analog watchdog.
Bit 13: Injected conversion in progress status.
Bit 14: Regular conversion in progress status.
Bits 16-23: Clock absence flag.
Bits 24-31: short-circuit detector flag.
interrupt flag clear register
Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
injected channel group selection register
Offset: 0x290, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JCHG
rw |
filter control register
Offset: 0x294, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
data register for injected group
Offset: 0x298, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
data register for the regular channel
Offset: 0x29c, size: 32, reset: 0x00000000, access: read-only
3/3 fields covered.
analog watchdog high threshold register
Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog low threshold register
Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
analog watchdog status register
Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
analog watchdog clear flag register
Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Extremes detector maximum register
Offset: 0x2b0, size: 32, reset: 0x80000000, access: read-only
2/2 fields covered.
Extremes detector minimum register
Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: read-only
2/2 fields covered.
0x40020000: Direct memory access controller
147/161 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ISR | ||||||||||||||||||||||||||||||||
0x4 | IFCR | ||||||||||||||||||||||||||||||||
0x8 | CR [1] | ||||||||||||||||||||||||||||||||
0xc | NDTR [1] | ||||||||||||||||||||||||||||||||
0x10 | PAR [1] | ||||||||||||||||||||||||||||||||
0x14 | MAR [1] | ||||||||||||||||||||||||||||||||
0x1c | CR [2] | ||||||||||||||||||||||||||||||||
0x20 | NDTR [2] | ||||||||||||||||||||||||||||||||
0x24 | PAR [2] | ||||||||||||||||||||||||||||||||
0x28 | MAR [2] | ||||||||||||||||||||||||||||||||
0x30 | CR [3] | ||||||||||||||||||||||||||||||||
0x34 | NDTR [3] | ||||||||||||||||||||||||||||||||
0x38 | PAR [3] | ||||||||||||||||||||||||||||||||
0x3c | MAR [3] | ||||||||||||||||||||||||||||||||
0x44 | CR [4] | ||||||||||||||||||||||||||||||||
0x48 | NDTR [4] | ||||||||||||||||||||||||||||||||
0x4c | PAR [4] | ||||||||||||||||||||||||||||||||
0x50 | MAR [4] | ||||||||||||||||||||||||||||||||
0x58 | CR [5] | ||||||||||||||||||||||||||||||||
0x5c | NDTR [5] | ||||||||||||||||||||||||||||||||
0x60 | PAR [5] | ||||||||||||||||||||||||||||||||
0x64 | MAR [5] | ||||||||||||||||||||||||||||||||
0x6c | CR [6] | ||||||||||||||||||||||||||||||||
0x70 | NDTR [6] | ||||||||||||||||||||||||||||||||
0x74 | PAR [6] | ||||||||||||||||||||||||||||||||
0x78 | MAR [6] | ||||||||||||||||||||||||||||||||
0x80 | CR [7] | ||||||||||||||||||||||||||||||||
0x84 | NDTR [7] | ||||||||||||||||||||||||||||||||
0x88 | PAR [7] | ||||||||||||||||||||||||||||||||
0x8c | MAR [7] |
interrupt status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEIF[7]
r |
HTIF[7]
r |
TCIF[7]
r |
GIF[7]
r |
TEIF[6]
r |
HTIF[6]
r |
TCIF[6]
r |
GIF[6]
r |
TEIF[5]
r |
HTIF[5]
r |
TCIF[5]
r |
GIF[5]
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEIF[4]
r |
HTIF[4]
r |
TCIF[4]
r |
GIF[4]
r |
TEIF[3]
r |
HTIF[3]
r |
TCIF[3]
r |
GIF[3]
r |
TEIF[2]
r |
HTIF[2]
r |
TCIF[2]
r |
GIF[2]
r |
TEIF[1]
r |
HTIF[1]
r |
TCIF[1]
r |
GIF[1]
r |
Bit 0: Channel 1 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 1: Channel 1 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 2: Channel 1 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 3: Channel 1 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 4: Channel 2 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 5: Channel 2 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 6: Channel 2 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 7: Channel 2 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 8: Channel 3 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 9: Channel 3 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 10: Channel 3 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 11: Channel 3 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 12: Channel 4 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 13: Channel 4 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 14: Channel 4 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 15: Channel 4 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 16: Channel 5 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 17: Channel 5 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 18: Channel 5 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 19: Channel 5 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 20: Channel 6 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 21: Channel 6 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 22: Channel 6 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 23: Channel 6 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 24: Channel 7 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 25: Channel 7 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 26: Channel 7 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 27: Channel 7 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
interrupt flag clear register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CTEIF[7]
w |
CHTIF[7]
w |
CTCIF[7]
w |
CGIF[7]
w |
CTEIF[6]
w |
CHTIF[6]
w |
CTCIF[6]
w |
CGIF[6]
w |
CTEIF[5]
w |
CHTIF[5]
w |
CTCIF[5]
w |
CGIF[5]
w |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTEIF[4]
w |
CHTIF[4]
w |
CTCIF[4]
w |
CGIF[4]
w |
CTEIF[3]
w |
CHTIF[3]
w |
CTCIF[3]
w |
CGIF[3]
w |
CTEIF[2]
w |
CHTIF[2]
w |
CTCIF[2]
w |
CGIF[2]
w |
CTEIF[1]
w |
CHTIF[1]
w |
CTCIF[1]
w |
CGIF[1]
w |
Bit 0: Channel 1 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 1: Channel 1 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 2: Channel 1 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 3: Channel 1 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 4: Channel 2 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 5: Channel 2 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 6: Channel 2 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 7: Channel 2 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 8: Channel 3 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 9: Channel 3 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 10: Channel 3 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 11: Channel 3 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 12: Channel 4 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 13: Channel 4 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 14: Channel 4 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 15: Channel 4 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 16: Channel 5 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 17: Channel 5 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 18: Channel 5 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 19: Channel 5 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 20: Channel 6 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 21: Channel 6 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 22: Channel 6 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 23: Channel 6 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 24: Channel 7 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 25: Channel 7 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 26: Channel 7 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 27: Channel 7 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
channel x configuration register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
0x40020400: Direct memory access controller
147/161 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ISR | ||||||||||||||||||||||||||||||||
0x4 | IFCR | ||||||||||||||||||||||||||||||||
0x8 | CR [1] | ||||||||||||||||||||||||||||||||
0xc | NDTR [1] | ||||||||||||||||||||||||||||||||
0x10 | PAR [1] | ||||||||||||||||||||||||||||||||
0x14 | MAR [1] | ||||||||||||||||||||||||||||||||
0x1c | CR [2] | ||||||||||||||||||||||||||||||||
0x20 | NDTR [2] | ||||||||||||||||||||||||||||||||
0x24 | PAR [2] | ||||||||||||||||||||||||||||||||
0x28 | MAR [2] | ||||||||||||||||||||||||||||||||
0x30 | CR [3] | ||||||||||||||||||||||||||||||||
0x34 | NDTR [3] | ||||||||||||||||||||||||||||||||
0x38 | PAR [3] | ||||||||||||||||||||||||||||||||
0x3c | MAR [3] | ||||||||||||||||||||||||||||||||
0x44 | CR [4] | ||||||||||||||||||||||||||||||||
0x48 | NDTR [4] | ||||||||||||||||||||||||||||||||
0x4c | PAR [4] | ||||||||||||||||||||||||||||||||
0x50 | MAR [4] | ||||||||||||||||||||||||||||||||
0x58 | CR [5] | ||||||||||||||||||||||||||||||||
0x5c | NDTR [5] | ||||||||||||||||||||||||||||||||
0x60 | PAR [5] | ||||||||||||||||||||||||||||||||
0x64 | MAR [5] | ||||||||||||||||||||||||||||||||
0x6c | CR [6] | ||||||||||||||||||||||||||||||||
0x70 | NDTR [6] | ||||||||||||||||||||||||||||||||
0x74 | PAR [6] | ||||||||||||||||||||||||||||||||
0x78 | MAR [6] | ||||||||||||||||||||||||||||||||
0x80 | CR [7] | ||||||||||||||||||||||||||||||||
0x84 | NDTR [7] | ||||||||||||||||||||||||||||||||
0x88 | PAR [7] | ||||||||||||||||||||||||||||||||
0x8c | MAR [7] |
interrupt status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEIF[7]
r |
HTIF[7]
r |
TCIF[7]
r |
GIF[7]
r |
TEIF[6]
r |
HTIF[6]
r |
TCIF[6]
r |
GIF[6]
r |
TEIF[5]
r |
HTIF[5]
r |
TCIF[5]
r |
GIF[5]
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEIF[4]
r |
HTIF[4]
r |
TCIF[4]
r |
GIF[4]
r |
TEIF[3]
r |
HTIF[3]
r |
TCIF[3]
r |
GIF[3]
r |
TEIF[2]
r |
HTIF[2]
r |
TCIF[2]
r |
GIF[2]
r |
TEIF[1]
r |
HTIF[1]
r |
TCIF[1]
r |
GIF[1]
r |
Bit 0: Channel 1 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 1: Channel 1 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 2: Channel 1 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 3: Channel 1 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 4: Channel 2 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 5: Channel 2 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 6: Channel 2 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 7: Channel 2 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 8: Channel 3 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 9: Channel 3 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 10: Channel 3 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 11: Channel 3 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 12: Channel 4 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 13: Channel 4 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 14: Channel 4 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 15: Channel 4 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 16: Channel 5 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 17: Channel 5 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 18: Channel 5 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 19: Channel 5 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 20: Channel 6 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 21: Channel 6 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 22: Channel 6 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 23: Channel 6 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
Bit 24: Channel 7 Global interrupt flag.
Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured
Bit 25: Channel 7 Transfer Complete flag.
Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured
Bit 26: Channel 7 Half Transfer Complete flag.
Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured
Bit 27: Channel 7 Transfer Error flag.
Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured
interrupt flag clear register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CTEIF[7]
w |
CHTIF[7]
w |
CTCIF[7]
w |
CGIF[7]
w |
CTEIF[6]
w |
CHTIF[6]
w |
CTCIF[6]
w |
CGIF[6]
w |
CTEIF[5]
w |
CHTIF[5]
w |
CTCIF[5]
w |
CGIF[5]
w |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTEIF[4]
w |
CHTIF[4]
w |
CTCIF[4]
w |
CGIF[4]
w |
CTEIF[3]
w |
CHTIF[3]
w |
CTCIF[3]
w |
CGIF[3]
w |
CTEIF[2]
w |
CHTIF[2]
w |
CTCIF[2]
w |
CGIF[2]
w |
CTEIF[1]
w |
CHTIF[1]
w |
CTCIF[1]
w |
CGIF[1]
w |
Bit 0: Channel 1 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 1: Channel 1 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 2: Channel 1 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 3: Channel 1 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 4: Channel 2 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 5: Channel 2 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 6: Channel 2 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 7: Channel 2 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 8: Channel 3 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 9: Channel 3 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 10: Channel 3 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 11: Channel 3 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 12: Channel 4 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 13: Channel 4 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 14: Channel 4 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 15: Channel 4 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 16: Channel 5 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 17: Channel 5 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 18: Channel 5 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 19: Channel 5 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 20: Channel 6 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 21: Channel 6 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 22: Channel 6 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 23: Channel 6 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
Bit 24: Channel 7 Global interrupt clear.
Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
Bit 25: Channel 7 Transfer Complete clear.
Allowed values:
1: Clear: Clears the TCIF flag in the ISR register
Bit 26: Channel 7 Half Transfer clear.
Allowed values:
1: Clear: Clears the HTIF flag in the ISR register
Bit 27: Channel 7 Transfer Error clear.
Allowed values:
1: Clear: Clears the TEIF flag in the ISR register
channel x configuration register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
channel x peripheral address register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x memory address register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
channel x configuration register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MEM2MEM
rw |
PL
rw |
MSIZE
rw |
PSIZE
rw |
MINC
rw |
PINC
rw |
CIRC
rw |
DIR
rw |
TEIE
rw |
HTIE
rw |
TCIE
rw |
EN
rw |
Bit 0: Channel enable.
Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled
Bit 1: Transfer complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 2: Half transfer interrupt enable.
Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled
Bit 3: Transfer error interrupt enable.
Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled
Bit 4: Data transfer direction.
Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory
Bit 5: Circular mode.
Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled
Bit 6: Peripheral increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bit 7: Memory increment mode.
Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled
Bits 8-9: Peripheral size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 10-11: Memory size.
Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size
Bits 12-13: Channel priority level.
Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority
Bit 14: Memory to memory mode.
Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled
channel x number of data register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NDT
rw |
0x4002b000: DMA2D controller
48/72 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | ISR | ||||||||||||||||||||||||||||||||
0x8 | IFCR | ||||||||||||||||||||||||||||||||
0xc | FGMAR | ||||||||||||||||||||||||||||||||
0x10 | FGOR | ||||||||||||||||||||||||||||||||
0x14 | BGMAR | ||||||||||||||||||||||||||||||||
0x18 | BGOR | ||||||||||||||||||||||||||||||||
0x1c | FGPFCCR | ||||||||||||||||||||||||||||||||
0x20 | FGCOLR | ||||||||||||||||||||||||||||||||
0x24 | BGPFCCR | ||||||||||||||||||||||||||||||||
0x28 | BGCOLR | ||||||||||||||||||||||||||||||||
0x2c | FGCMAR | ||||||||||||||||||||||||||||||||
0x30 | BGCMAR | ||||||||||||||||||||||||||||||||
0x34 | OPFCCR | ||||||||||||||||||||||||||||||||
0x38 | OCOLR | ||||||||||||||||||||||||||||||||
0x3c | OMAR | ||||||||||||||||||||||||||||||||
0x40 | OOR | ||||||||||||||||||||||||||||||||
0x44 | NLR | ||||||||||||||||||||||||||||||||
0x48 | LWR | ||||||||||||||||||||||||||||||||
0x4c | AMTCR | ||||||||||||||||||||||||||||||||
0x400 | FGCLUT | ||||||||||||||||||||||||||||||||
0x800 | BGCLUT |
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
10/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CEIE
rw |
CTCIE
rw |
CAEIE
rw |
TWIE
rw |
TCIE
rw |
TEIE
rw |
ABORT
rw |
SUSP
rw |
START
rw |
Bit 0: Start.
Allowed values:
1: Start: Launch the DMA2D
Bit 1: Suspend.
Allowed values:
0: NotSuspended: Transfer not suspended
1: Suspended: Transfer suspended
Bit 2: Abort.
Allowed values:
1: AbortRequest: Transfer abort requested
Bit 8: Transfer error interrupt enable.
Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled
Bit 9: Transfer complete interrupt enable.
Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled
Bit 10: Transfer watermark interrupt enable.
Allowed values:
0: Disabled: TW interrupt disabled
1: Enabled: TW interrupt enabled
Bit 11: CLUT access error interrupt enable.
Allowed values:
0: Disabled: CAE interrupt disabled
1: Enabled: CAE interrupt enabled
Bit 12: CLUT transfer complete interrupt enable.
Allowed values:
0: Disabled: CTC interrupt disabled
1: Enabled: CTC interrupt enabled
Bit 13: Configuration Error Interrupt Enable.
Allowed values:
0: Disabled: CE interrupt disabled
1: Enabled: CE interrupt enabled
Bits 16-17: DMA2D mode.
Allowed values:
0: MemoryToMemory: Memory-to-memory (FG fetch only)
1: MemoryToMemoryPFC: Memory-to-memory with PFC (FG fetch only with FG PFC active)
2: MemoryToMemoryPFCBlending: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
3: RegisterToMemory: Register-to-memory
Interrupt Status Register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-only
6/6 fields covered.
interrupt flag clear register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
6/6 fields covered.
Bit 0: Clear Transfer error interrupt flag.
Allowed values:
1: Clear: Clear the TEIF flag in the ISR register
Bit 1: Clear transfer complete interrupt flag.
Allowed values:
1: Clear: Clear the TCIF flag in the ISR register
Bit 2: Clear transfer watermark interrupt flag.
Allowed values:
1: Clear: Clear the TWIF flag in the ISR register
Bit 3: Clear CLUT access error interrupt flag.
Allowed values:
1: Clear: Clear the CAEIF flag in the ISR register
Bit 4: Clear CLUT transfer complete interrupt flag.
Allowed values:
1: Clear: Clear the CTCIF flag in the ISR register
Bit 5: Clear configuration error interrupt flag.
Allowed values:
1: Clear: Clear the CEIF flag in the ISR register
foreground memory address register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
foreground offset register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LO
rw |
background memory address register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
background offset register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LO
rw |
foreground PFC control register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
6/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALPHA
rw |
RBS
rw |
AI
rw |
AM
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CS
rw |
START
rw |
CCM
rw |
CM
rw |
Bits 0-3: Color mode.
Allowed values:
0: ARGB8888: Color mode ARGB8888
1: RGB888: Color mode RGB888
2: RGB565: Color mode RGB565
3: ARGB1555: Color mode ARGB1555
4: ARGB4444: Color mode ARGB4444
5: L8: Color mode L8
6: AL44: Color mode AL44
7: AL88: Color mode AL88
8: L4: Color mode L4
9: A8: Color mode A8
10: A4: Color mode A4
Bit 4: CLUT color mode.
Allowed values:
0: ARGB8888: CLUT color format ARGB8888
1: RGB888: CLUT color format RGB888
Bit 5: Start.
Allowed values:
1: Start: Start the automatic loading of the CLUT
Bits 8-15: CLUT size.
Allowed values: 0x0-0xff
Bits 16-17: Alpha mode.
Allowed values:
0: NoModify: No modification of alpha channel
1: Replace: Replace with value in ALPHA[7:0]
2: Multiply: Multiply with value in ALPHA[7:0]
Bit 20: Alpha Inverted.
Bit 21: Red Blue Swap.
Bits 24-31: Alpha value.
Allowed values: 0x0-0xff
foreground color register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
background PFC control register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
6/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALPHA
rw |
RBS
rw |
AI
rw |
AM
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CS
rw |
START
rw |
CCM
rw |
CM
rw |
Bits 0-3: Color mode.
Allowed values:
0: ARGB8888: Color mode ARGB8888
1: RGB888: Color mode RGB888
2: RGB565: Color mode RGB565
3: ARGB1555: Color mode ARGB1555
4: ARGB4444: Color mode ARGB4444
5: L8: Color mode L8
6: AL44: Color mode AL44
7: AL88: Color mode AL88
8: L4: Color mode L4
9: A8: Color mode A8
10: A4: Color mode A4
Bit 4: CLUT Color mode.
Allowed values:
0: ARGB8888: CLUT color format ARGB8888
1: RGB888: CLUT color format RGB888
Bit 5: Start.
Allowed values:
1: Start: Start the automatic loading of the CLUT
Bits 8-15: CLUT size.
Allowed values: 0x0-0xff
Bits 16-17: Alpha mode.
Allowed values:
0: NoModify: No modification of alpha channel
1: Replace: Replace with value in ALPHA[7:0]
2: Multiply: Multiply with value in ALPHA[7:0]
Bit 20: Alpha Inverted.
Bit 21: Red Blue Swap.
Bits 24-31: Alpha value.
Allowed values: 0x0-0xff
background color register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
foreground CLUT memory address register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
background CLUT memory address register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
output PFC control register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
1/3 fields covered.
output color register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
output memory address register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
output offset register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LO
rw |
number of line register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
line watermark register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LW
rw |
AHB master timer configuration register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
FGCLUT
Offset: 0x400, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
0x40020800: DMA request multiplexer
122/154 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CCR[0] | ||||||||||||||||||||||||||||||||
0x4 | CCR[1] | ||||||||||||||||||||||||||||||||
0x8 | CCR[2] | ||||||||||||||||||||||||||||||||
0xc | CCR[3] | ||||||||||||||||||||||||||||||||
0x10 | CCR[4] | ||||||||||||||||||||||||||||||||
0x14 | CCR[5] | ||||||||||||||||||||||||||||||||
0x18 | CCR[6] | ||||||||||||||||||||||||||||||||
0x1c | CCR[7] | ||||||||||||||||||||||||||||||||
0x20 | CCR[8] | ||||||||||||||||||||||||||||||||
0x24 | CCR[9] | ||||||||||||||||||||||||||||||||
0x28 | CCR[10] | ||||||||||||||||||||||||||||||||
0x2c | CCR[11] | ||||||||||||||||||||||||||||||||
0x30 | CCR[12] | ||||||||||||||||||||||||||||||||
0x34 | CCR[13] | ||||||||||||||||||||||||||||||||
0x80 | CSR | ||||||||||||||||||||||||||||||||
0x84 | CFR | ||||||||||||||||||||||||||||||||
0x100 | RGCR[0] | ||||||||||||||||||||||||||||||||
0x104 | RGCR[1] | ||||||||||||||||||||||||||||||||
0x108 | RGCR[2] | ||||||||||||||||||||||||||||||||
0x10c | RGCR[3] | ||||||||||||||||||||||||||||||||
0x140 | RGSR | ||||||||||||||||||||||||||||||||
0x144 | RGCFR |
DMA Multiplexer Channel 0 Control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 1 Control register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 2 Control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 3 Control register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 4 Control register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 5 Control register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 6 Control register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 7 Control register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 8 Control register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 9 Control register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 10 Control register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 11 Control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 12 Control register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
DMA Multiplexer Channel 13 Control register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
5/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYNC_ID
rw |
NBREQ
rw |
SPOL
rw |
SE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EGE
rw |
SOIE
rw |
DMAREQ_ID
rw |
Bits 0-6: DMA request identification.
Bit 8: Synchronization overrun interrupt enable.
Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled
Bit 9: Event generation enable.
Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled
Bit 16: Synchronization enable.
Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled
Bits 17-18: Synchronization polarity.
Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests minus 1 to forward.
Allowed values: 0x0-0x1f
Bits 24-28: Synchronization identification.
channel status register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-only
14/14 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SOF[13]
r |
SOF[12]
r |
SOF[11]
r |
SOF[10]
r |
SOF[9]
r |
SOF[8]
r |
SOF[7]
r |
SOF[6]
r |
SOF[5]
r |
SOF[4]
r |
SOF[3]
r |
SOF[2]
r |
SOF[1]
r |
SOF[0]
r |
Bit 0: Synchronization Overrun Flag 0.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 1: Synchronization Overrun Flag 1.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 2: Synchronization Overrun Flag 2.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 3: Synchronization Overrun Flag 3.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 4: Synchronization Overrun Flag 4.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 5: Synchronization Overrun Flag 5.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 6: Synchronization Overrun Flag 6.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 7: Synchronization Overrun Flag 7.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 8: Synchronization Overrun Flag 8.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 9: Synchronization Overrun Flag 9.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 10: Synchronization Overrun Flag 10.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 11: Synchronization Overrun Flag 11.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 12: Synchronization Overrun Flag 12.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
Bit 13: Synchronization Overrun Flag 13.
Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
clear flag register
Offset: 0x84, size: 32, reset: 0x00000000, access: write-only
14/14 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CSOF[13]
w1c |
CSOF[12]
w1c |
CSOF[11]
w1c |
CSOF[10]
w1c |
CSOF[9]
w1c |
CSOF[8]
w1c |
CSOF[7]
w1c |
CSOF[6]
w1c |
CSOF[5]
w1c |
CSOF[4]
w1c |
CSOF[3]
w1c |
CSOF[2]
w1c |
CSOF[1]
w1c |
CSOF[0]
w1c |
Bit 0: Synchronization Clear Overrun Flag 0.
Allowed values:
1: Clear: Clear synchronization flag
Bit 1: Synchronization Clear Overrun Flag 1.
Allowed values:
1: Clear: Clear synchronization flag
Bit 2: Synchronization Clear Overrun Flag 2.
Allowed values:
1: Clear: Clear synchronization flag
Bit 3: Synchronization Clear Overrun Flag 3.
Allowed values:
1: Clear: Clear synchronization flag
Bit 4: Synchronization Clear Overrun Flag 4.
Allowed values:
1: Clear: Clear synchronization flag
Bit 5: Synchronization Clear Overrun Flag 5.
Allowed values:
1: Clear: Clear synchronization flag
Bit 6: Synchronization Clear Overrun Flag 6.
Allowed values:
1: Clear: Clear synchronization flag
Bit 7: Synchronization Clear Overrun Flag 7.
Allowed values:
1: Clear: Clear synchronization flag
Bit 8: Synchronization Clear Overrun Flag 8.
Allowed values:
1: Clear: Clear synchronization flag
Bit 9: Synchronization Clear Overrun Flag 9.
Allowed values:
1: Clear: Clear synchronization flag
Bit 10: Synchronization Clear Overrun Flag 10.
Allowed values:
1: Clear: Clear synchronization flag
Bit 11: Synchronization Clear Overrun Flag 11.
Allowed values:
1: Clear: Clear synchronization flag
Bit 12: Synchronization Clear Overrun Flag 12.
Allowed values:
1: Clear: Clear synchronization flag
Bit 13: Synchronization Clear Overrun Flag 13.
Allowed values:
1: Clear: Clear synchronization flag
request generator channel 0 configuration register
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
4/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GNBREQ
rw |
GPOL
rw |
GE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIE
rw |
SIG_ID
rw |
Bits 0-4: Signal identification.
Bit 8: Trigger overrun interrupt enable.
Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled
Bit 16: DMA request generator channel 0 enable.
Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled
Bits 17-18: DMA request generator trigger polarity.
Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests to be generated minus 1.
Allowed values: 0x0-0x1f
request generator channel 1 configuration register
Offset: 0x104, size: 32, reset: 0x00000000, access: read-write
4/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GNBREQ
rw |
GPOL
rw |
GE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIE
rw |
SIG_ID
rw |
Bits 0-4: Signal identification.
Bit 8: Trigger overrun interrupt enable.
Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled
Bit 16: DMA request generator channel 0 enable.
Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled
Bits 17-18: DMA request generator trigger polarity.
Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests to be generated minus 1.
Allowed values: 0x0-0x1f
request generator channel 2 configuration register
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
4/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GNBREQ
rw |
GPOL
rw |
GE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIE
rw |
SIG_ID
rw |
Bits 0-4: Signal identification.
Bit 8: Trigger overrun interrupt enable.
Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled
Bit 16: DMA request generator channel 0 enable.
Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled
Bits 17-18: DMA request generator trigger polarity.
Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests to be generated minus 1.
Allowed values: 0x0-0x1f
request generator channel 3 configuration register
Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write
4/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GNBREQ
rw |
GPOL
rw |
GE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIE
rw |
SIG_ID
rw |
Bits 0-4: Signal identification.
Bit 8: Trigger overrun interrupt enable.
Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled
Bit 16: DMA request generator channel 0 enable.
Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled
Bits 17-18: DMA request generator trigger polarity.
Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges
Bits 19-23: Number of DMA requests to be generated minus 1.
Allowed values: 0x0-0x1f
request generator interrupt status register
Offset: 0x140, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
Bit 0: Generator Overrun Flag 0.
Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun
Bit 1: Generator Overrun Flag 1.
Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun
Bit 2: Generator Overrun Flag 2.
Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun
Bit 3: Generator Overrun Flag 3.
Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun
request generator interrupt clear flag register
Offset: 0x144, size: 32, reset: 0x00000000, access: write-only
4/4 fields covered.
Bit 0: Generator Clear Overrun Flag 0.
Allowed values:
1: Clear: Clear overrun flag
Bit 1: Generator Clear Overrun Flag 1.
Allowed values:
1: Clear: Clear overrun flag
Bit 2: Generator Clear Overrun Flag 2.
Allowed values:
1: Clear: Clear overrun flag
Bit 3: Generator Clear Overrun Flag 3.
Allowed values:
1: Clear: Clear overrun flag
0x40016c00: DSI Host
82/303 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | VR | ||||||||||||||||||||||||||||||||
0x4 | CR | ||||||||||||||||||||||||||||||||
0x8 | CCR | ||||||||||||||||||||||||||||||||
0xc | LVCIDR | ||||||||||||||||||||||||||||||||
0x10 | LCOLCR | ||||||||||||||||||||||||||||||||
0x14 | LPCR | ||||||||||||||||||||||||||||||||
0x18 | LPMCR | ||||||||||||||||||||||||||||||||
0x2c | PCR | ||||||||||||||||||||||||||||||||
0x30 | GVCIDR | ||||||||||||||||||||||||||||||||
0x34 | MCR | ||||||||||||||||||||||||||||||||
0x38 | VMCR | ||||||||||||||||||||||||||||||||
0x3c | VPCR | ||||||||||||||||||||||||||||||||
0x40 | VCCR | ||||||||||||||||||||||||||||||||
0x44 | VNPCR | ||||||||||||||||||||||||||||||||
0x48 | VHSACR | ||||||||||||||||||||||||||||||||
0x4c | VHBPCR | ||||||||||||||||||||||||||||||||
0x50 | VLCR | ||||||||||||||||||||||||||||||||
0x54 | VVSACR | ||||||||||||||||||||||||||||||||
0x58 | VVBPCR | ||||||||||||||||||||||||||||||||
0x5c | VVFPCR | ||||||||||||||||||||||||||||||||
0x60 | VVACR | ||||||||||||||||||||||||||||||||
0x64 | LCCR | ||||||||||||||||||||||||||||||||
0x68 | CMCR | ||||||||||||||||||||||||||||||||
0x6c | GHCR | ||||||||||||||||||||||||||||||||
0x70 | GPDR | ||||||||||||||||||||||||||||||||
0x74 | GPSR | ||||||||||||||||||||||||||||||||
0x78 | TCCR0 | ||||||||||||||||||||||||||||||||
0x7c | TCCR1 | ||||||||||||||||||||||||||||||||
0x80 | TCCR2 | ||||||||||||||||||||||||||||||||
0x84 | TCCR3 | ||||||||||||||||||||||||||||||||
0x88 | TCCR4 | ||||||||||||||||||||||||||||||||
0x8c | TCCR5 | ||||||||||||||||||||||||||||||||
0x94 | CLCR | ||||||||||||||||||||||||||||||||
0x98 | CLTCR | ||||||||||||||||||||||||||||||||
0x9c | DLTRC | ||||||||||||||||||||||||||||||||
0xa0 | PCTLR | ||||||||||||||||||||||||||||||||
0xa4 | PCONFR | ||||||||||||||||||||||||||||||||
0xa8 | PUCR | ||||||||||||||||||||||||||||||||
0xac | PTTCR | ||||||||||||||||||||||||||||||||
0xb0 | PSR | ||||||||||||||||||||||||||||||||
0xbc | ISR0 | ||||||||||||||||||||||||||||||||
0xc0 | ISR1 | ||||||||||||||||||||||||||||||||
0xc4 | IER0 | ||||||||||||||||||||||||||||||||
0xc8 | IER1 | ||||||||||||||||||||||||||||||||
0xd8 | FIR0 | ||||||||||||||||||||||||||||||||
0xdc | FIR1 | ||||||||||||||||||||||||||||||||
0x100 | VSCR | ||||||||||||||||||||||||||||||||
0x10c | LCVCIDR | ||||||||||||||||||||||||||||||||
0x110 | LCCCR | ||||||||||||||||||||||||||||||||
0x118 | LPMCCR | ||||||||||||||||||||||||||||||||
0x138 | VMCCR | ||||||||||||||||||||||||||||||||
0x13c | VPCCR | ||||||||||||||||||||||||||||||||
0x140 | VCCCR | ||||||||||||||||||||||||||||||||
0x144 | VNPCCR | ||||||||||||||||||||||||||||||||
0x148 | VHSACCR | ||||||||||||||||||||||||||||||||
0x14c | VHBPCCR | ||||||||||||||||||||||||||||||||
0x150 | VLCCR | ||||||||||||||||||||||||||||||||
0x154 | VVSACCR | ||||||||||||||||||||||||||||||||
0x158 | VVBPCCR | ||||||||||||||||||||||||||||||||
0x15c | VVFPCCR | ||||||||||||||||||||||||||||||||
0x160 | VVACCR | ||||||||||||||||||||||||||||||||
0x400 | WCFGR | ||||||||||||||||||||||||||||||||
0x404 | WCR | ||||||||||||||||||||||||||||||||
0x408 | WIER | ||||||||||||||||||||||||||||||||
0x40c | WISR | ||||||||||||||||||||||||||||||||
0x410 | WIFCR | ||||||||||||||||||||||||||||||||
0x418 | WPCR0 | ||||||||||||||||||||||||||||||||
0x41c | WPCR1 | ||||||||||||||||||||||||||||||||
0x420 | WPCR2 | ||||||||||||||||||||||||||||||||
0x424 | WPCR3 | ||||||||||||||||||||||||||||||||
0x428 | WPCR4 | ||||||||||||||||||||||||||||||||
0x430 | WRPCR |
DSI Host Version Register
Offset: 0x0, size: 32, reset: 0x3133302A, access: read-only
1/1 fields covered.
DSI Host Control Register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EN
rw |
DSI HOST Clock Control Register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DSI Host LTDC VCID Register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VCID
rw |
DSI Host LTDC Color Coding Register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DSI Host LTDC Polarity Configuration Register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
DSI Host Low-Power mode Configuration Register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DSI Host Protocol Configuration Register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
DSI Host Generic VCID Register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VCID
rw |
DSI Host mode Configuration Register
Offset: 0x34, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMDM
rw |
DSI Host Video mode Configuration Register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PGO
rw |
PGM
rw |
PGE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPCE
rw |
FBTAAE
rw |
LPHFPE
rw |
LPHBPE
rw |
LPVAE
rw |
LPVFPE
rw |
LPVBPE
rw |
LPVSAE
rw |
VMT
rw |
Bits 0-1: Video mode Type.
Bit 8: Low-Power Vertical Sync Active Enable.
Bit 9: Low-power Vertical Back-Porch Enable.
Bit 10: Low-power Vertical Front-porch Enable.
Bit 11: Low-Power Vertical Active Enable.
Bit 12: Low-Power Horizontal Back-Porch Enable.
Bit 13: Low-Power Horizontal Front-Porch Enable.
Bit 14: Frame Bus-Turn-Around Acknowledge Enable.
Bit 15: Low-Power Command Enable.
Bit 16: Pattern Generator Enable.
Bit 20: Pattern Generator mode.
Bit 24: Pattern Generator Orientation.
DSI Host Video Packet Configuration Register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPSIZE
rw |
DSI Host Video Chunks Configuration Register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NUMC
rw |
DSI Host Video Null Packet Configuration Register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NPSIZE
rw |
DSI Host Video HSA Configuration Register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HSA
rw |
DSI Host Video HBP Configuration Register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HBP
rw |
DSI Host Video Line Configuration Register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HLINE
rw |
DSI Host Video VSA Configuration Register
Offset: 0x54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VSA
rw |
DSI Host Video VBP Configuration Register
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VBP
rw |
DSI Host Video VFP Configuration Register
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VFP
rw |
DSI Host Video VA Configuration Register
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VA
rw |
DSI Host LTDC Command Configuration Register
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMDSIZE
rw |
DSI Host Command mode Configuration Register
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MRDPS
rw |
DLWTX
rw |
DSR0TX
rw |
DSW1TX
rw |
DSW0TX
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GLWTX
rw |
GSR2TX
rw |
GSR1TX
rw |
GSR0TX
rw |
GSW2TX
rw |
GSW1TX
rw |
GSW0TX
rw |
ARE
rw |
TEARE
rw |
Bit 0: Tearing Effect Acknowledge Request Enable.
Bit 1: Acknowledge Request Enable.
Bit 8: Generic Short Write Zero parameters Transmission.
Bit 9: Generic Short Write One parameters Transmission.
Bit 10: Generic Short Write Two parameters Transmission.
Bit 11: Generic Short Read Zero parameters Transmission.
Bit 12: Generic Short Read One parameters Transmission.
Bit 13: Generic Short Read Two parameters Transmission.
Bit 14: Generic Long Write Transmission.
Bit 16: DCS Short Write Zero parameter Transmission.
Bit 17: DCS Short Read One parameter Transmission.
Bit 18: DCS Short Read Zero parameter Transmission.
Bit 19: DCS Long Write Transmission.
Bit 24: Maximum Read Packet Size.
DSI Host Generic Header Configuration Register
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
DSI Host Generic Payload Data Register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
DSI Host Generic Packet Status Register
Offset: 0x74, size: 32, reset: 0x00000015, access: read-only
7/7 fields covered.
DSI Host Timeout Counter Configuration Register 0
Offset: 0x78, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HSTX_TOCNT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPRX_TOCNT
rw |
DSI Host Timeout Counter Configuration Register 1
Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HSRD_TOCNT
rw |
DSI Host Timeout Counter Configuration Register 2
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPRD_TOCNT
rw |
DSI Host Timeout Counter Configuration Register 3
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PM
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HSWR_TOCNT
rw |
DSI Host Timeout Counter Configuration Register 4
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LSWR_TOCNT
rw |
DSI Host Timeout Counter Configuration Register 5
Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BTA_TOCNT
rw |
DSI Host Clock Lane Configuration Register
Offset: 0x94, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DSI Host Clock Lane Timer Configuration Register
Offset: 0x98, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HS2LP_TIME
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LP2HS_TIME
rw |
DSI Host Data Lane Timer Configuration Register
Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HS2LP_TIME
rw |
LP2HS_TIME
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MRD_TIME
rw |
DSI Host PHY Control Register
Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DSI Host PHY Configuration Register
Offset: 0xa4, size: 32, reset: 0x00000001, access: read-write
0/2 fields covered.
DSI Host PHY ULPS Control Register
Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
DSI Host PHY TX Triggers Configuration Register
Offset: 0xac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TX_TRIG
rw |
DSI Host PHY Status Register
Offset: 0xb0, size: 32, reset: 0x00001528, access: read-only
8/8 fields covered.
DSI Host Interrupt & Status Register 0
Offset: 0xbc, size: 32, reset: 0x00000000, access: read-only
21/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PE[4]
r |
PE[3]
r |
PE[2]
r |
PE[1]
r |
PE[0]
r |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AE[15]
r |
AE[14]
r |
AE[13]
r |
AE[12]
r |
AE[11]
r |
AE[10]
r |
AE[9]
r |
AE[8]
r |
AE[7]
r |
AE[6]
r |
AE[5]
r |
AE[4]
r |
AE[3]
r |
AE[2]
r |
AE[1]
r |
AE[0]
r |
Bit 0: Acknowledge error 0.
Bit 1: Acknowledge error 1.
Bit 2: Acknowledge error 2.
Bit 3: Acknowledge error 3.
Bit 4: Acknowledge error 4.
Bit 5: Acknowledge error 5.
Bit 6: Acknowledge error 6.
Bit 7: Acknowledge error 7.
Bit 8: Acknowledge error 8.
Bit 9: Acknowledge error 9.
Bit 10: Acknowledge error 10.
Bit 11: Acknowledge error 11.
Bit 12: Acknowledge error 12.
Bit 13: Acknowledge error 13.
Bit 14: Acknowledge error 14.
Bit 15: Acknowledge error 15.
Bit 16: PHY error 0.
Bit 17: PHY error 1.
Bit 18: PHY error 2.
Bit 19: PHY error 3.
Bit 20: PHY error 4.
DSI Host Interrupt & Status Register 1
Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only
13/13 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPRXE
r |
GPRDE
r |
GPTXE
r |
GPWRE
r |
GCWRE
r |
LPWRE
r |
EOTPE
r |
PSE
r |
CRCE
r |
ECCME
r |
ECCSE
r |
TOLPRX
r |
TOHSTX
r |
Bit 0: Timeout High-Speed Transmission.
Bit 1: Timeout Low-Power Reception.
Bit 2: ECC Single-bit Error.
Bit 3: ECC Multi-bit Error.
Bit 4: CRC Error.
Bit 5: Packet Size Error.
Bit 6: EoTp Error.
Bit 7: LTDC Payload Write Error.
Bit 8: Generic Command Write Error.
Bit 9: Generic Payload Write Error.
Bit 10: Generic Payload Transmit Error.
Bit 11: Generic Payload Read Error.
Bit 12: Generic Payload Receive Error.
DSI Host Interrupt Enable Register 0
Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write
0/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PE[4]IE
rw |
PE[3]IE
rw |
PE[2]IE
rw |
PE[1]IE
rw |
PE[0]IE
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AE[15]IE
rw |
AE[14]IE
rw |
AE[13]IE
rw |
AE[12]IE
rw |
AE[11]IE
rw |
AE[10]IE
rw |
AE[9]IE
rw |
AE[8]IE
rw |
AE[7]IE
rw |
AE[6]IE
rw |
AE[5]IE
rw |
AE[4]IE
rw |
AE[3]IE
rw |
AE[2]IE
rw |
AE[1]IE
rw |
AE[0]IE
rw |
Bit 0: Acknowledge error 0 interrupt enable.
Bit 1: Acknowledge error 1 interrupt enable.
Bit 2: Acknowledge error 2 interrupt enable.
Bit 3: Acknowledge error 3 interrupt enable.
Bit 4: Acknowledge error 4 interrupt enable.
Bit 5: Acknowledge error 5 interrupt enable.
Bit 6: Acknowledge error 6 interrupt enable.
Bit 7: Acknowledge error 7 interrupt enable.
Bit 8: Acknowledge error 8 interrupt enable.
Bit 9: Acknowledge error 9 interrupt enable.
Bit 10: Acknowledge error 10 interrupt enable.
Bit 11: Acknowledge error 11 interrupt enable.
Bit 12: Acknowledge error 12 interrupt enable.
Bit 13: Acknowledge error 13 interrupt enable.
Bit 14: Acknowledge error 14 interrupt enable.
Bit 15: Acknowledge error 15 interrupt enable.
Bit 16: PHY error 0 interrupt enable.
Bit 17: PHY error 1 interrupt enable.
Bit 18: PHY error 2 interrupt enable.
Bit 19: PHY error 3 interrupt enable.
Bit 20: PHY error 4 interrupt enable.
DSI Host Interrupt Enable Register 1
Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GPRXEIE
rw |
GPRDEIE
rw |
GPTXEIE
rw |
GPWREIE
rw |
GCWREIE
rw |
LPWREIE
rw |
EOTPEIE
rw |
PSEIE
rw |
CRCEIE
rw |
ECCMEIE
rw |
ECCSEIE
rw |
TOLPRXIE
rw |
TOHSTXIE
rw |
Bit 0: Timeout High-Speed Transmission Interrupt Enable.
Bit 1: Timeout Low-Power Reception Interrupt Enable.
Bit 2: ECC Single-bit Error Interrupt Enable.
Bit 3: ECC Multi-bit Error Interrupt Enable.
Bit 4: CRC Error Interrupt Enable.
Bit 5: Packet Size Error Interrupt Enable.
Bit 6: EoTp Error Interrupt Enable.
Bit 7: LTDC Payload Write Error Interrupt Enable.
Bit 8: Generic Command Write Error Interrupt Enable.
Bit 9: Generic Payload Write Error Interrupt Enable.
Bit 10: Generic Payload Transmit Error Interrupt Enable.
Bit 11: Generic Payload Read Error Interrupt Enable.
Bit 12: Generic Payload Receive Error Interrupt Enable.
DSI Host Force Interrupt Register 0
Offset: 0xd8, size: 32, reset: 0x00000000, access: write-only
0/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FPE[4]
w |
FPE[3]
w |
FPE[2]
w |
FPE[1]
w |
FPE[0]
w |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAE[15]
w |
FAE[14]
w |
FAE[13]
w |
FAE[12]
w |
FAE[11]
w |
FAE[10]
w |
FAE[9]
w |
FAE[8]
w |
FAE[7]
w |
FAE[6]
w |
FAE[5]
w |
FAE[4]
w |
FAE[3]
w |
FAE[2]
w |
FAE[1]
w |
FAE[0]
w |
Bit 0: Force acknowledge error 0.
Bit 1: Force acknowledge error 1.
Bit 2: Force acknowledge error 2.
Bit 3: Force acknowledge error 3.
Bit 4: Force acknowledge error 4.
Bit 5: Force acknowledge error 5.
Bit 6: Force acknowledge error 6.
Bit 7: Force acknowledge error 7.
Bit 8: Force acknowledge error 8.
Bit 9: Force acknowledge error 9.
Bit 10: Force acknowledge error 10.
Bit 11: Force acknowledge error 11.
Bit 12: Force acknowledge error 12.
Bit 13: Force acknowledge error 13.
Bit 14: Force acknowledge error 14.
Bit 15: Force acknowledge error 15.
Bit 16: Force PHY error 0.
Bit 17: Force PHY error 1.
Bit 18: Force PHY error 2.
Bit 19: Force PHY error 3.
Bit 20: Force PHY error 4.
DSI Host Force Interrupt Register 1
Offset: 0xdc, size: 32, reset: 0x00000000, access: write-only
0/13 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FGPRXE
w |
FGPRDE
w |
FGPTXE
w |
FGPWRE
w |
FGCWRE
w |
FLPWRE
w |
FEOTPE
w |
FPSE
w |
FCRCE
w |
FECCME
w |
FECCSE
w |
FTOLPRX
w |
FTOHSTX
w |
Bit 0: Force Timeout High-Speed Transmission.
Bit 1: Force Timeout Low-Power Reception.
Bit 2: Force ECC Single-bit Error.
Bit 3: Force ECC Multi-bit Error.
Bit 4: Force CRC Error.
Bit 5: Force Packet Size Error.
Bit 6: Force EoTp Error.
Bit 7: Force LTDC Payload Write Error.
Bit 8: Force Generic Command Write Error.
Bit 9: Force Generic Payload Write Error.
Bit 10: Force Generic Payload Transmit Error.
Bit 11: Force Generic Payload Read Error.
Bit 12: Force Generic Payload Receive Error.
DSI Host Video Shadow Control Register
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
DSI Host LTDC Current VCID Register
Offset: 0x10c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VCID
r |
DSI Host LTDC Current Color Coding Register
Offset: 0x110, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
DSI Host Low-Power mode Current Configuration Register
Offset: 0x118, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
DSI Host Video mode Current Configuration Register
Offset: 0x138, size: 32, reset: 0x00000000, access: read-only
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPCE
r |
FBTAAE
r |
LPHFE
r |
LPHBPE
r |
LPVAE
r |
LPVFPE
r |
LPVBPE
r |
LPVSAE
r |
VMT
r |
Bits 0-1: Video mode Type.
Bit 2: Low-Power Vertical Sync time Enable.
Bit 3: Low-power Vertical Back-Porch Enable.
Bit 4: Low-power Vertical Front-Porch Enable.
Bit 5: Low-Power Vertical Active Enable.
Bit 6: Low-power Horizontal Back-Porch Enable.
Bit 7: Low-Power Horizontal Front-Porch Enable.
Bit 8: Frame BTA Acknowledge Enable.
Bit 9: Low-Power Command Enable.
DSI Host Video Packet Current Configuration Register
Offset: 0x13c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPSIZE
r |
DSI Host Video Chunks Current Configuration Register
Offset: 0x140, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NUMC
r |
DSI Host Video Null Packet Current Configuration Register
Offset: 0x144, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NPSIZE
r |
DSI Host Video HSA Current Configuration Register
Offset: 0x148, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HSA
r |
DSI Host Video HBP Current Configuration Register
Offset: 0x14c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HBP
r |
DSI Host Video Line Current Configuration Register
Offset: 0x150, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HLINE
r |
DSI Host Video VSA Current Configuration Register
Offset: 0x154, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VSA
r |
DSI Host Video VBP Current Configuration Register
Offset: 0x158, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VBP
r |
DSI Host Video VFP Current Configuration Register
Offset: 0x15c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VFP
r |
DSI Host Video VA Current Configuration Register
Offset: 0x160, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VA
r |
DSI Wrapper Configuration Register
Offset: 0x400, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
DSI Wrapper Control Register
Offset: 0x404, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
DSI Wrapper Interrupt Enable Register
Offset: 0x408, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
DSI Wrapper Interrupt & Status Register
Offset: 0x40c, size: 32, reset: 0x00000000, access: read-only
8/8 fields covered.
Bit 0: Tearing Effect Interrupt Flag.
Bit 1: End of Refresh Interrupt Flag.
Bit 2: Busy Flag.
Bit 8: PLL Lock Status.
Bit 9: PLL Lock Interrupt Flag.
Bit 10: PLL Unlock Interrupt Flag.
Bit 12: Regulator Ready Status.
Bit 13: Regulator Ready Interrupt Flag.
DSI Wrapper Interrupt Flag Clear Register
Offset: 0x410, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
DSI Wrapper PHY Configuration Register 0
Offset: 0x418, size: 32, reset: 0x00000000, access: read-write
0/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TCLKPOSTEN
rw |
TLPXCEN
rw |
THSEXITEN
rw |
TLPXDEN
rw |
THSZEROEN
rw |
THSTRAILEN
rw |
THSPREPEN
rw |
TCLKZEROEN
rw |
TCLKPREPEN
rw |
PDEN
rw |
TDDL
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CDOFFDL
rw |
FTXSMDL
rw |
FTXSMCL
rw |
HSIDL1
rw |
HSIDL0
rw |
HSICL
rw |
SWDL1
rw |
SWDL0
rw |
SWCL
rw |
UIX4
rw |
Bits 0-5: Unit Interval multiplied by 4.
Bit 6: Swap Clock Lane pins.
Bit 7: Swap Data Lane 0 pins.
Bit 8: Swap Data Lane 1 pins.
Bit 9: Invert Hight-Speed data signal on Clock Lane.
Bit 10: Invert the Hight-Speed data signal on Data Lane 0.
Bit 11: Invert the High-Speed data signal on Data Lane 1.
Bit 12: Force in TX Stop Mode the Clock Lane.
Bit 13: Force in TX Stop Mode the Data Lanes.
Bit 14: Contention Detection OFF on Data Lanes.
Bit 16: Turn Disable Data Lanes.
Bit 18: Pull-Down Enable.
Bit 19: custom time for tCLK-PREPARE Enable.
Bit 20: custom time for tCLK-ZERO Enable.
Bit 21: custom time for tHS-PREPARE Enable.
Bit 22: custom time for tHS-TRAIL Enable.
Bit 23: custom time for tHS-ZERO Enable.
Bit 24: custom time for tLPX for Data lanes Enable.
Bit 25: custom time for tHS-EXIT Enable.
Bit 26: custom time for tLPX for Clock lane Enable.
Bit 27: custom time for tCLK-POST Enable.
DSI Wrapper PHY Configuration Register 1
Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPRXFT
rw |
FLPRXLPM
rw |
HSTXSRCDL
rw |
HSTXSRCCL
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SDCC
rw |
LPSRDL
rw |
LPSRCL
rw |
HSTXDLL
rw |
HSTXDCL
rw |
Bits 0-1: High-Speed Transmission Delay on Clock Lane.
Bits 2-3: High-Speed Transmission Delay on Data Lanes.
Bits 6-7: Low-Power transmission Slew Rate Compensation on Clock Lane.
Bits 8-9: Low-Power transmission Slew Rate Compensation on Data Lanes.
Bit 12: SDD Control.
Bits 16-17: High-Speed Transmission Slew Rate Control on Clock Lane.
Bits 18-19: High-Speed Transmission Slew Rate Control on Data Lanes.
Bit 22: Forces LP Receiver in Low-Power Mode.
Bits 25-26: Low-Power RX low-pass Filtering Tuning.
DSI Wrapper PHY Configuration Register 2
Offset: 0x420, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
DSI_WPCR3
Offset: 0x424, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
DSI Wrapper PHY Configuration Register 4
Offset: 0x428, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
THSZERO
rw |
0x40010400: External interrupt/event controller
184/184 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | IMR1 | ||||||||||||||||||||||||||||||||
0x4 | EMR1 | ||||||||||||||||||||||||||||||||
0x8 | RTSR1 | ||||||||||||||||||||||||||||||||
0xc | FTSR1 | ||||||||||||||||||||||||||||||||
0x10 | SWIER1 | ||||||||||||||||||||||||||||||||
0x14 | PR1 | ||||||||||||||||||||||||||||||||
0x20 | IMR2 | ||||||||||||||||||||||||||||||||
0x24 | EMR2 | ||||||||||||||||||||||||||||||||
0x28 | RTSR2 | ||||||||||||||||||||||||||||||||
0x2c | FTSR2 | ||||||||||||||||||||||||||||||||
0x30 | SWIER2 | ||||||||||||||||||||||||||||||||
0x34 | PR2 |
Interrupt mask register
Offset: 0x0, size: 32, reset: 0xFF820000, access: read-write
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MR31
rw |
MR30
rw |
MR29
rw |
MR28
rw |
MR27
rw |
MR26
rw |
MR25
rw |
MR24
rw |
MR23
rw |
MR22
rw |
MR21
rw |
MR20
rw |
MR19
rw |
MR18
rw |
MR17
rw |
MR16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MR15
rw |
MR14
rw |
MR13
rw |
MR12
rw |
MR11
rw |
MR10
rw |
MR9
rw |
MR8
rw |
MR7
rw |
MR6
rw |
MR5
rw |
MR4
rw |
MR3
rw |
MR2
rw |
MR1
rw |
MR0
rw |
Bit 0: Interrupt Mask on line 0.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 1: Interrupt Mask on line 1.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 2: Interrupt Mask on line 2.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 3: Interrupt Mask on line 3.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 4: Interrupt Mask on line 4.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 5: Interrupt Mask on line 5.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 6: Interrupt Mask on line 6.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 7: Interrupt Mask on line 7.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 8: Interrupt Mask on line 8.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 9: Interrupt Mask on line 9.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 10: Interrupt Mask on line 10.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 11: Interrupt Mask on line 11.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 12: Interrupt Mask on line 12.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 13: Interrupt Mask on line 13.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 14: Interrupt Mask on line 14.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 15: Interrupt Mask on line 15.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 16: Interrupt Mask on line 16.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 17: Interrupt Mask on line 17.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 18: Interrupt Mask on line 18.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 19: Interrupt Mask on line 19.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 20: Interrupt Mask on line 20.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 21: Interrupt Mask on line 21.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 22: Interrupt Mask on line 22.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 23: Interrupt Mask on line 23.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 24: Interrupt Mask on line 24.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 25: Interrupt Mask on line 25.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 26: Interrupt Mask on line 26.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 27: Interrupt Mask on line 27.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 28: Interrupt Mask on line 28.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 29: Interrupt Mask on line 29.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 30: Interrupt Mask on line 30.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 31: Interrupt Mask on line 31.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Event mask register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MR31
rw |
MR30
rw |
MR29
rw |
MR28
rw |
MR27
rw |
MR26
rw |
MR25
rw |
MR24
rw |
MR23
rw |
MR22
rw |
MR21
rw |
MR20
rw |
MR19
rw |
MR18
rw |
MR17
rw |
MR16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MR15
rw |
MR14
rw |
MR13
rw |
MR12
rw |
MR11
rw |
MR10
rw |
MR9
rw |
MR8
rw |
MR7
rw |
MR6
rw |
MR5
rw |
MR4
rw |
MR3
rw |
MR2
rw |
MR1
rw |
MR0
rw |
Bit 0: Event Mask on line 0.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 1: Event Mask on line 1.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 2: Event Mask on line 2.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 3: Event Mask on line 3.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 4: Event Mask on line 4.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 5: Event Mask on line 5.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 6: Event Mask on line 6.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 7: Event Mask on line 7.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 8: Event Mask on line 8.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 9: Event Mask on line 9.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 10: Event Mask on line 10.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 11: Event Mask on line 11.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 12: Event Mask on line 12.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 13: Event Mask on line 13.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 14: Event Mask on line 14.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 15: Event Mask on line 15.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 16: Event Mask on line 16.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 17: Event Mask on line 17.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 18: Event Mask on line 18.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 19: Event Mask on line 19.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 20: Event Mask on line 20.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 21: Event Mask on line 21.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 22: Event Mask on line 22.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 23: Event Mask on line 23.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 24: Event Mask on line 24.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 25: Event Mask on line 25.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 26: Event Mask on line 26.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 27: Event Mask on line 27.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 28: Event Mask on line 28.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 29: Event Mask on line 29.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 30: Event Mask on line 30.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 31: Event Mask on line 31.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Rising Trigger selection register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
22/22 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TR22
rw |
TR21
rw |
TR20
rw |
TR19
rw |
TR18
rw |
TR16
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TR15
rw |
TR14
rw |
TR13
rw |
TR12
rw |
TR11
rw |
TR10
rw |
TR9
rw |
TR8
rw |
TR7
rw |
TR6
rw |
TR5
rw |
TR4
rw |
TR3
rw |
TR2
rw |
TR1
rw |
TR0
rw |
Bit 0: Rising trigger event configuration of line 0.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 1: Rising trigger event configuration of line 1.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 2: Rising trigger event configuration of line 2.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 3: Rising trigger event configuration of line 3.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 4: Rising trigger event configuration of line 4.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 5: Rising trigger event configuration of line 5.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 6: Rising trigger event configuration of line 6.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 7: Rising trigger event configuration of line 7.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 8: Rising trigger event configuration of line 8.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 9: Rising trigger event configuration of line 9.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 10: Rising trigger event configuration of line 10.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 11: Rising trigger event configuration of line 11.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 12: Rising trigger event configuration of line 12.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 13: Rising trigger event configuration of line 13.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 14: Rising trigger event configuration of line 14.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 15: Rising trigger event configuration of line 15.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 16: Rising trigger event configuration of line 16.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 18: Rising trigger event configuration of line 18.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 19: Rising trigger event configuration of line 19.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 20: Rising trigger event configuration of line 20.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 21: Rising trigger event configuration of line 21.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 22: Rising trigger event configuration of line 22.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Falling Trigger selection register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
22/22 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TR22
rw |
TR21
rw |
TR20
rw |
TR19
rw |
TR18
rw |
TR16
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TR15
rw |
TR14
rw |
TR13
rw |
TR12
rw |
TR11
rw |
TR10
rw |
TR9
rw |
TR8
rw |
TR7
rw |
TR6
rw |
TR5
rw |
TR4
rw |
TR3
rw |
TR2
rw |
TR1
rw |
TR0
rw |
Bit 0: Falling trigger event configuration of line 0.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 1: Falling trigger event configuration of line 1.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 2: Falling trigger event configuration of line 2.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 3: Falling trigger event configuration of line 3.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 4: Falling trigger event configuration of line 4.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 5: Falling trigger event configuration of line 5.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 6: Falling trigger event configuration of line 6.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 7: Falling trigger event configuration of line 7.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 8: Falling trigger event configuration of line 8.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 9: Falling trigger event configuration of line 9.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 10: Falling trigger event configuration of line 10.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 11: Falling trigger event configuration of line 11.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 12: Falling trigger event configuration of line 12.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 13: Falling trigger event configuration of line 13.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 14: Falling trigger event configuration of line 14.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 15: Falling trigger event configuration of line 15.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 16: Falling trigger event configuration of line 16.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 18: Falling trigger event configuration of line 18.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 19: Falling trigger event configuration of line 19.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 20: Falling trigger event configuration of line 20.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 21: Falling trigger event configuration of line 21.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 22: Falling trigger event configuration of line 22.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Software interrupt event register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
22/22 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SWIER22
rw |
SWIER21
rw |
SWIER20
rw |
SWIER19
rw |
SWIER18
rw |
SWIER16
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWIER15
rw |
SWIER14
rw |
SWIER13
rw |
SWIER12
rw |
SWIER11
rw |
SWIER10
rw |
SWIER9
rw |
SWIER8
rw |
SWIER7
rw |
SWIER6
rw |
SWIER5
rw |
SWIER4
rw |
SWIER3
rw |
SWIER2
rw |
SWIER1
rw |
SWIER0
rw |
Bit 0: Software Interrupt on line 0.
Allowed values:
1: Pend: Generates an interrupt request
Bit 1: Software Interrupt on line 1.
Allowed values:
1: Pend: Generates an interrupt request
Bit 2: Software Interrupt on line 2.
Allowed values:
1: Pend: Generates an interrupt request
Bit 3: Software Interrupt on line 3.
Allowed values:
1: Pend: Generates an interrupt request
Bit 4: Software Interrupt on line 4.
Allowed values:
1: Pend: Generates an interrupt request
Bit 5: Software Interrupt on line 5.
Allowed values:
1: Pend: Generates an interrupt request
Bit 6: Software Interrupt on line 6.
Allowed values:
1: Pend: Generates an interrupt request
Bit 7: Software Interrupt on line 7.
Allowed values:
1: Pend: Generates an interrupt request
Bit 8: Software Interrupt on line 8.
Allowed values:
1: Pend: Generates an interrupt request
Bit 9: Software Interrupt on line 9.
Allowed values:
1: Pend: Generates an interrupt request
Bit 10: Software Interrupt on line 10.
Allowed values:
1: Pend: Generates an interrupt request
Bit 11: Software Interrupt on line 11.
Allowed values:
1: Pend: Generates an interrupt request
Bit 12: Software Interrupt on line 12.
Allowed values:
1: Pend: Generates an interrupt request
Bit 13: Software Interrupt on line 13.
Allowed values:
1: Pend: Generates an interrupt request
Bit 14: Software Interrupt on line 14.
Allowed values:
1: Pend: Generates an interrupt request
Bit 15: Software Interrupt on line 15.
Allowed values:
1: Pend: Generates an interrupt request
Bit 16: Software Interrupt on line 16.
Allowed values:
1: Pend: Generates an interrupt request
Bit 18: Software Interrupt on line 18.
Allowed values:
1: Pend: Generates an interrupt request
Bit 19: Software Interrupt on line 19.
Allowed values:
1: Pend: Generates an interrupt request
Bit 20: Software Interrupt on line 20.
Allowed values:
1: Pend: Generates an interrupt request
Bit 21: Software Interrupt on line 21.
Allowed values:
1: Pend: Generates an interrupt request
Bit 22: Software Interrupt on line 22.
Allowed values:
1: Pend: Generates an interrupt request
Pending register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
22/22 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PR22
r/w1c |
PR21
r/w1c |
PR20
r/w1c |
PR19
r/w1c |
PR18
r/w1c |
PR16
r/w1c |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PR15
r/w1c |
PR14
r/w1c |
PR13
r/w1c |
PR12
r/w1c |
PR11
r/w1c |
PR10
r/w1c |
PR9
r/w1c |
PR8
r/w1c |
PR7
r/w1c |
PR6
r/w1c |
PR5
r/w1c |
PR4
r/w1c |
PR3
r/w1c |
PR2
r/w1c |
PR1
r/w1c |
PR0
r/w1c |
Bit 0: Pending bit 0.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 1: Pending bit 1.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 2: Pending bit 2.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 3: Pending bit 3.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 4: Pending bit 4.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 5: Pending bit 5.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 6: Pending bit 6.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 7: Pending bit 7.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 8: Pending bit 8.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 9: Pending bit 9.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 10: Pending bit 10.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 11: Pending bit 11.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 12: Pending bit 12.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 13: Pending bit 13.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 14: Pending bit 14.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 15: Pending bit 15.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 16: Pending bit 16.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 18: Pending bit 18.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 19: Pending bit 19.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 20: Pending bit 20.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 21: Pending bit 21.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 22: Pending bit 22.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Interrupt mask register
Offset: 0x20, size: 32, reset: 0xFFFFFF87, access: read-write
8/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MR39
rw |
MR38
rw |
MR37
rw |
MR36
rw |
MR35
rw |
MR34
rw |
MR33
rw |
MR32
rw |
Bit 0: Interrupt Mask on external/internal line 32.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 1: Interrupt Mask on external/internal line 33.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 2: Interrupt Mask on external/internal line 34.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 3: Interrupt Mask on external/internal line 35.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 4: Interrupt Mask on external/internal line 36.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 5: Interrupt Mask on external/internal line 37.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 6: Interrupt Mask on external/internal line 38.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Bit 7: Interrupt Mask on external/internal line 39.
Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked
Event mask register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MR39
rw |
MR38
rw |
MR37
rw |
MR36
rw |
MR35
rw |
MR34
rw |
MR33
rw |
MR32
rw |
Bit 0: Event mask on external/internal line 32.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 1: Event mask on external/internal line 33.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 2: Event mask on external/internal line 34.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 3: Event mask on external/internal line 35.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 4: Event mask on external/internal line 36.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 5: Event mask on external/internal line 37.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 6: Event mask on external/internal line 38.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Bit 7: Event mask on external/internal line 39.
Allowed values:
0: Masked: Event request line is masked
1: Unmasked: Event request line is unmasked
Rising Trigger selection register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bit 3: Rising trigger event configuration bit of line 35.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 4: Rising trigger event configuration bit of line 36.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 5: Rising trigger event configuration bit of line 37.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Bit 6: Rising trigger event configuration bit of line 38.
Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled
Falling Trigger selection register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bit 3: Falling trigger event configuration bit of line 35.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 4: Falling trigger event configuration bit of line 36.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 5: Falling trigger event configuration bit of line 37.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Bit 6: Falling trigger event configuration bit of line 38.
Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled
Software interrupt event register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bit 3: Software interrupt on line 35.
Allowed values:
1: Pend: Generates an interrupt request
Bit 4: Software interrupt on line 36.
Allowed values:
1: Pend: Generates an interrupt request
Bit 5: Software interrupt on line 37.
Allowed values:
1: Pend: Generates an interrupt request
Bit 6: Software interrupt on line 38.
Allowed values:
1: Pend: Generates an interrupt request
Pending register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bit 3: Pending interrupt flag on line 35.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 4: Pending interrupt flag on line 36.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 5: Pending interrupt flag on line 37.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
Bit 6: Pending interrupt flag on line 38.
Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred
0x40011c00: Firewall
9/9 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CSSA | ||||||||||||||||||||||||||||||||
0x4 | CSL | ||||||||||||||||||||||||||||||||
0x8 | NVDSSA | ||||||||||||||||||||||||||||||||
0xc | NVDSL | ||||||||||||||||||||||||||||||||
0x10 | VDSSA | ||||||||||||||||||||||||||||||||
0x14 | VDSL | ||||||||||||||||||||||||||||||||
0x20 | CR |
Code segment start address
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
Code segment length
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
Non-volatile data segment start address
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
Non-volatile data segment length
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
Volatile data segment start address
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
Volatile data segment length
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LENG
rw |
Configuration register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bit 0: Firewall pre alarm.
Allowed values:
0: PreArmReset: Any code executed outside the protected segment when the Firewall is opened will generate a system reset
1: PreArmSet: Any code executed outside the protected segment will close the Firewall
Bit 1: Volatile data shared.
Allowed values:
0: NotShared: Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed
1: Shared: Volatile data segment is shared with non protected application code
Bit 2: Volatile data execution.
Allowed values:
0: NotExecutable: Volatile data segment cannot be executed if VDS = 0
1: Executable: Volatile data segment is declared executable whatever VDS bit value
0x40022000: Flash
4/72 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ACR | ||||||||||||||||||||||||||||||||
0x4 | PDKEYR | ||||||||||||||||||||||||||||||||
0x8 | KEYR | ||||||||||||||||||||||||||||||||
0xc | OPTKEYR | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 | CR | ||||||||||||||||||||||||||||||||
0x18 | ECCR | ||||||||||||||||||||||||||||||||
0x20 | OPTR | ||||||||||||||||||||||||||||||||
0x24 | PCROP1SR | ||||||||||||||||||||||||||||||||
0x28 | PCROP1ER | ||||||||||||||||||||||||||||||||
0x2c | WRP1AR | ||||||||||||||||||||||||||||||||
0x30 | WRP1BR | ||||||||||||||||||||||||||||||||
0x44 | PCROP2SR | ||||||||||||||||||||||||||||||||
0x48 | PCROP2ER | ||||||||||||||||||||||||||||||||
0x4c | WRP2AR | ||||||||||||||||||||||||||||||||
0x50 | WRP2BR |
Access control register
Offset: 0x0, size: 32, reset: 0x00000600, access: read-write
0/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SLEEP_PD
rw |
RUN_PD
rw |
DCRST
rw |
ICRST
rw |
DCEN
rw |
ICEN
rw |
PRFTEN
rw |
LATENCY
rw |
Bits 0-2: Latency.
Bit 8: Prefetch enable.
Bit 9: Instruction cache enable.
Bit 10: Data cache enable.
Bit 11: Instruction cache reset.
Bit 12: Data cache reset.
Bit 13: Flash Power-down mode during Low-power run mode.
Bit 14: Flash Power-down mode during Low-power sleep mode.
Power down key register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
0/1 fields covered.
Flash key register
Offset: 0x8, size: 32, reset: 0x00000000, access: write-only
0/1 fields covered.
Option byte key register
Offset: 0xc, size: 32, reset: 0x00000000, access: write-only
0/1 fields covered.
Status register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
1/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BSY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OPTVERR
rw |
RDERR
rw |
FASTERR
rw |
MISERR
rw |
PGSERR
rw |
SIZERR
rw |
PGAERR
rw |
WRPERR
rw |
PROGERR
rw |
OPERR
rw |
EOP
rw |
Bit 0: End of operation.
Bit 1: Operation error.
Bit 3: Programming error.
Bit 4: Write protected error.
Bit 5: Programming alignment error.
Bit 6: Size error.
Bit 7: Programming sequence error.
Bit 8: Fast programming data miss error.
Bit 9: Fast programming error.
Bit 14: PCROP read error.
Bit 15: Option validity error.
Bit 16: Busy.
Flash control register
Offset: 0x14, size: 32, reset: 0xC0000000, access: read-write
0/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LOCK
rw |
OPTLOCK
rw |
OBL_LAUNCH
rw |
RDERRIE
rw |
ERRIE
rw |
EOPIE
rw |
FSTPG
rw |
OPTSTRT
rw |
START
rw |
|||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MER2
rw |
BKER
rw |
PNB
rw |
MER1
rw |
PER
rw |
PG
rw |
Bit 0: Programming.
Bit 1: Page erase.
Bit 2: Bank 1 Mass erase.
Bits 3-10: Page number.
Bit 11: Bank erase.
Bit 15: Bank 2 Mass erase.
Bit 16: Start.
Bit 17: Options modification start.
Bit 18: Fast programming.
Bit 24: End of operation interrupt enable.
Bit 25: Error interrupt enable.
Bit 26: PCROP read error interrupt enable.
Bit 27: Force the option byte loading.
Bit 30: Options Lock.
Bit 31: FLASH_CR Lock.
Flash ECC register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
3/6 fields covered.
Flash option register
Offset: 0x20, size: 32, reset: 0xF0000000, access: read-write
0/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
nBOOT0
rw |
nSWBOOT0
rw |
SRAM2_RST
rw |
SRAM2_PE
rw |
nBOOT1
rw |
DUALBANK
rw |
BFB2
rw |
WWDG_SW
rw |
IWDG_STDBY
rw |
IWDG_STOP
rw |
IDWG_SW
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
nRST_STDBY
rw |
nRST_STOP
rw |
BOR_LEV
rw |
RDP
rw |
Bits 0-7: Read protection level.
Bits 8-10: BOR reset Level.
Bit 12: nRST_STOP.
Bit 13: nRST_STDBY.
Bit 16: Independent watchdog selection.
Bit 17: Independent watchdog counter freeze in Stop mode.
Bit 18: Independent watchdog counter freeze in Standby mode.
Bit 19: Window watchdog selection.
Bit 20: Dual-bank boot.
Bit 21: Dual-Bank on 512 KB or 256 KB Flash memory devices.
Bit 23: Boot configuration.
Bit 24: SRAM2 parity check enable.
Bit 25: SRAM2 Erase when system reset.
Bit 26: Software BOOT0.
Bit 27: nBOOT0 option bit.
Flash Bank 1 PCROP Start address register
Offset: 0x24, size: 32, reset: 0xFFFF0000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCROP1_STRT
rw |
Flash Bank 1 PCROP End address register
Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCROP_RDP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCROP1_END
rw |
Flash Bank 1 WRP area A address register
Offset: 0x2c, size: 32, reset: 0xFF00FF00, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WRP1A_END
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRP1A_STRT
rw |
Flash Bank 1 WRP area B address register
Offset: 0x30, size: 32, reset: 0xFF00FF00, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WRP1B_END
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRP1B_STRT
rw |
Flash Bank 2 PCROP Start address register
Offset: 0x44, size: 32, reset: 0xFFFF0000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCROP2_STRT
rw |
Flash Bank 2 PCROP End address register
Offset: 0x48, size: 32, reset: 0xFFFF0000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCROP2_END
rw |
Flash Bank 2 WRP area A address register
Offset: 0x4c, size: 32, reset: 0xFF00FF00, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WRP2A_END
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRP2A_STRT
rw |
Flash Bank 2 WRP area B address register
Offset: 0x50, size: 32, reset: 0xFF00FF00, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WRP2B_END
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WRP2B_STRT
rw |
0xa0000000: Flexible memory controller
130/147 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | BCR1 | ||||||||||||||||||||||||||||||||
0x4 | BTR[1] | ||||||||||||||||||||||||||||||||
0x8 | BCR[2] | ||||||||||||||||||||||||||||||||
0xc | BTR[2] | ||||||||||||||||||||||||||||||||
0x10 | BCR[3] | ||||||||||||||||||||||||||||||||
0x14 | BTR[3] | ||||||||||||||||||||||||||||||||
0x18 | BCR[4] | ||||||||||||||||||||||||||||||||
0x1c | BTR[4] | ||||||||||||||||||||||||||||||||
0x20 | PCSCNTR | ||||||||||||||||||||||||||||||||
0x80 | PCR | ||||||||||||||||||||||||||||||||
0x84 | SR | ||||||||||||||||||||||||||||||||
0x88 | PMEM | ||||||||||||||||||||||||||||||||
0x8c | PATT | ||||||||||||||||||||||||||||||||
0x94 | ECCR | ||||||||||||||||||||||||||||||||
0x104 | BWTR[1] | ||||||||||||||||||||||||||||||||
0x10c | BWTR[2] | ||||||||||||||||||||||||||||||||
0x114 | BWTR[3] | ||||||||||||||||||||||||||||||||
0x11c | BWTR[4] |
SRAM/NOR-Flash chip-select control register 1
Offset: 0x0, size: 32, reset: 0x000030D0, access: read-write
16/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NBLSET
rw |
WFDIS
rw |
CCLKEN
rw |
CBURSTRW
rw |
CPSIZE
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASYNCWAIT
rw |
EXTMOD
rw |
WAITEN
rw |
WREN
rw |
WAITCFG
rw |
WAITPOL
rw |
BURSTEN
rw |
FACCEN
rw |
MWID
rw |
MTYP
rw |
MUXEN
rw |
MBKEN
rw |
Bit 0: MBKEN.
Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled
Bit 1: MUXEN.
Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus
Bits 2-3: MTYP.
Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash
Bits 4-5: MWID.
Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits
Bit 6: FACCEN.
Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled
Bit 8: BURSTEN.
Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled
Bit 9: WAITPOL.
Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high
Bit 11: WAITCFG.
Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state
Bit 12: WREN.
Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC
Bit 13: WAITEN.
Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled
Bit 14: EXTMOD.
Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account
Bit 15: ASYNCWAIT.
Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode
Bits 16-18: CRAM page size.
Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size
Bit 19: CBURSTRW.
Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode
Bit 20: CCLKEN.
Allowed values:
0: Disabled: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set
1: Enabled: The FMC_CLK is only generated during the synchronous memory access (read/write transaction)
Bit 21: Write FIFO Disable.
Allowed values:
0: Enabled: Write FIFO enabled
1: Disabled: Write FIFO disabled
Bits 22-23: Byte lane (NBL) setup.
SRAM/NOR-Flash chip-select timing register 1
Offset: 0x4, size: 32, reset: 0xFFFFFFFF, access: read-write
7/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAHLD
rw |
ACCMOD
rw |
DATLAT
rw |
CLKDIV
rw |
BUSTURN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAST
rw |
ADDHLD
rw |
ADDSET
rw |
Bits 0-3: ADDSET.
Allowed values: 0x0-0xf
Bits 4-7: ADDHLD.
Allowed values: 0x1-0xf
Bits 8-15: DATAST.
Allowed values: 0x1-0xff
Bits 16-19: BUSTURN.
Allowed values: 0x0-0xf
Bits 20-23: CLKDIV.
Allowed values: 0x1-0xf
Bits 24-27: DATLAT.
Allowed values: 0x0-0xf
Bits 28-29: ACCMOD.
Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D
Bits 30-31: Data hold phase duration.
SRAM/NOR-Flash chip-select control register 2
Offset: 0x8, size: 32, reset: 0x000030D0, access: read-write
14/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NBLSET
rw |
CBURSTRW
rw |
CPSIZE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASYNCWAIT
rw |
EXTMOD
rw |
WAITEN
rw |
WREN
rw |
WAITCFG
rw |
WAITPOL
rw |
BURSTEN
rw |
FACCEN
rw |
MWID
rw |
MTYP
rw |
MUXEN
rw |
MBKEN
rw |
Bit 0: MBKEN.
Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled
Bit 1: MUXEN.
Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus
Bits 2-3: MTYP.
Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash
Bits 4-5: MWID.
Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits
Bit 6: FACCEN.
Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled
Bit 8: BURSTEN.
Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled
Bit 9: WAITPOL.
Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high
Bit 11: WAITCFG.
Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state
Bit 12: WREN.
Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC
Bit 13: WAITEN.
Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled
Bit 14: EXTMOD.
Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account
Bit 15: ASYNCWAIT.
Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode
Bits 16-18: CRAM page size.
Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size
Bit 19: CBURSTRW.
Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode
Bits 22-23: Byte lane (NBL) setup.
SRAM/NOR-Flash chip-select timing register 2
Offset: 0xc, size: 32, reset: 0xFFFFFFFF, access: read-write
7/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAHLD
rw |
ACCMOD
rw |
DATLAT
rw |
CLKDIV
rw |
BUSTURN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAST
rw |
ADDHLD
rw |
ADDSET
rw |
Bits 0-3: ADDSET.
Allowed values: 0x0-0xf
Bits 4-7: ADDHLD.
Allowed values: 0x1-0xf
Bits 8-15: DATAST.
Allowed values: 0x1-0xff
Bits 16-19: BUSTURN.
Allowed values: 0x0-0xf
Bits 20-23: CLKDIV.
Allowed values: 0x1-0xf
Bits 24-27: DATLAT.
Allowed values: 0x0-0xf
Bits 28-29: ACCMOD.
Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D
Bits 30-31: Data hold phase duration.
SRAM/NOR-Flash chip-select control register 3
Offset: 0x10, size: 32, reset: 0x000030D0, access: read-write
14/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NBLSET
rw |
CBURSTRW
rw |
CPSIZE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASYNCWAIT
rw |
EXTMOD
rw |
WAITEN
rw |
WREN
rw |
WAITCFG
rw |
WAITPOL
rw |
BURSTEN
rw |
FACCEN
rw |
MWID
rw |
MTYP
rw |
MUXEN
rw |
MBKEN
rw |
Bit 0: MBKEN.
Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled
Bit 1: MUXEN.
Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus
Bits 2-3: MTYP.
Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash
Bits 4-5: MWID.
Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits
Bit 6: FACCEN.
Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled
Bit 8: BURSTEN.
Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled
Bit 9: WAITPOL.
Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high
Bit 11: WAITCFG.
Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state
Bit 12: WREN.
Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC
Bit 13: WAITEN.
Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled
Bit 14: EXTMOD.
Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account
Bit 15: ASYNCWAIT.
Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode
Bits 16-18: CRAM page size.
Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size
Bit 19: CBURSTRW.
Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode
Bits 22-23: Byte lane (NBL) setup.
SRAM/NOR-Flash chip-select timing register 3
Offset: 0x14, size: 32, reset: 0xFFFFFFFF, access: read-write
7/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAHLD
rw |
ACCMOD
rw |
DATLAT
rw |
CLKDIV
rw |
BUSTURN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAST
rw |
ADDHLD
rw |
ADDSET
rw |
Bits 0-3: ADDSET.
Allowed values: 0x0-0xf
Bits 4-7: ADDHLD.
Allowed values: 0x1-0xf
Bits 8-15: DATAST.
Allowed values: 0x1-0xff
Bits 16-19: BUSTURN.
Allowed values: 0x0-0xf
Bits 20-23: CLKDIV.
Allowed values: 0x1-0xf
Bits 24-27: DATLAT.
Allowed values: 0x0-0xf
Bits 28-29: ACCMOD.
Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D
Bits 30-31: Data hold phase duration.
SRAM/NOR-Flash chip-select control register 4
Offset: 0x18, size: 32, reset: 0x000030D0, access: read-write
14/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NBLSET
rw |
CBURSTRW
rw |
CPSIZE
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ASYNCWAIT
rw |
EXTMOD
rw |
WAITEN
rw |
WREN
rw |
WAITCFG
rw |
WAITPOL
rw |
BURSTEN
rw |
FACCEN
rw |
MWID
rw |
MTYP
rw |
MUXEN
rw |
MBKEN
rw |
Bit 0: MBKEN.
Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled
Bit 1: MUXEN.
Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus
Bits 2-3: MTYP.
Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash
Bits 4-5: MWID.
Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits
Bit 6: FACCEN.
Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled
Bit 8: BURSTEN.
Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled
Bit 9: WAITPOL.
Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high
Bit 11: WAITCFG.
Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state
Bit 12: WREN.
Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC
Bit 13: WAITEN.
Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled
Bit 14: EXTMOD.
Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account
Bit 15: ASYNCWAIT.
Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode
Bits 16-18: CRAM page size.
Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size
Bit 19: CBURSTRW.
Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode
Bits 22-23: Byte lane (NBL) setup.
SRAM/NOR-Flash chip-select timing register 4
Offset: 0x1c, size: 32, reset: 0xFFFFFFFF, access: read-write
7/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAHLD
rw |
ACCMOD
rw |
DATLAT
rw |
CLKDIV
rw |
BUSTURN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAST
rw |
ADDHLD
rw |
ADDSET
rw |
Bits 0-3: ADDSET.
Allowed values: 0x0-0xf
Bits 4-7: ADDHLD.
Allowed values: 0x1-0xf
Bits 8-15: DATAST.
Allowed values: 0x1-0xff
Bits 16-19: BUSTURN.
Allowed values: 0x0-0xf
Bits 20-23: CLKDIV.
Allowed values: 0x1-0xf
Bits 24-27: DATLAT.
Allowed values: 0x0-0xf
Bits 28-29: ACCMOD.
Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D
Bits 30-31: Data hold phase duration.
PSRAM chip select counter register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
0/5 fields covered.
PC Card/NAND Flash control register 3
Offset: 0x80, size: 32, reset: 0x00000018, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ECCPS
rw |
TAR
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAR
rw |
TCLR
rw |
ECCEN
rw |
PWID
rw |
PTYP
rw |
PBKEN
rw |
PWAITEN
rw |
Bit 1: PWAITEN.
Allowed values:
0: Disabled: Wait feature disabled
1: Enabled: Wait feature enabled
Bit 2: PBKEN.
Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled
Bit 3: PTYP.
Allowed values:
1: NANDFlash: NAND Flash
Bits 4-5: PWID.
Allowed values:
0: Bits8: External memory device width 8 bits
1: Bits16: External memory device width 16 bits
Bit 6: ECCEN.
Allowed values:
0: Disabled: ECC logic is disabled and reset
1: Enabled: ECC logic is enabled
Bits 9-12: TCLR.
Allowed values: 0x0-0xf
Bits 13-16: TAR.
Allowed values: 0x0-0xf
Bits 17-19: ECCPS.
Allowed values:
0: Bytes256: ECC page size 256 bytes
1: Bytes512: ECC page size 512 bytes
2: Bytes1024: ECC page size 1024 bytes
3: Bytes2048: ECC page size 2048 bytes
4: Bytes4096: ECC page size 4096 bytes
5: Bytes8192: ECC page size 8192 bytes
FIFO status and interrupt register 3
Offset: 0x84, size: 32, reset: 0x00000040, access: Unspecified
7/7 fields covered.
Bit 0: IRS.
Allowed values:
0: DidNotOccur: Interrupt rising edge did not occur
1: Occurred: Interrupt rising edge occurred
Bit 1: ILS.
Allowed values:
0: DidNotOccur: Interrupt high-level did not occur
1: Occurred: Interrupt high-level occurred
Bit 2: IFS.
Allowed values:
0: DidNotOccur: Interrupt falling edge did not occur
1: Occurred: Interrupt falling edge occurred
Bit 3: IREN.
Allowed values:
0: Disabled: Interrupt rising edge detection request disabled
1: Enabled: Interrupt rising edge detection request enabled
Bit 4: ILEN.
Allowed values:
0: Disabled: Interrupt high-level detection request disabled
1: Enabled: Interrupt high-level detection request enabled
Bit 5: IFEN.
Allowed values:
0: Disabled: Interrupt falling edge detection request disabled
1: Enabled: Interrupt falling edge detection request enabled
Bit 6: FEMPT.
Allowed values:
0: NotEmpty: FIFO not empty
1: Empty: FIFO empty
Common memory space timing register 3
Offset: 0x88, size: 32, reset: 0xFCFCFCFC, access: read-write
4/4 fields covered.
Attribute memory space timing register 3
Offset: 0x8c, size: 32, reset: 0xFCFCFCFC, access: read-write
4/4 fields covered.
ECC result register 3
Offset: 0x94, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
SRAM/NOR-Flash write timing registers 1
Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write
5/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAHLD
rw |
ACCMOD
rw |
BUSTURN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAST
rw |
ADDHLD
rw |
ADDSET
rw |
Bits 0-3: ADDSET.
Allowed values: 0x0-0xf
Bits 4-7: ADDHLD.
Allowed values: 0x1-0xf
Bits 8-15: DATAST.
Allowed values: 0x1-0xff
Bits 16-19: Bus turnaround phase duration.
Allowed values: 0x0-0xf
Bits 28-29: ACCMOD.
Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D
Bits 30-31: Data hold phase duration.
SRAM/NOR-Flash write timing registers 2
Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write
5/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAHLD
rw |
ACCMOD
rw |
BUSTURN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAST
rw |
ADDHLD
rw |
ADDSET
rw |
Bits 0-3: ADDSET.
Allowed values: 0x0-0xf
Bits 4-7: ADDHLD.
Allowed values: 0x1-0xf
Bits 8-15: DATAST.
Allowed values: 0x1-0xff
Bits 16-19: Bus turnaround phase duration.
Allowed values: 0x0-0xf
Bits 28-29: ACCMOD.
Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D
Bits 30-31: Data hold phase duration.
SRAM/NOR-Flash write timing registers 3
Offset: 0x114, size: 32, reset: 0x0FFFFFFF, access: read-write
5/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAHLD
rw |
ACCMOD
rw |
BUSTURN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAST
rw |
ADDHLD
rw |
ADDSET
rw |
Bits 0-3: ADDSET.
Allowed values: 0x0-0xf
Bits 4-7: ADDHLD.
Allowed values: 0x1-0xf
Bits 8-15: DATAST.
Allowed values: 0x1-0xff
Bits 16-19: Bus turnaround phase duration.
Allowed values: 0x0-0xf
Bits 28-29: ACCMOD.
Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D
Bits 30-31: Data hold phase duration.
SRAM/NOR-Flash write timing registers 4
Offset: 0x11c, size: 32, reset: 0x0FFFFFFF, access: read-write
5/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATAHLD
rw |
ACCMOD
rw |
BUSTURN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATAST
rw |
ADDHLD
rw |
ADDSET
rw |
Bits 0-3: ADDSET.
Allowed values: 0x0-0xf
Bits 4-7: ADDHLD.
Allowed values: 0x1-0xf
Bits 8-15: DATAST.
Allowed values: 0x1-0xff
Bits 16-19: Bus turnaround phase duration.
Allowed values: 0x0-0xf
Bits 28-29: ACCMOD.
Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D
Bits 30-31: Data hold phase duration.
0xe000ef34: Floting point unit
0/24 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | FPCCR | ||||||||||||||||||||||||||||||||
0x4 | FPCAR | ||||||||||||||||||||||||||||||||
0x8 | FPSCR |
Floating-point context control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
Floating-point context address register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Floating-point status control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
N
rw |
Z
rw |
C
rw |
V
rw |
AHP
rw |
DN
rw |
FZ
rw |
RMode
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDC
rw |
IXC
rw |
UFC
rw |
OFC
rw |
DZC
rw |
IOC
rw |
Bit 0: Invalid operation cumulative exception bit.
Bit 1: Division by zero cumulative exception bit..
Bit 2: Overflow cumulative exception bit.
Bit 3: Underflow cumulative exception bit.
Bit 4: Inexact cumulative exception bit.
Bit 7: Input denormal cumulative exception bit..
Bits 22-23: Rounding Mode control field.
Bit 24: Flush-to-zero mode control bit:.
Bit 25: Default NaN mode control bit.
Bit 26: Alternative half-precision control bit.
Bit 28: Overflow condition code flag.
Bit 29: Carry condition code flag.
Bit 30: Zero condition code flag.
Bit 31: Negative condition code flag.
0xe000ed88: Floating point unit CPACR
0/1 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CPACR |
Coprocessor access control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0x4002c000: Graphic MMU
9/4125 fields covered.
Graphic MMU configuration register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
Graphic MMU status register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-only
5/5 fields covered.
Graphic MMU flag clear register
Offset: 0x8, size: 32, reset: 0x00000000, access: write-only
0/5 fields covered.
Graphic MMU default value register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU buffer 0 configuration register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Graphic MMU buffer 1 configuration register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Graphic MMU buffer 2 configuration register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Graphic MMU buffer 3 configuration register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
Graphic MMU version register
Offset: 0xff4, size: 32, reset: 0x00000010, access: read-only
2/2 fields covered.
Graphic MMU identification register
Offset: 0xff8, size: 32, reset: 0x00160061, access: read-only
1/1 fields covered.
Graphic MMU size identification register
Offset: 0xffc, size: 32, reset: 0xA3C5DD04, access: read-only
1/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1000, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1004, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1008, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x100c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1010, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1014, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1018, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x101c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1020, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1024, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1028, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x102c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1030, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1034, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1038, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x103c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1040, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1044, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1048, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x104c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1050, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1054, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1058, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x105c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1060, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1064, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1068, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x106c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1070, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1074, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1078, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x107c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1080, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1084, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1088, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x108c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1090, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1094, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1098, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x109c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x10f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x10fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1100, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1104, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1108, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x110c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1110, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1114, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1118, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x111c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1120, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1124, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1128, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x112c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1130, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1134, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1138, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x113c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1140, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1144, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1148, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x114c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1150, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1154, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1158, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x115c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1160, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1164, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1168, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x116c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1170, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1174, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1178, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x117c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1180, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1184, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1188, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x118c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1190, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1194, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1198, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x119c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x11f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x11fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1200, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1204, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1208, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x120c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1210, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1214, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1218, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x121c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1220, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1224, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1228, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x122c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1230, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1234, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1238, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x123c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1240, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1244, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1248, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x124c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1250, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1254, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1258, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x125c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1260, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1264, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1268, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x126c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1270, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1274, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1278, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x127c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1280, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1284, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1288, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x128c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1290, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1294, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1298, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x129c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x12f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x12fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1300, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1304, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1308, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x130c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1310, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1314, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1318, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x131c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1320, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1324, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1328, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x132c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1330, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1334, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1338, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x133c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1340, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1344, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1348, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x134c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1350, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1354, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1358, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x135c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1360, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1364, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1368, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x136c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1370, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1374, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1378, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x137c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1380, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1384, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1388, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x138c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1390, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1394, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1398, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x139c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x13f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x13fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1400, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1404, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1408, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x140c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1410, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1414, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1418, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x141c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1420, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1424, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1428, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x142c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1430, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1434, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1438, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x143c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1440, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1444, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1448, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x144c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1450, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1454, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1458, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x145c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1460, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1464, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1468, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x146c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1470, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1474, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1478, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x147c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1480, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1484, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1488, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x148c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1490, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1494, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1498, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x149c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x14f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x14fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1500, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1504, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1508, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x150c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1510, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1514, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1518, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x151c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1520, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1524, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1528, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x152c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1530, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1534, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1538, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x153c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1540, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1544, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1548, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x154c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1550, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1554, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1558, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x155c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1560, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1564, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1568, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x156c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1570, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1574, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1578, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x157c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1580, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1584, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1588, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x158c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1590, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1594, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1598, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x159c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x15f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x15fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1600, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1604, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1608, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x160c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1610, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1614, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1618, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x161c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1620, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1624, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1628, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x162c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1630, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1634, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1638, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x163c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1640, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1644, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1648, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x164c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1650, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1654, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1658, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x165c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1660, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1664, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1668, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x166c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1670, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1674, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1678, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x167c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1680, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1684, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1688, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x168c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1690, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1694, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1698, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x169c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x16f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x16fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1700, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1704, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1708, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x170c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1710, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1714, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1718, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x171c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1720, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1724, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1728, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x172c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1730, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1734, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1738, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x173c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1740, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1744, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1748, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x174c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1750, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1754, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1758, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x175c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1760, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1764, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1768, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x176c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1770, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1774, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1778, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x177c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1780, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1784, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1788, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x178c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1790, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1794, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1798, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x179c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x17f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x17fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1800, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1804, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1808, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x180c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1810, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1814, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1818, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x181c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1820, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1824, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1828, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x182c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1830, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1834, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1838, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x183c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1840, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1844, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1848, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x184c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1850, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1854, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1858, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x185c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1860, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1864, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1868, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x186c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1870, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1874, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1878, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x187c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1880, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1884, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1888, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x188c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1890, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1894, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1898, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x189c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x18f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x18fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1900, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1904, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1908, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x190c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1910, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1914, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1918, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x191c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1920, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1924, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1928, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x192c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1930, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1934, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1938, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x193c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1940, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1944, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1948, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x194c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1950, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1954, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1958, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x195c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1960, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1964, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1968, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x196c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1970, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1974, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1978, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x197c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1980, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1984, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1988, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x198c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1990, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1994, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1998, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x199c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x19f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x19fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1a98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1a9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1aa0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1aa4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1aa8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1aac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ab0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ab4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ab8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1abc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ac0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ac4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ac8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1acc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ad0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ad4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ad8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1adc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ae0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ae4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ae8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1aec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1af0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1af4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1af8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1afc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1b98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1b9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ba0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ba4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ba8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1bb0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1bb8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bbc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1bc0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bc4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1bc8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bcc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1bd0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1bd8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bdc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1be0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1be4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1be8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1bf0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bf4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1bf8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1bfc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1c98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1c9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ca0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ca4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ca8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1cb0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1cb8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cbc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1cc0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cc4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1cc8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ccc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1cd0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1cd8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cdc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ce0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ce4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ce8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1cf0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cf4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1cf8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1cfc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1d98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1d9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1da0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1da4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1da8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1dac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1db0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1db4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1db8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1dbc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1dc0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1dc4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1dc8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1dcc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1dd0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1dd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1dd8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ddc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1de0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1de4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1de8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1dec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1df0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1df4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1df8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1dfc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1e98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1e9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ea0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ea4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ea8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1eac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1eb0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1eb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1eb8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ebc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ec0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ec4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ec8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ecc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ed0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ed4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ed8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1edc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ee0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ee4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ee8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1eec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ef0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ef4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ef8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1efc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1f98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1f9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fa0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fa4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fa8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fb0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fb8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fbc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fc0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fc4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fc8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fcc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fd0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fd8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fdc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fe0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fe4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1fe8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1fec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ff0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ff4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x1ff8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x1ffc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2000, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2004, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2008, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x200c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2010, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2014, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2018, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x201c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2020, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2024, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2028, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x202c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2030, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2034, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2038, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x203c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2040, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2044, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2048, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x204c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2050, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2054, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2058, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x205c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2060, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2064, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2068, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x206c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2070, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2074, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2078, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x207c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2080, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2084, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2088, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x208c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2090, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2094, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2098, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x209c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x20f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x20fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2100, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2104, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2108, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x210c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2110, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2114, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2118, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x211c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2120, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2124, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2128, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x212c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2130, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2134, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2138, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x213c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2140, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2144, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2148, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x214c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2150, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2154, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2158, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x215c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2160, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2164, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2168, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x216c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2170, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2174, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2178, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x217c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2180, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2184, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2188, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x218c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2190, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2194, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2198, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x219c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x21f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x21fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2200, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2204, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2208, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x220c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2210, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2214, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2218, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x221c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2220, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2224, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2228, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x222c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2230, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2234, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2238, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x223c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2240, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2244, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2248, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x224c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2250, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2254, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2258, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x225c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2260, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2264, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2268, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x226c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2270, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2274, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2278, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x227c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2280, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2284, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2288, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x228c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2290, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2294, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2298, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x229c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x22f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x22fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2300, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2304, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2308, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x230c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2310, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2314, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2318, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x231c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2320, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2324, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2328, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x232c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2330, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2334, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2338, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x233c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2340, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2344, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2348, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x234c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2350, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2354, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2358, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x235c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2360, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2364, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2368, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x236c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2370, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2374, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2378, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x237c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2380, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2384, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2388, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x238c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2390, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2394, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2398, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x239c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x23f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x23fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2400, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2404, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2408, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x240c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2410, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2414, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2418, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x241c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2420, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2424, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2428, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x242c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2430, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2434, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2438, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x243c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2440, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2444, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2448, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x244c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2450, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2454, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2458, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x245c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2460, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2464, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2468, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x246c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2470, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2474, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2478, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x247c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2480, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2484, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2488, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x248c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2490, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2494, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2498, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x249c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x24f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x24fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2500, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2504, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2508, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x250c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2510, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2514, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2518, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x251c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2520, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2524, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2528, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x252c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2530, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2534, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2538, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x253c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2540, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2544, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2548, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x254c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2550, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2554, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2558, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x255c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2560, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2564, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2568, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x256c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2570, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2574, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2578, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x257c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2580, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2584, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2588, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x258c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2590, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2594, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2598, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x259c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x25f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x25fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2600, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2604, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2608, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x260c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2610, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2614, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2618, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x261c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2620, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2624, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2628, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x262c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2630, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2634, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2638, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x263c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2640, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2644, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2648, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x264c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2650, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2654, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2658, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x265c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2660, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2664, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2668, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x266c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2670, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2674, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2678, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x267c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2680, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2684, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2688, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x268c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2690, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2694, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2698, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x269c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x26f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x26fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2700, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2704, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2708, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x270c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2710, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2714, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2718, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x271c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2720, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2724, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2728, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x272c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2730, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2734, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2738, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x273c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2740, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2744, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2748, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x274c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2750, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2754, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2758, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x275c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2760, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2764, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2768, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x276c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2770, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2774, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2778, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x277c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2780, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2784, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2788, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x278c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2790, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2794, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2798, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x279c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x27f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x27fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2800, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2804, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2808, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x280c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2810, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2814, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2818, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x281c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2820, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2824, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2828, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x282c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2830, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2834, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2838, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x283c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2840, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2844, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2848, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x284c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2850, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2854, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2858, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x285c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2860, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2864, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2868, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x286c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2870, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2874, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2878, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x287c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2880, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2884, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2888, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x288c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2890, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2894, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2898, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x289c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x28f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x28fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2900, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2904, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2908, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x290c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2910, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2914, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2918, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x291c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2920, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2924, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2928, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x292c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2930, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2934, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2938, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x293c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2940, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2944, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2948, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x294c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2950, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2954, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2958, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x295c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2960, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2964, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2968, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x296c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2970, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2974, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2978, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x297c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2980, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2984, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2988, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x298c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2990, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2994, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2998, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x299c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29a0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29a8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29b8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29c0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29c8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29d4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29d8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29dc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29e0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29e4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29e8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29ec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29f4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x29f8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x29fc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2a98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2a9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2aa0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2aa4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2aa8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2aac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ab0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ab4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ab8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2abc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ac0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ac4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ac8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2acc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ad0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ad4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ad8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2adc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ae0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ae4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ae8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2aec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2af0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2af4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2af8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2afc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2b98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2b9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ba0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ba4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ba8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2bb0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2bb8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bbc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2bc0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bc4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2bc8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bcc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2bd0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2bd8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bdc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2be0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2be4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2be8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2bf0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bf4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2bf8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2bfc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2c98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2c9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ca0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ca4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ca8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2cb0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2cb8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cbc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2cc0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cc4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2cc8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ccc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2cd0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2cd8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cdc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ce0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ce4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ce8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2cf0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cf4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2cf8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2cfc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2d98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2d9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2da0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2da4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2da8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2dac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2db0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2db4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2db8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2dbc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2dc0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2dc4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2dc8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2dcc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2dd0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2dd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2dd8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ddc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2de0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2de4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2de8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2dec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2df0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2df4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2df8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2dfc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2e98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2e9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ea0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ea4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ea8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2eac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2eb0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2eb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2eb8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ebc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ec0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ec4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ec8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ecc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ed0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ed4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ed8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2edc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ee0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ee4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ee8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2eec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ef0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ef4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ef8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2efc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f00, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f04, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f08, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f0c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f20, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f28, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f2c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f30, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f38, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f3c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f40, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f44, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f48, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f4c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f50, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f54, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f58, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f5c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f60, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f64, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f68, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f6c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f70, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f74, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f78, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f7c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f80, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f88, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f8c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2f98, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2f9c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fa0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fa4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fa8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fb0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fb8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fbc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fc0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fc4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fc8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fcc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fd0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fd4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fd8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fdc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fe0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fe4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2fe8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2fec, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Graphic MMU LUT entry x low
Offset: 0x2ff0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Graphic MMU LUT entry x high
Offset: 0x2ff4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
0x48000000: General-purpose I/Os
177/193 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR | ||||||||||||||||||||||||||||||||
0x2c | ASCR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0xA8000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x64000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
GPIO port analog switch control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ASC15
rw |
ASC14
rw |
ASC13
rw |
ASC12
rw |
ASC11
rw |
ASC10
rw |
ASC9
rw |
ASC8
rw |
ASC7
rw |
ASC6
rw |
ASC5
rw |
ASC4
rw |
ASC3
rw |
ASC2
rw |
ASC1
rw |
ASC0
rw |
Bit 0: Port analog switch control.
Bit 1: Port analog switch control.
Bit 2: Port analog switch control.
Bit 3: Port analog switch control.
Bit 4: Port analog switch control.
Bit 5: Port analog switch control.
Bit 6: Port analog switch control.
Bit 7: Port analog switch control.
Bit 8: Port analog switch control.
Bit 9: Port analog switch control.
Bit 10: Port analog switch control.
Bit 11: Port analog switch control.
Bit 12: Port analog switch control.
Bit 13: Port analog switch control.
Bit 14: Port analog switch control.
Bit 15: Port analog switch control.
0x48000400: General-purpose I/Os
177/193 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR | ||||||||||||||||||||||||||||||||
0x2c | ASCR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000280, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000100, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
GPIO port analog switch control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ASC15
rw |
ASC14
rw |
ASC13
rw |
ASC12
rw |
ASC11
rw |
ASC10
rw |
ASC9
rw |
ASC8
rw |
ASC7
rw |
ASC6
rw |
ASC5
rw |
ASC4
rw |
ASC3
rw |
ASC2
rw |
ASC1
rw |
ASC0
rw |
Bit 0: Port analog switch control.
Bit 1: Port analog switch control.
Bit 2: Port analog switch control.
Bit 3: Port analog switch control.
Bit 4: Port analog switch control.
Bit 5: Port analog switch control.
Bit 6: Port analog switch control.
Bit 7: Port analog switch control.
Bit 8: Port analog switch control.
Bit 9: Port analog switch control.
Bit 10: Port analog switch control.
Bit 11: Port analog switch control.
Bit 12: Port analog switch control.
Bit 13: Port analog switch control.
Bit 14: Port analog switch control.
Bit 15: Port analog switch control.
0x48000800: General-purpose I/Os
177/193 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR | ||||||||||||||||||||||||||||||||
0x2c | ASCR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
GPIO port analog switch control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ASC15
rw |
ASC14
rw |
ASC13
rw |
ASC12
rw |
ASC11
rw |
ASC10
rw |
ASC9
rw |
ASC8
rw |
ASC7
rw |
ASC6
rw |
ASC5
rw |
ASC4
rw |
ASC3
rw |
ASC2
rw |
ASC1
rw |
ASC0
rw |
Bit 0: Port analog switch control.
Bit 1: Port analog switch control.
Bit 2: Port analog switch control.
Bit 3: Port analog switch control.
Bit 4: Port analog switch control.
Bit 5: Port analog switch control.
Bit 6: Port analog switch control.
Bit 7: Port analog switch control.
Bit 8: Port analog switch control.
Bit 9: Port analog switch control.
Bit 10: Port analog switch control.
Bit 11: Port analog switch control.
Bit 12: Port analog switch control.
Bit 13: Port analog switch control.
Bit 14: Port analog switch control.
Bit 15: Port analog switch control.
0x48000c00: General-purpose I/Os
177/193 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR | ||||||||||||||||||||||||||||||||
0x2c | ASCR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
GPIO port analog switch control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ASC15
rw |
ASC14
rw |
ASC13
rw |
ASC12
rw |
ASC11
rw |
ASC10
rw |
ASC9
rw |
ASC8
rw |
ASC7
rw |
ASC6
rw |
ASC5
rw |
ASC4
rw |
ASC3
rw |
ASC2
rw |
ASC1
rw |
ASC0
rw |
Bit 0: Port analog switch control.
Bit 1: Port analog switch control.
Bit 2: Port analog switch control.
Bit 3: Port analog switch control.
Bit 4: Port analog switch control.
Bit 5: Port analog switch control.
Bit 6: Port analog switch control.
Bit 7: Port analog switch control.
Bit 8: Port analog switch control.
Bit 9: Port analog switch control.
Bit 10: Port analog switch control.
Bit 11: Port analog switch control.
Bit 12: Port analog switch control.
Bit 13: Port analog switch control.
Bit 14: Port analog switch control.
Bit 15: Port analog switch control.
0x48001000: General-purpose I/Os
177/193 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR | ||||||||||||||||||||||||||||||||
0x2c | ASCR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
GPIO port analog switch control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ASC15
rw |
ASC14
rw |
ASC13
rw |
ASC12
rw |
ASC11
rw |
ASC10
rw |
ASC9
rw |
ASC8
rw |
ASC7
rw |
ASC6
rw |
ASC5
rw |
ASC4
rw |
ASC3
rw |
ASC2
rw |
ASC1
rw |
ASC0
rw |
Bit 0: Port analog switch control.
Bit 1: Port analog switch control.
Bit 2: Port analog switch control.
Bit 3: Port analog switch control.
Bit 4: Port analog switch control.
Bit 5: Port analog switch control.
Bit 6: Port analog switch control.
Bit 7: Port analog switch control.
Bit 8: Port analog switch control.
Bit 9: Port analog switch control.
Bit 10: Port analog switch control.
Bit 11: Port analog switch control.
Bit 12: Port analog switch control.
Bit 13: Port analog switch control.
Bit 14: Port analog switch control.
Bit 15: Port analog switch control.
0x48001400: General-purpose I/Os
177/193 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR | ||||||||||||||||||||||||||||||||
0x2c | ASCR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
GPIO port analog switch control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ASC15
rw |
ASC14
rw |
ASC13
rw |
ASC12
rw |
ASC11
rw |
ASC10
rw |
ASC9
rw |
ASC8
rw |
ASC7
rw |
ASC6
rw |
ASC5
rw |
ASC4
rw |
ASC3
rw |
ASC2
rw |
ASC1
rw |
ASC0
rw |
Bit 0: Port analog switch control.
Bit 1: Port analog switch control.
Bit 2: Port analog switch control.
Bit 3: Port analog switch control.
Bit 4: Port analog switch control.
Bit 5: Port analog switch control.
Bit 6: Port analog switch control.
Bit 7: Port analog switch control.
Bit 8: Port analog switch control.
Bit 9: Port analog switch control.
Bit 10: Port analog switch control.
Bit 11: Port analog switch control.
Bit 12: Port analog switch control.
Bit 13: Port analog switch control.
Bit 14: Port analog switch control.
Bit 15: Port analog switch control.
0x48001800: General-purpose I/Os
177/193 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR | ||||||||||||||||||||||||||||||||
0x2c | ASCR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
GPIO port analog switch control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ASC15
rw |
ASC14
rw |
ASC13
rw |
ASC12
rw |
ASC11
rw |
ASC10
rw |
ASC9
rw |
ASC8
rw |
ASC7
rw |
ASC6
rw |
ASC5
rw |
ASC4
rw |
ASC3
rw |
ASC2
rw |
ASC1
rw |
ASC0
rw |
Bit 0: Port analog switch control.
Bit 1: Port analog switch control.
Bit 2: Port analog switch control.
Bit 3: Port analog switch control.
Bit 4: Port analog switch control.
Bit 5: Port analog switch control.
Bit 6: Port analog switch control.
Bit 7: Port analog switch control.
Bit 8: Port analog switch control.
Bit 9: Port analog switch control.
Bit 10: Port analog switch control.
Bit 11: Port analog switch control.
Bit 12: Port analog switch control.
Bit 13: Port analog switch control.
Bit 14: Port analog switch control.
Bit 15: Port analog switch control.
0x48001c00: General-purpose I/Os
177/193 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR | ||||||||||||||||||||||||||||||||
0x2c | ASCR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
GPIO port analog switch control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ASC15
rw |
ASC14
rw |
ASC13
rw |
ASC12
rw |
ASC11
rw |
ASC10
rw |
ASC9
rw |
ASC8
rw |
ASC7
rw |
ASC6
rw |
ASC5
rw |
ASC4
rw |
ASC3
rw |
ASC2
rw |
ASC1
rw |
ASC0
rw |
Bit 0: Port analog switch control.
Bit 1: Port analog switch control.
Bit 2: Port analog switch control.
Bit 3: Port analog switch control.
Bit 4: Port analog switch control.
Bit 5: Port analog switch control.
Bit 6: Port analog switch control.
Bit 7: Port analog switch control.
Bit 8: Port analog switch control.
Bit 9: Port analog switch control.
Bit 10: Port analog switch control.
Bit 11: Port analog switch control.
Bit 12: Port analog switch control.
Bit 13: Port analog switch control.
Bit 14: Port analog switch control.
Bit 15: Port analog switch control.
0x48002000: General-purpose I/Os
177/177 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MODER | ||||||||||||||||||||||||||||||||
0x4 | OTYPER | ||||||||||||||||||||||||||||||||
0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
0xc | PUPDR | ||||||||||||||||||||||||||||||||
0x10 | IDR | ||||||||||||||||||||||||||||||||
0x14 | ODR | ||||||||||||||||||||||||||||||||
0x18 | BSRR | ||||||||||||||||||||||||||||||||
0x1c | LCKR | ||||||||||||||||||||||||||||||||
0x20 | AFRL | ||||||||||||||||||||||||||||||||
0x24 | AFRH | ||||||||||||||||||||||||||||||||
0x28 | BRR |
GPIO port mode register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MODER[15]
rw |
MODER[14]
rw |
MODER[13]
rw |
MODER[12]
rw |
MODER[11]
rw |
MODER[10]
rw |
MODER[9]
rw |
MODER[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODER[7]
rw |
MODER[6]
rw |
MODER[5]
rw |
MODER[4]
rw |
MODER[3]
rw |
MODER[2]
rw |
MODER[1]
rw |
MODER[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode
GPIO port output type register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OT[15]
rw |
OT[14]
rw |
OT[13]
rw |
OT[12]
rw |
OT[11]
rw |
OT[10]
rw |
OT[9]
rw |
OT[8]
rw |
OT[7]
rw |
OT[6]
rw |
OT[5]
rw |
OT[4]
rw |
OT[3]
rw |
OT[2]
rw |
OT[1]
rw |
OT[0]
rw |
Bit 0: Port x configuration pin 0.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 1: Port x configuration pin 1.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 2: Port x configuration pin 2.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 3: Port x configuration pin 3.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 4: Port x configuration pin 4.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 5: Port x configuration pin 5.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 6: Port x configuration pin 6.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 7: Port x configuration pin 7.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 8: Port x configuration pin 8.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 9: Port x configuration pin 9.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 10: Port x configuration pin 10.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 11: Port x configuration pin 11.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 12: Port x configuration pin 12.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 13: Port x configuration pin 13.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 14: Port x configuration pin 14.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
Bit 15: Port x configuration pin 15.
Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain
GPIO port output speed register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPEEDR[15]
rw |
OSPEEDR[14]
rw |
OSPEEDR[13]
rw |
OSPEEDR[12]
rw |
OSPEEDR[11]
rw |
OSPEEDR[10]
rw |
OSPEEDR[9]
rw |
OSPEEDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSPEEDR[7]
rw |
OSPEEDR[6]
rw |
OSPEEDR[5]
rw |
OSPEEDR[4]
rw |
OSPEEDR[3]
rw |
OSPEEDR[2]
rw |
OSPEEDR[1]
rw |
OSPEEDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed
GPIO port pull-up/pull-down register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUPDR[15]
rw |
PUPDR[14]
rw |
PUPDR[13]
rw |
PUPDR[12]
rw |
PUPDR[11]
rw |
PUPDR[10]
rw |
PUPDR[9]
rw |
PUPDR[8]
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PUPDR[7]
rw |
PUPDR[6]
rw |
PUPDR[5]
rw |
PUPDR[4]
rw |
PUPDR[3]
rw |
PUPDR[2]
rw |
PUPDR[1]
rw |
PUPDR[0]
rw |
Bits 0-1: Port x configuration pin 0.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 2-3: Port x configuration pin 1.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 4-5: Port x configuration pin 2.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 6-7: Port x configuration pin 3.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 8-9: Port x configuration pin 4.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 10-11: Port x configuration pin 5.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 12-13: Port x configuration pin 6.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 14-15: Port x configuration pin 7.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 16-17: Port x configuration pin 8.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 18-19: Port x configuration pin 9.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 20-21: Port x configuration pin 10.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 22-23: Port x configuration pin 11.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 24-25: Port x configuration pin 12.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 26-27: Port x configuration pin 13.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 28-29: Port x configuration pin 14.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
Bits 30-31: Port x configuration pin 15.
Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down
GPIO port input data register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IDR[15]
r |
IDR[14]
r |
IDR[13]
r |
IDR[12]
r |
IDR[11]
r |
IDR[10]
r |
IDR[9]
r |
IDR[8]
r |
IDR[7]
r |
IDR[6]
r |
IDR[5]
r |
IDR[4]
r |
IDR[3]
r |
IDR[2]
r |
IDR[1]
r |
IDR[0]
r |
Bit 0: Port input data pin 0.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 1: Port input data pin 1.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 2: Port input data pin 2.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 3: Port input data pin 3.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 4: Port input data pin 4.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 5: Port input data pin 5.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 6: Port input data pin 6.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 7: Port input data pin 7.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 8: Port input data pin 8.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 9: Port input data pin 9.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 10: Port input data pin 10.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 11: Port input data pin 11.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 12: Port input data pin 12.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 13: Port input data pin 13.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 14: Port input data pin 14.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
Bit 15: Port input data pin 15.
Allowed values:
0: Low: Input is logic low
1: High: Input is logic high
GPIO port output data register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ODR[15]
rw |
ODR[14]
rw |
ODR[13]
rw |
ODR[12]
rw |
ODR[11]
rw |
ODR[10]
rw |
ODR[9]
rw |
ODR[8]
rw |
ODR[7]
rw |
ODR[6]
rw |
ODR[5]
rw |
ODR[4]
rw |
ODR[3]
rw |
ODR[2]
rw |
ODR[1]
rw |
ODR[0]
rw |
Bit 0: Port output data pin 0.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 1: Port output data pin 1.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 2: Port output data pin 2.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 3: Port output data pin 3.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 4: Port output data pin 4.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 5: Port output data pin 5.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 6: Port output data pin 6.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 7: Port output data pin 7.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 8: Port output data pin 8.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 9: Port output data pin 9.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 10: Port output data pin 10.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 11: Port output data pin 11.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 12: Port output data pin 12.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 13: Port output data pin 13.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 14: Port output data pin 14.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
Bit 15: Port output data pin 15.
Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high
GPIO port bit set/reset register
Offset: 0x18, size: 32, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BS[15]
w |
BS[14]
w |
BS[13]
w |
BS[12]
w |
BS[11]
w |
BS[10]
w |
BS[9]
w |
BS[8]
w |
BS[7]
w |
BS[6]
w |
BS[5]
w |
BS[4]
w |
BS[3]
w |
BS[2]
w |
BS[1]
w |
BS[0]
w |
Bit 0: Port x set pin 0.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 1: Port x set pin 1.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 2: Port x set pin 2.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 3: Port x set pin 3.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 4: Port x set pin 4.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 5: Port x set pin 5.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 6: Port x set pin 6.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 7: Port x set pin 7.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 8: Port x set pin 8.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 9: Port x set pin 9.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 10: Port x set pin 10.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 11: Port x set pin 11.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 12: Port x set pin 12.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 13: Port x set pin 13.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 14: Port x set pin 14.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 15: Port x set pin 15.
Allowed values:
1: Set: Sets the corresponding ODRx bit
Bit 16: Port x reset pin 0.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 17: Port x reset pin 1.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 18: Port x reset pin 2.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 19: Port x reset pin 3.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 20: Port x reset pin 4.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 21: Port x reset pin 5.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 22: Port x reset pin 6.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 23: Port x reset pin 7.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 24: Port x reset pin 8.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 25: Port x reset pin 9.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 26: Port x reset pin 10.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 27: Port x reset pin 11.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 28: Port x reset pin 12.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 29: Port x reset pin 13.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 30: Port x reset pin 14.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
Bit 31: Port x reset pin 15.
Allowed values:
1: Reset: Resets the corresponding ODRx bit
GPIO port configuration lock register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LCKK
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCK[15]
rw |
LCK[14]
rw |
LCK[13]
rw |
LCK[12]
rw |
LCK[11]
rw |
LCK[10]
rw |
LCK[9]
rw |
LCK[8]
rw |
LCK[7]
rw |
LCK[6]
rw |
LCK[5]
rw |
LCK[4]
rw |
LCK[3]
rw |
LCK[2]
rw |
LCK[1]
rw |
LCK[0]
rw |
Bit 0: Port x lock pin 0.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 1: Port x lock pin 1.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 2: Port x lock pin 2.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 3: Port x lock pin 3.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 4: Port x lock pin 4.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 5: Port x lock pin 5.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 6: Port x lock pin 6.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 7: Port x lock pin 7.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 8: Port x lock pin 8.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 9: Port x lock pin 9.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 10: Port x lock pin 10.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 11: Port x lock pin 11.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 12: Port x lock pin 12.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 13: Port x lock pin 13.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 14: Port x lock pin 14.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 15: Port x lock pin 15.
Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked
Bit 16: Port x lock bit y (y= 0..15).
Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active
GPIO alternate function low register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[L7]
rw |
AFR[L6]
rw |
AFR[L5]
rw |
AFR[L4]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[L3]
rw |
AFR[L2]
rw |
AFR[L1]
rw |
AFR[L0]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 0..7).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO alternate function high register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFR[H15]
rw |
AFR[H14]
rw |
AFR[H13]
rw |
AFR[H12]
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFR[H11]
rw |
AFR[H10]
rw |
AFR[H9]
rw |
AFR[H8]
rw |
Bits 0-3: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 4-7: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 8-11: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 12-15: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 16-19: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 20-23: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 24-27: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
Bits 28-31: Alternate function selection for port x bit y (y = 8..15).
Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15
GPIO port bit reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: write-only
16/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR[15]
w |
BR[14]
w |
BR[13]
w |
BR[12]
w |
BR[11]
w |
BR[10]
w |
BR[9]
w |
BR[8]
w |
BR[7]
w |
BR[6]
w |
BR[5]
w |
BR[4]
w |
BR[3]
w |
BR[2]
w |
BR[1]
w |
BR[0]
w |
Bit 0: Port x reset pin 0.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 1: Port x reset pin 1.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 2: Port x reset pin 2.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 3: Port x reset pin 3.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 4: Port x reset pin 4.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 5: Port x reset pin 5.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 6: Port x reset pin 6.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 7: Port x reset pin 7.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 8: Port x reset pin 8.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 9: Port x reset pin 9.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 10: Port x reset pin 10.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 11: Port x reset pin 11.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 12: Port x reset pin 12.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 13: Port x reset pin 13.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 14: Port x reset pin 14.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
Bit 15: Port x reset pin 15.
Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit
0x50060400: Hash processor
13/82 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | DIN | ||||||||||||||||||||||||||||||||
0x8 | STR | ||||||||||||||||||||||||||||||||
0xc | HR[0] | ||||||||||||||||||||||||||||||||
0x20 | IMR | ||||||||||||||||||||||||||||||||
0x24 | SR | ||||||||||||||||||||||||||||||||
0xf8 | CSR[0] | ||||||||||||||||||||||||||||||||
0xfc | CSR[1] | ||||||||||||||||||||||||||||||||
0x100 | CSR[2] | ||||||||||||||||||||||||||||||||
0x104 | CSR[3] | ||||||||||||||||||||||||||||||||
0x108 | CSR[4] | ||||||||||||||||||||||||||||||||
0x10c | CSR[5] | ||||||||||||||||||||||||||||||||
0x110 | CSR[6] | ||||||||||||||||||||||||||||||||
0x114 | CSR[7] | ||||||||||||||||||||||||||||||||
0x118 | CSR[8] | ||||||||||||||||||||||||||||||||
0x11c | CSR[9] | ||||||||||||||||||||||||||||||||
0x120 | CSR[10] | ||||||||||||||||||||||||||||||||
0x124 | CSR[11] | ||||||||||||||||||||||||||||||||
0x128 | CSR[12] | ||||||||||||||||||||||||||||||||
0x12c | CSR[13] | ||||||||||||||||||||||||||||||||
0x130 | CSR[14] | ||||||||||||||||||||||||||||||||
0x134 | CSR[15] | ||||||||||||||||||||||||||||||||
0x138 | CSR[16] | ||||||||||||||||||||||||||||||||
0x13c | CSR[17] | ||||||||||||||||||||||||||||||||
0x140 | CSR[18] | ||||||||||||||||||||||||||||||||
0x144 | CSR[19] | ||||||||||||||||||||||||||||||||
0x148 | CSR[20] | ||||||||||||||||||||||||||||||||
0x14c | CSR[21] | ||||||||||||||||||||||||||||||||
0x150 | CSR[22] | ||||||||||||||||||||||||||||||||
0x154 | CSR[23] | ||||||||||||||||||||||||||||||||
0x158 | CSR[24] | ||||||||||||||||||||||||||||||||
0x15c | CSR[25] | ||||||||||||||||||||||||||||||||
0x160 | CSR[26] | ||||||||||||||||||||||||||||||||
0x164 | CSR[27] | ||||||||||||||||||||||||||||||||
0x168 | CSR[28] | ||||||||||||||||||||||||||||||||
0x16c | CSR[29] | ||||||||||||||||||||||||||||||||
0x170 | CSR[30] | ||||||||||||||||||||||||||||||||
0x174 | CSR[31] | ||||||||||||||||||||||||||||||||
0x178 | CSR[32] | ||||||||||||||||||||||||||||||||
0x17c | CSR[33] | ||||||||||||||||||||||||||||||||
0x180 | CSR[34] | ||||||||||||||||||||||||||||||||
0x184 | CSR[35] | ||||||||||||||||||||||||||||||||
0x188 | CSR[36] | ||||||||||||||||||||||||||||||||
0x18c | CSR[37] | ||||||||||||||||||||||||||||||||
0x190 | CSR[38] | ||||||||||||||||||||||||||||||||
0x194 | CSR[39] | ||||||||||||||||||||||||||||||||
0x198 | CSR[40] | ||||||||||||||||||||||||||||||||
0x19c | CSR[41] | ||||||||||||||||||||||||||||||||
0x1a0 | CSR[42] | ||||||||||||||||||||||||||||||||
0x1a4 | CSR[43] | ||||||||||||||||||||||||||||||||
0x1a8 | CSR[44] | ||||||||||||||||||||||||||||||||
0x1ac | CSR[45] | ||||||||||||||||||||||||||||||||
0x1b0 | CSR[46] | ||||||||||||||||||||||||||||||||
0x1b4 | CSR[47] | ||||||||||||||||||||||||||||||||
0x1b8 | CSR[48] | ||||||||||||||||||||||||||||||||
0x1bc | CSR[49] | ||||||||||||||||||||||||||||||||
0x1c0 | CSR[50] | ||||||||||||||||||||||||||||||||
0x1c4 | CSR[51] | ||||||||||||||||||||||||||||||||
0x1c8 | CSR[52] | ||||||||||||||||||||||||||||||||
0x1cc | CSR[53] | ||||||||||||||||||||||||||||||||
0x310 | HASH_HR[0] | ||||||||||||||||||||||||||||||||
0x314 | HASH_HR[1] | ||||||||||||||||||||||||||||||||
0x318 | HASH_HR[2] | ||||||||||||||||||||||||||||||||
0x31c | HASH_HR[3] | ||||||||||||||||||||||||||||||||
0x320 | HASH_HR[4] | ||||||||||||||||||||||||||||||||
0x324 | HASH_HR[5] | ||||||||||||||||||||||||||||||||
0x328 | HASH_HR[6] | ||||||||||||||||||||||||||||||||
0x32c | HASH_HR[7] |
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
2/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALGO1
rw |
LKEY
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDMAT
rw |
DINNE
r |
NBW
r |
ALGO0
rw |
MODE
rw |
DATATYPE
rw |
DMAE
rw |
INIT
w |
Bit 2: Initialize message digest calculation.
Bit 3: DMA enable.
Bits 4-5: Data type selection.
Bit 6: Mode selection.
Bit 7: Algorithm selection.
Bits 8-11: Number of words already pushed.
Bit 12: DIN not empty.
Bit 13: Multiple DMA Transfers.
Bit 16: Long key selection.
Bit 18: ALGO.
data input register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
start register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
0/2 fields covered.
digest registers
Offset: 0xc, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
interrupt enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
status register
Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified
2/4 fields covered.
context swap registers
Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x104, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x110, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x114, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x118, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x120, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x124, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x128, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x130, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x134, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x138, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x140, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x144, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x148, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x150, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x154, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x158, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x160, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x164, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x168, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x170, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x174, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x178, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x184, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x188, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x190, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x194, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x198, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
context swap registers
Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
HASH digest register 0
Offset: 0x310, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
HASH digest register 1
Offset: 0x314, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
HASH digest register 2
Offset: 0x318, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
HASH digest register 3
Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
HASH digest register 4
Offset: 0x320, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
HASH digest register 5
Offset: 0x324, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
0x40005400: Inter-integrated circuit
76/76 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | OAR1 | ||||||||||||||||||||||||||||||||
0xc | OAR2 | ||||||||||||||||||||||||||||||||
0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
0x18 | ISR | ||||||||||||||||||||||||||||||||
0x1c | ICR | ||||||||||||||||||||||||||||||||
0x20 | PECR | ||||||||||||||||||||||||||||||||
0x24 | RXDR | ||||||||||||||||||||||||||||||||
0x28 | TXDR |
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECEN
rw |
ALERTEN
rw |
SMBDEN
rw |
SMBHEN
rw |
GCEN
rw |
WUPEN
rw |
NOSTRETCH
rw |
SBC
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDMAEN
rw |
TXDMAEN
rw |
ANFOFF
rw |
DNF
rw |
ERRIE
rw |
TCIE
rw |
STOPIE
rw |
NACKIE
rw |
ADDRIE
rw |
RXIE
rw |
TXIE
rw |
PE
rw |
Bit 0: Peripheral enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 1: TX Interrupt enable.
Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled
Bit 2: RX Interrupt enable.
Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled
Bit 3: Address match interrupt enable (slave only).
Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled
Bit 4: Not acknowledge received interrupt enable.
Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled
Bit 5: STOP detection Interrupt enable.
Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled
Bit 6: Transfer Complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 7: Error interrupts enable.
Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 12: Analog noise filter OFF.
Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled
Bit 14: DMA transmission requests enable.
Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission
Bit 15: DMA reception requests enable.
Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception
Bit 16: Slave byte control.
Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled
Bit 17: Clock stretching disable.
Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled
Bit 18: Wakeup from STOP enable.
Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled
Bit 19: General call enable.
Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed
Bit 20: SMBus Host address enable.
Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed
Bit 21: SMBus Device Default address enable.
Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Bit 23: PEC enable.
Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECBYTE
r/w1s |
AUTOEND
rw |
RELOAD
rw |
NBYTES
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NACK
r/w1s |
STOP
r/w1s |
START
r/w1s |
HEAD10R
rw |
ADD10
rw |
RD_WRN
rw |
SADD
rw |
Bits 0-9: Slave address bit (master mode).
Allowed values: 0x0-0x3ff
Bit 10: Transfer direction (master mode).
Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer
Bit 11: 10-bit addressing mode (master mode).
Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode
Bit 12: 10-bit address header only read direction (master receiver mode).
Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
Bit 13: Start generation.
Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation
Bit 14: Stop generation (master mode).
Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer
Bit 15: NACK generation (slave mode).
Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte
Bits 16-23: Number of bytes.
Allowed values: 0x0-0xff
Bit 24: NBYTES reload mode.
Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
Bit 25: Automatic end mode (master mode).
Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
Bit 26: Packet error checking byte.
Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 0-9: Interface address.
Allowed values: 0x0-0x3ff
Bit 10: Own Address 1 10-bit mode.
Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address
Bit 15: Own Address 1 enable.
Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed
Own address register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 1-7: Interface address.
Allowed values: 0x0-0x7f
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
Bit 15: Own Address 2 enable.
Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed
Timing register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESC
rw |
SCLDEL
rw |
SDADEL
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCLH
rw |
SCLL
rw |
Bits 0-7: SCL low period (master mode).
Allowed values: 0x0-0xff
Bits 8-15: SCL high period (master mode).
Allowed values: 0x0-0xff
Bits 16-19: Data hold time.
Allowed values: 0x0-0xf
Bits 20-23: Data setup time.
Allowed values: 0x0-0xf
Bits 28-31: Timing prescaler.
Allowed values: 0x0-0xf
Status register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEXTEN
rw |
TIMEOUTB
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMOUTEN
rw |
TIDLE
rw |
TIMEOUTA
rw |
Bits 0-11: Bus timeout A.
Allowed values: 0x0-0xfff
Bit 12: Idle clock timeout detection.
Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Bit 15: Clock timeout enable.
Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled
Bits 16-27: Bus timeout B.
Allowed values: 0x0-0xfff
Bit 31: Extended clock timeout enable.
Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled
Interrupt and Status register
Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDCODE
r |
DIR
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUSY
r |
ALERT
r |
TIMEOUT
r |
PECERR
r |
OVR
r |
ARLO
r |
BERR
r |
TCR
r |
TC
r |
STOPF
r |
NACKF
r |
ADDR
r |
RXNE
r |
TXIS
r/w1s |
TXE
r/w1s |
Bit 0: Transmit data register empty (transmitters).
Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty
Bit 1: Transmit interrupt status (transmitters).
Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Bit 2: Receive data register not empty (receivers).
Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read
Bit 3: Address matched (slave mode).
Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses
Bit 4: Not acknowledge received flag.
Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received
Bit 5: Stop detection flag.
Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected
Bit 6: Transfer Complete (master mode).
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 7: Transfer Complete Reload.
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 8: Bus error.
Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected
Bit 9: Arbitration lost.
Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost
Bit 10: Overrun/Underrun (slave mode).
Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
Bit 11: PEC Error in reception.
Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register
Bit 12: Timeout or t_low detection flag.
Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured
Bit 13: SMBus alert.
Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin
Bit 15: Bus busy.
Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus
Bit 16: Transfer direction (Slave mode).
Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode
Bits 17-23: Address match code (Slave mode).
Allowed values: 0x0-0x7f
Interrupt clear register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALERTCF
w1c |
TIMOUTCF
w1c |
PECCF
w1c |
OVRCF
w1c |
ARLOCF
w1c |
BERRCF
w1c |
STOPCF
w1c |
NACKCF
w1c |
ADDRCF
w1c |
Bit 3: Address Matched flag clear.
Allowed values:
1: Clear: Clears the ADDR flag in ISR register
Bit 4: Not Acknowledge flag clear.
Allowed values:
1: Clear: Clears the NACK flag in ISR register
Bit 5: Stop detection flag clear.
Allowed values:
1: Clear: Clears the STOP flag in ISR register
Bit 8: Bus error flag clear.
Allowed values:
1: Clear: Clears the BERR flag in ISR register
Bit 9: Arbitration lost flag clear.
Allowed values:
1: Clear: Clears the ARLO flag in ISR register
Bit 10: Overrun/Underrun flag clear.
Allowed values:
1: Clear: Clears the OVR flag in ISR register
Bit 11: PEC Error flag clear.
Allowed values:
1: Clear: Clears the PEC flag in ISR register
Bit 12: Timeout detection flag clear.
Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register
Bit 13: Alert flag clear.
Allowed values:
1: Clear: Clears the ALERT flag in ISR register
PEC register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PEC
r |
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
rw |
0x40005800: Inter-integrated circuit
76/76 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | OAR1 | ||||||||||||||||||||||||||||||||
0xc | OAR2 | ||||||||||||||||||||||||||||||||
0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
0x18 | ISR | ||||||||||||||||||||||||||||||||
0x1c | ICR | ||||||||||||||||||||||||||||||||
0x20 | PECR | ||||||||||||||||||||||||||||||||
0x24 | RXDR | ||||||||||||||||||||||||||||||||
0x28 | TXDR |
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECEN
rw |
ALERTEN
rw |
SMBDEN
rw |
SMBHEN
rw |
GCEN
rw |
WUPEN
rw |
NOSTRETCH
rw |
SBC
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDMAEN
rw |
TXDMAEN
rw |
ANFOFF
rw |
DNF
rw |
ERRIE
rw |
TCIE
rw |
STOPIE
rw |
NACKIE
rw |
ADDRIE
rw |
RXIE
rw |
TXIE
rw |
PE
rw |
Bit 0: Peripheral enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 1: TX Interrupt enable.
Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled
Bit 2: RX Interrupt enable.
Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled
Bit 3: Address match interrupt enable (slave only).
Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled
Bit 4: Not acknowledge received interrupt enable.
Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled
Bit 5: STOP detection Interrupt enable.
Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled
Bit 6: Transfer Complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 7: Error interrupts enable.
Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 12: Analog noise filter OFF.
Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled
Bit 14: DMA transmission requests enable.
Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission
Bit 15: DMA reception requests enable.
Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception
Bit 16: Slave byte control.
Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled
Bit 17: Clock stretching disable.
Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled
Bit 18: Wakeup from STOP enable.
Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled
Bit 19: General call enable.
Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed
Bit 20: SMBus Host address enable.
Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed
Bit 21: SMBus Device Default address enable.
Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Bit 23: PEC enable.
Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECBYTE
r/w1s |
AUTOEND
rw |
RELOAD
rw |
NBYTES
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NACK
r/w1s |
STOP
r/w1s |
START
r/w1s |
HEAD10R
rw |
ADD10
rw |
RD_WRN
rw |
SADD
rw |
Bits 0-9: Slave address bit (master mode).
Allowed values: 0x0-0x3ff
Bit 10: Transfer direction (master mode).
Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer
Bit 11: 10-bit addressing mode (master mode).
Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode
Bit 12: 10-bit address header only read direction (master receiver mode).
Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
Bit 13: Start generation.
Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation
Bit 14: Stop generation (master mode).
Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer
Bit 15: NACK generation (slave mode).
Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte
Bits 16-23: Number of bytes.
Allowed values: 0x0-0xff
Bit 24: NBYTES reload mode.
Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
Bit 25: Automatic end mode (master mode).
Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
Bit 26: Packet error checking byte.
Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 0-9: Interface address.
Allowed values: 0x0-0x3ff
Bit 10: Own Address 1 10-bit mode.
Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address
Bit 15: Own Address 1 enable.
Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed
Own address register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 1-7: Interface address.
Allowed values: 0x0-0x7f
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
Bit 15: Own Address 2 enable.
Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed
Timing register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESC
rw |
SCLDEL
rw |
SDADEL
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCLH
rw |
SCLL
rw |
Bits 0-7: SCL low period (master mode).
Allowed values: 0x0-0xff
Bits 8-15: SCL high period (master mode).
Allowed values: 0x0-0xff
Bits 16-19: Data hold time.
Allowed values: 0x0-0xf
Bits 20-23: Data setup time.
Allowed values: 0x0-0xf
Bits 28-31: Timing prescaler.
Allowed values: 0x0-0xf
Status register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEXTEN
rw |
TIMEOUTB
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMOUTEN
rw |
TIDLE
rw |
TIMEOUTA
rw |
Bits 0-11: Bus timeout A.
Allowed values: 0x0-0xfff
Bit 12: Idle clock timeout detection.
Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Bit 15: Clock timeout enable.
Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled
Bits 16-27: Bus timeout B.
Allowed values: 0x0-0xfff
Bit 31: Extended clock timeout enable.
Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled
Interrupt and Status register
Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDCODE
r |
DIR
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUSY
r |
ALERT
r |
TIMEOUT
r |
PECERR
r |
OVR
r |
ARLO
r |
BERR
r |
TCR
r |
TC
r |
STOPF
r |
NACKF
r |
ADDR
r |
RXNE
r |
TXIS
r/w1s |
TXE
r/w1s |
Bit 0: Transmit data register empty (transmitters).
Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty
Bit 1: Transmit interrupt status (transmitters).
Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Bit 2: Receive data register not empty (receivers).
Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read
Bit 3: Address matched (slave mode).
Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses
Bit 4: Not acknowledge received flag.
Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received
Bit 5: Stop detection flag.
Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected
Bit 6: Transfer Complete (master mode).
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 7: Transfer Complete Reload.
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 8: Bus error.
Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected
Bit 9: Arbitration lost.
Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost
Bit 10: Overrun/Underrun (slave mode).
Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
Bit 11: PEC Error in reception.
Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register
Bit 12: Timeout or t_low detection flag.
Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured
Bit 13: SMBus alert.
Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin
Bit 15: Bus busy.
Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus
Bit 16: Transfer direction (Slave mode).
Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode
Bits 17-23: Address match code (Slave mode).
Allowed values: 0x0-0x7f
Interrupt clear register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALERTCF
w1c |
TIMOUTCF
w1c |
PECCF
w1c |
OVRCF
w1c |
ARLOCF
w1c |
BERRCF
w1c |
STOPCF
w1c |
NACKCF
w1c |
ADDRCF
w1c |
Bit 3: Address Matched flag clear.
Allowed values:
1: Clear: Clears the ADDR flag in ISR register
Bit 4: Not Acknowledge flag clear.
Allowed values:
1: Clear: Clears the NACK flag in ISR register
Bit 5: Stop detection flag clear.
Allowed values:
1: Clear: Clears the STOP flag in ISR register
Bit 8: Bus error flag clear.
Allowed values:
1: Clear: Clears the BERR flag in ISR register
Bit 9: Arbitration lost flag clear.
Allowed values:
1: Clear: Clears the ARLO flag in ISR register
Bit 10: Overrun/Underrun flag clear.
Allowed values:
1: Clear: Clears the OVR flag in ISR register
Bit 11: PEC Error flag clear.
Allowed values:
1: Clear: Clears the PEC flag in ISR register
Bit 12: Timeout detection flag clear.
Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register
Bit 13: Alert flag clear.
Allowed values:
1: Clear: Clears the ALERT flag in ISR register
PEC register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PEC
r |
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
rw |
0x40005c00: Inter-integrated circuit
76/76 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | OAR1 | ||||||||||||||||||||||||||||||||
0xc | OAR2 | ||||||||||||||||||||||||||||||||
0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
0x18 | ISR | ||||||||||||||||||||||||||||||||
0x1c | ICR | ||||||||||||||||||||||||||||||||
0x20 | PECR | ||||||||||||||||||||||||||||||||
0x24 | RXDR | ||||||||||||||||||||||||||||||||
0x28 | TXDR |
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECEN
rw |
ALERTEN
rw |
SMBDEN
rw |
SMBHEN
rw |
GCEN
rw |
WUPEN
rw |
NOSTRETCH
rw |
SBC
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDMAEN
rw |
TXDMAEN
rw |
ANFOFF
rw |
DNF
rw |
ERRIE
rw |
TCIE
rw |
STOPIE
rw |
NACKIE
rw |
ADDRIE
rw |
RXIE
rw |
TXIE
rw |
PE
rw |
Bit 0: Peripheral enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 1: TX Interrupt enable.
Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled
Bit 2: RX Interrupt enable.
Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled
Bit 3: Address match interrupt enable (slave only).
Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled
Bit 4: Not acknowledge received interrupt enable.
Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled
Bit 5: STOP detection Interrupt enable.
Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled
Bit 6: Transfer Complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 7: Error interrupts enable.
Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 12: Analog noise filter OFF.
Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled
Bit 14: DMA transmission requests enable.
Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission
Bit 15: DMA reception requests enable.
Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception
Bit 16: Slave byte control.
Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled
Bit 17: Clock stretching disable.
Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled
Bit 18: Wakeup from STOP enable.
Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled
Bit 19: General call enable.
Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed
Bit 20: SMBus Host address enable.
Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed
Bit 21: SMBus Device Default address enable.
Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Bit 23: PEC enable.
Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECBYTE
r/w1s |
AUTOEND
rw |
RELOAD
rw |
NBYTES
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NACK
r/w1s |
STOP
r/w1s |
START
r/w1s |
HEAD10R
rw |
ADD10
rw |
RD_WRN
rw |
SADD
rw |
Bits 0-9: Slave address bit (master mode).
Allowed values: 0x0-0x3ff
Bit 10: Transfer direction (master mode).
Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer
Bit 11: 10-bit addressing mode (master mode).
Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode
Bit 12: 10-bit address header only read direction (master receiver mode).
Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
Bit 13: Start generation.
Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation
Bit 14: Stop generation (master mode).
Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer
Bit 15: NACK generation (slave mode).
Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte
Bits 16-23: Number of bytes.
Allowed values: 0x0-0xff
Bit 24: NBYTES reload mode.
Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
Bit 25: Automatic end mode (master mode).
Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
Bit 26: Packet error checking byte.
Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 0-9: Interface address.
Allowed values: 0x0-0x3ff
Bit 10: Own Address 1 10-bit mode.
Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address
Bit 15: Own Address 1 enable.
Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed
Own address register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 1-7: Interface address.
Allowed values: 0x0-0x7f
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
Bit 15: Own Address 2 enable.
Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed
Timing register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESC
rw |
SCLDEL
rw |
SDADEL
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCLH
rw |
SCLL
rw |
Bits 0-7: SCL low period (master mode).
Allowed values: 0x0-0xff
Bits 8-15: SCL high period (master mode).
Allowed values: 0x0-0xff
Bits 16-19: Data hold time.
Allowed values: 0x0-0xf
Bits 20-23: Data setup time.
Allowed values: 0x0-0xf
Bits 28-31: Timing prescaler.
Allowed values: 0x0-0xf
Status register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEXTEN
rw |
TIMEOUTB
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMOUTEN
rw |
TIDLE
rw |
TIMEOUTA
rw |
Bits 0-11: Bus timeout A.
Allowed values: 0x0-0xfff
Bit 12: Idle clock timeout detection.
Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Bit 15: Clock timeout enable.
Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled
Bits 16-27: Bus timeout B.
Allowed values: 0x0-0xfff
Bit 31: Extended clock timeout enable.
Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled
Interrupt and Status register
Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDCODE
r |
DIR
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUSY
r |
ALERT
r |
TIMEOUT
r |
PECERR
r |
OVR
r |
ARLO
r |
BERR
r |
TCR
r |
TC
r |
STOPF
r |
NACKF
r |
ADDR
r |
RXNE
r |
TXIS
r/w1s |
TXE
r/w1s |
Bit 0: Transmit data register empty (transmitters).
Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty
Bit 1: Transmit interrupt status (transmitters).
Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Bit 2: Receive data register not empty (receivers).
Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read
Bit 3: Address matched (slave mode).
Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses
Bit 4: Not acknowledge received flag.
Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received
Bit 5: Stop detection flag.
Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected
Bit 6: Transfer Complete (master mode).
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 7: Transfer Complete Reload.
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 8: Bus error.
Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected
Bit 9: Arbitration lost.
Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost
Bit 10: Overrun/Underrun (slave mode).
Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
Bit 11: PEC Error in reception.
Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register
Bit 12: Timeout or t_low detection flag.
Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured
Bit 13: SMBus alert.
Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin
Bit 15: Bus busy.
Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus
Bit 16: Transfer direction (Slave mode).
Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode
Bits 17-23: Address match code (Slave mode).
Allowed values: 0x0-0x7f
Interrupt clear register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALERTCF
w1c |
TIMOUTCF
w1c |
PECCF
w1c |
OVRCF
w1c |
ARLOCF
w1c |
BERRCF
w1c |
STOPCF
w1c |
NACKCF
w1c |
ADDRCF
w1c |
Bit 3: Address Matched flag clear.
Allowed values:
1: Clear: Clears the ADDR flag in ISR register
Bit 4: Not Acknowledge flag clear.
Allowed values:
1: Clear: Clears the NACK flag in ISR register
Bit 5: Stop detection flag clear.
Allowed values:
1: Clear: Clears the STOP flag in ISR register
Bit 8: Bus error flag clear.
Allowed values:
1: Clear: Clears the BERR flag in ISR register
Bit 9: Arbitration lost flag clear.
Allowed values:
1: Clear: Clears the ARLO flag in ISR register
Bit 10: Overrun/Underrun flag clear.
Allowed values:
1: Clear: Clears the OVR flag in ISR register
Bit 11: PEC Error flag clear.
Allowed values:
1: Clear: Clears the PEC flag in ISR register
Bit 12: Timeout detection flag clear.
Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register
Bit 13: Alert flag clear.
Allowed values:
1: Clear: Clears the ALERT flag in ISR register
PEC register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PEC
r |
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
rw |
0x40008400: Inter-integrated circuit
76/76 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | OAR1 | ||||||||||||||||||||||||||||||||
0xc | OAR2 | ||||||||||||||||||||||||||||||||
0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
0x18 | ISR | ||||||||||||||||||||||||||||||||
0x1c | ICR | ||||||||||||||||||||||||||||||||
0x20 | PECR | ||||||||||||||||||||||||||||||||
0x24 | RXDR | ||||||||||||||||||||||||||||||||
0x28 | TXDR |
Control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECEN
rw |
ALERTEN
rw |
SMBDEN
rw |
SMBHEN
rw |
GCEN
rw |
WUPEN
rw |
NOSTRETCH
rw |
SBC
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXDMAEN
rw |
TXDMAEN
rw |
ANFOFF
rw |
DNF
rw |
ERRIE
rw |
TCIE
rw |
STOPIE
rw |
NACKIE
rw |
ADDRIE
rw |
RXIE
rw |
TXIE
rw |
PE
rw |
Bit 0: Peripheral enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 1: TX Interrupt enable.
Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled
Bit 2: RX Interrupt enable.
Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled
Bit 3: Address match interrupt enable (slave only).
Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled
Bit 4: Not acknowledge received interrupt enable.
Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled
Bit 5: STOP detection Interrupt enable.
Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled
Bit 6: Transfer Complete interrupt enable.
Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled
Bit 7: Error interrupts enable.
Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled
Bits 8-11: Digital noise filter.
Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK
Bit 12: Analog noise filter OFF.
Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled
Bit 14: DMA transmission requests enable.
Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission
Bit 15: DMA reception requests enable.
Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception
Bit 16: Slave byte control.
Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled
Bit 17: Clock stretching disable.
Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled
Bit 18: Wakeup from STOP enable.
Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled
Bit 19: General call enable.
Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed
Bit 20: SMBus Host address enable.
Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed
Bit 21: SMBus Device Default address enable.
Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed
Bit 22: SMBUS alert enable.
Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported
Bit 23: PEC enable.
Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled
Control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
11/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PECBYTE
r/w1s |
AUTOEND
rw |
RELOAD
rw |
NBYTES
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NACK
r/w1s |
STOP
r/w1s |
START
r/w1s |
HEAD10R
rw |
ADD10
rw |
RD_WRN
rw |
SADD
rw |
Bits 0-9: Slave address bit (master mode).
Allowed values: 0x0-0x3ff
Bit 10: Transfer direction (master mode).
Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer
Bit 11: 10-bit addressing mode (master mode).
Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode
Bit 12: 10-bit address header only read direction (master receiver mode).
Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
Bit 13: Start generation.
Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation
Bit 14: Stop generation (master mode).
Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer
Bit 15: NACK generation (slave mode).
Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte
Bits 16-23: Number of bytes.
Allowed values: 0x0-0xff
Bit 24: NBYTES reload mode.
Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
Bit 25: Automatic end mode (master mode).
Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred
Bit 26: Packet error checking byte.
Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 0-9: Interface address.
Allowed values: 0x0-0x3ff
Bit 10: Own Address 1 10-bit mode.
Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address
Bit 15: Own Address 1 enable.
Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed
Own address register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
3/3 fields covered.
Bits 1-7: Interface address.
Allowed values: 0x0-0x7f
Bits 8-10: Own Address 2 masks.
Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
Bit 15: Own Address 2 enable.
Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed
Timing register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESC
rw |
SCLDEL
rw |
SDADEL
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCLH
rw |
SCLL
rw |
Bits 0-7: SCL low period (master mode).
Allowed values: 0x0-0xff
Bits 8-15: SCL high period (master mode).
Allowed values: 0x0-0xff
Bits 16-19: Data hold time.
Allowed values: 0x0-0xf
Bits 20-23: Data setup time.
Allowed values: 0x0-0xf
Bits 28-31: Timing prescaler.
Allowed values: 0x0-0xf
Status register 1
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEXTEN
rw |
TIMEOUTB
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMOUTEN
rw |
TIDLE
rw |
TIMEOUTA
rw |
Bits 0-11: Bus timeout A.
Allowed values: 0x0-0xfff
Bit 12: Idle clock timeout detection.
Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Bit 15: Clock timeout enable.
Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled
Bits 16-27: Bus timeout B.
Allowed values: 0x0-0xfff
Bit 31: Extended clock timeout enable.
Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled
Interrupt and Status register
Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDCODE
r |
DIR
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BUSY
r |
ALERT
r |
TIMEOUT
r |
PECERR
r |
OVR
r |
ARLO
r |
BERR
r |
TCR
r |
TC
r |
STOPF
r |
NACKF
r |
ADDR
r |
RXNE
r |
TXIS
r/w1s |
TXE
r/w1s |
Bit 0: Transmit data register empty (transmitters).
Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty
Bit 1: Transmit interrupt status (transmitters).
Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Bit 2: Receive data register not empty (receivers).
Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read
Bit 3: Address matched (slave mode).
Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses
Bit 4: Not acknowledge received flag.
Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received
Bit 5: Stop detection flag.
Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected
Bit 6: Transfer Complete (master mode).
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 7: Transfer Complete Reload.
Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered
Bit 8: Bus error.
Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected
Bit 9: Arbitration lost.
Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost
Bit 10: Overrun/Underrun (slave mode).
Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs
Bit 11: PEC Error in reception.
Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register
Bit 12: Timeout or t_low detection flag.
Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured
Bit 13: SMBus alert.
Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin
Bit 15: Bus busy.
Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus
Bit 16: Transfer direction (Slave mode).
Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode
Bits 17-23: Address match code (Slave mode).
Allowed values: 0x0-0x7f
Interrupt clear register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ALERTCF
w1c |
TIMOUTCF
w1c |
PECCF
w1c |
OVRCF
w1c |
ARLOCF
w1c |
BERRCF
w1c |
STOPCF
w1c |
NACKCF
w1c |
ADDRCF
w1c |
Bit 3: Address Matched flag clear.
Allowed values:
1: Clear: Clears the ADDR flag in ISR register
Bit 4: Not Acknowledge flag clear.
Allowed values:
1: Clear: Clears the NACK flag in ISR register
Bit 5: Stop detection flag clear.
Allowed values:
1: Clear: Clears the STOP flag in ISR register
Bit 8: Bus error flag clear.
Allowed values:
1: Clear: Clears the BERR flag in ISR register
Bit 9: Arbitration lost flag clear.
Allowed values:
1: Clear: Clears the ARLO flag in ISR register
Bit 10: Overrun/Underrun flag clear.
Allowed values:
1: Clear: Clears the OVR flag in ISR register
Bit 11: PEC Error flag clear.
Allowed values:
1: Clear: Clears the PEC flag in ISR register
Bit 12: Timeout detection flag clear.
Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register
Bit 13: Alert flag clear.
Allowed values:
1: Clear: Clears the ALERT flag in ISR register
PEC register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PEC
r |
Receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDATA
r |
Transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXDATA
rw |
0x40003000: Independent watchdog
7/7 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | KR | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | PR | ||||||||||||||||||||||||||||||||
0x8 (16-bit) | RLR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | WINR |
Key register
Offset: 0x0, size: 16, reset: 0x00000000, access: write-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
w |
Prescaler register
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PR
rw |
Reload register
Offset: 0x8, size: 16, reset: 0x00000FFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RL
rw |
Window register
Offset: 0x10, size: 16, reset: 0x00000FFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WIN
rw |
0x40007c00: Low power timer
8/40 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ISR | ||||||||||||||||||||||||||||||||
0x4 | ICR | ||||||||||||||||||||||||||||||||
0x8 | IER | ||||||||||||||||||||||||||||||||
0xc | CFGR | ||||||||||||||||||||||||||||||||
0x10 | CR | ||||||||||||||||||||||||||||||||
0x14 | CMP | ||||||||||||||||||||||||||||||||
0x18 | ARR | ||||||||||||||||||||||||||||||||
0x1c | CNT |
Interrupt and Status Register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
7/7 fields covered.
Interrupt Clear Register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DOWNCF
w |
UPCF
w |
ARROKCF
w |
CMPOKCF
w |
EXTTRIGCF
w |
ARRMCF
w |
CMPMCF
w |
Bit 0: compare match Clear Flag.
Bit 1: Autoreload match Clear Flag.
Bit 2: External trigger valid edge Clear Flag.
Bit 3: Compare register update OK Clear Flag.
Bit 4: Autoreload register update OK Clear Flag.
Bit 5: Direction change to UP Clear Flag.
Bit 6: Direction change to down Clear Flag.
Interrupt Enable Register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DOWNIE
rw |
UPIE
rw |
ARROKIE
rw |
CMPOKIE
rw |
EXTTRIGIE
rw |
ARRMIE
rw |
CMPMIE
rw |
Bit 0: Compare match Interrupt Enable.
Bit 1: Autoreload match Interrupt Enable.
Bit 2: External trigger valid edge Interrupt Enable.
Bit 3: Compare register update OK Interrupt Enable.
Bit 4: Autoreload register update OK Interrupt Enable.
Bit 5: Direction change to UP Interrupt Enable.
Bit 6: Direction change to down Interrupt Enable.
Configuration Register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENC
rw |
COUNTMODE
rw |
PRELOAD
rw |
WAVPOL
rw |
WAVE
rw |
TIMOUT
rw |
TRIGEN
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIGSEL
rw |
PRESC
rw |
TRGFLT
rw |
CKFLT
rw |
CKPOL
rw |
CKSEL
rw |
Bit 0: Clock selector.
Bits 1-2: Clock Polarity.
Bits 3-4: Configurable digital filter for external clock.
Bits 6-7: Configurable digital filter for trigger.
Bits 9-11: Clock prescaler.
Bits 13-15: Trigger selector.
Bits 17-18: Trigger enable and polarity.
Bit 19: Timeout enable.
Bit 20: Waveform shape.
Bit 21: Waveform shape polarity.
Bit 22: Registers update mode.
Bit 23: counter mode enabled.
Bit 24: Encoder mode enable.
Control Register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Compare Register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP
rw |
Autoreload Register
Offset: 0x18, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Counter Register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
0x40009400: Low power timer
8/40 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ISR | ||||||||||||||||||||||||||||||||
0x4 | ICR | ||||||||||||||||||||||||||||||||
0x8 | IER | ||||||||||||||||||||||||||||||||
0xc | CFGR | ||||||||||||||||||||||||||||||||
0x10 | CR | ||||||||||||||||||||||||||||||||
0x14 | CMP | ||||||||||||||||||||||||||||||||
0x18 | ARR | ||||||||||||||||||||||||||||||||
0x1c | CNT |
Interrupt and Status Register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-only
7/7 fields covered.
Interrupt Clear Register
Offset: 0x4, size: 32, reset: 0x00000000, access: write-only
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DOWNCF
w |
UPCF
w |
ARROKCF
w |
CMPOKCF
w |
EXTTRIGCF
w |
ARRMCF
w |
CMPMCF
w |
Bit 0: compare match Clear Flag.
Bit 1: Autoreload match Clear Flag.
Bit 2: External trigger valid edge Clear Flag.
Bit 3: Compare register update OK Clear Flag.
Bit 4: Autoreload register update OK Clear Flag.
Bit 5: Direction change to UP Clear Flag.
Bit 6: Direction change to down Clear Flag.
Interrupt Enable Register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DOWNIE
rw |
UPIE
rw |
ARROKIE
rw |
CMPOKIE
rw |
EXTTRIGIE
rw |
ARRMIE
rw |
CMPMIE
rw |
Bit 0: Compare match Interrupt Enable.
Bit 1: Autoreload match Interrupt Enable.
Bit 2: External trigger valid edge Interrupt Enable.
Bit 3: Compare register update OK Interrupt Enable.
Bit 4: Autoreload register update OK Interrupt Enable.
Bit 5: Direction change to UP Interrupt Enable.
Bit 6: Direction change to down Interrupt Enable.
Configuration Register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENC
rw |
COUNTMODE
rw |
PRELOAD
rw |
WAVPOL
rw |
WAVE
rw |
TIMOUT
rw |
TRIGEN
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRIGSEL
rw |
PRESC
rw |
TRGFLT
rw |
CKFLT
rw |
CKPOL
rw |
CKSEL
rw |
Bit 0: Clock selector.
Bits 1-2: Clock Polarity.
Bits 3-4: Configurable digital filter for external clock.
Bits 6-7: Configurable digital filter for trigger.
Bits 9-11: Clock prescaler.
Bits 13-15: Trigger selector.
Bits 17-18: Trigger enable and polarity.
Bit 19: Timeout enable.
Bit 20: Waveform shape.
Bit 21: Waveform shape polarity.
Bit 22: Registers update mode.
Bit 23: counter mode enabled.
Bit 24: Encoder mode enable.
Control Register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Compare Register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP
rw |
Autoreload Register
Offset: 0x18, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Counter Register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
0x40008000: Universal synchronous asynchronous receiver transmitter
84/84 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | BRR | ||||||||||||||||||||||||||||||||
0x18 | RQR | ||||||||||||||||||||||||||||||||
0x1c | ISR | ||||||||||||||||||||||||||||||||
0x20 | ICR | ||||||||||||||||||||||||||||||||
0x24 | RDR | ||||||||||||||||||||||||||||||||
0x28 | TDR | ||||||||||||||||||||||||||||||||
0x2c | PRESC |
LPUART control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
21/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFFIE
rw |
TXFEIE
rw |
FIFOEN
rw |
M1
rw |
DEAT
rw |
DEDT
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMIE
rw |
MME
rw |
M0
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit..
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode. When this bit is set, the LPUART is able to wake up the MCU from low-power mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it on exit from low-power mode..
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. Note: When TE is set there is a 1 bit-time delay before the transmission starts..
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: TXFIFO not full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description). This bit can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bits 16-20: Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 34.4.13: RS232 Hardware flow control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values: 0x0-0x1f
Bits 21-25: Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 33.5.20: RS232 Hardware flow control and RS485 Driver Enable. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values: 0x0-0x1f
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 Start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 Start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UE = 0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits
Bit 29: FIFO mode enable This bit is set and cleared by software..
Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled
Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register
Bit 31: RXFIFO full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register
LPUART control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAP
rw |
STOP
rw |
ADDM7
rw |
Bit 4: 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bits 12-13: STOP bits These bits are used for programming the stop bits. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bit
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bits 24-31: Address of the LPUART node These bits give the address of the LPUART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)..
Allowed values: 0x0-0xff
LPUART control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
HDSEL
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FE = 1 or ORE = 1 or NE = 1 in the LPUART_ISR register)..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 6: DMA enable receiver This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable This bit can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable This bit can only be written when the LPUART is disabled (UE = 0).
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable.
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 12: Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data..
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA disable on reception error This bit can only be written when the LPUART is disabled (UE = 0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection This bit can only be written when the LPUART is disabled (UE = 0)..
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UE = 0). Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation..
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved..
Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full
Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved..
Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty
LPUART baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
LPUART request register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request Writing 1 to this bit puts the LPUART in Mute mode and resets the RWU flag..
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request Writing 1 to this bit clears the RXNE flag. This enables discarding the received data without reading it, and avoid an overrun condition..
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
LPUART interrupt and status register
Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified
21/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFT
r |
RXFT
r |
RXFF
r |
TXFE
r |
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTS
r |
CTSIF
r |
TXFNF
r |
TC
r |
RXFNE
r |
IDLE
r |
ORE
r |
NE
r |
FE
r |
PE
r |
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the LPUART_CR3 register. Note: This error is associated with the character in the LPUART_RDR..
Bit 2: Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NECF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: This error is associated with the character in the LPUART_RDR..
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the LPUART_CR1 register, or EIE = 1 in the LPUART_CR3 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register..
Bit 4: Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIE = 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the LPUART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIE = 1 in the LPUART_CR1 register..
Bit 6: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXFF is set. An interrupt is generated if TCIE = 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register. An interrupt is generated if TCIE = 1 in the LPUART_CR1 register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit = 1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission..
Bit 9: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIE = 1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIE = 1in the LPUART_CR1 register..
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Bit 19: Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIE = 1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value.
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the LPUART_CR1 register, in order to respect the TE = 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the LPUART_CR1 register..
Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the LPUART_CR1 register..
Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.
Bit 26: RXFIFO threshold flag This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the LPUART_CR3 register..
Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the LPUART_CR3 register..
Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.
LPUART interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
9/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUCF
w1c |
CMCF
w1c |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTSCF
w1c |
TCCF
w1c |
IDLECF
w1c |
ORECF
w1c |
NECF
w1c |
FECF
w1c |
PECF
w1c |
Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the LPUART_ISR register..
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the LPUART_ISR register..
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the LPUART_ISR register..
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the LPUART_ISR register..
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register..
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the LPUART_ISR register..
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register..
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the LPUART_ISR register..
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the LPUART_ISR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation..
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
LPUART receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDR
r |
Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 347). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..
Allowed values: 0x0-0x1ff
LPUART transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDR
rw |
Bits 0-8: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 347). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1..
Allowed values: 0x0-0x1ff
LPUART prescaler register
Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESCALER
rw |
Bits 0-3: Clock prescaler The LPUART input clock can be divided by a prescaler: Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div6: /6
4: Div8: /8
5: Div10: /10
6: Div12: /12
7: Div16: /16
8: Div32: /32
9: Div64: /64
10: Div128: /128
11: Div256: /256
0x40016800: LCD-TFT display controller
13/93 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x8 | SSCR | ||||||||||||||||||||||||||||||||
0xc | BPCR | ||||||||||||||||||||||||||||||||
0x10 | AWCR | ||||||||||||||||||||||||||||||||
0x14 | TWCR | ||||||||||||||||||||||||||||||||
0x18 | GCR | ||||||||||||||||||||||||||||||||
0x24 | SRCR | ||||||||||||||||||||||||||||||||
0x2c | BCCR | ||||||||||||||||||||||||||||||||
0x34 | IER | ||||||||||||||||||||||||||||||||
0x38 | ISR | ||||||||||||||||||||||||||||||||
0x3c | ICR | ||||||||||||||||||||||||||||||||
0x40 | LIPCR | ||||||||||||||||||||||||||||||||
0x44 | CPSR | ||||||||||||||||||||||||||||||||
0x48 | CDSR | ||||||||||||||||||||||||||||||||
0x84 | L1CR | ||||||||||||||||||||||||||||||||
0x88 | L1WHPCR | ||||||||||||||||||||||||||||||||
0x8c | L1WVPCR | ||||||||||||||||||||||||||||||||
0x90 | L1CKCR | ||||||||||||||||||||||||||||||||
0x94 | L1PFCR | ||||||||||||||||||||||||||||||||
0x98 | L1CACR | ||||||||||||||||||||||||||||||||
0x9c | L1DCCR | ||||||||||||||||||||||||||||||||
0xa0 | L1BFCR | ||||||||||||||||||||||||||||||||
0xac | L1CFBAR | ||||||||||||||||||||||||||||||||
0xb0 | L1CFBLR | ||||||||||||||||||||||||||||||||
0xb4 | L1CFBLNR | ||||||||||||||||||||||||||||||||
0xc4 | L1CLUTWR | ||||||||||||||||||||||||||||||||
0x104 | L2CR | ||||||||||||||||||||||||||||||||
0x108 | L2WHPCR | ||||||||||||||||||||||||||||||||
0x10c | L2WVPCR | ||||||||||||||||||||||||||||||||
0x110 | L2CKCR | ||||||||||||||||||||||||||||||||
0x114 | L2PFCR | ||||||||||||||||||||||||||||||||
0x118 | L2CACR | ||||||||||||||||||||||||||||||||
0x11c | L2DCCR | ||||||||||||||||||||||||||||||||
0x124 | L2BFCR | ||||||||||||||||||||||||||||||||
0x12c | L2CFBAR | ||||||||||||||||||||||||||||||||
0x130 | L2CFBLR | ||||||||||||||||||||||||||||||||
0x134 | L2CFBLNR | ||||||||||||||||||||||||||||||||
0x144 | L2CLUTWR |
LTDC Synchronization Size Configuration Register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Back Porch Configuration Register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Active Width Configuration Register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Total Width Configuration Register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Global Control Register
Offset: 0x18, size: 32, reset: 0x00002220, access: Unspecified
3/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HSPOL
rw |
VSPOL
rw |
DEPOL
rw |
PCPOL
rw |
DEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DRW
r |
DGW
r |
DBW
r |
LTDCEN
rw |
Bit 0: LCD-TFT controller enable bit.
Bits 4-6: Dither Blue Width.
Bits 8-10: Dither Green Width.
Bits 12-14: Dither Red Width.
Bit 16: Dither Enable.
Bit 28: Pixel Clock Polarity.
Bit 29: Not Data Enable Polarity.
Bit 30: Vertical Synchronization Polarity.
Bit 31: Horizontal Synchronization Polarity.
LTDC Shadow Reload Configuration Register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Background Color Configuration Register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
LTDC Interrupt Enable Register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
LTDC Interrupt Status Register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
LTDC Interrupt Clear Register
Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only
0/4 fields covered.
LTDC Line Interrupt Position Configuration Register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LIPOS
rw |
LTDC Current Position Status Register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
LTDC Current Display Status Register
Offset: 0x48, size: 32, reset: 0x0000000F, access: read-only
4/4 fields covered.
LTDC Layer Control Register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
LTDC Layer Window Horizontal Position Configuration Register
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Layer Window Vertical Position Configuration Register
Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Layer Color Keying Configuration Register
Offset: 0x90, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
LTDC Layer Pixel Format Configuration Register
Offset: 0x94, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PF
rw |
LTDC Layer Constant Alpha Configuration Register
Offset: 0x98, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CONSTA
rw |
LTDC Layer Default Color Configuration Register
Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
LTDC Layer Blending Factors Configuration Register
Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Layer Color Frame Buffer Address Register
Offset: 0xac, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
LTDC Layer Color Frame Buffer Length Register
Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Layer ColorFrame Buffer Line Number Register
Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CFBLNBR
rw |
LTDC Layerx CLUT Write Register
Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only
0/4 fields covered.
LTDC Layer Control Register
Offset: 0x104, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
LTDC Layerx Window Horizontal Position Configuration Register
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Layer Window Vertical Position Configuration Register
Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Layer Color Keying Configuration Register
Offset: 0x110, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
LTDC Layer Pixel Format Configuration Register
Offset: 0x114, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PF
rw |
LTDC Layer Constant Alpha Configuration Register
Offset: 0x118, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CONSTA
rw |
LTDC Layer Default Color Configuration Register
Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
LTDC Layer Blending Factors Configuration Register
Offset: 0x124, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Layer Color Frame Buffer Address Register
Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
LTDC Layer Color Frame Buffer Length Register
Offset: 0x130, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
LTDC Layer ColorFrame Buffer Line Number Register
Offset: 0x134, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CFBLNBR
rw |
0xe000ed90: Memory protection unit
3/19 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | TYPER | ||||||||||||||||||||||||||||||||
0x4 | CTRL | ||||||||||||||||||||||||||||||||
0x8 | RNR | ||||||||||||||||||||||||||||||||
0xc | RBAR | ||||||||||||||||||||||||||||||||
0x10 | RASR |
MPU type register
Offset: 0x0, size: 32, reset: 0x00000800, access: read-only
3/3 fields covered.
MPU control register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRIVDEFENA
rw |
HFNMIENA
rw |
ENABLE
rw |
MPU region number register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REGION
rw |
MPU region base address register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
MPU region attribute and size register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
XN
rw |
AP
rw |
TEX
rw |
S
rw |
C
rw |
B
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRD
rw |
SIZE
rw |
ENABLE
rw |
Bit 0: Region enable bit..
Bits 1-5: Size of the MPU protection region.
Bits 8-15: Subregion disable bits.
Bit 16: memory attribute.
Bit 17: memory attribute.
Bit 18: Shareable memory attribute.
Bits 19-21: memory attribute.
Bits 24-26: Access permission.
Bit 28: Instruction access disable bit.
0xe000e100: Nested Vectored Interrupt Controller
3/99 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ISER0 | ||||||||||||||||||||||||||||||||
0x4 | ISER1 | ||||||||||||||||||||||||||||||||
0x8 | ISER2 | ||||||||||||||||||||||||||||||||
0x80 | ICER0 | ||||||||||||||||||||||||||||||||
0x84 | ICER1 | ||||||||||||||||||||||||||||||||
0x88 | ICER2 | ||||||||||||||||||||||||||||||||
0x100 | ISPR0 | ||||||||||||||||||||||||||||||||
0x104 | ISPR1 | ||||||||||||||||||||||||||||||||
0x108 | ISPR2 | ||||||||||||||||||||||||||||||||
0x180 | ICPR0 | ||||||||||||||||||||||||||||||||
0x184 | ICPR1 | ||||||||||||||||||||||||||||||||
0x188 | ICPR2 | ||||||||||||||||||||||||||||||||
0x200 | IABR0 | ||||||||||||||||||||||||||||||||
0x204 | IABR1 | ||||||||||||||||||||||||||||||||
0x208 | IABR2 | ||||||||||||||||||||||||||||||||
0x300 | IPR0 | ||||||||||||||||||||||||||||||||
0x304 | IPR1 | ||||||||||||||||||||||||||||||||
0x308 | IPR2 | ||||||||||||||||||||||||||||||||
0x30c | IPR3 | ||||||||||||||||||||||||||||||||
0x310 | IPR4 | ||||||||||||||||||||||||||||||||
0x314 | IPR5 | ||||||||||||||||||||||||||||||||
0x318 | IPR6 | ||||||||||||||||||||||||||||||||
0x31c | IPR7 | ||||||||||||||||||||||||||||||||
0x320 | IPR8 | ||||||||||||||||||||||||||||||||
0x324 | IPR9 | ||||||||||||||||||||||||||||||||
0x328 | IPR10 | ||||||||||||||||||||||||||||||||
0x32c | IPR11 | ||||||||||||||||||||||||||||||||
0x330 | IPR12 | ||||||||||||||||||||||||||||||||
0x334 | IPR13 | ||||||||||||||||||||||||||||||||
0x338 | IPR14 | ||||||||||||||||||||||||||||||||
0x33c | IPR15 | ||||||||||||||||||||||||||||||||
0x340 | IPR16 | ||||||||||||||||||||||||||||||||
0x344 | IPR17 | ||||||||||||||||||||||||||||||||
0x348 | IPR18 | ||||||||||||||||||||||||||||||||
0x34c | IPR19 | ||||||||||||||||||||||||||||||||
0x350 | IPR20 |
Interrupt Set-Enable Register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Enable Register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Enable Register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Enable Register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Enable Register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Enable Register
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Pending Register
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Pending Register
Offset: 0x104, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Set-Pending Register
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Pending Register
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Pending Register
Offset: 0x184, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Clear-Pending Register
Offset: 0x188, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Interrupt Active Bit Register
Offset: 0x200, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
Interrupt Active Bit Register
Offset: 0x204, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
Interrupt Active Bit Register
Offset: 0x208, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
Interrupt Priority Register
Offset: 0x300, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x304, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x308, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x310, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x314, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x318, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x320, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x324, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x328, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x330, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x334, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x338, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x340, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x344, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x348, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
Interrupt Priority Register
Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
0xe000ef00: Nested vectored interrupt controller
0/1 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | STIR |
Software trigger interrupt register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INTID
rw |
0xa0001000: OctoSPI
9/88 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x8 | DCR1 | ||||||||||||||||||||||||||||||||
0xc | DCR2 | ||||||||||||||||||||||||||||||||
0x10 | DCR3 | ||||||||||||||||||||||||||||||||
0x20 | SR | ||||||||||||||||||||||||||||||||
0x24 | FCR | ||||||||||||||||||||||||||||||||
0x40 | DLR | ||||||||||||||||||||||||||||||||
0x48 | AR | ||||||||||||||||||||||||||||||||
0x50 | DR | ||||||||||||||||||||||||||||||||
0x80 | PSMKR | ||||||||||||||||||||||||||||||||
0x88 | PSMAR | ||||||||||||||||||||||||||||||||
0x90 | PIR | ||||||||||||||||||||||||||||||||
0x100 | CCR | ||||||||||||||||||||||||||||||||
0x108 | TCR | ||||||||||||||||||||||||||||||||
0x110 | IR | ||||||||||||||||||||||||||||||||
0x120 | ABR | ||||||||||||||||||||||||||||||||
0x130 | LPTR | ||||||||||||||||||||||||||||||||
0x180 | WCCR | ||||||||||||||||||||||||||||||||
0x188 | WTCR | ||||||||||||||||||||||||||||||||
0x190 | WIR | ||||||||||||||||||||||||||||||||
0x1a0 | WABR | ||||||||||||||||||||||||||||||||
0x200 | HLCR | ||||||||||||||||||||||||||||||||
0x3f0 | HWCFGR | ||||||||||||||||||||||||||||||||
0x3f4 | VER | ||||||||||||||||||||||||||||||||
0x3f8 | ID | ||||||||||||||||||||||||||||||||
0x3fc | MID |
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FMODE
rw |
PMM
rw |
APMS
rw |
TOIE
rw |
SMIE
rw |
FTIE
rw |
TCIE
rw |
TEIE
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FTHRES
rw |
FSEL
rw |
DQM
rw |
TCEN
rw |
DMAEN
rw |
ABORT
rw |
EN
rw |
Bit 0: Enable.
Bit 1: Abort request.
Bit 2: DMA enable.
Bit 3: Timeout counter enable.
Bit 6: Dual-quad mode.
Bit 7: FLASH memory selection.
Bits 8-12: IFO threshold level.
Bit 16: Transfer error interrupt enable.
Bit 17: Transfer complete interrupt enable.
Bit 18: FIFO threshold interrupt enable.
Bit 19: Status match interrupt enable.
Bit 20: TimeOut interrupt enable.
Bit 22: Automatic poll mode stop.
Bit 23: Polling match mode.
Bits 28-29: Functional mode.
device configuration register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
device configuration register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
device configuration register 3
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CSBOUND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
status register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
flag clear register
Offset: 0x24, size: 32, reset: 0x00000000, access: write-only
0/4 fields covered.
data length register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
address register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
data register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
polling status mask register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
polling status match register
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
polling interval register
Offset: 0x90, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INTERVAL
rw |
communication configuration register
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SIOO
rw |
DQSE
rw |
DDTR
rw |
DMODE
rw |
ABSIZE
rw |
ABDTR
rw |
ABMODE
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADSIZE
rw |
ADDTR
rw |
ADMODE
rw |
ISIZE
rw |
IDTR
rw |
IMODE
rw |
Bits 0-2: Instruction mode.
Bit 3: Instruction double transfer rate.
Bits 4-5: Instruction size.
Bits 8-10: Address mode.
Bit 11: Address double transfer rate.
Bits 12-13: Address size.
Bits 16-18: Alternate byte mode.
Bit 19: Alternate bytes double transfer rate.
Bits 20-21: Alternate bytes size.
Bits 24-26: Data mode.
Bit 27: Alternate bytes double transfer rate.
Bit 29: DQS enable.
Bit 31: Send instruction only once mode.
timing configuration register
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
instruction register
Offset: 0x110, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INSTRUCTION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INSTRUCTION
rw |
alternate bytes register
Offset: 0x120, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
low-power timeout register
Offset: 0x130, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TIMEOUT
rw |
write communication configuration register
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SIOO
rw |
DQSE
rw |
DDTR
rw |
DMODE
rw |
ABSIZE
rw |
ABDTR
rw |
ABMODE
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADSIZE
rw |
ADDTR
rw |
ADMODE
rw |
ISIZE
rw |
IDTR
rw |
IMODE
rw |
Bits 0-2: Instruction mode.
Bit 3: Instruction double transfer rate.
Bits 4-5: Instruction size.
Bits 8-10: Address mode.
Bit 11: Address double transfer rate.
Bits 12-13: Address size.
Bits 16-18: Alternate byte mode.
Bit 19: Alternate bytes double transfer rate.
Bits 20-21: Alternate bytes size.
Bits 24-26: Data mode.
Bit 27: alternate bytes double transfer rate.
Bit 29: DQS enable.
Bit 31: Send instruction only once mode.
write timing configuration register
Offset: 0x188, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DCYC
rw |
write instruction register
Offset: 0x190, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INSTRUCTION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INSTRUCTION
rw |
write alternate bytes register
Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
HyperBusTM latency configuration register
Offset: 0x200, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
HW configuration register
Offset: 0x3f0, size: 32, reset: 0x11300080, access: read-only
6/6 fields covered.
version register
Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VER
r |
0xa0001400: OctoSPI
9/88 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x8 | DCR1 | ||||||||||||||||||||||||||||||||
0xc | DCR2 | ||||||||||||||||||||||||||||||||
0x10 | DCR3 | ||||||||||||||||||||||||||||||||
0x20 | SR | ||||||||||||||||||||||||||||||||
0x24 | FCR | ||||||||||||||||||||||||||||||||
0x40 | DLR | ||||||||||||||||||||||||||||||||
0x48 | AR | ||||||||||||||||||||||||||||||||
0x50 | DR | ||||||||||||||||||||||||||||||||
0x80 | PSMKR | ||||||||||||||||||||||||||||||||
0x88 | PSMAR | ||||||||||||||||||||||||||||||||
0x90 | PIR | ||||||||||||||||||||||||||||||||
0x100 | CCR | ||||||||||||||||||||||||||||||||
0x108 | TCR | ||||||||||||||||||||||||||||||||
0x110 | IR | ||||||||||||||||||||||||||||||||
0x120 | ABR | ||||||||||||||||||||||||||||||||
0x130 | LPTR | ||||||||||||||||||||||||||||||||
0x180 | WCCR | ||||||||||||||||||||||||||||||||
0x188 | WTCR | ||||||||||||||||||||||||||||||||
0x190 | WIR | ||||||||||||||||||||||||||||||||
0x1a0 | WABR | ||||||||||||||||||||||||||||||||
0x200 | HLCR | ||||||||||||||||||||||||||||||||
0x3f0 | HWCFGR | ||||||||||||||||||||||||||||||||
0x3f4 | VER | ||||||||||||||||||||||||||||||||
0x3f8 | ID | ||||||||||||||||||||||||||||||||
0x3fc | MID |
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FMODE
rw |
PMM
rw |
APMS
rw |
TOIE
rw |
SMIE
rw |
FTIE
rw |
TCIE
rw |
TEIE
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FTHRES
rw |
FSEL
rw |
DQM
rw |
TCEN
rw |
DMAEN
rw |
ABORT
rw |
EN
rw |
Bit 0: Enable.
Bit 1: Abort request.
Bit 2: DMA enable.
Bit 3: Timeout counter enable.
Bit 6: Dual-quad mode.
Bit 7: FLASH memory selection.
Bits 8-12: IFO threshold level.
Bit 16: Transfer error interrupt enable.
Bit 17: Transfer complete interrupt enable.
Bit 18: FIFO threshold interrupt enable.
Bit 19: Status match interrupt enable.
Bit 20: TimeOut interrupt enable.
Bit 22: Automatic poll mode stop.
Bit 23: Polling match mode.
Bits 28-29: Functional mode.
device configuration register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
device configuration register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
device configuration register 3
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CSBOUND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
status register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
flag clear register
Offset: 0x24, size: 32, reset: 0x00000000, access: write-only
0/4 fields covered.
data length register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
address register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
data register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
polling status mask register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
polling status match register
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
polling interval register
Offset: 0x90, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INTERVAL
rw |
communication configuration register
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SIOO
rw |
DQSE
rw |
DDTR
rw |
DMODE
rw |
ABSIZE
rw |
ABDTR
rw |
ABMODE
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADSIZE
rw |
ADDTR
rw |
ADMODE
rw |
ISIZE
rw |
IDTR
rw |
IMODE
rw |
Bits 0-2: Instruction mode.
Bit 3: Instruction double transfer rate.
Bits 4-5: Instruction size.
Bits 8-10: Address mode.
Bit 11: Address double transfer rate.
Bits 12-13: Address size.
Bits 16-18: Alternate byte mode.
Bit 19: Alternate bytes double transfer rate.
Bits 20-21: Alternate bytes size.
Bits 24-26: Data mode.
Bit 27: Alternate bytes double transfer rate.
Bit 29: DQS enable.
Bit 31: Send instruction only once mode.
timing configuration register
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
instruction register
Offset: 0x110, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INSTRUCTION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INSTRUCTION
rw |
alternate bytes register
Offset: 0x120, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
low-power timeout register
Offset: 0x130, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TIMEOUT
rw |
write communication configuration register
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SIOO
rw |
DQSE
rw |
DDTR
rw |
DMODE
rw |
ABSIZE
rw |
ABDTR
rw |
ABMODE
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADSIZE
rw |
ADDTR
rw |
ADMODE
rw |
ISIZE
rw |
IDTR
rw |
IMODE
rw |
Bits 0-2: Instruction mode.
Bit 3: Instruction double transfer rate.
Bits 4-5: Instruction size.
Bits 8-10: Address mode.
Bit 11: Address double transfer rate.
Bits 12-13: Address size.
Bits 16-18: Alternate byte mode.
Bit 19: Alternate bytes double transfer rate.
Bits 20-21: Alternate bytes size.
Bits 24-26: Data mode.
Bit 27: alternate bytes double transfer rate.
Bit 29: DQS enable.
Bit 31: Send instruction only once mode.
write timing configuration register
Offset: 0x188, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DCYC
rw |
write instruction register
Offset: 0x190, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INSTRUCTION
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INSTRUCTION
rw |
write alternate bytes register
Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
HyperBusTM latency configuration register
Offset: 0x200, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
HW configuration register
Offset: 0x3f0, size: 32, reset: 0x11300080, access: read-only
6/6 fields covered.
version register
Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VER
r |
0x50061c00: OctoSPI IO Manager
0/20 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x4 | P1CR | ||||||||||||||||||||||||||||||||
0x8 | P2CR |
OctoSPI IO Manager Port 1 Configuration Register
Offset: 0x4, size: 32, reset: 0x03010111, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IOHSRC
rw |
IOHEN
rw |
IOLSRC
rw |
IOLEN
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCSSRC
rw |
NCSEN
rw |
DQSSRC
rw |
DQSEN
rw |
CLKSRC
rw |
CLKEN
rw |
Bit 0: CLK/CLK Enable for Port.
Bit 1: CLK/CLK Source for Port.
Bit 4: DQS Enable for Port.
Bit 5: DQS Source for Port.
Bit 8: CS Enable for Port.
Bit 9: CS Source for Port.
Bit 16: Enable for Port.
Bits 17-18: Source for Port.
Bit 24: Enable for Port n.
Bits 25-26: Source for Port.
OctoSPI IO Manager Port 2 Configuration Register
Offset: 0x8, size: 32, reset: 0x07050333, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IOHSRC
rw |
IOHEN
rw |
IOLSRC
rw |
IOLEN
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NCSSRC
rw |
NCSEN
rw |
DQSSRC
rw |
DQSEN
rw |
CLKSRC
rw |
CLKEN
rw |
Bit 0: CLK/CLK Enable for Port.
Bit 1: CLK/CLK Source for Port.
Bit 4: DQS Enable for Port.
Bit 5: DQS Source for Port.
Bit 8: CS Enable for Port.
Bit 9: CS Source for Port.
Bit 16: Enable for Port.
Bits 17-18: Source for Port.
Bit 24: Enable for Port n.
Bits 25-26: Source for Port.
0x40007800: Operational amplifiers
0/29 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | OPAMP1_CSR | ||||||||||||||||||||||||||||||||
0x4 | OPAMP1_OTR | ||||||||||||||||||||||||||||||||
0x8 | OPAMP1_LPOTR | ||||||||||||||||||||||||||||||||
0x10 | OPAMP2_CSR | ||||||||||||||||||||||||||||||||
0x14 | OPAMP2_OTR | ||||||||||||||||||||||||||||||||
0x18 | OPAMP2_LPOTR |
OPAMP1 control/status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OPA_RANGE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CALOUT
rw |
USERTRIM
rw |
CALSEL
rw |
CALON
rw |
VP_SEL
rw |
VM_SEL
rw |
PGA_GAIN
rw |
OPAMODE
rw |
OPALPM
rw |
OPAEN
rw |
Bit 0: Operational amplifier Enable.
Bit 1: Operational amplifier Low Power Mode.
Bits 2-3: Operational amplifier PGA mode.
Bits 4-5: Operational amplifier Programmable amplifier gain value.
Bits 8-9: Inverting input selection.
Bit 10: Non inverted input selection.
Bit 12: Calibration mode enabled.
Bit 13: Calibration selection.
Bit 14: allows to switch from AOP offset trimmed values to AOP offset.
Bit 15: Operational amplifier calibration output.
Bit 31: Operational amplifier power supply range for stability.
OPAMP1 offset trimming register in normal mode
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRIMOFFSETP
rw |
TRIMOFFSETN
rw |
OPAMP1 offset trimming register in low-power mode
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRIMLPOFFSETP
rw |
TRIMLPOFFSETN
rw |
OPAMP2 control/status register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CALOUT
rw |
USERTRIM
rw |
CALSEL
rw |
CALON
rw |
VP_SEL
rw |
VM_SEL
rw |
PGA_GAIN
rw |
OPAMODE
rw |
OPALPM
rw |
OPAEN
rw |
Bit 0: Operational amplifier Enable.
Bit 1: Operational amplifier Low Power Mode.
Bits 2-3: Operational amplifier PGA mode.
Bits 4-5: Operational amplifier Programmable amplifier gain value.
Bits 8-9: Inverting input selection.
Bit 10: Non inverted input selection.
Bit 12: Calibration mode enabled.
Bit 13: Calibration selection.
Bit 14: allows to switch from AOP offset trimmed values to AOP offset.
Bit 15: Operational amplifier calibration output.
OPAMP2 offset trimming register in normal mode
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRIMOFFSETP
rw |
TRIMOFFSETN
rw |
OPAMP2 offset trimming register in low-power mode
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRIMLPOFFSETP
rw |
TRIMLPOFFSETN
rw |
0x50000800: USB on the go full speed
49/292 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | DCFG | ||||||||||||||||||||||||||||||||
0x4 | DCTL | ||||||||||||||||||||||||||||||||
0x8 | DSTS | ||||||||||||||||||||||||||||||||
0x10 | DIEPMSK | ||||||||||||||||||||||||||||||||
0x14 | DOEPMSK | ||||||||||||||||||||||||||||||||
0x18 | DAINT | ||||||||||||||||||||||||||||||||
0x1c | DAINTMSK | ||||||||||||||||||||||||||||||||
0x28 | DVBUSDIS | ||||||||||||||||||||||||||||||||
0x2c | DVBUSPULSE | ||||||||||||||||||||||||||||||||
0x34 | DIEPEMPMSK | ||||||||||||||||||||||||||||||||
0x100 | CTL [0] | ||||||||||||||||||||||||||||||||
0x108 | INT [0] | ||||||||||||||||||||||||||||||||
0x110 | TSIZ [0] | ||||||||||||||||||||||||||||||||
0x118 | TXFSTS [0] | ||||||||||||||||||||||||||||||||
0x120 | CTL [1] | ||||||||||||||||||||||||||||||||
0x128 | INT [1] | ||||||||||||||||||||||||||||||||
0x130 | TSIZ [1] | ||||||||||||||||||||||||||||||||
0x138 | TXFSTS [1] | ||||||||||||||||||||||||||||||||
0x140 | CTL [2] | ||||||||||||||||||||||||||||||||
0x148 | INT [2] | ||||||||||||||||||||||||||||||||
0x150 | TSIZ [2] | ||||||||||||||||||||||||||||||||
0x158 | TXFSTS [2] | ||||||||||||||||||||||||||||||||
0x160 | CTL [3] | ||||||||||||||||||||||||||||||||
0x168 | INT [3] | ||||||||||||||||||||||||||||||||
0x170 | TSIZ [3] | ||||||||||||||||||||||||||||||||
0x178 | TXFSTS [3] | ||||||||||||||||||||||||||||||||
0x180 | CTL [4] | ||||||||||||||||||||||||||||||||
0x188 | INT [4] | ||||||||||||||||||||||||||||||||
0x190 | TSIZ [4] | ||||||||||||||||||||||||||||||||
0x198 | TXFSTS [4] | ||||||||||||||||||||||||||||||||
0x1a0 | CTL [5] | ||||||||||||||||||||||||||||||||
0x1a8 | INT [5] | ||||||||||||||||||||||||||||||||
0x1b0 | TSIZ [5] | ||||||||||||||||||||||||||||||||
0x1b8 | TXFSTS [5] | ||||||||||||||||||||||||||||||||
0x300 | CTL [0] | ||||||||||||||||||||||||||||||||
0x308 | INT [0] | ||||||||||||||||||||||||||||||||
0x310 | TSIZ [0] | ||||||||||||||||||||||||||||||||
0x320 | CTL [1] | ||||||||||||||||||||||||||||||||
0x328 | INT [1] | ||||||||||||||||||||||||||||||||
0x330 | TSIZ [1] | ||||||||||||||||||||||||||||||||
0x340 | CTL [2] | ||||||||||||||||||||||||||||||||
0x348 | INT [2] | ||||||||||||||||||||||||||||||||
0x350 | TSIZ [2] | ||||||||||||||||||||||||||||||||
0x360 | CTL [3] | ||||||||||||||||||||||||||||||||
0x368 | INT [3] | ||||||||||||||||||||||||||||||||
0x370 | TSIZ [3] | ||||||||||||||||||||||||||||||||
0x380 | CTL [4] | ||||||||||||||||||||||||||||||||
0x388 | INT [4] | ||||||||||||||||||||||||||||||||
0x390 | TSIZ [4] | ||||||||||||||||||||||||||||||||
0x3a0 | CTL [5] | ||||||||||||||||||||||||||||||||
0x3a8 | INT [5] | ||||||||||||||||||||||||||||||||
0x3b0 | TSIZ [5] |
OTG_FS device configuration register (OTG_FS_DCFG)
Offset: 0x0, size: 32, reset: 0x02200000, access: read-write
0/4 fields covered.
OTG_FS device control register (OTG_FS_DCTL)
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
2/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
POPRGDNE
rw |
CGONAK
rw |
SGONAK
rw |
CGINAK
rw |
SGINAK
rw |
TCTL
rw |
GONSTS
r |
GINSTS
r |
SDIS
rw |
RWUSIG
rw |
Bit 0: Remote wakeup signaling.
Bit 1: Soft disconnect.
Bit 2: Global IN NAK status.
Bit 3: Global OUT NAK status.
Bits 4-6: Test control.
Bit 7: Set global IN NAK.
Bit 8: Clear global IN NAK.
Bit 9: Set global OUT NAK.
Bit 10: Clear global OUT NAK.
Bit 11: Power-on programming done.
OTG_FS device status register (OTG_FS_DSTS)
Offset: 0x8, size: 32, reset: 0x00000010, access: read-only
4/4 fields covered.
OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
Bit 0: Transfer completed interrupt mask.
Bit 1: Endpoint disabled interrupt mask.
Bit 3: Timeout condition mask (Non-isochronous endpoints).
Bit 4: IN token received when TxFIFO empty mask.
Bit 5: IN token received with EP mismatch mask.
Bit 6: IN endpoint NAK effective mask.
OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
Offset: 0x18, size: 32, reset: 0x00000000, access: read-only
2/2 fields covered.
OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
OTG_FS device VBUS discharge time register
Offset: 0x28, size: 32, reset: 0x000017D7, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VBUSDT
rw |
OTG_FS device VBUS pulsing time register
Offset: 0x2c, size: 32, reset: 0x000005B8, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DVBUSP
rw |
OTG_FS device IN endpoint FIFO empty interrupt mask register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INEPTXFEM
rw |
OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified
4/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
r |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
r |
NAKSTS
r |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
r |
MPSIZ
rw |
Bits 0-1: Maximum packet size.
Bit 15: USB active endpoint.
Bit 17: NAK status.
Bits 18-19: Endpoint type.
Bit 21: STALL handshake.
Bits 22-25: TxFIFO number.
Bit 26: Clear NAK.
Bit 27: Set NAK.
Bit 30: Endpoint disable.
Bit 31: Endpoint enable.
device endpoint-x interrupt register
Offset: 0x108, size: 32, reset: 0x00000080, access: Unspecified
1/6 fields covered.
device endpoint-0 transfer size register
Offset: 0x110, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x118, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INEPTFSAV
r |
OTG device endpoint-1 control register
Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM_SD1PID
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 21: STALL handshake.
Bits 22-25: TXFNUM.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM/SD1PID.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x128, size: 32, reset: 0x00000080, access: Unspecified
1/6 fields covered.
device endpoint-1 transfer size register
Offset: 0x130, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x138, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INEPTFSAV
r |
OTG device endpoint-1 control register
Offset: 0x140, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM_SD1PID
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 21: STALL handshake.
Bits 22-25: TXFNUM.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM/SD1PID.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x148, size: 32, reset: 0x00000080, access: Unspecified
1/6 fields covered.
device endpoint-1 transfer size register
Offset: 0x150, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x158, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INEPTFSAV
r |
OTG device endpoint-1 control register
Offset: 0x160, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM_SD1PID
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 21: STALL handshake.
Bits 22-25: TXFNUM.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM/SD1PID.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x168, size: 32, reset: 0x00000080, access: Unspecified
1/6 fields covered.
device endpoint-1 transfer size register
Offset: 0x170, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x178, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INEPTFSAV
r |
OTG device endpoint-1 control register
Offset: 0x180, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM_SD1PID
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 21: STALL handshake.
Bits 22-25: TXFNUM.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM/SD1PID.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x188, size: 32, reset: 0x00000080, access: Unspecified
1/6 fields covered.
device endpoint-1 transfer size register
Offset: 0x190, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x198, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INEPTFSAV
r |
OTG device endpoint-1 control register
Offset: 0x1a0, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM_SD1PID
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 21: STALL handshake.
Bits 22-25: TXFNUM.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM/SD1PID.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x1a8, size: 32, reset: 0x00000080, access: Unspecified
1/6 fields covered.
device endpoint-1 transfer size register
Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS device IN endpoint transmit FIFO status register
Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INEPTFSAV
r |
device endpoint-0 control register
Offset: 0x300, size: 32, reset: 0x00008000, access: Unspecified
5/10 fields covered.
device endpoint-0 interrupt register
Offset: 0x308, size: 32, reset: 0x00000080, access: read-write
0/5 fields covered.
device OUT endpoint-0 transfer size register
Offset: 0x310, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
device endpoint-1 control register
Offset: 0x320, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNPM
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 20: SNPM.
Bit 21: STALL handshake.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x328, size: 32, reset: 0x00000080, access: read-write
0/5 fields covered.
device OUT endpoint-1 transfer size register
Offset: 0x330, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XFRSIZ
rw |
device endpoint-1 control register
Offset: 0x340, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNPM
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 20: SNPM.
Bit 21: STALL handshake.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x348, size: 32, reset: 0x00000080, access: read-write
0/5 fields covered.
device OUT endpoint-1 transfer size register
Offset: 0x350, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XFRSIZ
rw |
device endpoint-1 control register
Offset: 0x360, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNPM
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 20: SNPM.
Bit 21: STALL handshake.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x368, size: 32, reset: 0x00000080, access: read-write
0/5 fields covered.
device OUT endpoint-1 transfer size register
Offset: 0x370, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XFRSIZ
rw |
device endpoint-1 control register
Offset: 0x380, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNPM
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 20: SNPM.
Bit 21: STALL handshake.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x388, size: 32, reset: 0x00000080, access: read-write
0/5 fields covered.
device OUT endpoint-1 transfer size register
Offset: 0x390, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XFRSIZ
rw |
device endpoint-1 control register
Offset: 0x3a0, size: 32, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPENA
rw |
EPDIS
rw |
SODDFRM
w |
SD0PID_SEVNFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNPM
rw |
EPTYP
rw |
NAKSTS
r |
EONUM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USBAEP
rw |
MPSIZ
rw |
Bits 0-10: MPSIZ.
Bit 15: USBAEP.
Bit 16: EONUM/DPID.
Bit 17: NAKSTS.
Bits 18-19: EPTYP.
Bit 20: SNPM.
Bit 21: STALL handshake.
Bit 26: CNAK.
Bit 27: SNAK.
Bit 28: SD0PID/SEVNFRM.
Bit 29: SODDFRM.
Bit 30: EPDIS.
Bit 31: EPENA.
device endpoint-1 interrupt register
Offset: 0x3a8, size: 32, reset: 0x00000080, access: read-write
0/5 fields covered.
device OUT endpoint-1 transfer size register
Offset: 0x3b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXDPID_STUPCNT
rw |
PKTCNT
rw |
XFRSIZ
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XFRSIZ
rw |
0x50000000: USB on the go full speed
39/127 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | GOTGCTL | ||||||||||||||||||||||||||||||||
0x4 | GOTGINT | ||||||||||||||||||||||||||||||||
0x8 | GAHBCFG | ||||||||||||||||||||||||||||||||
0xc | GUSBCFG | ||||||||||||||||||||||||||||||||
0x10 | GRSTCTL | ||||||||||||||||||||||||||||||||
0x14 | GINTSTS | ||||||||||||||||||||||||||||||||
0x18 | GINTMSK | ||||||||||||||||||||||||||||||||
0x1c | GRXSTSR_Device | ||||||||||||||||||||||||||||||||
0x1c | GRXSTSR_Host | ||||||||||||||||||||||||||||||||
0x20 | GRXSTSP_Device | ||||||||||||||||||||||||||||||||
0x20 | GRXSTSP_Host | ||||||||||||||||||||||||||||||||
0x24 | GRXFSIZ | ||||||||||||||||||||||||||||||||
0x28 | DIEPTXF0 | ||||||||||||||||||||||||||||||||
0x28 | HNPTXFSIZ | ||||||||||||||||||||||||||||||||
0x2c | GNPTXSTS | ||||||||||||||||||||||||||||||||
0x38 | GCCFG | ||||||||||||||||||||||||||||||||
0x3c | CID | ||||||||||||||||||||||||||||||||
0x100 | HPTXFSIZ | ||||||||||||||||||||||||||||||||
0x104 | DIEPTXF[1] | ||||||||||||||||||||||||||||||||
0x108 | DIEPTXF[2] | ||||||||||||||||||||||||||||||||
0x10c | DIEPTXF[3] | ||||||||||||||||||||||||||||||||
0x110 | DIEPTXF[4] | ||||||||||||||||||||||||||||||||
0x114 | DIEPTXF[5] |
OTG_FS control and status register (OTG_FS_GOTGCTL)
Offset: 0x0, size: 32, reset: 0x00000800, access: Unspecified
6/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BSVLD
r |
ASVLD
r |
DBCT
r |
CIDSTS
r |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DHNPEN
rw |
HSHNPEN
rw |
HNPRQ
rw |
HNGSCS
r |
SRQ
rw |
SRQSCS
r |
Bit 0: Session request success.
Bit 1: Session request.
Bit 8: Host negotiation success.
Bit 9: HNP request.
Bit 10: Host set HNP enable.
Bit 11: Device HNP enabled.
Bit 16: Connector ID status.
Bit 17: Long/short debounce time.
Bit 18: A-session valid.
Bit 19: B-session valid.
OTG_FS interrupt register (OTG_FS_GOTGINT)
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS USB configuration register (OTG_FS_GUSBCFG)
Offset: 0xc, size: 32, reset: 0x00000A00, access: Unspecified
0/8 fields covered.
OTG_FS reset register (OTG_FS_GRSTCTL)
Offset: 0x10, size: 32, reset: 0x20000000, access: Unspecified
1/7 fields covered.
OTG_FS core interrupt register (OTG_FS_GINTSTS)
Offset: 0x14, size: 32, reset: 0x04000020, access: Unspecified
11/25 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WKUPINT
rw |
SRQINT
rw |
DISCINT
rw |
CIDSCHG
rw |
PTXFE
r |
HCINT
r |
HPRTINT
r |
IPXFR_INCOMPISOOUT
rw |
IISOIXFR
rw |
OEPINT
r |
IEPINT
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOPF
rw |
ISOODRP
rw |
ENUMDNE
rw |
USBRST
rw |
USBSUSP
rw |
ESUSP
rw |
GOUTNAKEFF
r |
GINAKEFF
r |
NPTXFE
r |
RXFLVL
r |
SOF
rw |
OTGINT
r |
MMIS
rw |
CMOD
r |
Bit 0: Current mode of operation.
Bit 1: Mode mismatch interrupt.
Bit 2: OTG interrupt.
Bit 3: Start of frame.
Bit 4: RxFIFO non-empty.
Bit 5: Non-periodic TxFIFO empty.
Bit 6: Global IN non-periodic NAK effective.
Bit 7: Global OUT NAK effective.
Bit 10: Early suspend.
Bit 11: USB suspend.
Bit 12: USB reset.
Bit 13: Enumeration done.
Bit 14: Isochronous OUT packet dropped interrupt.
Bit 15: End of periodic frame interrupt.
Bit 18: IN endpoint interrupt.
Bit 19: OUT endpoint interrupt.
Bit 20: Incomplete isochronous IN transfer.
Bit 21: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode).
Bit 24: Host port interrupt.
Bit 25: Host channels interrupt.
Bit 26: Periodic TxFIFO empty.
Bit 28: Connector ID status change.
Bit 29: Disconnect detected interrupt.
Bit 30: Session request/new session detected interrupt.
Bit 31: Resume/remote wakeup detected interrupt.
OTG_FS interrupt mask register (OTG_FS_GINTMSK)
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
0/25 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUIM
rw |
SRQIM
rw |
DISCINT
rw |
CIDSCHGM
rw |
PTXFEM
rw |
HCIM
rw |
PRTIM
rw |
IPXFRM_IISOOXFRM
rw |
IISOIXFRM
rw |
OEPINT
rw |
IEPINT
rw |
EPMISM
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOPFM
rw |
ISOODRPM
rw |
ENUMDNEM
rw |
USBRST
rw |
USBSUSPM
rw |
ESUSPM
rw |
GONAKEFFM
rw |
GINAKEFFM
rw |
NPTXFEM
rw |
RXFLVLM
rw |
SOFM
rw |
OTGINT
rw |
MMISM
rw |
Bit 1: Mode mismatch interrupt mask.
Bit 2: OTG interrupt mask.
Bit 3: Start of frame mask.
Bit 4: Receive FIFO non-empty mask.
Bit 5: Non-periodic TxFIFO empty mask.
Bit 6: Global non-periodic IN NAK effective mask.
Bit 7: Global OUT NAK effective mask.
Bit 10: Early suspend mask.
Bit 11: USB suspend mask.
Bit 12: USB reset mask.
Bit 13: Enumeration done mask.
Bit 14: Isochronous OUT packet dropped interrupt mask.
Bit 15: End of periodic frame interrupt mask.
Bit 17: Endpoint mismatch interrupt mask.
Bit 18: IN endpoints interrupt mask.
Bit 19: OUT endpoints interrupt mask.
Bit 20: Incomplete isochronous IN transfer mask.
Bit 21: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode).
Bit 24: Host port interrupt mask.
Bit 25: Host channels interrupt mask.
Bit 26: Periodic TxFIFO empty mask.
Bit 28: Connector ID status change mask.
Bit 29: Disconnect detected interrupt mask.
Bit 30: Session request/new session detected interrupt mask.
Bit 31: Resume/remote wakeup detected interrupt mask.
OTG_FS Receive status debug read(Device mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only
5/5 fields covered.
OTG status debug read (host mode)
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
OTG status read and pop (device mode)
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
5/5 fields covered.
OTG status read and pop (host mode)
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
4/4 fields covered.
OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
Offset: 0x24, size: 32, reset: 0x00000200, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFD
rw |
OTG_FS non-periodic transmit FIFO size register (Device mode)
Offset: 0x28, size: 32, reset: 0x00000200, access: read-write
0/2 fields covered.
OTG_FS non-periodic transmit FIFO size register (Host mode)
Offset: 0x28, size: 32, reset: 0x00000200, access: read-write
0/2 fields covered.
OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
Offset: 0x2c, size: 32, reset: 0x00080200, access: read-only
3/3 fields covered.
OTG_FS general core configuration register (OTG_FS_GCCFG)
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
core ID register
Offset: 0x3c, size: 32, reset: 0x00001000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRODUCT_ID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRODUCT_ID
rw |
OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
Offset: 0x100, size: 32, reset: 0x02000600, access: read-write
0/2 fields covered.
OTF_FS device IN endpoint transmit FIFO size register
Offset: 0x104, size: 32, reset: 0x02000400, access: read-write
0/2 fields covered.
OTF_FS device IN endpoint transmit FIFO size register
Offset: 0x108, size: 32, reset: 0x02000400, access: read-write
0/2 fields covered.
OTF_FS device IN endpoint transmit FIFO size register
Offset: 0x10c, size: 32, reset: 0x02000400, access: read-write
0/2 fields covered.
OTF_FS device IN endpoint transmit FIFO size register
Offset: 0x110, size: 32, reset: 0x02000400, access: read-write
0/2 fields covered.
0x50000400: USB on the go full speed
9/407 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | HCFG | ||||||||||||||||||||||||||||||||
0x4 | HFIR | ||||||||||||||||||||||||||||||||
0x8 | HFNUM | ||||||||||||||||||||||||||||||||
0x10 | HPTXSTS | ||||||||||||||||||||||||||||||||
0x14 | HAINT | ||||||||||||||||||||||||||||||||
0x18 | HAINTMSK | ||||||||||||||||||||||||||||||||
0x40 | HPRT | ||||||||||||||||||||||||||||||||
0x100 | CHAR [0] | ||||||||||||||||||||||||||||||||
0x108 | INT [0] | ||||||||||||||||||||||||||||||||
0x10c | INTMSK [0] | ||||||||||||||||||||||||||||||||
0x110 | TSIZ [0] | ||||||||||||||||||||||||||||||||
0x120 | CHAR [1] | ||||||||||||||||||||||||||||||||
0x128 | INT [1] | ||||||||||||||||||||||||||||||||
0x12c | INTMSK [1] | ||||||||||||||||||||||||||||||||
0x130 | TSIZ [1] | ||||||||||||||||||||||||||||||||
0x140 | CHAR [2] | ||||||||||||||||||||||||||||||||
0x148 | INT [2] | ||||||||||||||||||||||||||||||||
0x14c | INTMSK [2] | ||||||||||||||||||||||||||||||||
0x150 | TSIZ [2] | ||||||||||||||||||||||||||||||||
0x160 | CHAR [3] | ||||||||||||||||||||||||||||||||
0x168 | INT [3] | ||||||||||||||||||||||||||||||||
0x16c | INTMSK [3] | ||||||||||||||||||||||||||||||||
0x170 | TSIZ [3] | ||||||||||||||||||||||||||||||||
0x180 | CHAR [4] | ||||||||||||||||||||||||||||||||
0x188 | INT [4] | ||||||||||||||||||||||||||||||||
0x18c | INTMSK [4] | ||||||||||||||||||||||||||||||||
0x190 | TSIZ [4] | ||||||||||||||||||||||||||||||||
0x1a0 | CHAR [5] | ||||||||||||||||||||||||||||||||
0x1a8 | INT [5] | ||||||||||||||||||||||||||||||||
0x1ac | INTMSK [5] | ||||||||||||||||||||||||||||||||
0x1b0 | TSIZ [5] | ||||||||||||||||||||||||||||||||
0x1c0 | CHAR [6] | ||||||||||||||||||||||||||||||||
0x1c8 | INT [6] | ||||||||||||||||||||||||||||||||
0x1cc | INTMSK [6] | ||||||||||||||||||||||||||||||||
0x1d0 | TSIZ [6] | ||||||||||||||||||||||||||||||||
0x1e0 | CHAR [7] | ||||||||||||||||||||||||||||||||
0x1e8 | INT [7] | ||||||||||||||||||||||||||||||||
0x1ec | INTMSK [7] | ||||||||||||||||||||||||||||||||
0x1f0 | TSIZ [7] | ||||||||||||||||||||||||||||||||
0x200 | CHAR [8] | ||||||||||||||||||||||||||||||||
0x208 | INT [8] | ||||||||||||||||||||||||||||||||
0x20c | INTMSK [8] | ||||||||||||||||||||||||||||||||
0x210 | TSIZ [8] | ||||||||||||||||||||||||||||||||
0x220 | CHAR [9] | ||||||||||||||||||||||||||||||||
0x228 | INT [9] | ||||||||||||||||||||||||||||||||
0x22c | INTMSK [9] | ||||||||||||||||||||||||||||||||
0x230 | TSIZ [9] | ||||||||||||||||||||||||||||||||
0x240 | CHAR [10] | ||||||||||||||||||||||||||||||||
0x248 | INT [10] | ||||||||||||||||||||||||||||||||
0x24c | INTMSK [10] | ||||||||||||||||||||||||||||||||
0x250 | TSIZ [10] | ||||||||||||||||||||||||||||||||
0x260 | CHAR [11] | ||||||||||||||||||||||||||||||||
0x268 | INT [11] | ||||||||||||||||||||||||||||||||
0x26c | INTMSK [11] | ||||||||||||||||||||||||||||||||
0x270 | TSIZ [11] |
OTG_FS host configuration register (OTG_FS_HCFG)
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
0/2 fields covered.
OTG_FS Host frame interval register
Offset: 0x4, size: 32, reset: 0x0000EA60, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FRIVL
rw |
OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
Offset: 0x8, size: 32, reset: 0x00003FFF, access: read-only
2/2 fields covered.
OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
Offset: 0x10, size: 32, reset: 0x00080100, access: Unspecified
2/3 fields covered.
OTG_FS Host all channels interrupt register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HAINT
r |
OTG_FS host all channels interrupt mask register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HAINTM
rw |
OTG_FS host port control and status register (OTG_FS_HPRT)
Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified
4/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSPD
r |
PTCTL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PTCTL
rw |
PPWR
rw |
PLSTS
r |
PRST
rw |
PSUSP
rw |
PRES
rw |
POCCHNG
rw |
POCA
r |
PENCHNG
rw |
PENA
rw |
PCDET
rw |
PCSTS
r |
Bit 0: Port connect status.
Bit 1: Port connect detected.
Bit 2: Port enable.
Bit 3: Port enable/disable change.
Bit 4: Port overcurrent active.
Bit 5: Port overcurrent change.
Bit 6: Port resume.
Bit 7: Port suspend.
Bit 8: Port reset.
Bits 10-11: Port line status.
Bit 12: Port power.
Bits 13-16: Port test control.
Bits 17-18: Port speed.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x100, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x108, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x110, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x120, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x128, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x130, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x140, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x148, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x150, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x160, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x168, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x170, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x180, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x188, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x190, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x200, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x208, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x210, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x220, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x228, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x230, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x240, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x248, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
OTG_FS host channel-0 transfer size register
Offset: 0x250, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
Offset: 0x260, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CHENA
rw |
CHDIS
rw |
ODDFRM
rw |
DAD
rw |
MCNT
rw |
EPTYP
rw |
LSDEV
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPDIR
rw |
EPNUM
rw |
MPSIZ
rw |
Bits 0-10: Maximum packet size.
Bits 11-14: Endpoint number.
Bit 15: Endpoint direction.
Bit 17: Low-speed device.
Bits 18-19: Endpoint type.
Bits 20-21: Multicount.
Bits 22-28: Device address.
Bit 29: Odd frame.
Bit 30: Channel disable.
Bit 31: Channel enable.
OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
Offset: 0x268, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERR
rw |
FRMOR
rw |
BBERR
rw |
TXERR
rw |
ACK
rw |
NAK
rw |
STALL
rw |
CHH
rw |
XFRC
rw |
Bit 0: Transfer completed.
Bit 1: Channel halted.
Bit 3: STALL response received interrupt.
Bit 4: NAK response received interrupt.
Bit 5: ACK response received/transmitted interrupt.
Bit 7: Transaction error.
Bit 8: Babble error.
Bit 9: Frame overrun.
Bit 10: Data toggle error.
OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DTERRM
rw |
FRMORM
rw |
BBERRM
rw |
TXERRM
rw |
NYET
rw |
ACKM
rw |
NAKM
rw |
STALLM
rw |
CHHM
rw |
XFRCM
rw |
Bit 0: Transfer completed mask.
Bit 1: Channel halted mask.
Bit 3: STALL response received interrupt mask.
Bit 4: NAK response received interrupt mask.
Bit 5: ACK response received/transmitted interrupt mask.
Bit 6: response received interrupt mask.
Bit 7: Transaction error mask.
Bit 8: Babble error mask.
Bit 9: Frame overrun mask.
Bit 10: Data toggle error mask.
0x50000e00: USB on the go full speed
0/3 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | PCGCCTL |
0x40007000: Power control
16/314 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | CR4 | ||||||||||||||||||||||||||||||||
0x10 | SR1 | ||||||||||||||||||||||||||||||||
0x14 | SR2 | ||||||||||||||||||||||||||||||||
0x18 | SCR | ||||||||||||||||||||||||||||||||
0x20 | PUCRA | ||||||||||||||||||||||||||||||||
0x24 | PDCRA | ||||||||||||||||||||||||||||||||
0x28 | PUCRB | ||||||||||||||||||||||||||||||||
0x2c | PDCRB | ||||||||||||||||||||||||||||||||
0x30 | PUCRC | ||||||||||||||||||||||||||||||||
0x34 | PDCRC | ||||||||||||||||||||||||||||||||
0x38 | PUCRD | ||||||||||||||||||||||||||||||||
0x3c | PDCRD | ||||||||||||||||||||||||||||||||
0x44 | PDCRE | ||||||||||||||||||||||||||||||||
0x48 | PUCRF | ||||||||||||||||||||||||||||||||
0x4c | PDCRF | ||||||||||||||||||||||||||||||||
0x50 | PUCRG | ||||||||||||||||||||||||||||||||
0x54 | PDCRG | ||||||||||||||||||||||||||||||||
0x58 | PUCRH | ||||||||||||||||||||||||||||||||
0x5c | PDCRH | ||||||||||||||||||||||||||||||||
0x60 | PUCRI | ||||||||||||||||||||||||||||||||
0x64 | PDCRI | ||||||||||||||||||||||||||||||||
0x80 | CR5 |
Power control register 1
Offset: 0x0, size: 32, reset: 0x00000200, access: Unspecified
0/5 fields covered.
Bits 0-2: Low-power mode selection These bits select the low-power mode entered when CPU enters the Deepsleep mode. 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3..
Bit 4: SRAM3 retention in Stop 2 mode.
Bit 8: Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers..
Bits 9-10: Voltage scaling range selection.
Bit 14: Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead..
Power control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
0/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
USV
rw |
IOSV
rw |
PVME4
rw |
PVME3
rw |
PVME2
rw |
PVME1
rw |
PLS
rw |
PVDE
rw |
Bit 0: Power voltage detector enable Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: This bit is reset only by a system reset..
Bits 1-3: Power voltage detector level selection. These bits select the voltage threshold detected by the power voltage detector: Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: These bits are reset only by a system reset..
Bit 4: Peripheral voltage monitoring 1 enable: V<sub>DDUSB</sub> vs. 1.2V.
Bit 5: Peripheral voltage monitoring 2 enable: V<sub>DDIO2</sub> vs. 0.9V.
Bit 6: Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. 1.62V.
Bit 7: Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. 2.2V.
Bit 9: V<sub>DDIO2</sub> Independent I/Os supply valid This bit is used to validate the V<sub>DDIO2</sub> supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If V<sub>DDIO2</sub> is not always present in the application, the PVM can be used to determine whether this supply is ready or not..
Bit 10: V<sub>DDUSB</sub> USB supply valid This bit is used to validate the V<sub>DDUSB</sub> supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB OTG_FS peripheral. If V<sub>DDUSB</sub> is not always present in the application, the PVM can be used to determine whether this supply is ready or not..
Power control register 3
Offset: 0x8, size: 32, reset: 0x00008000, access: Unspecified
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EIWUL
rw |
DSIPDEN
rw |
ENULP
rw |
APC
rw |
RRS
rw |
EWUP5
rw |
EWUP4
rw |
EWUP3
rw |
EWUP2
rw |
EWUP1
rw |
Bit 0: Enable Wakeup pin WKUP1 When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP1 bit in the PWR_CR4 register..
Bit 1: Enable Wakeup pin WKUP2 When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP2 bit in the PWR_CR4 register..
Bit 2: Enable Wakeup pin WKUP3 When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP3 bit in the PWR_CR4 register..
Bit 3: Enable Wakeup pin WKUP4 When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WP4 bit in the PWR_CR4 register..
Bit 4: Enable Wakeup pin WKUP5 When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs.The active edge is configured via the WP5 bit in the PWR_CR4 register..
Bits 8-9: SRAM2 retention in Standby mode For STM32L4Rxxx and STM32L4Sxxx devices bit 9 is reserved For STM32L4P5xx and STM32L4Q5xx devices:.
Bit 10: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os will be in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during Run mode..
Bit 11: Enable ULP sampling When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes. Note: Available on STM32L4P5xx andSTM32L4Q5xx only..
Bit 12: Enable Pull-down activation on DSI pins.
Bit 15: Enable internal wakeup line.
Power control register 4
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
0/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EXT_SMPS_ON
rw |
VBRS
rw |
VBE
rw |
WP5
rw |
WP4
rw |
WP3
rw |
WP2
rw |
WP1
rw |
Bit 0: Wakeup pin WKUP1 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP1.
Bit 1: Wakeup pin WKUP2 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP2.
Bit 2: Wakeup pin WKUP3 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP3.
Bit 3: Wakeup pin WKUP4 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP4.
Bit 4: Wakeup pin WKUP5 polarity This bit defines the polarity used for an event detection on external wake-up pin, WKUP5.
Bit 8: V<sub>BAT</sub> battery charging enable.
Bit 9: V<sub>BAT</sub> battery charging resistor selection.
Bit 13: external SMPS on. This bit informs the internal regulator about external SMPS switch status to decrease regulator output to 0.95 V in Range 2, allowing the external SMPS output down to 1.00 V. Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices..
Power status register 1
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
8/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUFI
r |
EXT_SMPS_RDY
r |
SBF
r |
WUF5
r |
WUF4
r |
WUF3
r |
WUF2
r |
WUF1
r |
Bit 0: Wakeup flag 1 This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by writing 1 in the CWUF1 bit of the PWR_SCR register..
Bit 1: Wakeup flag 2 This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by writing 1 in the CWUF2 bit of the PWR_SCR register..
Bit 2: Wakeup flag 3 This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by writing 1 in the CWUF3 bit of the PWR_SCR register..
Bit 3: Wakeup flag 4 This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by writing 1 in the CWUF4 bit of the PWR_SCR register..
Bit 4: Wakeup flag 5 This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by writing 1 in the CWUF5 bit of the PWR_SCR register..
Bit 8: Standby flag This bit is set by hardware when the device enters the Standby mode and is cleared by setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the system reset..
Bit 13: External SMPS ready This bit informs the state of regulator transition from Range 1 to Range 2 Note: This bit is only available on STM32L4P5xx and STM32L4Q5xx devices..
Bit 15: Wakeup flag internal This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared..
Power status register 2
Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified
8/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PVMO4
r |
PVMO3
r |
PVMO2
r |
PVMO1
r |
PVDO
r |
VOSF
r |
REGLPF
r |
REGLPS
r |
Bit 8: Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wakeup from Standby mode time may be increased..
Bit 9: Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready..
Bit 10: Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register..
Bit 11: Power voltage detector output.
Bit 12: Peripheral voltage monitoring output: V<sub>DDUSB</sub> vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wakeup time..
Bit 13: Peripheral voltage monitoring output: V<sub>DDIO2</sub> vs. 0.9 V Note: PVMO2 is cleared when PVM2 is disabled (PVME2 = 0). After enabling PVM2, the PVM2 output is valid after the PVM2 wakeup time..
Bit 14: Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.62 V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wakeup time..
Bit 15: Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 2.2 V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wakeup time..
Power status clear register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
0/6 fields covered.
Bit 0: Clear wakeup flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register..
Bit 1: Clear wakeup flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register..
Bit 2: Clear wakeup flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register..
Bit 3: Clear wakeup flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register..
Bit 4: Clear wakeup flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register..
Bit 8: Clear standby flag Setting this bit clears the SBF flag in the PWR_SR1 register..
Power Port A pull-up control register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
0/15 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PU15
rw |
PU13
rw |
PU12
rw |
PU11
rw |
PU10
rw |
PU9
rw |
PU8
rw |
PU7
rw |
PU6
rw |
PU5
rw |
PU4
rw |
PU3
rw |
PU2
rw |
PU1
rw |
PU0
rw |
Bit 0: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 1: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 2: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 3: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 4: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 5: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 6: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 7: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 8: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 9: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 10: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 11: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 12: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 13: Port A pull-up bit y (y=0...13) When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 15: Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. If the corresponding PD15 bit is also set, the pull-up is not activated and the pull-down is activated instead with highest priority..
Power Port A pull-down control register
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
0/14 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD14
rw |
PD12
rw |
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD4
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 4: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 12: Port A pull-down bit y (y=0..12) When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register..
Bit 14: Port A pull-down bit 14 When set, this bit activates the pull-down on PA[14] when APC bit is set in PWR_CR3 register..
Power Port B pull-up control register
Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PU15
rw |
PU14
rw |
PU13
rw |
PU12
rw |
PU11
rw |
PU10
rw |
PU9
rw |
PU8
rw |
PU7
rw |
PU6
rw |
PU5
rw |
PU4
rw |
PU3
rw |
PU2
rw |
PU1
rw |
PU0
rw |
Bit 0: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 1: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 2: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 3: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 4: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 5: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 6: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 7: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 8: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 9: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 10: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 11: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 12: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 13: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 14: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 15: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Power Port B pull-down control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified
0/15 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD15
rw |
PD14
rw |
PD13
rw |
PD12
rw |
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port B pull-down bit y (y=0..3) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 12: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 13: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 14: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Bit 15: Port B pull-down bit y (y=5..15) When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register..
Power Port C pull-up control register
Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PU15
rw |
PU14
rw |
PU13
rw |
PU12
rw |
PU11
rw |
PU10
rw |
PU9
rw |
PU8
rw |
PU7
rw |
PU6
rw |
PU5
rw |
PU4
rw |
PU3
rw |
PU2
rw |
PU1
rw |
PU0
rw |
Bit 0: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 1: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 2: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 3: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 4: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 5: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 6: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 7: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 8: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 9: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 10: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 11: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 12: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 13: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 14: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 15: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Power Port C pull-down control register
Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD15
rw |
PD14
rw |
PD13
rw |
PD12
rw |
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD4
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 4: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 12: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 13: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 14: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Bit 15: Port C pull-down bit y (y=0..15) When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register..
Power Port D pull-up control register
Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PU15
rw |
PU14
rw |
PU13
rw |
PU12
rw |
PU11
rw |
PU10
rw |
PU9
rw |
PU8
rw |
PU7
rw |
PU6
rw |
PU5
rw |
PU4
rw |
PU3
rw |
PU2
rw |
PU1
rw |
PU0
rw |
Bit 0: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 1: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 2: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 3: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 4: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 5: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 6: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 7: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 8: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 9: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 10: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 11: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 12: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 13: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 14: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 15: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Power Port D pull-down control register
Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD15
rw |
PD14
rw |
PD13
rw |
PD12
rw |
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD4
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 4: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 12: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 13: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 14: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Bit 15: Port D pull-down bit y (y=0..15) When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register..
Power Port E pull-down control register
Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD15
rw |
PD14
rw |
PD13
rw |
PD12
rw |
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD4
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 4: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 12: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 13: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 14: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Bit 15: Port E pull-down bit y (y=0..15) When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register..
Power Port F pull-up control register
Offset: 0x48, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PU15
rw |
PU14
rw |
PU13
rw |
PU12
rw |
PU11
rw |
PU10
rw |
PU9
rw |
PU8
rw |
PU7
rw |
PU6
rw |
PU5
rw |
PU4
rw |
PU3
rw |
PU2
rw |
PU1
rw |
PU0
rw |
Bit 0: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 1: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 2: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 3: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 4: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 5: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 6: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 7: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 8: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 9: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 10: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 11: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 12: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 13: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 14: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 15: Port F pull-up bit y (y=0..15) When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Power Port F pull-down control register
Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD15
rw |
PD14
rw |
PD13
rw |
PD12
rw |
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD4
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 4: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 12: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 13: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 14: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Bit 15: Port F pull-down bit y (y=0..15) When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register..
Power Port G pull-up control register
Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PU15
rw |
PU14
rw |
PU13
rw |
PU12
rw |
PU11
rw |
PU10
rw |
PU9
rw |
PU8
rw |
PU7
rw |
PU6
rw |
PU5
rw |
PU4
rw |
PU3
rw |
PU2
rw |
PU1
rw |
PU0
rw |
Bit 0: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 1: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 2: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 3: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 4: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 5: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 6: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 7: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 8: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 9: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 10: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 11: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 12: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 13: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 14: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 15: Port G pull-up bit y (y=0..15) When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Power Port G pull-down control register
Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD15
rw |
PD14
rw |
PD13
rw |
PD12
rw |
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD4
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 4: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 12: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 13: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 14: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Bit 15: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register..
Power Port H pull-up control register
Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PU15
rw |
PU14
rw |
PU13
rw |
PU12
rw |
PU11
rw |
PU10
rw |
PU9
rw |
PU8
rw |
PU7
rw |
PU6
rw |
PU5
rw |
PU4
rw |
PU3
rw |
PU2
rw |
PU1
rw |
PU0
rw |
Bit 0: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 1: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 2: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 3: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 4: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 5: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 6: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 7: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 8: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 9: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 10: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 11: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 12: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 13: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 14: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 15: Port H pull-up bit y (y=0..15) When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Power Port H pull-down control register
Offset: 0x5c, size: 32, reset: 0x00000000, access: Unspecified
0/16 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD15
rw |
PD14
rw |
PD13
rw |
PD12
rw |
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD4
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 4: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 12: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 13: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 14: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Bit 15: Port H pull-down bit x (y =15...0) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register..
Power Port I pull-up control register
Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified
0/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PU11
rw |
PU10
rw |
PU9
rw |
PU8
rw |
PU7
rw |
PU6
rw |
PU5
rw |
PU4
rw |
PU3
rw |
PU2
rw |
PU1
rw |
PU0
rw |
Bit 0: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 1: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 2: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 3: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 4: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 5: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 6: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 7: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 8: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 9: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 10: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Bit 11: Port I pull-up bit y (y=0..11) When set, this bit activates the pull-up on PI[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set..
Power Port I pull-down control register
Offset: 0x64, size: 32, reset: 0x00000000, access: Unspecified
0/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PD11
rw |
PD10
rw |
PD9
rw |
PD8
rw |
PD7
rw |
PD6
rw |
PD5
rw |
PD4
rw |
PD3
rw |
PD2
rw |
PD1
rw |
PD0
rw |
Bit 0: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 1: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 2: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 3: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 4: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 5: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 6: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 7: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 8: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 9: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 10: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
Bit 11: Port I pull-down bit y (y=0..11) When set, this bit activates the pull-down on PI[y] when APC bit is set in PWR_CR3 register..
PWR control register
Offset: 0x80, size: 32, reset: 0x00000100, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
R1MODE
rw |
0x40021000: Reset and clock control
56/341 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | ICSCR | ||||||||||||||||||||||||||||||||
0x8 | CFGR | ||||||||||||||||||||||||||||||||
0xc | PLLCFGR | ||||||||||||||||||||||||||||||||
0x10 | PLLSAI1CFGR | ||||||||||||||||||||||||||||||||
0x14 | PLLSAI2CFGR | ||||||||||||||||||||||||||||||||
0x18 | CIER | ||||||||||||||||||||||||||||||||
0x1c | CIFR | ||||||||||||||||||||||||||||||||
0x20 | CICR | ||||||||||||||||||||||||||||||||
0x28 | AHB1RSTR | ||||||||||||||||||||||||||||||||
0x2c | AHB2RSTR | ||||||||||||||||||||||||||||||||
0x30 | AHB3RSTR | ||||||||||||||||||||||||||||||||
0x38 | APB1RSTR1 | ||||||||||||||||||||||||||||||||
0x3c | APB1RSTR2 | ||||||||||||||||||||||||||||||||
0x40 | APB2RSTR | ||||||||||||||||||||||||||||||||
0x48 | AHB1ENR | ||||||||||||||||||||||||||||||||
0x4c | AHB2ENR | ||||||||||||||||||||||||||||||||
0x50 | AHB3ENR | ||||||||||||||||||||||||||||||||
0x58 | APB1ENR1 | ||||||||||||||||||||||||||||||||
0x5c | APB1ENR2 | ||||||||||||||||||||||||||||||||
0x60 | APB2ENR | ||||||||||||||||||||||||||||||||
0x68 | AHB1SMENR | ||||||||||||||||||||||||||||||||
0x6c | AHB2SMENR | ||||||||||||||||||||||||||||||||
0x70 | AHB3SMENR | ||||||||||||||||||||||||||||||||
0x78 | APB1SMENR1 | ||||||||||||||||||||||||||||||||
0x7c | APB1SMENR2 | ||||||||||||||||||||||||||||||||
0x80 | APB2SMENR | ||||||||||||||||||||||||||||||||
0x88 | CCIPR | ||||||||||||||||||||||||||||||||
0x90 | BDCR | ||||||||||||||||||||||||||||||||
0x94 | CSR | ||||||||||||||||||||||||||||||||
0x98 | CRRCR | ||||||||||||||||||||||||||||||||
0x9c | CCIPR2 |
Clock control register
Offset: 0x0, size: 32, reset: 0x00000063, access: Unspecified
7/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLLSAI2RDY
r |
PLLSAI2ON
rw |
PLLSAI1RDY
r |
PLLSAI1ON
rw |
PLLRDY
r |
PLLON
rw |
CSSON
w |
HSEBYP
rw |
HSERDY
r |
HSEON
rw |
||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HSIASFS
rw |
HSIRDY
r |
HSIKERON
rw |
HSION
rw |
MSIRANGE
rw |
MSIRGSEL
w |
MSIPLLEN
rw |
MSIRDY
r |
MSION
rw |
Bit 0: MSI clock enable.
Bit 1: MSI clock ready flag.
Bit 2: MSI clock PLL enable.
Bit 3: MSI clock range selection.
Bits 4-7: MSI clock ranges.
Allowed values:
0: Range100K: range 0 around 100 kHz
1: Range200K: range 1 around 200 kHz
2: Range400K: range 2 around 400 kHz
3: Range800K: range 3 around 800 kHz
4: Range1M: range 4 around 1 MHz
5: Range2M: range 5 around 2 MHz
6: Range4M: range 6 around 4 MHz
7: Range8M: range 7 around 8 MHz
8: Range16M: range 8 around 16 MHz
9: Range24M: range 9 around 24 MHz
10: Range32M: range 10 around 32 MHz
11: Range48M: range 11 around 48 MHz
Bit 8: HSI clock enable.
Bit 9: HSI always enable for peripheral kernels.
Bit 10: HSI clock ready flag.
Bit 11: HSI automatic start from Stop.
Bit 16: HSE clock enable.
Bit 17: HSE clock ready flag.
Bit 18: HSE crystal oscillator bypass.
Bit 19: Clock security system enable.
Bit 24: Main PLL enable.
Bit 25: Main PLL clock ready flag.
Bit 26: SAI1 PLL enable.
Bit 27: SAI1 PLL clock ready flag.
Bit 28: SAI2 PLL enable.
Bit 29: SAI2 PLL clock ready flag.
Internal clock sources calibration register
Offset: 0x4, size: 32, reset: 0x10000000, access: Unspecified
2/4 fields covered.
Clock configuration register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
2/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MCOPRE
r |
MCOSEL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STOPWUCK
rw |
PPRE2
rw |
PPRE1
rw |
HPRE
rw |
SWS
r |
SW
rw |
Bits 0-1: System clock switch.
Bits 2-3: System clock switch status.
Bits 4-7: AHB prescaler.
Bits 8-10: PB low-speed prescaler (APB1).
Bits 11-13: APB high-speed prescaler (APB2).
Bit 15: Wakeup from Stop and CSS backup clock selection.
Bits 24-26: Microcontroller clock output.
Bits 28-30: Microcontroller clock output prescaler.
PLL configuration register
Offset: 0xc, size: 32, reset: 0x00001000, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLLPDIV
rw |
PLLR
rw |
PLLREN
rw |
PLLQ
rw |
PLLQEN
rw |
PLLP
rw |
PLLPEN
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLLN
rw |
PLLM
rw |
PLLSRC
rw |
Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.
Bits 4-7: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.
Bits 8-14: Main PLL multiplication factor for VCO.
Bit 16: Main PLL PLLSAI3CLK output enable.
Bit 17: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).
Bit 20: Main PLL PLLUSB1CLK output enable.
Bits 21-22: Main PLL division factor for PLLUSB1CLK(48 MHz clock).
Bit 24: Main PLL PLLCLK output enable.
Bits 25-26: Main PLL division factor for PLLCLK (system clock).
Bits 27-31: Main PLL division factor for PLLSAI2CLK.
PLLSAI1 configuration register
Offset: 0x10, size: 32, reset: 0x00001000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLLSAI1PDIV
rw |
PLLSAI1R
rw |
PLLSAI1REN
rw |
PLLSAI1Q
rw |
PLLSAI1QEN
rw |
PLLSAI1P
rw |
PLLSAI1PEN
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLLSAI1N
rw |
PLLSAI1M
rw |
Bits 4-7: Division factor for PLLSAI1 input clock.
Bits 8-14: SAI1PLL multiplication factor for VCO.
Bit 16: SAI1PLL PLLSAI1CLK output enable.
Bit 17: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).
Bit 20: SAI1PLL PLLUSB2CLK output enable.
Bits 21-22: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock).
Bit 24: PLLSAI1 PLLADC1CLK output enable.
Bits 25-26: PLLSAI1 division factor for PLLADC1CLK (ADC clock).
Bits 27-31: PLLSAI1 division factor for PLLSAI1CLK.
PLLSAI2 configuration register
Offset: 0x14, size: 32, reset: 0x00001000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLLSAI2PDIV
rw |
PLLSAI2R
rw |
PLLSAI2REN
rw |
PLLSAI2Q
rw |
PLLSAI2QEN
rw |
PLLSAI2P
rw |
PLLSAI2PEN
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLLSAI2N
rw |
PLLSAI2M
rw |
Bits 4-7: Division factor for PLLSAI2 input clock.
Bits 8-14: SAI2PLL multiplication factor for VCO.
Bit 16: SAI2PLL PLLSAI2CLK output enable.
Bit 17: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock).
Bit 20: PLLSAI2 division factor for PLLDISCLK.
Bits 21-22: SAI2PLL PLLSAI2CLK output enable.
Bit 24: PLLSAI2 PLLADC2CLK output enable.
Bits 25-26: PLLSAI2 division factor for PLLADC2CLK (ADC clock).
Bits 27-31: PLLSAI2 division factor for PLLSAI2CLK.
Clock interrupt enable register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HSI48RDYIE
rw |
LSECSSIE
rw |
PLLSAI2RDYIE
rw |
PLLSAI1RDYIE
rw |
PLLRDYIE
rw |
HSERDYIE
rw |
HSIRDYIE
rw |
MSIRDYIE
rw |
LSERDYIE
rw |
LSIRDYIE
rw |
Bit 0: LSI ready interrupt enable.
Bit 1: LSE ready interrupt enable.
Bit 2: MSI ready interrupt enable.
Bit 3: HSI ready interrupt enable.
Bit 4: HSE ready interrupt enable.
Bit 5: PLL ready interrupt enable.
Bit 6: PLLSAI1 ready interrupt enable.
Bit 7: PLLSAI2 ready interrupt enable.
Bit 9: LSE clock security system interrupt enable.
Bit 10: HSI48 ready interrupt enable.
Clock interrupt flag register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only
11/11 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HSI48RDYF
r |
LSECSSF
r |
CSSF
r |
PLLSAI2RDYF
r |
PLLSAI1RDYF
r |
PLLRDYF
r |
HSERDYF
r |
HSIRDYF
r |
MSIRDYF
r |
LSERDYF
r |
LSIRDYF
r |
Bit 0: LSI ready interrupt flag.
Bit 1: LSE ready interrupt flag.
Bit 2: MSI ready interrupt flag.
Bit 3: HSI ready interrupt flag.
Bit 4: HSE ready interrupt flag.
Bit 5: PLL ready interrupt flag.
Bit 6: PLLSAI1 ready interrupt flag.
Bit 7: PLLSAI2 ready interrupt flag.
Bit 8: Clock security system interrupt flag.
Bit 9: LSE Clock security system interrupt flag.
Bit 10: HSI48 ready interrupt flag.
Clock interrupt clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: write-only
0/11 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HSI48RDYC
w |
LSECSSC
w |
CSSC
w |
PLLSAI2RDYC
w |
PLLSAI1RDYC
w |
PLLRDYC
w |
HSERDYC
w |
HSIRDYC
w |
MSIRDYC
w |
LSERDYC
w |
LSIRDYC
w |
Bit 0: LSI ready interrupt clear.
Bit 1: LSE ready interrupt clear.
Bit 2: MSI ready interrupt clear.
Bit 3: HSI ready interrupt clear.
Bit 4: HSE ready interrupt clear.
Bit 5: PLL ready interrupt clear.
Bit 6: PLLSAI1 ready interrupt clear.
Bit 7: PLLSAI2 ready interrupt clear.
Bit 8: Clock security system interrupt clear.
Bit 9: LSE Clock security system interrupt clear.
Bit 10: HSI48 oscillator ready interrupt clear.
AHB1 peripheral reset register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/8 fields covered.
AHB2 peripheral reset register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SDMMC1RST
rw |
OSPIMRST
rw |
RNGRST
rw |
HASHRST
rw |
AESRST
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCMIRST
rw |
ADCRST
rw |
OTGFSRST
rw |
GPIOIRST
rw |
GPIOHRST
rw |
GPIOGRST
rw |
GPIOFRST
rw |
GPIOERST
rw |
GPIODRST
rw |
GPIOCRST
rw |
GPIOBRST
rw |
GPIOARST
rw |
Bit 0: IO port A reset.
Bit 1: IO port B reset.
Bit 2: IO port C reset.
Bit 3: IO port D reset.
Bit 4: IO port E reset.
Bit 5: IO port F reset.
Bit 6: IO port G reset.
Bit 7: IO port H reset.
Bit 8: IO port I reset.
Bit 12: USB OTG FS reset.
Bit 13: ADC reset.
Bit 14: Digital Camera Interface reset.
Bit 16: AES hardware accelerator reset.
Bit 17: Hash reset.
Bit 18: Random number generator reset.
Bit 20: OCTOSPI IO manager reset.
Bit 22: SDMMC1 reset.
AHB3 peripheral reset register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
APB1 peripheral reset register 1
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPTIM1RST
rw |
OPAMPRST
rw |
DAC1RST
rw |
PWRRST
rw |
CAN1RST
rw |
CRSRST
rw |
I2C3RST
rw |
I2C2RST
rw |
I2C1RST
rw |
UART5RST
rw |
UART4RST
rw |
USART3RST
rw |
USART2RST
rw |
|||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPI3RST
rw |
SPI2RST
rw |
TIM7RST
rw |
TIM6RST
rw |
TIM5RST
rw |
TIM4RST
rw |
TIM3RST
rw |
TIM2RST
rw |
Bit 0: TIM2 timer reset.
Bit 1: TIM3 timer reset.
Bit 2: TIM3 timer reset.
Bit 3: TIM5 timer reset.
Bit 4: TIM6 timer reset.
Bit 5: TIM7 timer reset.
Bit 14: SPI2 reset.
Bit 15: SPI3 reset.
Bit 17: USART2 reset.
Bit 18: USART3 reset.
Bit 19: UART4 reset.
Bit 20: UART5 reset.
Bit 21: I2C1 reset.
Bit 22: I2C2 reset.
Bit 23: I2C3 reset.
Bit 24: CRS reset.
Bit 25: CAN1 reset.
Bit 28: Power interface reset.
Bit 29: DAC1 interface reset.
Bit 30: OPAMP interface reset.
Bit 31: Low Power Timer 1 reset.
APB1 peripheral reset register 2
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPTIM2RST
rw |
I2C4RST
rw |
LPUART1RST
rw |
APB2 peripheral reset register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DSIRST
rw |
LTDCRST
rw |
DFSDM1RST
rw |
SAI2RST
rw |
SAI1RST
rw |
TIM17RST
rw |
TIM16RST
rw |
TIM15RST
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USART1RST
rw |
TIM8RST
rw |
SPI1RST
rw |
TIM1RST
rw |
SYSCFGRST
rw |
Bit 0: System configuration (SYSCFG) reset.
Bit 11: TIM1 timer reset.
Bit 12: SPI1 reset.
Bit 13: TIM8 timer reset.
Bit 14: USART1 reset.
Bit 16: TIM15 timer reset.
Bit 17: TIM16 timer reset.
Bit 18: TIM17 timer reset.
Bit 21: Serial audio interface 1 (SAI1) reset.
Bit 22: Serial audio interface 2 (SAI2) reset.
Bit 24: Digital filters for sigma-delata modulators (DFSDM) reset.
Bit 26: LCD-TFT reset.
Bit 27: DSI reset.
AHB1 peripheral clock enable register
Offset: 0x48, size: 32, reset: 0x00000100, access: read-write
0/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GFXMMUEN
rw |
DMA2DEN
rw |
TSCEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRCEN
rw |
FLASHEN
rw |
DMAMUX1EN
rw |
DMA2EN
rw |
DMA1EN
rw |
Bit 0: DMA1 clock enable.
Bit 1: DMA2 clock enable.
Bit 2: DMAMUX clock enable.
Bit 8: Flash memory interface clock enable.
Bit 12: CRC clock enable.
Bit 16: Touch Sensing Controller clock enable.
Bit 17: DMA2D clock enable.
Bit 18: Graphic MMU clock enable.
AHB2 peripheral clock enable register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
1/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SDMMC1EN
rw |
OSPIMEN
rw |
RNGEN
rw |
HASHEN
rw |
AESEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCMIEN
rw |
ADCEN
rw |
OTGFSEN
rw |
GPIOIEN
rw |
GPIOHEN
rw |
GPIOGEN
rw |
GPIOFEN
rw |
GPIOEEN
rw |
GPIODEN
rw |
GPIOCEN
rw |
GPIOBEN
rw |
GPIOAEN
rw |
Bit 0: IO port A clock enable.
Bit 1: IO port B clock enable.
Bit 2: IO port C clock enable.
Bit 3: IO port D clock enable.
Bit 4: IO port E clock enable.
Bit 5: IO port F clock enable.
Bit 6: IO port G clock enable.
Bit 7: IO port H clock enable.
Bit 8: IO port I clock enable.
Bit 12: OTG full speed clock enable.
Bit 13: ADC clock enable.
Allowed values:
0: Disabled: ADC clock disabled
1: Enabled: ADC clock enabled
Bit 14: DCMI clock enable.
Bit 16: AES accelerator clock enable.
Bit 17: HASH clock enable.
Bit 18: Random Number Generator clock enable.
Bit 20: OctoSPI IO manager clock enable.
Bit 22: SDMMC1 clock enable.
AHB3 peripheral clock enable register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
APB1ENR1
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
4/23 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPTIM1EN
rw |
OPAMPEN
rw |
DAC1EN
rw |
PWREN
rw |
CAN1EN
rw |
CRSEN
rw |
I2C3EN
rw |
I2C2EN
rw |
I2C1EN
rw |
UART5EN
rw |
UART4EN
rw |
USART3EN
rw |
USART2EN
rw |
|||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPI3EN
rw |
SPI2EN
rw |
WWDGEN
rw |
RTCAPBEN
rw |
TIM7EN
rw |
TIM6EN
rw |
TIM5EN
rw |
TIM4EN
rw |
TIM3EN
rw |
TIM2EN
rw |
Bit 0: TIM2 timer clock enable.
Bit 1: TIM3 timer clock enable.
Bit 2: TIM4 timer clock enable.
Bit 3: TIM5 timer clock enable.
Bit 4: TIM6 timer clock enable.
Bit 5: TIM7 timer clock enable.
Bit 10: RTC APB clock enable.
Bit 11: Window watchdog clock enable.
Bit 14: SPI2 clock enable.
Bit 15: SPI peripheral 3 clock enable.
Bit 17: USART2 clock enable.
Bit 18: USART3 clock enable.
Bit 19: UART4 clock enable.
Bit 20: UART5 clock enable.
Bit 21: I2C1 clock enable.
Allowed values:
0: Disabled: I2C1 clock disabled
1: Enabled: I2C1 clock enabled
Bit 22: I2C2 clock enable.
Allowed values:
0: Disabled: I2C2 clock disabled
1: Enabled: I2C2 clock enabled
Bit 23: I2C3 clock enable.
Allowed values:
0: Disabled: I2C3 clock disabled
1: Enabled: I2C3 clock enabled
Bit 24: Clock Recovery System clock enable.
Bit 25: CAN1 clock enable.
Bit 28: Power interface clock enable.
Bit 29: DAC1 interface clock enable.
Bit 30: OPAMP interface clock enable.
Bit 31: Low power timer 1 clock enable.
Allowed values:
0: Disabled: LPTIM1 clock disabled
1: Enabled: LPTIM1 clock enabled
APB1 peripheral clock enable register 2
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
2/3 fields covered.
APB2ENR
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
1/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DSIEN
rw |
LTDCEN
rw |
DFSDM1EN
rw |
SAI2EN
rw |
SAI1EN
rw |
TIM17EN
rw |
TIM16EN
rw |
TIM15EN
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USART1EN
rw |
TIM8EN
rw |
SPI1EN
rw |
TIM1EN
rw |
FWEN
rw |
SYSCFGEN
rw |
Bit 0: SYSCFG clock enable.
Bit 7: Firewall clock enable.
Bit 11: TIM1 timer clock enable.
Bit 12: SPI1 clock enable.
Bit 13: TIM8 timer clock enable.
Bit 14: USART1clock enable.
Allowed values:
0: Disabled: USART1 clock disabled
1: Enabled: USART1 clock enabled
Bit 16: TIM15 timer clock enable.
Bit 17: TIM16 timer clock enable.
Bit 18: TIM17 timer clock enable.
Bit 21: SAI1 clock enable.
Bit 22: SAI2 clock enable.
Bit 24: DFSDM timer clock enable.
Bit 26: LCD-TFT clock enable.
Bit 27: DSI clock enable.
AHB1 peripheral clocks enable in Sleep and Stop modes register
Offset: 0x68, size: 32, reset: 0x00011303, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GFXMMUSMEN
rw |
DMA2DSMEN
rw |
TSCSMEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRCSMEN
rw |
SRAM1SMEN
rw |
FLASHSMEN
rw |
DMAMUX1SMEN
rw |
DMA2SMEN
rw |
DMA1SMEN
rw |
Bit 0: DMA1 clocks enable during Sleep and Stop modes.
Bit 1: DMA2 clocks enable during Sleep and Stop modes.
Bit 2: DMAMUX clock enable during Sleep and Stop modes.
Bit 8: Flash memory interface clocks enable during Sleep and Stop modes.
Bit 9: SRAM1 interface clocks enable during Sleep and Stop modes.
Bit 12: CRCSMEN.
Bit 16: Touch Sensing Controller clocks enable during Sleep and Stop modes.
Bit 17: DMA2D clock enable during Sleep and Stop modes.
Bit 18: GFXMMU clock enable during Sleep and Stop modes.
AHB2 peripheral clocks enable in Sleep and Stop modes register
Offset: 0x6c, size: 32, reset: 0x000532FF, access: read-write
0/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SDMMC1SMEN
rw |
OSPIMSMEN
rw |
RNGSMEN
rw |
HASHSMEN
rw |
AESSMEN
rw |
|||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCMISMEN
rw |
ADCFSSMEN
rw |
OTGFSSMEN
rw |
SRAM3SMEN
rw |
SRAM2SMEN
rw |
GPIOISMEN
rw |
GPIOHSMEN
rw |
GPIOGSMEN
rw |
GPIOFSMEN
rw |
GPIOESMEN
rw |
GPIODSMEN
rw |
GPIOCSMEN
rw |
GPIOBSMEN
rw |
GPIOASMEN
rw |
Bit 0: IO port A clocks enable during Sleep and Stop modes.
Bit 1: IO port B clocks enable during Sleep and Stop modes.
Bit 2: IO port C clocks enable during Sleep and Stop modes.
Bit 3: IO port D clocks enable during Sleep and Stop modes.
Bit 4: IO port E clocks enable during Sleep and Stop modes.
Bit 5: IO port F clocks enable during Sleep and Stop modes.
Bit 6: IO port G clocks enable during Sleep and Stop modes.
Bit 7: IO port H clocks enable during Sleep and Stop modes.
Bit 8: IO port I clocks enable during Sleep and Stop modes.
Bit 9: SRAM2 interface clocks enable during Sleep and Stop modes.
Bit 10: SRAM2 interface clocks enable during Sleep and Stop modes.
Bit 12: OTG full speed clocks enable during Sleep and Stop modes.
Bit 13: ADC clocks enable during Sleep and Stop modes.
Bit 14: DCMI clock enable during Sleep and Stop modes.
Bit 16: AES accelerator clocks enable during Sleep and Stop modes.
Bit 17: HASH clock enable during Sleep and Stop modes.
Bit 18: Random Number Generator clocks enable during Sleep and Stop modes.
Bit 20: OctoSPI IO manager clocks enable during Sleep and Stop modes.
Bit 22: SDMMC1 clocks enable during Sleep and Stop modes.
AHB3 peripheral clocks enable in Sleep and Stop modes register
Offset: 0x70, size: 32, reset: 0x00000101, access: read-write
0/2 fields covered.
APB1SMENR1
Offset: 0x78, size: 32, reset: 0xF2FECA3F, access: read-write
0/23 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPTIM1SMEN
rw |
OPAMPSMEN
rw |
DAC1SMEN
rw |
PWRSMEN
rw |
CAN1SMEN
rw |
CRSSMEN
rw |
I2C3SMEN
rw |
I2C2SMEN
rw |
I2C1SMEN
rw |
UART5SMEN
rw |
UART4SMEN
rw |
USART3SMEN
rw |
USART2SMEN
rw |
|||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SP3SMEN
rw |
SPI2SMEN
rw |
WWDGSMEN
rw |
RTCAPBSMEN
rw |
TIM7SMEN
rw |
TIM6SMEN
rw |
TIM5SMEN
rw |
TIM4SMEN
rw |
TIM3SMEN
rw |
TIM2SMEN
rw |
Bit 0: TIM2 timer clocks enable during Sleep and Stop modes.
Bit 1: TIM3 timer clocks enable during Sleep and Stop modes.
Bit 2: TIM4 timer clocks enable during Sleep and Stop modes.
Bit 3: TIM5 timer clocks enable during Sleep and Stop modes.
Bit 4: TIM6 timer clocks enable during Sleep and Stop modes.
Bit 5: TIM7 timer clocks enable during Sleep and Stop modes.
Bit 10: RTC APB clock enable during Sleep and Stop modes.
Bit 11: Window watchdog clocks enable during Sleep and Stop modes.
Bit 14: SPI2 clocks enable during Sleep and Stop modes.
Bit 15: SPI3 clocks enable during Sleep and Stop modes.
Bit 17: USART2 clocks enable during Sleep and Stop modes.
Bit 18: USART3 clocks enable during Sleep and Stop modes.
Bit 19: UART4 clocks enable during Sleep and Stop modes.
Bit 20: UART5 clocks enable during Sleep and Stop modes.
Bit 21: I2C1 clocks enable during Sleep and Stop modes.
Bit 22: I2C2 clocks enable during Sleep and Stop modes.
Bit 23: I2C3 clocks enable during Sleep and Stop modes.
Bit 24: CRS clock enable during Sleep and Stop modes.
Bit 25: CAN1 clocks enable during Sleep and Stop modes.
Bit 28: Power interface clocks enable during Sleep and Stop modes.
Bit 29: DAC1 interface clocks enable during Sleep and Stop modes.
Bit 30: OPAMP interface clocks enable during Sleep and Stop modes.
Bit 31: Low power timer 1 clocks enable during Sleep and Stop modes.
APB1 peripheral clocks enable in Sleep and Stop modes register 2
Offset: 0x7c, size: 32, reset: 0x00000025, access: read-write
0/3 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPTIM2SMEN
rw |
I2C4SMEN
rw |
LPUART1SMEN
rw |
APB2SMENR
Offset: 0x80, size: 32, reset: 0x01677C01, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DSISMEN
rw |
LTDCSMEN
rw |
DFSDM1SMEN
rw |
SAI2SMEN
rw |
SAI1SMEN
rw |
TIM17SMEN
rw |
TIM16SMEN
rw |
TIM15SMEN
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USART1SMEN
rw |
TIM8SMEN
rw |
SPI1SMEN
rw |
TIM1SMEN
rw |
SYSCFGSMEN
rw |
Bit 0: SYSCFG clocks enable during Sleep and Stop modes.
Bit 11: TIM1 timer clocks enable during Sleep and Stop modes.
Bit 12: SPI1 clocks enable during Sleep and Stop modes.
Bit 13: TIM8 timer clocks enable during Sleep and Stop modes.
Bit 14: USART1clocks enable during Sleep and Stop modes.
Bit 16: TIM15 timer clocks enable during Sleep and Stop modes.
Bit 17: TIM16 timer clocks enable during Sleep and Stop modes.
Bit 18: TIM17 timer clocks enable during Sleep and Stop modes.
Bit 21: SAI1 clocks enable during Sleep and Stop modes.
Bit 22: SAI2 clocks enable during Sleep and Stop modes.
Bit 24: DFSDM timer clocks enable during Sleep and Stop modes.
Bit 26: LCD-TFT timer clocks enable during Sleep and Stop modes.
Bit 27: DSI clocks enable during Sleep and Stop modes.
CCIPR
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
11/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADCSEL
rw |
CLK48SEL
rw |
SAI2SEL
rw |
SAI1SEL
rw |
LPTIM2SEL
rw |
LPTIM1SEL
rw |
I2C3SEL
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2C2SEL
rw |
I2C1SEL
rw |
LPUART1SEL
rw |
UART5SEL
rw |
UART4SEL
rw |
USART3SEL
rw |
USART2SEL
rw |
USART1SEL
rw |
Bits 0-1: USART1 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected
Bits 2-3: USART2 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected
Bits 4-5: USART3 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected
Bits 6-7: UART4 clock source selection.
Bits 8-9: UART5 clock source selection.
Bits 10-11: LPUART1 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected
Bits 12-13: I2C1 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
Bits 14-15: I2C2 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
Bits 16-17: I2C3 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
Bits 18-19: Low power timer 1 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected
Bits 20-21: Low power timer 2 clock source selection.
Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected
Bits 22-23: SAI1 clock source selection.
Bits 24-25: SAI2 clock source selection.
Bits 26-27: 48 MHz clock source selection.
Allowed values:
0: HSI48: HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)
1: PLLSAI1: PLLSAI1 clock selected
2: PLL: PLL clock selected
3: MSI: MSI clock selected
Bits 28-29: ADCs clock source selection.
Allowed values:
0: NoClock: No clock selected
1: PLLSAI1: PLLSAI1 clock selected
2: PLLSAI2: PLLSAI2 clock selected (only for STM32L47x/L48x/L49x/L4Ax devices)
3: SYSCLK: SYSCLK clock selected
BDCR
Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified
4/11 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LSCOSEL
rw |
LSCOEN
rw |
BDRST
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTCEN
rw |
RTCSEL
rw |
LSECSSD
r |
LSECSSON
rw |
LSEDRV
rw |
LSEBYP
rw |
LSERDY
r |
LSEON
rw |
Bit 0: LSE oscillator enable.
Bit 1: LSE oscillator ready.
Bit 2: LSE oscillator bypass.
Bits 3-4: SE oscillator drive capability.
Bit 5: LSECSSON.
Bit 6: LSECSSD.
Bits 8-9: RTC clock source selection.
Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock selected
2: LSI: LSI oscillator clock selected
3: HSE: HSE oscillator clock divided by 32 selected
Bit 15: RTC clock enable.
Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled
Bit 16: Backup domain software reset.
Bit 24: Low speed clock output enable.
Bit 25: Low speed clock output selection.
CSR
Offset: 0x94, size: 32, reset: 0x0C000600, access: Unspecified
9/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LPWRSTF
r |
WWDGRSTF
r |
IWDGRSTF
r |
SFTRSTF
r |
BORRSTF
r |
PINRSTF
r |
OBLRSTF
r |
FWRSTF
r |
RMVF
rw |
|||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSISRANGE
rw |
LSIRDY
r |
LSION
rw |
Bit 0: LSI oscillator enable.
Bit 1: LSI oscillator ready.
Bits 8-11: SI range after Standby mode.
Bit 23: Remove reset flag.
Bit 24: Firewall reset flag.
Bit 25: Option byte loader reset flag.
Bit 26: Pin reset flag.
Bit 27: BOR flag.
Bit 28: Software reset flag.
Bit 29: Independent window watchdog reset flag.
Bit 30: Window watchdog reset flag.
Bit 31: Low-power reset flag.
Clock recovery RC register
Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified
2/3 fields covered.
Peripherals independent clock configuration register
Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OSPISEL
rw |
PLLSAI2DIVR
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SDMMCSEL
rw |
DSISEL
rw |
SAI2SEL
rw |
SAI1SEL
rw |
ADFSDMSEL
rw |
DFSDMSEL
rw |
I2C4SEL
rw |
Bits 0-1: I2C4 clock source selection.
Bit 2: Digital filter for sigma delta modulator kernel clock source selection.
Bits 3-4: Digital filter for sigma delta modulator audio clock source selection.
Bits 5-7: SAI1 clock source selection.
Bits 8-10: SAI2 clock source selection.
Bit 12: clock selection.
Bit 14: SDMMC clock selection.
Bits 16-17: division factor for LTDC clock.
Bits 20-21: Octospi clock source selection.
0x50060800: Random number generator
4/8 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | SR | ||||||||||||||||||||||||||||||||
0x8 | DR |
0x40002800: Real-time clock
141/165 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | TR | ||||||||||||||||||||||||||||||||
0x4 | DR | ||||||||||||||||||||||||||||||||
0x8 | CR | ||||||||||||||||||||||||||||||||
0xc | ISR | ||||||||||||||||||||||||||||||||
0x10 | PRER | ||||||||||||||||||||||||||||||||
0x14 | WUTR | ||||||||||||||||||||||||||||||||
0x1c | ALRM[A]R | ||||||||||||||||||||||||||||||||
0x20 | ALRM[B]R | ||||||||||||||||||||||||||||||||
0x24 | WPR | ||||||||||||||||||||||||||||||||
0x28 | SSR | ||||||||||||||||||||||||||||||||
0x2c | SHIFTR | ||||||||||||||||||||||||||||||||
0x30 | TSTR | ||||||||||||||||||||||||||||||||
0x34 | TSDR | ||||||||||||||||||||||||||||||||
0x38 | TSSSR | ||||||||||||||||||||||||||||||||
0x3c | CALR | ||||||||||||||||||||||||||||||||
0x40 | TAMPCR | ||||||||||||||||||||||||||||||||
0x44 | ALRM[A]SSR | ||||||||||||||||||||||||||||||||
0x48 | ALRM[B]SSR | ||||||||||||||||||||||||||||||||
0x4c | OR | ||||||||||||||||||||||||||||||||
0x50 | BKP[0]R | ||||||||||||||||||||||||||||||||
0x54 | BKP[1]R | ||||||||||||||||||||||||||||||||
0x58 | BKP[2]R | ||||||||||||||||||||||||||||||||
0x5c | BKP[3]R | ||||||||||||||||||||||||||||||||
0x60 | BKP[4]R | ||||||||||||||||||||||||||||||||
0x64 | BKP[5]R | ||||||||||||||||||||||||||||||||
0x68 | BKP[6]R | ||||||||||||||||||||||||||||||||
0x6c | BKP[7]R | ||||||||||||||||||||||||||||||||
0x70 | BKP[8]R | ||||||||||||||||||||||||||||||||
0x74 | BKP[9]R | ||||||||||||||||||||||||||||||||
0x78 | BKP[10]R | ||||||||||||||||||||||||||||||||
0x7c | BKP[11]R | ||||||||||||||||||||||||||||||||
0x80 | BKP[12]R | ||||||||||||||||||||||||||||||||
0x84 | BKP[13]R | ||||||||||||||||||||||||||||||||
0x88 | BKP[14]R | ||||||||||||||||||||||||||||||||
0x8c | BKP[15]R | ||||||||||||||||||||||||||||||||
0x90 | BKP[16]R | ||||||||||||||||||||||||||||||||
0x94 | BKP[17]R | ||||||||||||||||||||||||||||||||
0x98 | BKP[18]R | ||||||||||||||||||||||||||||||||
0x9c | BKP[19]R | ||||||||||||||||||||||||||||||||
0xa0 | BKP[20]R | ||||||||||||||||||||||||||||||||
0xa4 | BKP[21]R | ||||||||||||||||||||||||||||||||
0xa8 | BKP[22]R | ||||||||||||||||||||||||||||||||
0xac | BKP[23]R | ||||||||||||||||||||||||||||||||
0xb0 | BKP[24]R | ||||||||||||||||||||||||||||||||
0xb4 | BKP[25]R | ||||||||||||||||||||||||||||||||
0xb8 | BKP[26]R | ||||||||||||||||||||||||||||||||
0xbc | BKP[27]R | ||||||||||||||||||||||||||||||||
0xc0 | BKP[28]R | ||||||||||||||||||||||||||||||||
0xc4 | BKP[29]R | ||||||||||||||||||||||||||||||||
0xc8 | BKP[30]R | ||||||||||||||||||||||||||||||||
0xcc | BKP[31]R |
time register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PM
rw |
HT
rw |
HU
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MNT
rw |
MNU
rw |
ST
rw |
SU
rw |
Bits 0-3: Second units in BCD format.
Allowed values: 0x0-0xf
Bits 4-6: Second tens in BCD format.
Allowed values: 0x0-0x7
Bits 8-11: Minute units in BCD format.
Allowed values: 0x0-0xf
Bits 12-14: Minute tens in BCD format.
Allowed values: 0x0-0x7
Bits 16-19: Hour units in BCD format.
Allowed values: 0x0-0xf
Bits 20-21: Hour tens in BCD format.
Allowed values: 0x0-0x3
Bit 22: AM/PM notation.
Allowed values:
0: AM: AM or 24-hour format
1: PM: PM
date register
Offset: 0x4, size: 32, reset: 0x00002101, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
YT
rw |
YU
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDU
rw |
MT
rw |
MU
rw |
DT
rw |
DU
rw |
Bits 0-3: Date units in BCD format.
Allowed values: 0x0-0xf
Bits 4-5: Date tens in BCD format.
Allowed values: 0x0-0x3
Bits 8-11: Month units in BCD format.
Allowed values: 0x0-0xf
Bit 12: Month tens in BCD format.
Allowed values:
0: Zero: Month tens is 0
1: One: Month tens is 1
Bits 13-15: Week day units.
Allowed values: 0x1-0x7
Bits 16-19: Year units in BCD format.
Allowed values: 0x0-0xf
Bits 20-23: Year tens in BCD format.
Allowed values: 0x0-0xf
control register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
20/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ITSE
rw |
COE
rw |
OSEL
rw |
POL
rw |
COSEL
rw |
BKP
rw |
SUB1H
rw |
ADD1H
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSIE
rw |
WUTIE
rw |
ALR[B]IE
rw |
ALR[A]IE
rw |
TSE
rw |
WUTE
rw |
ALR[B]E
rw |
ALR[A]E
rw |
FMT
rw |
BYPSHAD
rw |
REFCKON
rw |
TSEDGE
rw |
WUCKSEL
rw |
Bits 0-2: Wakeup clock selection.
Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
Bit 3: Time-stamp event active edge.
Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event
Bit 4: Reference clock detection enable (50 or 60 Hz).
Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled
Bit 5: Bypass the shadow registers.
Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
Bit 6: Hour format.
Allowed values:
0: Twenty_Four_Hour: 24 hour/day format
1: AM_PM: AM/PM hour format
Bit 8: Alarm A enable.
Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled
Bit 9: Alarm B enable.
Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled
Bit 10: Wakeup timer enable.
Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled
Bit 11: Time stamp enable.
Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled
Bit 12: Alarm A interrupt enable.
Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled
Bit 13: Alarm B interrupt enable.
Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled
Bit 14: Wakeup timer interrupt enable.
Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled
Bit 15: Time-stamp interrupt enable.
Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled
Bit 16: Add 1 hour (summer time change).
Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
Bit 17: Subtract 1 hour (winter time change).
Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
Bit 18: Backup.
Allowed values:
0: DST_Not_Changed: Daylight Saving Time change has not been performed
1: DST_Changed: Daylight Saving Time change has been performed
Bit 19: Calibration output selection.
Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)
Bit 20: Output polarity.
Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
Bits 21-22: Output selection.
Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled
Bit 23: Calibration output enable.
Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled
Bit 24: timestamp on internal event enable.
initialization and status register
Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified
17/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RECALPF
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAMP3F
r/w0c |
TAMP2F
r/w0c |
TAMP1F
r/w0c |
TSOVF
r/w0c |
TSF
r/w0c |
WUTF
r/w0c |
ALR[B]F
r/w0c |
ALR[A]F
r/w0c |
INIT
rw |
INITF
r |
RSF
r/w0c |
INITS
r |
SHPF
rw |
WUTWF
r |
ALR[B]WF
r |
ALR[A]WF
r |
Bit 0: Alarm A write flag.
Allowed values:
0: UpdateNotAllowed: Alarm update not allowed
1: UpdateAllowed: Alarm update allowed
Bit 1: Alarm B write flag.
Allowed values:
0: UpdateNotAllowed: Alarm update not allowed
1: UpdateAllowed: Alarm update allowed
Bit 2: Wakeup timer write flag.
Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed
Bit 3: Shift operation pending.
Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending
Bit 4: Initialization status flag.
Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized
Bit 5: Registers synchronization flag.
Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized
Bit 6: Initialization flag.
Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed
Bit 7: Initialization mode.
Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Bit 8: Alarm A flag.
Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
Bit 9: Alarm B flag.
Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)
Bit 10: Wakeup timer flag.
Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0
Bit 11: Time-stamp flag.
Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs
Bit 12: Time-stamp overflow flag.
Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set
Bit 13: Tamper detection flag.
Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
Bit 14: RTC_TAMP2 detection flag.
Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
Bit 15: RTC_TAMP3 detection flag.
Allowed values:
1: Tampered: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input
Bit 16: Recalibration pending Flag.
Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
prescaler register
Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write
2/2 fields covered.
wakeup timer register
Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUT
rw |
Alarm A register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
14/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MSK4
rw |
WDSEL
rw |
DT
rw |
DU
rw |
MSK3
rw |
PM
rw |
HT
rw |
HU
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK2
rw |
MNT
rw |
MNU
rw |
MSK1
rw |
ST
rw |
SU
rw |
Bits 0-3: Second units in BCD format.
Allowed values: 0x0-0xf
Bits 4-6: Second tens in BCD format.
Allowed values: 0x0-0x7
Bit 7: Alarm seconds mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 8-11: Minute units in BCD format.
Allowed values: 0x0-0xf
Bits 12-14: Minute tens in BCD format.
Allowed values: 0x0-0x7
Bit 15: Alarm minutes mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 16-19: Hour units in BCD format.
Allowed values: 0x0-0xf
Bits 20-21: Hour tens in BCD format.
Allowed values: 0x0-0x3
Bit 22: AM/PM notation.
Allowed values:
0: AM: AM or 24-hour format
1: PM: PM
Bit 23: Alarm hours mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 24-27: Date units or day in BCD format.
Allowed values: 0x0-0xf
Bits 28-29: Date tens in BCD format.
Allowed values: 0x0-0x3
Bit 30: Week day selection.
Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bit 31: Alarm date mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Alarm B register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
14/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MSK4
rw |
WDSEL
rw |
DT
rw |
DU
rw |
MSK3
rw |
PM
rw |
HT
rw |
HU
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK2
rw |
MNT
rw |
MNU
rw |
MSK1
rw |
ST
rw |
SU
rw |
Bits 0-3: Second units in BCD format.
Allowed values: 0x0-0xf
Bits 4-6: Second tens in BCD format.
Allowed values: 0x0-0x7
Bit 7: Alarm seconds mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 8-11: Minute units in BCD format.
Allowed values: 0x0-0xf
Bits 12-14: Minute tens in BCD format.
Allowed values: 0x0-0x7
Bit 15: Alarm minutes mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 16-19: Hour units in BCD format.
Allowed values: 0x0-0xf
Bits 20-21: Hour tens in BCD format.
Allowed values: 0x0-0x3
Bit 22: AM/PM notation.
Allowed values:
0: AM: AM or 24-hour format
1: PM: PM
Bit 23: Alarm hours mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
Bits 24-27: Date units or day in BCD format.
Allowed values: 0x0-0xf
Bits 28-29: Date tens in BCD format.
Allowed values: 0x0-0x3
Bit 30: Week day selection.
Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bit 31: Alarm date mask.
Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison
write protection register
Offset: 0x24, size: 32, reset: 0x00000000, access: write-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
w |
sub second register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SS
r |
shift control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only
2/2 fields covered.
time stamp time register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PM
rw |
HT
rw |
HU
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MNT
rw |
MNU
rw |
ST
rw |
SU
rw |
Bits 0-3: Second units in BCD format.
Allowed values: 0x0-0xf
Bits 4-6: Second tens in BCD format.
Allowed values: 0x0-0x7
Bits 8-11: Minute units in BCD format.
Allowed values: 0x0-0xf
Bits 12-14: Minute tens in BCD format.
Allowed values: 0x0-0x7
Bits 16-19: Hour units in BCD format.
Allowed values: 0x0-0xf
Bits 20-21: Hour tens in BCD format.
Allowed values: 0x0-0x3
Bit 22: AM/PM notation.
Allowed values:
0: AM: AM or 24-hour format
1: PM: PM
time stamp date register
Offset: 0x34, size: 32, reset: 0x00002101, access: read-write
7/7 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
YT
rw |
YU
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDU
rw |
MT
rw |
MU
rw |
DT
rw |
DU
rw |
Bits 0-3: Date units in BCD format.
Allowed values: 0x0-0xf
Bits 4-5: Date tens in BCD format.
Allowed values: 0x0-0x3
Bits 8-11: Month units in BCD format.
Allowed values: 0x0-0xf
Bit 12: Month tens in BCD format.
Allowed values:
0: Zero: Month tens is 0
1: One: Month tens is 1
Bits 13-15: Week day units.
Allowed values: 0x1-0x7
Bits 16-19: Year units in BCD format.
Allowed values: 0x0-0xf
Bits 20-23: Year tens in BCD format.
Allowed values: 0x0-0xf
timestamp sub second register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SS
r |
calibration register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
4/4 fields covered.
Bits 0-8: Calibration minus.
Allowed values: 0x0-0x1ff
Bit 13: Use a 16-second calibration cycle period.
Allowed values:
1: Sixteen_Second: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1
Bit 14: Use an 8-second calibration cycle period.
Allowed values:
1: Eight_Second: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected
Bit 15: Increase frequency of RTC by 488.5 ppm.
Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)
tamper configuration register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-write
0/21 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TAMP3MF
rw |
TAMP3NOERASE
rw |
TAMP3IE
rw |
TAMP2MF
rw |
TAMP2NOERASE
rw |
TAMP2IE
rw |
TAMP1MF
rw |
TAMP1NOERASE
rw |
TAMP1IE
rw |
|||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAMPPUDIS
rw |
TAMPPRCH
rw |
TAMPFLT
rw |
TAMPFREQ
rw |
TAMPTS
rw |
TAMP3TRG
rw |
TAMP3E
rw |
TAMP2TRG
rw |
TAMP2E
rw |
TAMPIE
rw |
TAMP1TRG
rw |
TAMP1E
rw |
Bit 0: Tamper 1 detection enable.
Bit 1: Active level for tamper 1.
Bit 2: Tamper interrupt enable.
Bit 3: Tamper 2 detection enable.
Bit 4: Active level for tamper 2.
Bit 5: Tamper 3 detection enable.
Bit 6: Active level for tamper 3.
Bit 7: Activate timestamp on tamper detection event.
Bits 8-10: Tamper sampling frequency.
Bits 11-12: Tamper filter count.
Bits 13-14: Tamper precharge duration.
Bit 15: TAMPER pull-up disable.
Bit 16: Tamper 1 interrupt enable.
Bit 17: Tamper 1 no erase.
Bit 18: Tamper 1 mask flag.
Bit 19: Tamper 2 interrupt enable.
Bit 20: Tamper 2 no erase.
Bit 21: Tamper 2 mask flag.
Bit 22: Tamper 3 interrupt enable.
Bit 23: Tamper 3 no erase.
Bit 24: Tamper 3 mask flag.
Alarm A sub-second register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
Alarm B sub-second register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-write
2/2 fields covered.
option register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RTC_OUT_RMP
rw |
RTC_ALARM_TYPE
rw |
backup register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x54, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x58, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x60, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x64, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x68, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x70, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x74, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x78, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x80, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x84, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x88, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x90, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x94, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x98, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xac, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
backup register
Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write
1/1 fields covered.
0x40015400: Serial audio interface
84/102 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x4 | CR1 [A] | ||||||||||||||||||||||||||||||||
0x8 | CR2 [A] | ||||||||||||||||||||||||||||||||
0xc | FRCR [A] | ||||||||||||||||||||||||||||||||
0x10 | SLOTR [A] | ||||||||||||||||||||||||||||||||
0x14 | IM [A] | ||||||||||||||||||||||||||||||||
0x18 | SR [A] | ||||||||||||||||||||||||||||||||
0x1c | CLRFR [A] | ||||||||||||||||||||||||||||||||
0x20 | DR [A] | ||||||||||||||||||||||||||||||||
0x24 | CR1 [B] | ||||||||||||||||||||||||||||||||
0x28 | CR2 [B] | ||||||||||||||||||||||||||||||||
0x2c | FRCR [B] | ||||||||||||||||||||||||||||||||
0x30 | SLOTR [B] | ||||||||||||||||||||||||||||||||
0x34 | IM [B] | ||||||||||||||||||||||||||||||||
0x38 | SR [B] | ||||||||||||||||||||||||||||||||
0x3c | CLRFR [B] | ||||||||||||||||||||||||||||||||
0x40 | DR [B] |
AConfiguration register 1
Offset: 0x4, size: 32, reset: 0x00000040, access: read-write
11/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MCKDIV
rw |
NODIV
rw |
DMAEN
rw |
SAIEN
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUTDRIV
rw |
MONO
rw |
SYNCEN
rw |
CKSTR
rw |
LSBFIRST
rw |
DS
rw |
PRTCFG
rw |
MODE
rw |
Bits 0-1: Audio block mode.
Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver
Bits 2-3: Protocol configuration.
Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol
Bits 5-7: Data size.
Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits
Bit 8: Least significant bit first.
Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first
Bit 9: Clock strobing edge.
Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK
Bits 10-11: Synchronization enable.
Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
Bit 12: Mono mode.
Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode
Bit 13: Output drive.
Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit
Bit 16: Audio block A enable.
Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled
Bit 17: DMA enable.
Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled
Bit 19: No divider.
Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.
Bits 20-23: Master clock divider.
AConfiguration register 2
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
6/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMP
rw |
CPL
rw |
MUTECNT
rw |
MUTEVAL
rw |
MUTE
rw |
TRIS
rw |
FFLUSH
w |
FTH
rw |
Bits 0-2: FIFO threshold.
Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full
Bit 3: FIFO flush.
Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
Bit 4: Tristate management on data line.
Bit 5: Mute.
Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled
Bit 6: Mute value.
Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode
Bits 7-12: Mute counter.
Bit 13: Complement bit.
Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation
Bits 14-15: Companding mode.
Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm
AFRCR
Offset: 0xc, size: 32, reset: 0x00000007, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FSOFF
rw |
FSPOL
rw |
FSDEF
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSALL
rw |
FRL
rw |
Bits 0-7: Frame length.
Bits 8-14: Frame synchronization active level length.
Bit 16: Frame synchronization definition.
Bit 17: Frame synchronization polarity.
Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)
Bit 18: Frame synchronization offset.
Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0
ASlot register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SLOTEN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NBSLOT
rw |
SLOTSZ
rw |
FBOFF
rw |
Bits 0-4: First bit offset.
Bits 6-7: Slot size.
Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit
Bits 8-11: Number of slots in an audio frame.
Bits 16-31: Slot enable.
Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot
AInterrupt mask register2
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LFSDETIE
rw |
AFSDETIE
rw |
CNRDYIE
rw |
FREQIE
rw |
WCKCFGIE
rw |
MUTEDETIE
rw |
OVRUDRIE
rw |
Bit 0: Overrun/underrun interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 1: Mute detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 2: Wrong clock configuration interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 3: FIFO request interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 4: Codec not ready interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 5: Anticipated frame synchronization detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 6: Late frame synchronization detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
AStatus register
Offset: 0x18, size: 32, reset: 0x00000008, access: read-only
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LFSDET
r |
AFSDET
r |
CNRDY
r |
FREQ
r |
WCKCFG
r |
MUTEDET
r |
OVRUDR
r |
Bit 0: Overrun / underrun.
Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection
Bit 1: Mute detection.
Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
Bit 2: Wrong clock configuration flag. This bit is read only.
Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification
Bit 3: FIFO request.
Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR
Bit 4: Codec not ready.
Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready
Bit 5: Anticipated frame synchronization detection.
Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected
Bit 6: Late frame synchronization detection.
Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time
Bits 16-18: FIFO level threshold.
Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full
AClear flag register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Clear overrun / underrun.
Allowed values:
1: Clear: Clears the OVRUDR flag
Bit 1: Mute detection flag.
Allowed values:
1: Clear: Clears the MUTEDET flag
Bit 2: Clear wrong clock configuration flag.
Allowed values:
1: Clear: Clears the WCKCFG flag
Bit 4: Clear codec not ready flag.
Allowed values:
1: Clear: Clears the CNRDY flag
Bit 5: Clear anticipated frame synchronization detection flag.
Allowed values:
1: Clear: Clears the AFSDET flag
Bit 6: Clear late frame synchronization detection flag.
Allowed values:
1: Clear: Clears the LFSDET flag
AData register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
AConfiguration register 1
Offset: 0x24, size: 32, reset: 0x00000040, access: read-write
11/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MCKDIV
rw |
NODIV
rw |
DMAEN
rw |
SAIEN
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUTDRIV
rw |
MONO
rw |
SYNCEN
rw |
CKSTR
rw |
LSBFIRST
rw |
DS
rw |
PRTCFG
rw |
MODE
rw |
Bits 0-1: Audio block mode.
Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver
Bits 2-3: Protocol configuration.
Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol
Bits 5-7: Data size.
Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits
Bit 8: Least significant bit first.
Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first
Bit 9: Clock strobing edge.
Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK
Bits 10-11: Synchronization enable.
Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
Bit 12: Mono mode.
Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode
Bit 13: Output drive.
Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit
Bit 16: Audio block A enable.
Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled
Bit 17: DMA enable.
Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled
Bit 19: No divider.
Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.
Bits 20-23: Master clock divider.
AConfiguration register 2
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
6/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMP
rw |
CPL
rw |
MUTECNT
rw |
MUTEVAL
rw |
MUTE
rw |
TRIS
rw |
FFLUSH
w |
FTH
rw |
Bits 0-2: FIFO threshold.
Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full
Bit 3: FIFO flush.
Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
Bit 4: Tristate management on data line.
Bit 5: Mute.
Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled
Bit 6: Mute value.
Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode
Bits 7-12: Mute counter.
Bit 13: Complement bit.
Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation
Bits 14-15: Companding mode.
Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm
AFRCR
Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FSOFF
rw |
FSPOL
rw |
FSDEF
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSALL
rw |
FRL
rw |
Bits 0-7: Frame length.
Bits 8-14: Frame synchronization active level length.
Bit 16: Frame synchronization definition.
Bit 17: Frame synchronization polarity.
Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)
Bit 18: Frame synchronization offset.
Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0
ASlot register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SLOTEN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NBSLOT
rw |
SLOTSZ
rw |
FBOFF
rw |
Bits 0-4: First bit offset.
Bits 6-7: Slot size.
Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit
Bits 8-11: Number of slots in an audio frame.
Bits 16-31: Slot enable.
Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot
AInterrupt mask register2
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LFSDETIE
rw |
AFSDETIE
rw |
CNRDYIE
rw |
FREQIE
rw |
WCKCFGIE
rw |
MUTEDETIE
rw |
OVRUDRIE
rw |
Bit 0: Overrun/underrun interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 1: Mute detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 2: Wrong clock configuration interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 3: FIFO request interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 4: Codec not ready interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 5: Anticipated frame synchronization detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 6: Late frame synchronization detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
AStatus register
Offset: 0x38, size: 32, reset: 0x00000008, access: read-only
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LFSDET
r |
AFSDET
r |
CNRDY
r |
FREQ
r |
WCKCFG
r |
MUTEDET
r |
OVRUDR
r |
Bit 0: Overrun / underrun.
Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection
Bit 1: Mute detection.
Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
Bit 2: Wrong clock configuration flag. This bit is read only.
Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification
Bit 3: FIFO request.
Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR
Bit 4: Codec not ready.
Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready
Bit 5: Anticipated frame synchronization detection.
Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected
Bit 6: Late frame synchronization detection.
Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time
Bits 16-18: FIFO level threshold.
Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full
AClear flag register
Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Clear overrun / underrun.
Allowed values:
1: Clear: Clears the OVRUDR flag
Bit 1: Mute detection flag.
Allowed values:
1: Clear: Clears the MUTEDET flag
Bit 2: Clear wrong clock configuration flag.
Allowed values:
1: Clear: Clears the WCKCFG flag
Bit 4: Clear codec not ready flag.
Allowed values:
1: Clear: Clears the CNRDY flag
Bit 5: Clear anticipated frame synchronization detection flag.
Allowed values:
1: Clear: Clears the AFSDET flag
Bit 6: Clear late frame synchronization detection flag.
Allowed values:
1: Clear: Clears the LFSDET flag
0x40015800: Serial audio interface
84/102 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x4 | CR1 [A] | ||||||||||||||||||||||||||||||||
0x8 | CR2 [A] | ||||||||||||||||||||||||||||||||
0xc | FRCR [A] | ||||||||||||||||||||||||||||||||
0x10 | SLOTR [A] | ||||||||||||||||||||||||||||||||
0x14 | IM [A] | ||||||||||||||||||||||||||||||||
0x18 | SR [A] | ||||||||||||||||||||||||||||||||
0x1c | CLRFR [A] | ||||||||||||||||||||||||||||||||
0x20 | DR [A] | ||||||||||||||||||||||||||||||||
0x24 | CR1 [B] | ||||||||||||||||||||||||||||||||
0x28 | CR2 [B] | ||||||||||||||||||||||||||||||||
0x2c | FRCR [B] | ||||||||||||||||||||||||||||||||
0x30 | SLOTR [B] | ||||||||||||||||||||||||||||||||
0x34 | IM [B] | ||||||||||||||||||||||||||||||||
0x38 | SR [B] | ||||||||||||||||||||||||||||||||
0x3c | CLRFR [B] | ||||||||||||||||||||||||||||||||
0x40 | DR [B] |
AConfiguration register 1
Offset: 0x4, size: 32, reset: 0x00000040, access: read-write
11/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MCKDIV
rw |
NODIV
rw |
DMAEN
rw |
SAIEN
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUTDRIV
rw |
MONO
rw |
SYNCEN
rw |
CKSTR
rw |
LSBFIRST
rw |
DS
rw |
PRTCFG
rw |
MODE
rw |
Bits 0-1: Audio block mode.
Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver
Bits 2-3: Protocol configuration.
Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol
Bits 5-7: Data size.
Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits
Bit 8: Least significant bit first.
Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first
Bit 9: Clock strobing edge.
Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK
Bits 10-11: Synchronization enable.
Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
Bit 12: Mono mode.
Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode
Bit 13: Output drive.
Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit
Bit 16: Audio block A enable.
Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled
Bit 17: DMA enable.
Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled
Bit 19: No divider.
Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.
Bits 20-23: Master clock divider.
AConfiguration register 2
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
6/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMP
rw |
CPL
rw |
MUTECNT
rw |
MUTEVAL
rw |
MUTE
rw |
TRIS
rw |
FFLUSH
w |
FTH
rw |
Bits 0-2: FIFO threshold.
Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full
Bit 3: FIFO flush.
Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
Bit 4: Tristate management on data line.
Bit 5: Mute.
Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled
Bit 6: Mute value.
Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode
Bits 7-12: Mute counter.
Bit 13: Complement bit.
Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation
Bits 14-15: Companding mode.
Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm
AFRCR
Offset: 0xc, size: 32, reset: 0x00000007, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FSOFF
rw |
FSPOL
rw |
FSDEF
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSALL
rw |
FRL
rw |
Bits 0-7: Frame length.
Bits 8-14: Frame synchronization active level length.
Bit 16: Frame synchronization definition.
Bit 17: Frame synchronization polarity.
Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)
Bit 18: Frame synchronization offset.
Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0
ASlot register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SLOTEN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NBSLOT
rw |
SLOTSZ
rw |
FBOFF
rw |
Bits 0-4: First bit offset.
Bits 6-7: Slot size.
Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit
Bits 8-11: Number of slots in an audio frame.
Bits 16-31: Slot enable.
Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot
AInterrupt mask register2
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LFSDETIE
rw |
AFSDETIE
rw |
CNRDYIE
rw |
FREQIE
rw |
WCKCFGIE
rw |
MUTEDETIE
rw |
OVRUDRIE
rw |
Bit 0: Overrun/underrun interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 1: Mute detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 2: Wrong clock configuration interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 3: FIFO request interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 4: Codec not ready interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 5: Anticipated frame synchronization detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 6: Late frame synchronization detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
AStatus register
Offset: 0x18, size: 32, reset: 0x00000008, access: read-only
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LFSDET
r |
AFSDET
r |
CNRDY
r |
FREQ
r |
WCKCFG
r |
MUTEDET
r |
OVRUDR
r |
Bit 0: Overrun / underrun.
Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection
Bit 1: Mute detection.
Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
Bit 2: Wrong clock configuration flag. This bit is read only.
Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification
Bit 3: FIFO request.
Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR
Bit 4: Codec not ready.
Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready
Bit 5: Anticipated frame synchronization detection.
Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected
Bit 6: Late frame synchronization detection.
Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time
Bits 16-18: FIFO level threshold.
Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full
AClear flag register
Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Clear overrun / underrun.
Allowed values:
1: Clear: Clears the OVRUDR flag
Bit 1: Mute detection flag.
Allowed values:
1: Clear: Clears the MUTEDET flag
Bit 2: Clear wrong clock configuration flag.
Allowed values:
1: Clear: Clears the WCKCFG flag
Bit 4: Clear codec not ready flag.
Allowed values:
1: Clear: Clears the CNRDY flag
Bit 5: Clear anticipated frame synchronization detection flag.
Allowed values:
1: Clear: Clears the AFSDET flag
Bit 6: Clear late frame synchronization detection flag.
Allowed values:
1: Clear: Clears the LFSDET flag
AData register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
AConfiguration register 1
Offset: 0x24, size: 32, reset: 0x00000040, access: read-write
11/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MCKDIV
rw |
NODIV
rw |
DMAEN
rw |
SAIEN
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUTDRIV
rw |
MONO
rw |
SYNCEN
rw |
CKSTR
rw |
LSBFIRST
rw |
DS
rw |
PRTCFG
rw |
MODE
rw |
Bits 0-1: Audio block mode.
Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver
Bits 2-3: Protocol configuration.
Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol
Bits 5-7: Data size.
Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits
Bit 8: Least significant bit first.
Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first
Bit 9: Clock strobing edge.
Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK
Bits 10-11: Synchronization enable.
Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode
Bit 12: Mono mode.
Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode
Bit 13: Output drive.
Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit
Bit 16: Audio block A enable.
Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled
Bit 17: DMA enable.
Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled
Bit 19: No divider.
Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.
Bits 20-23: Master clock divider.
AConfiguration register 2
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
6/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMP
rw |
CPL
rw |
MUTECNT
rw |
MUTEVAL
rw |
MUTE
rw |
TRIS
rw |
FFLUSH
w |
FTH
rw |
Bits 0-2: FIFO threshold.
Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full
Bit 3: FIFO flush.
Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared
Bit 4: Tristate management on data line.
Bit 5: Mute.
Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled
Bit 6: Mute value.
Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode
Bits 7-12: Mute counter.
Bit 13: Complement bit.
Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation
Bits 14-15: Companding mode.
Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm
AFRCR
Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write
2/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FSOFF
rw |
FSPOL
rw |
FSDEF
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FSALL
rw |
FRL
rw |
Bits 0-7: Frame length.
Bits 8-14: Frame synchronization active level length.
Bit 16: Frame synchronization definition.
Bit 17: Frame synchronization polarity.
Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)
Bit 18: Frame synchronization offset.
Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0
ASlot register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-write
2/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SLOTEN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NBSLOT
rw |
SLOTSZ
rw |
FBOFF
rw |
Bits 0-4: First bit offset.
Bits 6-7: Slot size.
Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit
Bits 8-11: Number of slots in an audio frame.
Bits 16-31: Slot enable.
Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot
AInterrupt mask register2
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
7/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LFSDETIE
rw |
AFSDETIE
rw |
CNRDYIE
rw |
FREQIE
rw |
WCKCFGIE
rw |
MUTEDETIE
rw |
OVRUDRIE
rw |
Bit 0: Overrun/underrun interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 1: Mute detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 2: Wrong clock configuration interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 3: FIFO request interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 4: Codec not ready interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 5: Anticipated frame synchronization detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
Bit 6: Late frame synchronization detection interrupt enable.
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled
AStatus register
Offset: 0x38, size: 32, reset: 0x00000008, access: read-only
8/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FLVL
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LFSDET
r |
AFSDET
r |
CNRDY
r |
FREQ
r |
WCKCFG
r |
MUTEDET
r |
OVRUDR
r |
Bit 0: Overrun / underrun.
Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection
Bit 1: Mute detection.
Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame
Bit 2: Wrong clock configuration flag. This bit is read only.
Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification
Bit 3: FIFO request.
Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR
Bit 4: Codec not ready.
Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready
Bit 5: Anticipated frame synchronization detection.
Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected
Bit 6: Late frame synchronization detection.
Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time
Bits 16-18: FIFO level threshold.
Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full
AClear flag register
Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only
6/6 fields covered.
Bit 0: Clear overrun / underrun.
Allowed values:
1: Clear: Clears the OVRUDR flag
Bit 1: Mute detection flag.
Allowed values:
1: Clear: Clears the MUTEDET flag
Bit 2: Clear wrong clock configuration flag.
Allowed values:
1: Clear: Clears the WCKCFG flag
Bit 4: Clear codec not ready flag.
Allowed values:
1: Clear: Clears the CNRDY flag
Bit 5: Clear anticipated frame synchronization detection flag.
Allowed values:
1: Clear: Clears the AFSDET flag
Bit 6: Clear late frame synchronization detection flag.
Allowed values:
1: Clear: Clears the LFSDET flag
0xe000ed00: System control block
5/74 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CPUID | ||||||||||||||||||||||||||||||||
0x4 | ICSR | ||||||||||||||||||||||||||||||||
0x8 | VTOR | ||||||||||||||||||||||||||||||||
0xc | AIRCR | ||||||||||||||||||||||||||||||||
0x10 | SCR | ||||||||||||||||||||||||||||||||
0x14 | CCR | ||||||||||||||||||||||||||||||||
0x18 | SHPR1 | ||||||||||||||||||||||||||||||||
0x1c | SHPR2 | ||||||||||||||||||||||||||||||||
0x20 | SHPR3 | ||||||||||||||||||||||||||||||||
0x24 | SHCSR | ||||||||||||||||||||||||||||||||
0x28 | CFSR_UFSR_BFSR_MMFSR | ||||||||||||||||||||||||||||||||
0x2c | HFSR | ||||||||||||||||||||||||||||||||
0x34 | MMFAR | ||||||||||||||||||||||||||||||||
0x38 | BFAR | ||||||||||||||||||||||||||||||||
0x3c | AFSR |
CPUID base register
Offset: 0x0, size: 32, reset: 0x410FC241, access: read-only
5/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Implementer
r |
Variant
r |
Constant
r |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PartNo
r |
Revision
r |
Interrupt control and state register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NMIPENDSET
rw |
PENDSVSET
rw |
PENDSVCLR
rw |
PENDSTSET
rw |
PENDSTCLR
rw |
ISRPENDING
rw |
VECTPENDING
rw |
|||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECTPENDING
rw |
RETTOBASE
rw |
VECTACTIVE
rw |
Bits 0-8: Active vector.
Bit 11: Return to base level.
Bits 12-18: Pending vector.
Bit 22: Interrupt pending flag.
Bit 25: SysTick exception clear-pending bit.
Bit 26: SysTick exception set-pending bit.
Bit 27: PendSV clear-pending bit.
Bit 28: PendSV set-pending bit.
Bit 31: NMI set-pending bit..
Vector table offset register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
Application interrupt and reset control register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VECTKEYSTAT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENDIANESS
rw |
PRIGROUP
rw |
SYSRESETREQ
rw |
VECTCLRACTIVE
rw |
VECTRESET
rw |
System control register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SEVEONPEND
rw |
SLEEPDEEP
rw |
SLEEPONEXIT
rw |
Configuration and control register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/6 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STKALIGN
rw |
BFHFNMIGN
rw |
DIV_0_TRP
rw |
UNALIGN__TRP
rw |
USERSETMPEND
rw |
NONBASETHRDENA
rw |
System handler priority registers
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
System handler priority registers
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRI_11
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
System handler priority registers
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
System handler control and state register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/14 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
USGFAULTENA
rw |
BUSFAULTENA
rw |
MEMFAULTENA
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SVCALLPENDED
rw |
BUSFAULTPENDED
rw |
MEMFAULTPENDED
rw |
USGFAULTPENDED
rw |
SYSTICKACT
rw |
PENDSVACT
rw |
MONITORACT
rw |
SVCALLACT
rw |
USGFAULTACT
rw |
BUSFAULTACT
rw |
MEMFAULTACT
rw |
Bit 0: Memory management fault exception active bit.
Bit 1: Bus fault exception active bit.
Bit 3: Usage fault exception active bit.
Bit 7: SVC call active bit.
Bit 8: Debug monitor active bit.
Bit 10: PendSV exception active bit.
Bit 11: SysTick exception active bit.
Bit 12: Usage fault exception pending bit.
Bit 13: Memory management fault exception pending bit.
Bit 14: Bus fault exception pending bit.
Bit 15: SVC call pending bit.
Bit 16: Memory management fault enable bit.
Bit 17: Bus fault enable bit.
Bit 18: Usage fault enable bit.
Configurable fault status register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/18 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DIVBYZERO
rw |
UNALIGNED
rw |
NOCP
rw |
INVPC
rw |
INVSTATE
rw |
UNDEFINSTR
rw |
||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BFARVALID
rw |
LSPERR
rw |
STKERR
rw |
UNSTKERR
rw |
IMPRECISERR
rw |
PRECISERR
rw |
IBUSERR
rw |
MMARVALID
rw |
MLSPERR
rw |
MSTKERR
rw |
MUNSTKERR
rw |
IACCVIOL
rw |
Bit 1: Instruction access violation flag.
Bit 3: Memory manager fault on unstacking for a return from exception.
Bit 4: Memory manager fault on stacking for exception entry..
Bit 5: MLSPERR.
Bit 7: Memory Management Fault Address Register (MMAR) valid flag.
Bit 8: Instruction bus error.
Bit 9: Precise data bus error.
Bit 10: Imprecise data bus error.
Bit 11: Bus fault on unstacking for a return from exception.
Bit 12: Bus fault on stacking for exception entry.
Bit 13: Bus fault on floating-point lazy state preservation.
Bit 15: Bus Fault Address Register (BFAR) valid flag.
Bit 16: Undefined instruction usage fault.
Bit 17: Invalid state usage fault.
Bit 18: Invalid PC load usage fault.
Bit 19: No coprocessor usage fault..
Bit 24: Unaligned access usage fault.
Bit 25: Divide by zero usage fault.
Hard fault status register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
Memory management fault address register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
0xe000e008: System control block ACTLR
0/5 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | ACTRL |
Auxiliary control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/5 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DISOOFP
rw |
DISFPCA
rw |
DISFOLD
rw |
DISDEFWBUF
rw |
DISMCYCINT
rw |
0x50062400: Secure digital input/output interface
31/98 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | POWER | ||||||||||||||||||||||||||||||||
0x4 | CLKCR | ||||||||||||||||||||||||||||||||
0x8 | ARG | ||||||||||||||||||||||||||||||||
0xc | CMD | ||||||||||||||||||||||||||||||||
0x10 | RESPCMD | ||||||||||||||||||||||||||||||||
0x14 | RESP1 | ||||||||||||||||||||||||||||||||
0x18 | RESP2 | ||||||||||||||||||||||||||||||||
0x1c | RESP3 | ||||||||||||||||||||||||||||||||
0x20 | RESP4 | ||||||||||||||||||||||||||||||||
0x24 | DTIMER | ||||||||||||||||||||||||||||||||
0x28 | DLEN | ||||||||||||||||||||||||||||||||
0x2c | DCTRL | ||||||||||||||||||||||||||||||||
0x30 | DCOUNT | ||||||||||||||||||||||||||||||||
0x34 | STA | ||||||||||||||||||||||||||||||||
0x38 | ICR | ||||||||||||||||||||||||||||||||
0x3c | MASK | ||||||||||||||||||||||||||||||||
0x48 | FIFOCNT | ||||||||||||||||||||||||||||||||
0x80 | FIFO |
power control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PWRCTRL
rw |
SDI clock control register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HWFC_EN
rw |
NEGEDGE
rw |
WIDBUS
rw |
BYPASS
rw |
PWRSAV
rw |
CLKEN
rw |
CLKDIV
rw |
Bits 0-7: Clock divide factor.
Bit 8: Clock enable bit.
Bit 9: Power saving configuration bit.
Bit 10: Clock divider bypass enable bit.
Bits 11-12: Wide bus mode enable bit.
Bit 13: SDIO_CK dephasing selection bit.
Bit 14: HW Flow Control enable.
argument register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
command register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CE_ATACMD
rw |
nIEN
rw |
ENCMDcompl
rw |
SDIOSuspend
rw |
CPSMEN
rw |
WAITPEND
rw |
WAITINT
rw |
WAITRESP
rw |
CMDINDEX
rw |
Bits 0-5: Command index.
Bits 6-7: Wait for response bits.
Bit 8: CPSM waits for interrupt request.
Bit 9: CPSM Waits for ends of data transfer (CmdPend internal signal).
Bit 10: Command path state machine (CPSM) Enable bit.
Bit 11: SD I/O suspend command.
Bit 12: Enable CMD completion.
Bit 13: not Interrupt Enable.
Bit 14: CE-ATA command.
command response register
Offset: 0x10, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESPCMD
r |
response 1..4 register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CARDSTATUS1
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CARDSTATUS1
r |
response 1..4 register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CARDSTATUS2
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CARDSTATUS2
r |
response 1..4 register
Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CARDSTATUS3
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CARDSTATUS3
r |
response 1..4 register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CARDSTATUS4
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CARDSTATUS4
r |
data timer register
Offset: 0x24, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
data length register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATALENGTH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATALENGTH
rw |
data control register
Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SDIOEN
rw |
RWMOD
rw |
RWSTOP
rw |
RWSTART
rw |
DBLOCKSIZE
rw |
DMAEN
rw |
DTMODE
rw |
DTDIR
rw |
DTEN
rw |
Bit 0: DTEN.
Bit 1: Data transfer direction selection.
Bit 2: Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
Bit 3: DMA enable bit.
Bits 4-7: Data block size.
Bit 8: Read wait start.
Bit 9: Read wait stop.
Bit 10: Read wait mode.
Bit 11: SD I/O enable functions.
data counter register
Offset: 0x30, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
status register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-only
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CEATAEND
r |
SDIOIT
r |
RXDAVL
r |
TXDAVL
r |
RXFIFOE
r |
TXFIFOE
r |
RXFIFOF
r |
TXFIFOF
r |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXFIFOHF
r |
TXFIFOHE
r |
RXACT
r |
TXACT
r |
CMDACT
r |
DBCKEND
r |
STBITERR
r |
DATAEND
r |
CMDSENT
r |
CMDREND
r |
RXOVERR
r |
TXUNDERR
r |
DTIMEOUT
r |
CTIMEOUT
r |
DCRCFAIL
r |
CCRCFAIL
r |
Bit 0: Command response received (CRC check failed).
Bit 1: Data block sent/received (CRC check failed).
Bit 2: Command response timeout.
Bit 3: Data timeout.
Bit 4: Transmit FIFO underrun error.
Bit 5: Received FIFO overrun error.
Bit 6: Command response received (CRC check passed).
Bit 7: Command sent (no response required).
Bit 8: Data end (data counter, SDIDCOUNT, is zero).
Bit 9: Start bit not detected on all data signals in wide bus mode.
Bit 10: Data block sent/received (CRC check passed).
Bit 11: Command transfer in progress.
Bit 12: Data transmit in progress.
Bit 13: Data receive in progress.
Bit 14: Transmit FIFO half empty: at least 8 words can be written into the FIFO.
Bit 15: Receive FIFO half full: there are at least 8 words in the FIFO.
Bit 16: Transmit FIFO full.
Bit 17: Receive FIFO full.
Bit 18: Transmit FIFO empty.
Bit 19: Receive FIFO empty.
Bit 20: Data available in transmit FIFO.
Bit 21: Data available in receive FIFO.
Bit 22: SDIO interrupt received.
Bit 23: CE-ATA command completion signal received for CMD61.
interrupt clear register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-write
0/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CEATAENDC
rw |
SDIOITC
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBCKENDC
rw |
STBITERRC
rw |
DATAENDC
rw |
CMDSENTC
rw |
CMDRENDC
rw |
RXOVERRC
rw |
TXUNDERRC
rw |
DTIMEOUTC
rw |
CTIMEOUTC
rw |
DCRCFAILC
rw |
CCRCFAILC
rw |
Bit 0: CCRCFAIL flag clear bit.
Bit 1: DCRCFAIL flag clear bit.
Bit 2: CTIMEOUT flag clear bit.
Bit 3: DTIMEOUT flag clear bit.
Bit 4: TXUNDERR flag clear bit.
Bit 5: RXOVERR flag clear bit.
Bit 6: CMDREND flag clear bit.
Bit 7: CMDSENT flag clear bit.
Bit 8: DATAEND flag clear bit.
Bit 9: STBITERR flag clear bit.
Bit 10: DBCKEND flag clear bit.
Bit 22: SDIOIT flag clear bit.
Bit 23: CEATAEND flag clear bit.
mask register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write
0/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CEATAENDIE
rw |
SDIOITIE
rw |
RXDAVLIE
rw |
TXDAVLIE
rw |
RXFIFOEIE
rw |
TXFIFOEIE
rw |
RXFIFOFIE
rw |
TXFIFOFIE
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXFIFOHFIE
rw |
TXFIFOHEIE
rw |
RXACTIE
rw |
TXACTIE
rw |
CMDACTIE
rw |
DBCKENDIE
rw |
STBITERRIE
rw |
DATAENDIE
rw |
CMDSENTIE
rw |
CMDRENDIE
rw |
RXOVERRIE
rw |
TXUNDERRIE
rw |
DTIMEOUTIE
rw |
CTIMEOUTIE
rw |
DCRCFAILIE
rw |
CCRCFAILIE
rw |
Bit 0: Command CRC fail interrupt enable.
Bit 1: Data CRC fail interrupt enable.
Bit 2: Command timeout interrupt enable.
Bit 3: Data timeout interrupt enable.
Bit 4: Tx FIFO underrun error interrupt enable.
Bit 5: Rx FIFO overrun error interrupt enable.
Bit 6: Command response received interrupt enable.
Bit 7: Command sent interrupt enable.
Bit 8: Data end interrupt enable.
Bit 9: Start bit error interrupt enable.
Bit 10: Data block end interrupt enable.
Bit 11: Command acting interrupt enable.
Bit 12: Data transmit acting interrupt enable.
Bit 13: Data receive acting interrupt enable.
Bit 14: Tx FIFO half empty interrupt enable.
Bit 15: Rx FIFO half full interrupt enable.
Bit 16: Tx FIFO full interrupt enable.
Bit 17: Rx FIFO full interrupt enable.
Bit 18: Tx FIFO empty interrupt enable.
Bit 19: Rx FIFO empty interrupt enable.
Bit 20: Data available in Tx FIFO interrupt enable.
Bit 21: Data available in Rx FIFO interrupt enable.
Bit 22: SDIO mode interrupt received interrupt enable.
Bit 23: CE-ATA command completion signal received interrupt enable.
0x40013000: Serial peripheral interface/Inter-IC sound
40/40 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0x8 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DR | ||||||||||||||||||||||||||||||||
0xc (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | CRCPR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | RXCRCR | ||||||||||||||||||||||||||||||||
0x18 (16-bit) | TXCRCR |
control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: read-write
14/14 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BIDIMODE
rw |
BIDIOE
rw |
CRCEN
rw |
CRCNEXT
rw |
CRCL
rw |
RXONLY
rw |
SSM
rw |
SSI
rw |
LSBFIRST
rw |
SPE
rw |
BR
rw |
MSTR
rw |
CPOL
rw |
CPHA
rw |
Bit 0: Clock phase.
Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge
Bit 1: Clock polarity.
Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle
Bit 2: Master selection.
Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration
Bits 3-5: Baud rate control.
Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256
Bit 6: SPI enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 7: Frame format.
Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first
Bit 8: Internal slave select.
Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
Bit 9: Software slave management.
Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled
Bit 10: Receive only.
Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)
Bit 11: CRC length.
Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length
Bit 12: CRC transfer next.
Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register
Bit 13: Hardware CRC calculation enable.
Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled
Bit 14: Output enable in bidirectional mode.
Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable.
Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected
control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDMA_TX
rw |
LDMA_RX
rw |
FRXTH
rw |
DS
rw |
TXEIE
rw |
RXNEIE
rw |
ERRIE
rw |
FRF
rw |
NSSP
rw |
SSOE
rw |
TXDMAEN
rw |
RXDMAEN
rw |
Bit 0: Rx buffer DMA enable.
Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled
Bit 1: Tx buffer DMA enable.
Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled
Bit 2: SS output enable.
Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode
Bit 3: NSS pulse management.
Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated
Bit 4: Frame format.
Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode
Bit 5: Error interrupt enable.
Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked
Bit 6: RX buffer not empty interrupt enable.
Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked
Bit 7: Tx buffer empty interrupt enable.
Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked
Bits 8-11: Data size.
Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit
Bit 12: FIFO reception threshold.
Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception.
Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd
Bit 14: Last DMA transfer for transmission.
Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd
status register
Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FTLVL
r |
FRLVL
r |
FRE
r |
BSY
r |
OVR
r |
MODF
r |
CRCERR
r/w0c |
TXE
r |
RXNE
r |
Bit 0: Receive buffer not empty.
Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty
Bit 1: Transmit buffer empty.
Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty
Bit 4: CRC error flag.
Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value
Bit 5: Mode fault.
Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred
Bit 6: Overrun flag.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Busy flag.
Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy
Bit 8: Frame format error.
Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred
Bits 9-10: FIFO reception level.
Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full
Bits 11-12: FIFO transmission level.
Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full
data register
Offset: 0xc, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DR
rw |
Direct 8-bit access to data register
Offset: 0xc, size: 8, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DR
rw |
CRC polynomial register
Offset: 0x10, size: 16, reset: 0x00000007, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CRCPOLY
rw |
RX CRC register
Offset: 0x14, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RxCRC
r |
TX CRC register
Offset: 0x18, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TxCRC
r |
0x40003800: Serial peripheral interface/Inter-IC sound
40/40 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0x8 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DR | ||||||||||||||||||||||||||||||||
0xc (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | CRCPR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | RXCRCR | ||||||||||||||||||||||||||||||||
0x18 (16-bit) | TXCRCR |
control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: read-write
14/14 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BIDIMODE
rw |
BIDIOE
rw |
CRCEN
rw |
CRCNEXT
rw |
CRCL
rw |
RXONLY
rw |
SSM
rw |
SSI
rw |
LSBFIRST
rw |
SPE
rw |
BR
rw |
MSTR
rw |
CPOL
rw |
CPHA
rw |
Bit 0: Clock phase.
Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge
Bit 1: Clock polarity.
Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle
Bit 2: Master selection.
Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration
Bits 3-5: Baud rate control.
Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256
Bit 6: SPI enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 7: Frame format.
Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first
Bit 8: Internal slave select.
Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
Bit 9: Software slave management.
Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled
Bit 10: Receive only.
Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)
Bit 11: CRC length.
Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length
Bit 12: CRC transfer next.
Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register
Bit 13: Hardware CRC calculation enable.
Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled
Bit 14: Output enable in bidirectional mode.
Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable.
Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected
control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDMA_TX
rw |
LDMA_RX
rw |
FRXTH
rw |
DS
rw |
TXEIE
rw |
RXNEIE
rw |
ERRIE
rw |
FRF
rw |
NSSP
rw |
SSOE
rw |
TXDMAEN
rw |
RXDMAEN
rw |
Bit 0: Rx buffer DMA enable.
Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled
Bit 1: Tx buffer DMA enable.
Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled
Bit 2: SS output enable.
Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode
Bit 3: NSS pulse management.
Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated
Bit 4: Frame format.
Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode
Bit 5: Error interrupt enable.
Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked
Bit 6: RX buffer not empty interrupt enable.
Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked
Bit 7: Tx buffer empty interrupt enable.
Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked
Bits 8-11: Data size.
Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit
Bit 12: FIFO reception threshold.
Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception.
Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd
Bit 14: Last DMA transfer for transmission.
Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd
status register
Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FTLVL
r |
FRLVL
r |
FRE
r |
BSY
r |
OVR
r |
MODF
r |
CRCERR
r/w0c |
TXE
r |
RXNE
r |
Bit 0: Receive buffer not empty.
Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty
Bit 1: Transmit buffer empty.
Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty
Bit 4: CRC error flag.
Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value
Bit 5: Mode fault.
Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred
Bit 6: Overrun flag.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Busy flag.
Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy
Bit 8: Frame format error.
Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred
Bits 9-10: FIFO reception level.
Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full
Bits 11-12: FIFO transmission level.
Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full
data register
Offset: 0xc, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DR
rw |
Direct 8-bit access to data register
Offset: 0xc, size: 8, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DR
rw |
CRC polynomial register
Offset: 0x10, size: 16, reset: 0x00000007, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CRCPOLY
rw |
RX CRC register
Offset: 0x14, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RxCRC
r |
TX CRC register
Offset: 0x18, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TxCRC
r |
0x40003c00: Serial peripheral interface/Inter-IC sound
40/40 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0x8 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DR | ||||||||||||||||||||||||||||||||
0xc (8-bit) | DR8 | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | CRCPR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | RXCRCR | ||||||||||||||||||||||||||||||||
0x18 (16-bit) | TXCRCR |
control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: read-write
14/14 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BIDIMODE
rw |
BIDIOE
rw |
CRCEN
rw |
CRCNEXT
rw |
CRCL
rw |
RXONLY
rw |
SSM
rw |
SSI
rw |
LSBFIRST
rw |
SPE
rw |
BR
rw |
MSTR
rw |
CPOL
rw |
CPHA
rw |
Bit 0: Clock phase.
Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge
Bit 1: Clock polarity.
Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle
Bit 2: Master selection.
Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration
Bits 3-5: Baud rate control.
Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256
Bit 6: SPI enable.
Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled
Bit 7: Frame format.
Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first
Bit 8: Internal slave select.
Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
Bit 9: Software slave management.
Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled
Bit 10: Receive only.
Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)
Bit 11: CRC length.
Allowed values:
0: EightBit: 8-bit CRC length
1: SixteenBit: 16-bit CRC length
Bit 12: CRC transfer next.
Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register
Bit 13: Hardware CRC calculation enable.
Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled
Bit 14: Output enable in bidirectional mode.
Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable.
Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected
control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: read-write
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
LDMA_TX
rw |
LDMA_RX
rw |
FRXTH
rw |
DS
rw |
TXEIE
rw |
RXNEIE
rw |
ERRIE
rw |
FRF
rw |
NSSP
rw |
SSOE
rw |
TXDMAEN
rw |
RXDMAEN
rw |
Bit 0: Rx buffer DMA enable.
Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled
Bit 1: Tx buffer DMA enable.
Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled
Bit 2: SS output enable.
Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode
Bit 3: NSS pulse management.
Allowed values:
0: NoPulse: No NSS pulse
1: PulseGenerated: NSS pulse generated
Bit 4: Frame format.
Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode
Bit 5: Error interrupt enable.
Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked
Bit 6: RX buffer not empty interrupt enable.
Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked
Bit 7: Tx buffer empty interrupt enable.
Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked
Bits 8-11: Data size.
Allowed values:
3: FourBit: 4-bit
4: FiveBit: 5-bit
5: SixBit: 6-bit
6: SevenBit: 7-bit
7: EightBit: 8-bit
8: NineBit: 9-bit
9: TenBit: 10-bit
10: ElevenBit: 11-bit
11: TwelveBit: 12-bit
12: ThirteenBit: 13-bit
13: FourteenBit: 14-bit
14: FifteenBit: 15-bit
15: SixteenBit: 16-bit
Bit 12: FIFO reception threshold.
Allowed values:
0: Half: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
1: Quarter: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception.
Allowed values:
0: Even: Number of data to transfer for receive is even
1: Odd: Number of data to transfer for receive is odd
Bit 14: Last DMA transfer for transmission.
Allowed values:
0: Even: Number of data to transfer for transmit is even
1: Odd: Number of data to transfer for transmit is odd
status register
Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FTLVL
r |
FRLVL
r |
FRE
r |
BSY
r |
OVR
r |
MODF
r |
CRCERR
r/w0c |
TXE
r |
RXNE
r |
Bit 0: Receive buffer not empty.
Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty
Bit 1: Transmit buffer empty.
Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty
Bit 4: CRC error flag.
Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value
Bit 5: Mode fault.
Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred
Bit 6: Overrun flag.
Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred
Bit 7: Busy flag.
Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy
Bit 8: Frame format error.
Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred
Bits 9-10: FIFO reception level.
Allowed values:
0: Empty: Rx FIFO Empty
1: Quarter: Rx 1/4 FIFO
2: Half: Rx 1/2 FIFO
3: Full: Rx FIFO full
Bits 11-12: FIFO transmission level.
Allowed values:
0: Empty: Tx FIFO Empty
1: Quarter: Tx 1/4 FIFO
2: Half: Tx 1/2 FIFO
3: Full: Tx FIFO full
data register
Offset: 0xc, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DR
rw |
Direct 8-bit access to data register
Offset: 0xc, size: 8, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DR
rw |
CRC polynomial register
Offset: 0x10, size: 16, reset: 0x00000007, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CRCPOLY
rw |
RX CRC register
Offset: 0x14, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RxCRC
r |
TX CRC register
Offset: 0x18, size: 16, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TxCRC
r |
0xe000e010: SysTick timer
0/9 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CTRL | ||||||||||||||||||||||||||||||||
0x4 | LOAD | ||||||||||||||||||||||||||||||||
0x8 | VAL | ||||||||||||||||||||||||||||||||
0xc | CALIB |
SysTick control and status register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
SysTick reload value register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
SysTick current value register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
0x40008800: Single Wire Protocol Master Interface
13/38 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | BRR | ||||||||||||||||||||||||||||||||
0xc | ISR | ||||||||||||||||||||||||||||||||
0x10 | ICR | ||||||||||||||||||||||||||||||||
0x14 | IER | ||||||||||||||||||||||||||||||||
0x18 | RFL | ||||||||||||||||||||||||||||||||
0x1c | TDR | ||||||||||||||||||||||||||||||||
0x20 | RDR |
SWPMI Configuration/Control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEACT
rw |
SWPME
rw |
LPBK
rw |
TXMODE
rw |
RXMODE
rw |
TXDMA
rw |
RXDMA
rw |
Bit 0: Reception DMA enable.
Bit 1: Transmission DMA enable.
Bit 2: Reception buffering mode.
Bit 3: Transmission buffering mode.
Bit 4: Loopback mode enable.
Bit 5: Single wire protocol master interface enable.
Bit 10: Single wire protocol master interface deactivate.
SWPMI Bitrate register
Offset: 0x4, size: 32, reset: 0x00000001, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BR
rw |
SWPMI Interrupt and Status register
Offset: 0xc, size: 32, reset: 0x000002C2, access: read-only
11/11 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEACTF
r |
SUSP
r |
SRF
r |
TCF
r |
TXE
r |
RXNE
r |
TXUNRF
r |
RXOVRF
r |
RXBERF
r |
TXBEF
r |
RXBFF
r |
Bit 0: Receive buffer full flag.
Bit 1: Transmit buffer empty flag.
Bit 2: Receive CRC error flag.
Bit 3: Receive overrun error flag.
Bit 4: Transmit underrun error flag.
Bit 5: Receive data register not empty.
Bit 6: Transmit data register empty.
Bit 7: Transfer complete flag.
Bit 8: Slave resume flag.
Bit 9: SUSPEND flag.
Bit 10: DEACTIVATED flag.
SWPMI Interrupt Flag Clear register
Offset: 0x10, size: 32, reset: 0x00000000, access: write-only
0/7 fields covered.
Bit 0: Clear receive buffer full flag.
Bit 1: Clear transmit buffer empty flag.
Bit 2: Clear receive CRC error flag.
Bit 3: Clear receive overrun error flag.
Bit 4: Clear transmit underrun error flag.
Bit 7: Clear transfer complete flag.
Bit 8: Clear slave resume flag.
SWPMI Interrupt Enable register
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SRIE
rw |
TCIE
rw |
TIE
rw |
RIE
rw |
TXUNRIE
rw |
RXOVRIE
rw |
RXBERIE
rw |
TXBEIE
rw |
RXBFIE
rw |
Bit 0: Receive buffer full interrupt enable.
Bit 1: Transmit buffer empty interrupt enable.
Bit 2: Receive CRC error interrupt enable.
Bit 3: Receive overrun error interrupt enable.
Bit 4: Transmit underrun error interrupt enable.
Bit 5: Receive interrupt enable.
Bit 6: Transmit interrupt enable.
Bit 7: Transmit complete interrupt enable.
Bit 8: Slave resume interrupt enable.
SWPMI Receive Frame Length register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RFL
r |
0x40010000: System configuration controller
1/69 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | MEMRMP | ||||||||||||||||||||||||||||||||
0x4 | CFGR1 | ||||||||||||||||||||||||||||||||
0x8 | EXTICR1 | ||||||||||||||||||||||||||||||||
0xc | EXTICR2 | ||||||||||||||||||||||||||||||||
0x10 | EXTICR3 | ||||||||||||||||||||||||||||||||
0x14 | EXTICR4 | ||||||||||||||||||||||||||||||||
0x18 | SCSR | ||||||||||||||||||||||||||||||||
0x1c | CFGR2 | ||||||||||||||||||||||||||||||||
0x20 | SWPR | ||||||||||||||||||||||||||||||||
0x24 | SKR |
memory remap register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/3 fields covered.
configuration register 1
Offset: 0x4, size: 32, reset: 0x7C000001, access: read-write
0/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FPU_IE
rw |
I2C3_FMP
rw |
I2C2_FMP
rw |
I2C1_FMP
rw |
I2C_PB9_FMP
rw |
I2C_PB8_FMP
rw |
I2C_PB7_FMP
rw |
I2C_PB6_FMP
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOOSTEN
rw |
FWDIS
rw |
Bit 0: Firewall disable.
Bit 8: I/O analog switch voltage booster enable.
Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.
Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.
Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.
Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.
Bit 20: I2C1 Fast-mode Plus driving capability activation.
Bit 21: I2C2 Fast-mode Plus driving capability activation.
Bit 22: I2C3 Fast-mode Plus driving capability activation.
Bits 26-31: Floating Point Unit interrupts enable bits.
external interrupt configuration register 1
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
external interrupt configuration register 2
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
external interrupt configuration register 3
Offset: 0x10, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
external interrupt configuration register 4
Offset: 0x14, size: 32, reset: 0x00000000, access: read-write
0/4 fields covered.
SWPR
Offset: 0x20, size: 32, reset: 0x00000000, access: write-only
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
P31WP
w |
P30WP
w |
P29WP
w |
P28WP
w |
P27WP
w |
P26WP
w |
P25WP
w |
P24WP
w |
P23WP
w |
P22WP
w |
P21WP
w |
P20WP
w |
P19WP
w |
P18WP
w |
P17WP
w |
P16WP
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P15WP
w |
P14WP
w |
P13WP
w |
P12WP
w |
P11WP
w |
P10WP
w |
P9WP
w |
P8WP
w |
P7WP
w |
P6WP
w |
P5WP
w |
P4WP
w |
P3WP
w |
P2WP
w |
P1WP
w |
P0WP
w |
Bit 0: P0WP.
Bit 1: P1WP.
Bit 2: P2WP.
Bit 3: P3WP.
Bit 4: P4WP.
Bit 5: P5WP.
Bit 6: P6WP.
Bit 7: P7WP.
Bit 8: P8WP.
Bit 9: P9WP.
Bit 10: P10WP.
Bit 11: P11WP.
Bit 12: P12WP.
Bit 13: P13WP.
Bit 14: P14WP.
Bit 15: P15WP.
Bit 16: P16WP.
Bit 17: P17WP.
Bit 18: P18WP.
Bit 19: P19WP.
Bit 20: P20WP.
Bit 21: P21WP.
Bit 22: P22WP.
Bit 23: P23WP.
Bit 24: P24WP.
Bit 25: P25WP.
Bit 26: P26WP.
Bit 27: P27WP.
Bit 28: P28WP.
Bit 29: P29WP.
Bit 30: P30WP.
Bit 31: SRAM2 page 31 write protection.
SKR
Offset: 0x24, size: 32, reset: 0x00000000, access: write-only
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
w |
0x40012c00: Advanced-timers
157/186 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
0x20 | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c (16-bit) | ARR | ||||||||||||||||||||||||||||||||
0x30 (16-bit) | RCR | ||||||||||||||||||||||||||||||||
0x34 (16-bit) | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 (16-bit) | CCR[2] | ||||||||||||||||||||||||||||||||
0x3c (16-bit) | CCR[3] | ||||||||||||||||||||||||||||||||
0x40 (16-bit) | CCR[4] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c | DMAR | ||||||||||||||||||||||||||||||||
0x54 | CCMR3_Output | ||||||||||||||||||||||||||||||||
0x58 | CCR5 | ||||||||||||||||||||||||||||||||
0x5c (16-bit) | CCR6 | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x64 | AF2 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM1 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
8/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFREMAP
rw |
CKD
rw |
ARPE
rw |
CMS
rw |
DIR
rw |
OPM
rw |
URS
rw |
UDIS
rw |
CEN
rw |
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (ETR, TIx): Note: t<sub>DTS</sub> = 1/f<sub>DTS</sub>, t<sub>CK_INT</sub> = 1/f<sub>CK_INT</sub>..
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM1 control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
14/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MMS2
rw |
OIS[6]
rw |
OIS[5]
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIS[4]
rw |
OIS[3]N
rw |
OIS[3]
rw |
OIS[2]N
rw |
OIS[2]
rw |
OIS[1]N
rw |
OIS[1]
rw |
TI1S
rw |
MMS
rw |
CCDS
rw |
CCUS
rw |
CCPC
rw |
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
Bit 8: Output Idle state (OC1 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 9: Output Idle state (OC1N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 10: Output Idle state (OC2 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 11: Output Idle state (OC2N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 12: Output Idle state (OC3 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 13: Output Idle state (OC3N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 14: Output Idle state (OC4 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 16: Output Idle state (OC5 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 18: Output Idle state (OC6 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bits 20-23: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
TIM1 slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETP
rw |
ECE
rw |
ETPS
rw |
ETF
rw |
MSM
rw |
TS
rw |
SMS
rw |
Bits 0-2: SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 167: TIMxTIM1 internal trigger connection on page 777 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of f<sub>CK_INT</sub> frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
Bit 16: SMS[3].
Bits 20-21: TS[4:3].
TIM1 DMA/interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
15/15 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
COMDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
BIE
rw |
TIE
rw |
COMIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 5: COM interrupt enable.
Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 7: Break interrupt enable.
Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 13: COM DMA request enable.
Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
TIM1 status register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC6IF
r/w0c |
CC5IF
r/w0c |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SBIF
r/w0c |
CC[4]OF
r/w0c |
CC[3]OF
r/w0c |
CC[2]OF
r/w0c |
CC[1]OF
r/w0c |
B2IF
r/w0c |
BIF
r/w0c |
TIF
r/w0c |
COMIF
r/w0c |
CC[4]IF
r/w0c |
CC[3]IF
r/w0c |
CC[2]IF
r/w0c |
CC[1]IF
r/w0c |
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 24.4.3: TIMx slave mode control register (TIM1_SMCRTIMx_SMCR)(x = 1, 8)), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 5: COM interrupt flag.
Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 8: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 13: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 16: Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output).
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 17: Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output).
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
TIM1 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
B2G
w |
BG
w |
TG
w |
COMG
w |
CC[4]G
w |
CC[3]G
w |
CC[2]G
w |
CC[1]G
w |
UG
w |
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output..
Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
Bit 8: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled
TIM1 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM1 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC[1]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 1 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 2 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 2 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 1 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM1 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 3 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 4 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM1 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[4]M_3
rw |
OC[3]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 3 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 3 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 4 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 4 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 3 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 4 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM1 capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
19/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[6]P
rw |
CC[6]E
rw |
CC[5]P
rw |
CC[5]E
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]NE
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]NE
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]NE
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 2: Capture/Compare 1 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 3: Capture/Compare 1 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 4: Capture/Compare 2 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 5: Capture/Compare 2 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 6: Capture/Compare 2 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 7: Capture/Compare 2 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 8: Capture/Compare 3 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 9: Capture/Compare 3 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 10: Capture/Compare 3 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 11: Capture/Compare 3 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 12: Capture/Compare 4 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 13: Capture/Compare 4 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 15: Capture/Compare 4 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 16: Capture/Compare 5 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 17: Capture/Compare 5 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 20: Capture/Compare 6 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 21: Capture/Compare 6 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
TIM1 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
TIM1 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM1 auto-reload register
Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 24.3.1: Time-base unit on page 691 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
TIM1 repetition counter register
Offset: 0x30, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
Bits 0-15: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode..
Allowed values: 0x0-0xffff
capture/compare register
Offset: 0x34, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x38, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x3c, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x40, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM1 break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified
10/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BK2P
rw |
BK2E
rw |
BK2F
rw |
BKF
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup.
Allowed values: 0x0-0xff
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level
Bit 12: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per Figure 189: Break and Break2 circuitry overview). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8))..
Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 20-23: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 24: Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 189: Break and Break2 circuitry overview). Note: The BKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled
Bit 25: Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
TIM1 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-4: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....
Allowed values: 0x0-0x1f
Bits 8-12: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA..
Allowed values: 0x0-0x12
TIM1 DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMAB
rw |
Bits 0-31: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM1 capture/compare mode register 3
Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified
10/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[6]M_3
rw |
OC[5]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[6]CE
rw |
OC[6]M
rw |
OC[6]PE
rw |
OC[6]FE
rw |
OC[5]CE
rw |
OC[5]M
rw |
OC[5]PE
rw |
OC[5]FE
rw |
Bit 2: Output compare 5 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 5 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 5 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 5 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 10: Output compare 6 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 6 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 6 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 6 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 5 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 6 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
capture/compare register
Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GC5C3
rw |
GC5C2
rw |
GC5C1
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCR
rw |
Bits 0-15: Capture/Compare value.
Allowed values: 0x0-0xffff
Bit 29: Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..
Bit 30: Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..
Bit 31: Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals..
capture/compare register
Offset: 0x5c, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM1 alternate function option register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: Unspecified
0/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ETRSEL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETRSEL
rw |
BKCMP2P
rw |
BKCMP1P
rw |
BKINP
rw |
BKDF1BK0E
rw |
BKCMP2E
rw |
BKCMP1E
rw |
BKINE
rw |
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 8: BRK dfsdm1_break[0] enable This bit enables the dfsdm1_break[0] for the timer s BRK input. dfsdm1_break[0] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
TIM1 Alternate function register 2
Offset: 0x64, size: 32, reset: 0x00000001, access: Unspecified
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BK2CMP2P
rw |
BK2CMP1P
rw |
BK2INP
rw |
BK2DF1BK1E
rw |
BK2CMP2E
rw |
BK2CMP1E
rw |
BK2INE
rw |
Bit 0: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer s BRK2 input. BKIN2 input is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 1: BRK2 COMP1 enable This bit enables the COMP1 for the timer s BRK2 input. COMP1 output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 2: BRK2 COMP2 enable This bit enables the COMP2 for the timer s BRK2 input. COMP2 output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 8: BRK2 dfsdm1_break[1] enable This bit enables the dfsdm1_break[1] for the timer s BRK2 input. dfsdm1_break[1] output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 10: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
0x40014000: General purpose timers
74/95 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x20 (16-bit) | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c (16-bit) | ARR | ||||||||||||||||||||||||||||||||
0x30 (16-bit) | RCR | ||||||||||||||||||||||||||||||||
0x34 (16-bit) | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 (16-bit) | CCR[2] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c (16-bit) | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM15 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
6/7 fields covered.
Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>) used by the dead-time generators and the digital filters (TIx).
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM15 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
6/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OIS[2]
rw |
OIS[1]N
rw |
OIS[1]
rw |
TI1S
rw |
MMS
rw |
CCDS
rw |
CCUS
rw |
CCPC
rw |
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:.
Bit 7: TI1 selection.
Bit 8: Output Idle state (OC1 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 9: Output Idle state (OC1N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 10: Output Idle state (OC2 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
TIM15 slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSM
rw |
TS
rw |
SMS
rw |
Bits 0-2: SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS= 00100 ). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 4-6: TS[0]: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See Table 181: TIMx Internal trigger connection on page 910 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/slave mode.
Bit 16: SMS[3].
Bits 20-21: TS[4:3].
TIM15 DMA/interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
10/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
COMDE
rw |
CC[1]DE
rw |
UDE
rw |
BIE
rw |
TIE
rw |
COMIE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 5: COM interrupt enable.
Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 7: Break interrupt enable.
Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 13: COM DMA request enable.
Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
TIM15 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
8/8 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[2]OF
r/w0c |
CC[1]OF
r/w0c |
BIF
r/w0c |
TIF
r/w0c |
COMIF
r/w0c |
CC[2]IF
r/w0c |
CC[1]IF
r/w0c |
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 26.6.3: TIM15 slave mode control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 5: COM interrupt flag.
Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
TIM15 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
TIM15 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM15 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
10/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC[1]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 2 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved
Bit 16: Output compare 1 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM15 capture/compare enable register
Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified
7/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]NE
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 2: Capture/Compare 1 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 3: Capture/Compare 1 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 4: Capture/Compare 2 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 5: Capture/Compare 2 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 7: Capture/Compare 2 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
TIM15 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
TIM15 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM15 auto-reload register
Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 26.5.1: Time-base unit on page 862 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
TIM15 repetition counter register
Offset: 0x30, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
Bits 0-7: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..
Allowed values: 0x0-0xff
capture/compare register
Offset: 0x34, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x38, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM15 break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified
8/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKF
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup.
Allowed values: 0x0-0xff
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 26.6.9: TIM15 capture/compare enable register (TIM15_CCER) on page 918). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 26.6.9: TIM15 capture/compare enable register (TIM15_CCER) on page 918). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (Section 26.6.9: TIM15 capture/compare enable register (TIM15_CCER) on page 918)..
Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set
Bits 16-19: Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
TIM15 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
0/2 fields covered.
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
TIM15 DMA address for full transfer
Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM15 alternate register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: Unspecified
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKCMP2P
rw |
BKCMP1P
rw |
BKINP
rw |
BKDF1BK0E
rw |
BKCMP2E
rw |
BKCMP1E
rw |
BKINE
rw |
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 8: BRK dfsdm1_break[0] enable This bit enables the dfsdm1_break[0] for the timer s BRK input. dfsdm1_break[0] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
0x40014400: General purpose timers
51/65 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x20 (16-bit) | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c (16-bit) | ARR | ||||||||||||||||||||||||||||||||
0x30 (16-bit) | RCR | ||||||||||||||||||||||||||||||||
0x34 (16-bit) | CCR[1] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c (16-bit) | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM16 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
6/7 fields covered.
Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM16 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bit 8: Output Idle state (OC1 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 9: Output Idle state (OC1N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
TIM16 DMA/interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 5: COM interrupt enable.
Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled
Bit 7: Break interrupt enable.
Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
TIM16 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 5: COM interrupt flag.
Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
TIM16 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
TIM16 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
3/3 fields covered.
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM16 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
4/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[1]M_3
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 16: Output compare 1 mode, bit 3.
TIM16 capture/compare enable register
Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 2: Capture/Compare 1 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 3: Capture/Compare 1 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
TIM16 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
TIM16 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM16 auto-reload register
Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 26.5.1: Time-base unit on page 862 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
TIM16 repetition counter register
Offset: 0x30, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
Bits 0-7: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..
Allowed values: 0x0-0xff
capture/compare register
Offset: 0x34, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM16 break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified
8/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKF
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup.
Allowed values: 0x0-0xff
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946)..
Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
TIM16 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
0/2 fields covered.
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....
TIM16 DMA address for full transfer
Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM16 alternate function register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: Unspecified
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKCMP2P
rw |
BKCMP1P
rw |
BKINP
rw |
BKDF1BK1E
rw |
BKCMP2E
rw |
BKCMP1E
rw |
BKINE
rw |
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 8: BRK dfsdm1_break[1] enable This bit enables the dfsdm1_break[1] for the timer s BRK input. dfsdm1_break[1] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
TIM16 input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI1SEL
rw |
0x40014800: General purpose timers
51/65 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x20 (16-bit) | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c (16-bit) | ARR | ||||||||||||||||||||||||||||||||
0x30 (16-bit) | RCR | ||||||||||||||||||||||||||||||||
0x34 (16-bit) | CCR[1] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c (16-bit) | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM17 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
6/7 fields covered.
Bit 0: Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM17 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bit 8: Output Idle state (OC1 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 9: Output Idle state (OC1N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
TIM17 DMA/interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 5: COM interrupt enable.
Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled
Bit 7: Break interrupt enable.
Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
TIM17 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 5: COM interrupt flag.
Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
TIM17 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
TIM17 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
3/3 fields covered.
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM17 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
4/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[1]M_3
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1
Bit 16: Output compare 1 mode, bit 3.
TIM17 capture/compare enable register
Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified
4/4 fields covered.
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 2: Capture/Compare 1 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 3: Capture/Compare 1 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
TIM17 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
TIM17 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM17 auto-reload register
Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 26.5.1: Time-base unit on page 862 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
TIM17 repetition counter register
Offset: 0x30, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
Bits 0-7: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode..
Allowed values: 0x0-0xff
capture/compare register
Offset: 0x34, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM17 break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified
8/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKF
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup.
Allowed values: 0x0-0xff
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (Section 26.7.8: TIMx capture/compare enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 946)..
Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
TIM17 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
0/2 fields covered.
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....
TIM17 DMA address for full transfer
Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM17 alternate function register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: Unspecified
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BKCMP2P
rw |
BKCMP1P
rw |
BKINP
rw |
BKDF1BK2E
rw |
BKCMP2E
rw |
BKCMP1E
rw |
BKINE
rw |
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 8: BRK dfsdm1_break[2] enable This bit enables the dfsdm1_break[2] for the timer s BRK input. dfsdm1_break[2] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
TIM17 input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI1SEL
rw |
0x40000000: General-purpose-timers
99/114 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
0x20 (16-bit) | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x24 | CNT_ALTERNATE | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c (16-bit) | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM2 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
8/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFREMAP
rw |
CKD
rw |
ARPE
rw |
CMS
rw |
DIR
rw |
OPM
rw |
URS
rw |
UDIS
rw |
CEN
rw |
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM2 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
TIM2 slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETP
rw |
ECE
rw |
ETPS
rw |
ETF
rw |
MSM
rw |
TS
rw |
SMS
rw |
Bits 0-2: SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 179: TIMx internal trigger connection on page 846 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
Bit 16: SMS[3].
Bits 20-21: TS[4:3].
TIM2 DMA/Interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
TIM2 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
10/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]OF
r/w0c |
CC[3]OF
r/w0c |
CC[2]OF
r/w0c |
CC[1]OF
r/w0c |
TIF
r/w0c |
CC[4]IF
r/w0c |
CC[3]IF
r/w0c |
CC[2]IF
r/w0c |
CC[1]IF
r/w0c |
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow (for TIM2 to TIM4) and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
TIM2 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
TIM2 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM2 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC[1]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 1 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 2 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 2 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 1 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM2 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 3 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 4 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM2 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[4]M_3
rw |
OC[3]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 3 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 3 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 4 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 4 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 3 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 4 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM2 capture/compare enable register
Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified
8/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 5: Capture/Compare 2 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 9: Capture/Compare 3 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 13: Capture/Compare 4 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 15: Capture/Compare 4 output Polarity.
TIM2 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
0/2 fields covered.
TIM2 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM2 auto-reload register
Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: Unspecified
1/1 fields covered.
Bits 0-31: Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 25.3.1: Time-base unit on page 786 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffffffff
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
TIM2 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values: 0x0-0x1f
Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
Allowed values: 0x0-0x12
TIM2 DMA address for full transfer
Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM2 alternate function option register 1
Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified
0/1 fields covered.
TIM2 timer input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI4SEL
rw |
TI3SEL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI2SEL
rw |
TI1SEL
rw |
Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.
Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.
Bits 16-19: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved.
Bits 24-27: TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved.
0x40000400: General-purpose-timers
99/114 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
0x20 (16-bit) | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x24 | CNT_ALTERNATE | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c (16-bit) | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM2 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
8/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFREMAP
rw |
CKD
rw |
ARPE
rw |
CMS
rw |
DIR
rw |
OPM
rw |
URS
rw |
UDIS
rw |
CEN
rw |
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM2 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
TIM2 slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETP
rw |
ECE
rw |
ETPS
rw |
ETF
rw |
MSM
rw |
TS
rw |
SMS
rw |
Bits 0-2: SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 179: TIMx internal trigger connection on page 846 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
Bit 16: SMS[3].
Bits 20-21: TS[4:3].
TIM2 DMA/Interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
TIM2 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
10/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]OF
r/w0c |
CC[3]OF
r/w0c |
CC[2]OF
r/w0c |
CC[1]OF
r/w0c |
TIF
r/w0c |
CC[4]IF
r/w0c |
CC[3]IF
r/w0c |
CC[2]IF
r/w0c |
CC[1]IF
r/w0c |
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow (for TIM2 to TIM4) and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
TIM2 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
TIM2 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM2 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC[1]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 1 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 2 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 2 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 1 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM2 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 3 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 4 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM2 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[4]M_3
rw |
OC[3]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 3 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 3 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 4 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 4 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 3 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 4 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM2 capture/compare enable register
Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified
8/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 5: Capture/Compare 2 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 9: Capture/Compare 3 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 13: Capture/Compare 4 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 15: Capture/Compare 4 output Polarity.
TIM2 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
rw |
TIM2 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
0/2 fields covered.
TIM2 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM2 auto-reload register
Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 25.3.1: Time-base unit on page 786 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
TIM2 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values: 0x0-0x1f
Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
Allowed values: 0x0-0x12
TIM2 DMA address for full transfer
Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM2 alternate function option register 1
Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified
0/1 fields covered.
TIM2 timer input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI4SEL
rw |
TI3SEL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI2SEL
rw |
TI1SEL
rw |
Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.
Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.
Bits 16-19: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved.
Bits 24-27: TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved.
0x40000800: General-purpose-timers
99/114 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
0x20 (16-bit) | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x24 | CNT_ALTERNATE | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c (16-bit) | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM2 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
8/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFREMAP
rw |
CKD
rw |
ARPE
rw |
CMS
rw |
DIR
rw |
OPM
rw |
URS
rw |
UDIS
rw |
CEN
rw |
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM2 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
TIM2 slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETP
rw |
ECE
rw |
ETPS
rw |
ETF
rw |
MSM
rw |
TS
rw |
SMS
rw |
Bits 0-2: SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 179: TIMx internal trigger connection on page 846 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
Bit 16: SMS[3].
Bits 20-21: TS[4:3].
TIM2 DMA/Interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
TIM2 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
10/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]OF
r/w0c |
CC[3]OF
r/w0c |
CC[2]OF
r/w0c |
CC[1]OF
r/w0c |
TIF
r/w0c |
CC[4]IF
r/w0c |
CC[3]IF
r/w0c |
CC[2]IF
r/w0c |
CC[1]IF
r/w0c |
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow (for TIM2 to TIM4) and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
TIM2 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
TIM2 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM2 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC[1]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 1 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 2 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 2 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 1 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM2 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 3 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 4 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM2 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[4]M_3
rw |
OC[3]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 3 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 3 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 4 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 4 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 3 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 4 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM2 capture/compare enable register
Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified
8/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 5: Capture/Compare 2 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 9: Capture/Compare 3 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 13: Capture/Compare 4 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 15: Capture/Compare 4 output Polarity.
TIM2 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
rw |
TIM2 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
0/2 fields covered.
TIM2 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM2 auto-reload register
Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 25.3.1: Time-base unit on page 786 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
TIM2 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values: 0x0-0x1f
Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
Allowed values: 0x0-0x12
TIM2 DMA address for full transfer
Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM2 alternate function option register 1
Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified
0/1 fields covered.
TIM2 timer input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI4SEL
rw |
TI3SEL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI2SEL
rw |
TI1SEL
rw |
Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.
Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.
Bits 16-19: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved.
Bits 24-27: TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved.
0x40000c00: General-purpose-timers
99/114 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
0x20 (16-bit) | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x24 | CNT_ALTERNATE | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c | ARR | ||||||||||||||||||||||||||||||||
0x34 | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 | CCR[2] | ||||||||||||||||||||||||||||||||
0x3c | CCR[3] | ||||||||||||||||||||||||||||||||
0x40 | CCR[4] | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c (16-bit) | DMAR | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM5 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
8/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFREMAP
rw |
CKD
rw |
ARPE
rw |
CMS
rw |
DIR
rw |
OPM
rw |
URS
rw |
UDIS
rw |
CEN
rw |
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),.
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM5 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
3/3 fields covered.
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
TIM5 slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETP
rw |
ECE
rw |
ETPS
rw |
ETF
rw |
MSM
rw |
TS
rw |
SMS
rw |
Bits 0-2: SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 179: TIMx internal trigger connection on page 846 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
Bit 16: SMS[3].
Bits 20-21: TS[4:3].
TIM5 DMA/Interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
12/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
TIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
TIM5 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
10/10 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]OF
r/w0c |
CC[3]OF
r/w0c |
CC[2]OF
r/w0c |
CC[1]OF
r/w0c |
TIF
r/w0c |
CC[4]IF
r/w0c |
CC[3]IF
r/w0c |
CC[2]IF
r/w0c |
CC[1]IF
r/w0c |
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow (for TIM2 to TIM4) and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
TIM5 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
TIM5 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM5 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC[1]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 1 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 2 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 2 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 1 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM5 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 3 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 4 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM5 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[4]M_3
rw |
OC[3]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 3 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 3 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 4 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 4 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 3 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 4 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM5 capture/compare enable register
Offset: 0x20, size: 16, reset: 0x00000000, access: Unspecified
8/12 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 3: Capture/Compare 1 output Polarity.
Bit 4: Capture/Compare 2 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 5: Capture/Compare 2 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 7: Capture/Compare 2 output Polarity.
Bit 8: Capture/Compare 3 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 9: Capture/Compare 3 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 11: Capture/Compare 3 output Polarity.
Bit 12: Capture/Compare 4 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 13: Capture/Compare 4 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 15: Capture/Compare 4 output Polarity.
TIM5 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
0/2 fields covered.
TIM5 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM5 auto-reload register
Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: Unspecified
1/1 fields covered.
Bits 0-31: Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 25.3.1: Time-base unit on page 786 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffffffff
capture/compare register
Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x3c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
capture/compare register
Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
TIM5 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values: 0x0-0x1f
Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
Allowed values: 0x0-0x12
TIM5 DMA address for full transfer
Offset: 0x4c, size: 16, reset: 0x00000000, access: Unspecified
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
Bits 0-15: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM5 alternate function option register 1
Offset: 0x60, size: 32, reset: 0x00000000, access: Unspecified
0/1 fields covered.
TIM5 timer input selection register
Offset: 0x68, size: 32, reset: 0x00000000, access: Unspecified
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TI4SEL
rw |
TI3SEL
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI2SEL
rw |
TI1SEL
rw |
Bits 0-3: TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved.
Bits 8-11: TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved.
Bits 16-19: TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved.
Bits 24-27: TI4[0] to TI4[15] input selection These bits select the TI4[0] to TI4[15] input source. Others: Reserved.
0x40001000: TIM6 address block description
15/15 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c (16-bit) | ARR |
TIM6 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bit 11: UIF status bit remapping.
Allowed values:
0: Disabled: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31
1: Enabled: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31
TIM6 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MMS
rw |
Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event
TIM6 DMA/Interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
2/2 fields covered.
TIM6 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
TIM6 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UG
w |
TIM6 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFCPY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Bits 0-15: Counter value.
Allowed values: 0x0-0xffff
Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
TIM6 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM6 auto-reload register
Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Prescaler value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 46.3.1: Time-base unit on page 1760 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
0x40001400: TIM7 address block description
15/15 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CR2 | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 (16-bit) | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c (16-bit) | ARR |
TIM6 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One-pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bit 11: UIF status bit remapping.
Allowed values:
0: Disabled: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31
1: Enabled: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31
TIM6 control register 2
Offset: 0x4, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MMS
rw |
Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event
TIM6 DMA/Interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
2/2 fields covered.
TIM6 status register
Offset: 0x10, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
TIM6 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UG
w |
TIM6 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFCPY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Bits 0-15: Counter value.
Allowed values: 0x0-0xffff
Bit 31: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
TIM6 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM6 auto-reload register
Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Prescaler value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 46.3.1: Time-base unit on page 1760 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
0x40013400: Advanced-timers
157/186 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | SMCR | ||||||||||||||||||||||||||||||||
0xc (16-bit) | DIER | ||||||||||||||||||||||||||||||||
0x10 | SR | ||||||||||||||||||||||||||||||||
0x14 (16-bit) | EGR | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
0x20 | CCER | ||||||||||||||||||||||||||||||||
0x24 | CNT | ||||||||||||||||||||||||||||||||
0x28 (16-bit) | PSC | ||||||||||||||||||||||||||||||||
0x2c (16-bit) | ARR | ||||||||||||||||||||||||||||||||
0x30 (16-bit) | RCR | ||||||||||||||||||||||||||||||||
0x34 (16-bit) | CCR[1] | ||||||||||||||||||||||||||||||||
0x38 (16-bit) | CCR[2] | ||||||||||||||||||||||||||||||||
0x3c (16-bit) | CCR[3] | ||||||||||||||||||||||||||||||||
0x40 (16-bit) | CCR[4] | ||||||||||||||||||||||||||||||||
0x44 | BDTR | ||||||||||||||||||||||||||||||||
0x48 (16-bit) | DCR | ||||||||||||||||||||||||||||||||
0x4c | DMAR | ||||||||||||||||||||||||||||||||
0x54 | CCMR3_Output | ||||||||||||||||||||||||||||||||
0x58 | CCR5 | ||||||||||||||||||||||||||||||||
0x5c (16-bit) | CCR6 | ||||||||||||||||||||||||||||||||
0x60 | AF1 | ||||||||||||||||||||||||||||||||
0x64 | AF2 | ||||||||||||||||||||||||||||||||
0x68 | TISEL |
TIM8 control register 1
Offset: 0x0, size: 16, reset: 0x00000000, access: Unspecified
8/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UIFREMAP
rw |
CKD
rw |
ARPE
rw |
CMS
rw |
DIR
rw |
OPM
rw |
URS
rw |
UDIS
rw |
CEN
rw |
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware..
Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request
Bit 3: One pulse mode.
Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)
Bit 4: Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode..
Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter
Bits 5-6: Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
Bit 7: Auto-reload preload enable.
Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (t<sub>DTS</sub>)used by the dead-time generators and the digital filters (ETR, TIx): Note: t<sub>DTS</sub> = 1/f<sub>DTS</sub>, t<sub>CK_INT</sub> = 1/f<sub>CK_INT</sub>..
Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT
Bit 11: UIF status bit remapping.
TIM8 control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
14/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MMS2
rw |
OIS[6]
rw |
OIS[5]
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OIS[4]
rw |
OIS[3]N
rw |
OIS[3]
rw |
OIS[2]N
rw |
OIS[2]
rw |
OIS[1]N
rw |
OIS[1]
rw |
TI1S
rw |
MMS
rw |
CCDS
rw |
CCUS
rw |
CCPC
rw |
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
Bit 3: Capture/compare DMA selection.
Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs
Bits 4-6: Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output
Bit 7: TI1 selection.
Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
Bit 8: Output Idle state (OC1 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 9: Output Idle state (OC1N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 10: Output Idle state (OC2 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 11: Output Idle state (OC2N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 12: Output Idle state (OC3 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 13: Output Idle state (OC3N output).
Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0
Bit 14: Output Idle state (OC4 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 16: Output Idle state (OC5 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bit 18: Output Idle state (OC6 output).
Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0
Bits 20-23: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
TIM8 slave mode control register
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
7/9 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS2
rw |
SMS_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETP
rw |
ECE
rw |
ETPS
rw |
ETF
rw |
MSM
rw |
TS
rw |
SMS
rw |
Bits 0-2: SMS[0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Codes above 1000: Reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: TS[0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 167: TIMxTIM1 internal trigger connection on page 777 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)
Bit 7: Master/slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of f<sub>CK_INT</sub> frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 15: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations.
Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge
Bit 16: SMS[3].
Bits 20-21: TS[4:3].
TIM8 DMA/interrupt enable register
Offset: 0xc, size: 16, reset: 0x00000000, access: Unspecified
15/15 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDE
rw |
COMDE
rw |
CC[4]DE
rw |
CC[3]DE
rw |
CC[2]DE
rw |
CC[1]DE
rw |
UDE
rw |
BIE
rw |
TIE
rw |
COMIE
rw |
CC[4]IE
rw |
CC[3]IE
rw |
CC[2]IE
rw |
CC[1]IE
rw |
UIE
rw |
Bit 0: Update interrupt enable.
Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled
Bit 1: Capture/Compare 1 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 2: Capture/Compare 2 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 3: Capture/Compare 3 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 4: Capture/Compare 4 interrupt enable.
Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled
Bit 5: COM interrupt enable.
Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled
Bit 6: Trigger interrupt enable.
Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled
Bit 7: Break interrupt enable.
Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled
Bit 8: Update DMA request enable.
Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled
Bit 9: Capture/Compare 1 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 10: Capture/Compare 2 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 11: Capture/Compare 3 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 12: Capture/Compare 4 DMA request enable.
Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled
Bit 13: COM DMA request enable.
Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled
Bit 14: Trigger DMA request enable.
Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled
TIM8 status register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
16/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC6IF
r/w0c |
CC5IF
r/w0c |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SBIF
r/w0c |
CC[4]OF
r/w0c |
CC[3]OF
r/w0c |
CC[2]OF
r/w0c |
CC[1]OF
r/w0c |
B2IF
r/w0c |
BIF
r/w0c |
TIF
r/w0c |
COMIF
r/w0c |
CC[4]IF
r/w0c |
CC[3]IF
r/w0c |
CC[2]IF
r/w0c |
CC[1]IF
r/w0c |
UIF
r/w0c |
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to Section 24.4.3: TIMx slave mode control register (TIM1_SMCRTIMx_SMCR)(x = 1, 8)), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending
Bit 1: Capture/compare 1 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 interrupt flag.
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 5: COM interrupt flag.
Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 8: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 9: Capture/Compare 1 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 10: Capture/Compare 2 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 11: Capture/Compare 3 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 12: Capture/Compare 4 overcapture flag.
Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set
Bit 13: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation..
Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register
Bit 16: Compare 5 interrupt flag Refer to CC1IF description (Note: Channel 5 can only be configured as output).
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
Bit 17: Compare 6 interrupt flag Refer to CC1IF description (Note: Channel 6 can only be configured as output).
Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.
TIM8 event generation register
Offset: 0x14, size: 16, reset: 0x00000000, access: Unspecified
9/9 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
B2G
w |
BG
w |
TG
w |
COMG
w |
CC[4]G
w |
CC[3]G
w |
CC[2]G
w |
CC[1]G
w |
UG
w |
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.
Bit 1: Capture/compare 1 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 2: Capture/compare 2 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 3: Capture/compare 3 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 4: Capture/compare 4 generation.
Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output..
Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated
Bit 6: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
Bit 8: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled
TIM8 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC
Bits 2-3: Input capture 1 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 1 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC
Bits 10-11: Input capture 2 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 2 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM8 capture/compare mode register 1
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[2]M_3
rw |
OC[1]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[2]CE
rw |
OC[2]M
rw |
OC[2]PE
rw |
OC[2]FE
rw |
CC[2]S
rw |
OC[1]CE
rw |
OC[1]M
rw |
OC[1]PE
rw |
OC[1]FE
rw |
CC[1]S
rw |
Bits 0-1: Capture/Compare 1 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 1 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 1 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 1 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 1 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 2 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 2 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 2 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 2 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 1 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 2 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM8 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 0-1: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC
Bits 2-3: Input capture 3 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 4-7: Input capture 3 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC
Bits 10-11: Input capture 4 prescaler.
Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events
Bits 12-15: Input capture 4 filter.
Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8
TIM8 capture/compare mode register 2
Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified
12/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[4]M_3
rw |
OC[3]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[4]CE
rw |
OC[4]M
rw |
OC[4]PE
rw |
OC[4]FE
rw |
CC[4]S
rw |
OC[3]CE
rw |
OC[3]M
rw |
OC[3]PE
rw |
OC[3]FE
rw |
CC[3]S
rw |
Bits 0-1: Capture/Compare 3 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 2: Output compare 3 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 3 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 3 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bits 8-9: Capture/Compare 4 selection.
Allowed values:
0: Output: CCx channel is configured as output
Bit 10: Output compare 4 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 4 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 4 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 3 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 4 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
TIM8 capture/compare enable register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
19/19 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CC[6]P
rw |
CC[6]E
rw |
CC[5]P
rw |
CC[5]E
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CC[4]NP
rw |
CC[4]P
rw |
CC[4]E
rw |
CC[3]NP
rw |
CC[3]NE
rw |
CC[3]P
rw |
CC[3]E
rw |
CC[2]NP
rw |
CC[2]NE
rw |
CC[2]P
rw |
CC[2]E
rw |
CC[1]NP
rw |
CC[1]NE
rw |
CC[1]P
rw |
CC[1]E
rw |
Bit 0: Capture/Compare 1 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 1: Capture/Compare 1 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 2: Capture/Compare 1 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 3: Capture/Compare 1 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 4: Capture/Compare 2 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 5: Capture/Compare 2 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 6: Capture/Compare 2 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 7: Capture/Compare 2 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 8: Capture/Compare 3 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 9: Capture/Compare 3 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 10: Capture/Compare 3 complementary output enable.
Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled
Bit 11: Capture/Compare 3 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 12: Capture/Compare 4 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 13: Capture/Compare 4 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 15: Capture/Compare 4 output Polarity.
Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low
Bit 16: Capture/Compare 5 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 17: Capture/Compare 5 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
Bit 20: Capture/Compare 6 output enable.
Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled
Bit 21: Capture/Compare 6 output Polarity.
Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge
TIM8 counter
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
TIM8 prescaler
Offset: 0x28, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PSC
rw |
Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode )..
Allowed values: 0x0-0xffff
TIM8 auto-reload register
Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ARR
rw |
Bits 0-15: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 24.3.1: Time-base unit on page 691 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null..
Allowed values: 0x0-0xffff
TIM8 repetition counter register
Offset: 0x30, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
REP
rw |
Bits 0-15: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: the number of PWM periods in edge-aligned mode the number of half PWM period in center-aligned mode..
Allowed values: 0x0-0xffff
capture/compare register
Offset: 0x34, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x38, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x3c, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
capture/compare register
Offset: 0x40, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM8 break and dead-time register
Offset: 0x44, size: 32, reset: 0x00000000, access: Unspecified
10/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BK2P
rw |
BK2E
rw |
BK2F
rw |
BKF
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MOE
rw |
AOE
rw |
BKP
rw |
BKE
rw |
OSSR
rw |
OSSI
rw |
LOCK
rw |
DTG
rw |
Bits 0-7: Dead-time generator setup.
Allowed values: 0x0-0xff
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8)). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level
Bit 12: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per Figure 189: Break and Break2 circuitry overview). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (Section 24.4.11: TIMx capture/compare enable register (TIM1_CCERTIMx_CCER)(x = 1, 8))..
Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 20-23: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 24: Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per Figure 189: Break and Break2 circuitry overview). Note: The BKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled
Bit 25: Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high
TIM8 DMA control register
Offset: 0x48, size: 16, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-4: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....
Allowed values: 0x0-0x1f
Bits 8-12: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA..
Allowed values: 0x0-0x12
TIM8 DMA address for full transfer
Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DMAB
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMAB
rw |
Bits 0-31: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
TIM8 capture/compare mode register 3
Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified
10/10 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OC[6]M_3
rw |
OC[5]M_3
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OC[6]CE
rw |
OC[6]M
rw |
OC[6]PE
rw |
OC[6]FE
rw |
OC[5]CE
rw |
OC[5]M
rw |
OC[5]PE
rw |
OC[5]FE
rw |
Bit 2: Output compare 5 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 3: Output compare 5 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 4-6: Output compare 5 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 7: Output compare 5 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 10: Output compare 6 fast enable.
Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled
Bit 11: Output compare 6 preload enable.
Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
Bits 12-14: Output compare 6 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 15: Output compare 6 clear enable.
Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal
Bit 16: Output compare 5 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
Bit 24: Output compare 6 mode, bit 3.
Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)
capture/compare register
Offset: 0x58, size: 32, reset: 0x00000000, access: Unspecified
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
GC5C3
rw |
GC5C2
rw |
GC5C1
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CCR
rw |
Bits 0-15: Capture/Compare value.
Allowed values: 0x0-0xffff
Bit 29: Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..
Bit 30: Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..
Bit 31: Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals..
capture/compare register
Offset: 0x5c, size: 16, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CCR
rw |
TIM8 Alternate function option register 1
Offset: 0x60, size: 32, reset: 0x00000001, access: Unspecified
0/8 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ETRSEL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETRSEL
rw |
BKCMP2P
rw |
BKCMP1P
rw |
BKINP
rw |
BKDF1BK2E
rw |
BKCMP2E
rw |
BKCMP1E
rw |
BKINE
rw |
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer s BRK input. BKIN input is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timer s BRK input. COMP1 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timer s BRK input. COMP2 output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 8: BRK dfsdm1_break[2] enable This bit enables the dfsdm1_break[2] for the timer s BRK input. dfsdm1_break[2] output is ORed with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
TIM8 Alternate function option register 2
Offset: 0x64, size: 32, reset: 0x00000001, access: Unspecified
0/7 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BK2CMP2P
rw |
BK2CMP1P
rw |
BK2INP
rw |
BK2DF1BK3E
rw |
BK2CMP2E
rw |
BK2CMP1E
rw |
BK2INE
rw |
Bit 0: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timer s BRK2 input. BKIN2 input is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 1: BRK2 COMP1 enable This bit enables the COMP1 for the timer s BRK2 input. COMP1 output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 2: BRK2 COMP2 enable This bit enables the COMP2 for the timer s BRK2 input. COMP2 output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 8: BRK2 dfsdm1_break[3] enable This bit enables the dfsdm1_break[3] for the timer s BRK2 input. dfsdm1_break[3] output is ORed with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 9: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 10: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Bit 11: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
0x40024000: Touch sensing controller
16/170 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR | ||||||||||||||||||||||||||||||||
0x4 | IER | ||||||||||||||||||||||||||||||||
0x8 | ICR | ||||||||||||||||||||||||||||||||
0xc | ISR | ||||||||||||||||||||||||||||||||
0x10 | IOHCR | ||||||||||||||||||||||||||||||||
0x18 | IOASCR | ||||||||||||||||||||||||||||||||
0x20 | IOSCR | ||||||||||||||||||||||||||||||||
0x28 | IOCCR | ||||||||||||||||||||||||||||||||
0x30 | IOGCSR | ||||||||||||||||||||||||||||||||
0x34 | IOG[1]CR | ||||||||||||||||||||||||||||||||
0x38 | IOG[2]CR | ||||||||||||||||||||||||||||||||
0x3c | IOG[3]CR | ||||||||||||||||||||||||||||||||
0x40 | IOG[4]CR | ||||||||||||||||||||||||||||||||
0x44 | IOG[5]CR | ||||||||||||||||||||||||||||||||
0x48 | IOG[6]CR | ||||||||||||||||||||||||||||||||
0x4c | IOG[7]CR | ||||||||||||||||||||||||||||||||
0x50 | IOG[8]CR |
control register
Offset: 0x0, size: 32, reset: 0x00000000, access: read-write
0/12 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CTPH
rw |
CTPL
rw |
SSD
rw |
SSE
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SSPSC
rw |
PGPSC
rw |
MCV
rw |
IODEF
rw |
SYNCPOL
rw |
AM
rw |
START
rw |
TSCE
rw |
Bit 0: Touch sensing controller enable.
Bit 1: Start a new acquisition.
Bit 2: Acquisition mode.
Bit 3: Synchronization pin polarity.
Bit 4: I/O Default mode.
Bits 5-7: Max count value.
Bits 12-14: pulse generator prescaler.
Bit 15: Spread spectrum prescaler.
Bit 16: Spread spectrum enable.
Bits 17-23: Spread spectrum deviation.
Bits 24-27: Charge transfer pulse low.
Bits 28-31: Charge transfer pulse high.
interrupt enable register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
interrupt clear register
Offset: 0x8, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
interrupt status register
Offset: 0xc, size: 32, reset: 0x00000000, access: read-write
0/2 fields covered.
I/O hysteresis control register
Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
Bit 0: G1_IO1.
Bit 1: G1_IO2.
Bit 2: G1_IO3.
Bit 3: G1_IO4.
Bit 4: G2_IO1.
Bit 5: G2_IO2.
Bit 6: G2_IO3.
Bit 7: G2_IO4.
Bit 8: G3_IO1.
Bit 9: G3_IO2.
Bit 10: G3_IO3.
Bit 11: G3_IO4.
Bit 12: G4_IO1.
Bit 13: G4_IO2.
Bit 14: G4_IO3.
Bit 15: G4_IO4.
Bit 16: G5_IO1.
Bit 17: G5_IO2.
Bit 18: G5_IO3.
Bit 19: G5_IO4.
Bit 20: G6_IO1.
Bit 21: G6_IO2.
Bit 22: G6_IO3.
Bit 23: G6_IO4.
Bit 24: G7_IO1.
Bit 25: G7_IO2.
Bit 26: G7_IO3.
Bit 27: G7_IO4.
Bit 28: G8_IO1.
Bit 29: G8_IO2.
Bit 30: G8_IO3.
Bit 31: G8_IO4.
I/O analog switch control register
Offset: 0x18, size: 32, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
Bit 0: G1_IO1.
Bit 1: G1_IO2.
Bit 2: G1_IO3.
Bit 3: G1_IO4.
Bit 4: G2_IO1.
Bit 5: G2_IO2.
Bit 6: G2_IO3.
Bit 7: G2_IO4.
Bit 8: G3_IO1.
Bit 9: G3_IO2.
Bit 10: G3_IO3.
Bit 11: G3_IO4.
Bit 12: G4_IO1.
Bit 13: G4_IO2.
Bit 14: G4_IO3.
Bit 15: G4_IO4.
Bit 16: G5_IO1.
Bit 17: G5_IO2.
Bit 18: G5_IO3.
Bit 19: G5_IO4.
Bit 20: G6_IO1.
Bit 21: G6_IO2.
Bit 22: G6_IO3.
Bit 23: G6_IO4.
Bit 24: G7_IO1.
Bit 25: G7_IO2.
Bit 26: G7_IO3.
Bit 27: G7_IO4.
Bit 28: G8_IO1.
Bit 29: G8_IO2.
Bit 30: G8_IO3.
Bit 31: G8_IO4.
I/O sampling control register
Offset: 0x20, size: 32, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
Bit 0: G1_IO1.
Bit 1: G1_IO2.
Bit 2: G1_IO3.
Bit 3: G1_IO4.
Bit 4: G2_IO1.
Bit 5: G2_IO2.
Bit 6: G2_IO3.
Bit 7: G2_IO4.
Bit 8: G3_IO1.
Bit 9: G3_IO2.
Bit 10: G3_IO3.
Bit 11: G3_IO4.
Bit 12: G4_IO1.
Bit 13: G4_IO2.
Bit 14: G4_IO3.
Bit 15: G4_IO4.
Bit 16: G5_IO1.
Bit 17: G5_IO2.
Bit 18: G5_IO3.
Bit 19: G5_IO4.
Bit 20: G6_IO1.
Bit 21: G6_IO2.
Bit 22: G6_IO3.
Bit 23: G6_IO4.
Bit 24: G7_IO1.
Bit 25: G7_IO2.
Bit 26: G7_IO3.
Bit 27: G7_IO4.
Bit 28: G8_IO1.
Bit 29: G8_IO2.
Bit 30: G8_IO3.
Bit 31: G8_IO4.
I/O channel control register
Offset: 0x28, size: 32, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
G8_IO4
rw |
G8_IO3
rw |
G8_IO2
rw |
G8_IO1
rw |
G7_IO4
rw |
G7_IO3
rw |
G7_IO2
rw |
G7_IO1
rw |
G6_IO4
rw |
G6_IO3
rw |
G6_IO2
rw |
G6_IO1
rw |
G5_IO4
rw |
G5_IO3
rw |
G5_IO2
rw |
G5_IO1
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
G4_IO4
rw |
G4_IO3
rw |
G4_IO2
rw |
G4_IO1
rw |
G3_IO4
rw |
G3_IO3
rw |
G3_IO2
rw |
G3_IO1
rw |
G2_IO4
rw |
G2_IO3
rw |
G2_IO2
rw |
G2_IO1
rw |
G1_IO4
rw |
G1_IO3
rw |
G1_IO2
rw |
G1_IO1
rw |
Bit 0: G1_IO1.
Bit 1: G1_IO2.
Bit 2: G1_IO3.
Bit 3: G1_IO4.
Bit 4: G2_IO1.
Bit 5: G2_IO2.
Bit 6: G2_IO3.
Bit 7: G2_IO4.
Bit 8: G3_IO1.
Bit 9: G3_IO2.
Bit 10: G3_IO3.
Bit 11: G3_IO4.
Bit 12: G4_IO1.
Bit 13: G4_IO2.
Bit 14: G4_IO3.
Bit 15: G4_IO4.
Bit 16: G5_IO1.
Bit 17: G5_IO2.
Bit 18: G5_IO3.
Bit 19: G5_IO4.
Bit 20: G6_IO1.
Bit 21: G6_IO2.
Bit 22: G6_IO3.
Bit 23: G6_IO4.
Bit 24: G7_IO1.
Bit 25: G7_IO2.
Bit 26: G7_IO3.
Bit 27: G7_IO4.
Bit 28: G8_IO1.
Bit 29: G8_IO2.
Bit 30: G8_IO3.
Bit 31: G8_IO4.
I/O group control status register
Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified
8/16 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
G8S
r |
G7S
r |
G6S
r |
G5S
r |
G4S
r |
G3S
r |
G2S
r |
G1S
r |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
G8E
rw |
G7E
rw |
G6E
rw |
G5E
rw |
G4E
rw |
G3E
rw |
G2E
rw |
G1E
rw |
Bit 0: Analog I/O group x enable.
Bit 1: Analog I/O group x enable.
Bit 2: Analog I/O group x enable.
Bit 3: Analog I/O group x enable.
Bit 4: Analog I/O group x enable.
Bit 5: Analog I/O group x enable.
Bit 6: Analog I/O group x enable.
Bit 7: Analog I/O group x enable.
Bit 16: Analog I/O group x status.
Bit 17: Analog I/O group x status.
Bit 18: Analog I/O group x status.
Bit 19: Analog I/O group x status.
Bit 20: Analog I/O group x status.
Bit 21: Analog I/O group x status.
Bit 22: Analog I/O group x status.
Bit 23: Analog I/O group x status.
I/O group x counter register
Offset: 0x34, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
I/O group x counter register
Offset: 0x38, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
I/O group x counter register
Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
I/O group x counter register
Offset: 0x40, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
I/O group x counter register
Offset: 0x44, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
I/O group x counter register
Offset: 0x48, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
I/O group x counter register
Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
I/O group x counter register
Offset: 0x50, size: 32, reset: 0x00000000, access: read-only
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CNT
r |
0x40004c00: Universal synchronous asynchronous receiver transmitter
124/124 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | BRR | ||||||||||||||||||||||||||||||||
0x10 | GTPR | ||||||||||||||||||||||||||||||||
0x14 | RTOR | ||||||||||||||||||||||||||||||||
0x18 | RQR | ||||||||||||||||||||||||||||||||
0x1c | ISR | ||||||||||||||||||||||||||||||||
0x20 | ICR | ||||||||||||||||||||||||||||||||
0x24 | RDR | ||||||||||||||||||||||||||||||||
0x28 | TDR | ||||||||||||||||||||||||||||||||
0x2c | PRESC |
USART control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFFIE
rw |
TXFEIE
rw |
FIFOEN
rw |
M1
rw |
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVER8
rw |
CMIE
rw |
MME
rw |
M0
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: TXFIFO not-full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..
Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8
Bits 16-20: Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bits 21-25: Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register
Bit 27: End-of-block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported..
Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled
Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register
Bit 31: RXFIFO full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register
USART control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
DIS_NSS
rw |
SLVEN
rw |
Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled
Bit 3: NSS pin enable When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored
Bit 4: 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 326 and Figure 327) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1.
Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled
Bits 12-13: Stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled
Bits 24-31: Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)..
Allowed values: 0x0-0xff
USART control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode
Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled
Bit 6: DMA enable receiver This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method
Bit 12: Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA Disable on reception error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x7
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
Bit 24: Transmission complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full
Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty
USART baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BRR
rw |
USART guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-7: Prescaler value.
Allowed values: 0x0-0xff
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0xff
USART receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BLEN
rw |
RTO
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTO
rw |
Bits 0-23: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character..
Allowed values: 0x0-0xffffff
Bits 24-31: Block length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block..
Allowed values: 0x0-0xff
USART request register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
USART interrupt and status register
Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFT
r |
RXFT
r |
TCBGT
r |
RXFF
r |
TXFE
r |
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABRF
r |
ABRE
r |
UDR
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXFNF
r |
TC
r |
RXFNE
r |
IDLE
r |
ORE
r |
NE
r |
FE
r |
PE
r |
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No parity error
1: Error: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 33.5.8: Tolerance of the USART receiver to clock deviation on page 1055). Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..
Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register..
Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). Note: This bit is used during single buffer transmission..
Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line
Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..
Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register..
Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.
Bit 25: Transmission complete before guard time flag.
Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101 , RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.
USART interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
15/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUCF
w1c |
CMCF
w1c |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDRCF
w1c |
EOBCF
w1c |
RTOCF
w1c |
CTSCF
w1c |
LBDCF
w1c |
TCBGTCF
w1c |
TCCF
w1c |
TXFECF
w1c |
IDLECF
w1c |
ORECF
w1c |
NECF
w1c |
FECF
w1c |
PECF
w1c |
Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TXFE flag in the ISR register
Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register
Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the LBDF flag in the ISR register
Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the RTOF flag in the ISR register
Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the EOBF flag in the ISR register
Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038.
Allowed values:
1: Clear: Clear the UDR flag in the ISR register
Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
USART receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDR
r |
Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 320). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..
Allowed values: 0x0-0x1ff
USART transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDR
rw |
Bits 0-8: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 320). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1..
Allowed values: 0x0-0x1ff
USART prescaler register
Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESCALER
rw |
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256
0x40005000: Universal synchronous asynchronous receiver transmitter
124/124 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | BRR | ||||||||||||||||||||||||||||||||
0x10 | GTPR | ||||||||||||||||||||||||||||||||
0x14 | RTOR | ||||||||||||||||||||||||||||||||
0x18 | RQR | ||||||||||||||||||||||||||||||||
0x1c | ISR | ||||||||||||||||||||||||||||||||
0x20 | ICR | ||||||||||||||||||||||||||||||||
0x24 | RDR | ||||||||||||||||||||||||||||||||
0x28 | TDR | ||||||||||||||||||||||||||||||||
0x2c | PRESC |
USART control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFFIE
rw |
TXFEIE
rw |
FIFOEN
rw |
M1
rw |
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVER8
rw |
CMIE
rw |
MME
rw |
M0
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: TXFIFO not-full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..
Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8
Bits 16-20: Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bits 21-25: Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register
Bit 27: End-of-block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported..
Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled
Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register
Bit 31: RXFIFO full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register
USART control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
DIS_NSS
rw |
SLVEN
rw |
Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled
Bit 3: NSS pin enable When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored
Bit 4: 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 326 and Figure 327) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1.
Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled
Bits 12-13: Stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled
Bits 24-31: Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)..
Allowed values: 0x0-0xff
USART control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode
Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled
Bit 6: DMA enable receiver This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method
Bit 12: Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA Disable on reception error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x7
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
Bit 24: Transmission complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full
Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty
USART baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BRR
rw |
USART guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-7: Prescaler value.
Allowed values: 0x0-0xff
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0xff
USART receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BLEN
rw |
RTO
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTO
rw |
Bits 0-23: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character..
Allowed values: 0x0-0xffffff
Bits 24-31: Block length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block..
Allowed values: 0x0-0xff
USART request register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
USART interrupt and status register
Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFT
r |
RXFT
r |
TCBGT
r |
RXFF
r |
TXFE
r |
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABRF
r |
ABRE
r |
UDR
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXFNF
r |
TC
r |
RXFNE
r |
IDLE
r |
ORE
r |
NE
r |
FE
r |
PE
r |
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No parity error
1: Error: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 33.5.8: Tolerance of the USART receiver to clock deviation on page 1055). Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..
Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register..
Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). Note: This bit is used during single buffer transmission..
Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line
Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..
Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register..
Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.
Bit 25: Transmission complete before guard time flag.
Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101 , RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.
USART interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
15/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUCF
w1c |
CMCF
w1c |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDRCF
w1c |
EOBCF
w1c |
RTOCF
w1c |
CTSCF
w1c |
LBDCF
w1c |
TCBGTCF
w1c |
TCCF
w1c |
TXFECF
w1c |
IDLECF
w1c |
ORECF
w1c |
NECF
w1c |
FECF
w1c |
PECF
w1c |
Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TXFE flag in the ISR register
Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register
Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the LBDF flag in the ISR register
Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the RTOF flag in the ISR register
Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the EOBF flag in the ISR register
Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038.
Allowed values:
1: Clear: Clear the UDR flag in the ISR register
Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
USART receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDR
r |
Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 320). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..
Allowed values: 0x0-0x1ff
USART transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDR
rw |
Bits 0-8: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 320). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1..
Allowed values: 0x0-0x1ff
USART prescaler register
Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESCALER
rw |
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256
0x40013800: Universal synchronous asynchronous receiver transmitter
124/124 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | BRR | ||||||||||||||||||||||||||||||||
0x10 | GTPR | ||||||||||||||||||||||||||||||||
0x14 | RTOR | ||||||||||||||||||||||||||||||||
0x18 | RQR | ||||||||||||||||||||||||||||||||
0x1c | ISR | ||||||||||||||||||||||||||||||||
0x20 | ICR | ||||||||||||||||||||||||||||||||
0x24 | RDR | ||||||||||||||||||||||||||||||||
0x28 | TDR | ||||||||||||||||||||||||||||||||
0x2c | PRESC |
USART control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFFIE
rw |
TXFEIE
rw |
FIFOEN
rw |
M1
rw |
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVER8
rw |
CMIE
rw |
MME
rw |
M0
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: TXFIFO not-full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..
Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8
Bits 16-20: Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bits 21-25: Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register
Bit 27: End-of-block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported..
Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled
Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register
Bit 31: RXFIFO full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register
USART control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
DIS_NSS
rw |
SLVEN
rw |
Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled
Bit 3: NSS pin enable When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored
Bit 4: 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 326 and Figure 327) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1.
Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled
Bits 12-13: Stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled
Bits 24-31: Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)..
Allowed values: 0x0-0xff
USART control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode
Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled
Bit 6: DMA enable receiver This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method
Bit 12: Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA Disable on reception error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x7
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
Bit 24: Transmission complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full
Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty
USART baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BRR
rw |
USART guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-7: Prescaler value.
Allowed values: 0x0-0xff
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0xff
USART receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BLEN
rw |
RTO
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTO
rw |
Bits 0-23: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character..
Allowed values: 0x0-0xffffff
Bits 24-31: Block length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block..
Allowed values: 0x0-0xff
USART request register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
USART interrupt and status register
Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFT
r |
RXFT
r |
TCBGT
r |
RXFF
r |
TXFE
r |
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABRF
r |
ABRE
r |
UDR
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXFNF
r |
TC
r |
RXFNE
r |
IDLE
r |
ORE
r |
NE
r |
FE
r |
PE
r |
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No parity error
1: Error: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 33.5.8: Tolerance of the USART receiver to clock deviation on page 1055). Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..
Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register..
Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). Note: This bit is used during single buffer transmission..
Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line
Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..
Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register..
Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.
Bit 25: Transmission complete before guard time flag.
Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101 , RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.
USART interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
15/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUCF
w1c |
CMCF
w1c |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDRCF
w1c |
EOBCF
w1c |
RTOCF
w1c |
CTSCF
w1c |
LBDCF
w1c |
TCBGTCF
w1c |
TCCF
w1c |
TXFECF
w1c |
IDLECF
w1c |
ORECF
w1c |
NECF
w1c |
FECF
w1c |
PECF
w1c |
Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TXFE flag in the ISR register
Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register
Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the LBDF flag in the ISR register
Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the RTOF flag in the ISR register
Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the EOBF flag in the ISR register
Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038.
Allowed values:
1: Clear: Clear the UDR flag in the ISR register
Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
USART receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDR
r |
Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 320). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..
Allowed values: 0x0-0x1ff
USART transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDR
rw |
Bits 0-8: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 320). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1..
Allowed values: 0x0-0x1ff
USART prescaler register
Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESCALER
rw |
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256
0x40004400: Universal synchronous asynchronous receiver transmitter
124/124 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | BRR | ||||||||||||||||||||||||||||||||
0x10 | GTPR | ||||||||||||||||||||||||||||||||
0x14 | RTOR | ||||||||||||||||||||||||||||||||
0x18 | RQR | ||||||||||||||||||||||||||||||||
0x1c | ISR | ||||||||||||||||||||||||||||||||
0x20 | ICR | ||||||||||||||||||||||||||||||||
0x24 | RDR | ||||||||||||||||||||||||||||||||
0x28 | TDR | ||||||||||||||||||||||||||||||||
0x2c | PRESC |
USART control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFFIE
rw |
TXFEIE
rw |
FIFOEN
rw |
M1
rw |
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVER8
rw |
CMIE
rw |
MME
rw |
M0
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: TXFIFO not-full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..
Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8
Bits 16-20: Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bits 21-25: Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register
Bit 27: End-of-block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported..
Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled
Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register
Bit 31: RXFIFO full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register
USART control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
DIS_NSS
rw |
SLVEN
rw |
Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled
Bit 3: NSS pin enable When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored
Bit 4: 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 326 and Figure 327) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1.
Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled
Bits 12-13: Stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled
Bits 24-31: Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)..
Allowed values: 0x0-0xff
USART control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode
Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled
Bit 6: DMA enable receiver This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method
Bit 12: Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA Disable on reception error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x7
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
Bit 24: Transmission complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full
Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty
USART baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BRR
rw |
USART guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-7: Prescaler value.
Allowed values: 0x0-0xff
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0xff
USART receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BLEN
rw |
RTO
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTO
rw |
Bits 0-23: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character..
Allowed values: 0x0-0xffffff
Bits 24-31: Block length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block..
Allowed values: 0x0-0xff
USART request register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
USART interrupt and status register
Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFT
r |
RXFT
r |
TCBGT
r |
RXFF
r |
TXFE
r |
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABRF
r |
ABRE
r |
UDR
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXFNF
r |
TC
r |
RXFNE
r |
IDLE
r |
ORE
r |
NE
r |
FE
r |
PE
r |
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No parity error
1: Error: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 33.5.8: Tolerance of the USART receiver to clock deviation on page 1055). Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..
Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register..
Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). Note: This bit is used during single buffer transmission..
Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line
Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..
Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register..
Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.
Bit 25: Transmission complete before guard time flag.
Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101 , RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.
USART interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
15/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUCF
w1c |
CMCF
w1c |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDRCF
w1c |
EOBCF
w1c |
RTOCF
w1c |
CTSCF
w1c |
LBDCF
w1c |
TCBGTCF
w1c |
TCCF
w1c |
TXFECF
w1c |
IDLECF
w1c |
ORECF
w1c |
NECF
w1c |
FECF
w1c |
PECF
w1c |
Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TXFE flag in the ISR register
Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register
Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the LBDF flag in the ISR register
Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the RTOF flag in the ISR register
Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the EOBF flag in the ISR register
Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038.
Allowed values:
1: Clear: Clear the UDR flag in the ISR register
Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
USART receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDR
r |
Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 320). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..
Allowed values: 0x0-0x1ff
USART transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDR
rw |
Bits 0-8: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 320). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1..
Allowed values: 0x0-0x1ff
USART prescaler register
Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESCALER
rw |
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256
0x40004800: Universal synchronous asynchronous receiver transmitter
124/124 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CR1 | ||||||||||||||||||||||||||||||||
0x4 | CR2 | ||||||||||||||||||||||||||||||||
0x8 | CR3 | ||||||||||||||||||||||||||||||||
0xc | BRR | ||||||||||||||||||||||||||||||||
0x10 | GTPR | ||||||||||||||||||||||||||||||||
0x14 | RTOR | ||||||||||||||||||||||||||||||||
0x18 | RQR | ||||||||||||||||||||||||||||||||
0x1c | ISR | ||||||||||||||||||||||||||||||||
0x20 | ICR | ||||||||||||||||||||||||||||||||
0x24 | RDR | ||||||||||||||||||||||||||||||||
0x28 | TDR | ||||||||||||||||||||||||||||||||
0x2c | PRESC |
USART control register 1
Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RXFFIE
rw |
TXFEIE
rw |
FIFOEN
rw |
M1
rw |
EOBIE
rw |
RTOIE
rw |
DEAT
rw |
DEDT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVER8
rw |
CMIE
rw |
MME
rw |
M0
rw |
WAKE
rw |
PCE
rw |
PS
rw |
PEIE
rw |
TXEIE
rw |
TCIE
rw |
RXNEIE
rw |
IDLEIE
rw |
TE
rw |
RE
rw |
UESM
rw |
UE
rw |
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode
Bit 2: Receiver enable This bit enables the receiver. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled
Bit 4: IDLE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register
Bit 5: RXFIFO not empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register
Bit 6: Transmission complete interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register
Bit 7: TXFIFO not-full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register
Bit 8: PE interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Even: Even parity
1: Odd: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled
Bit 11: Receiver wakeup method This bit determines the USART wakeup method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Idle: Idle line
1: Address: Address mask
Bit 12: Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode
Bit 14: Character match interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register
Bit 15: Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared..
Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8
Bits 16-20: Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bits 21-25: Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x1f
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register
Bit 27: End-of-block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported..
Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled
Bit 30: TXFIFO empty interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register
Bit 31: RXFIFO full interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register
USART control register 2
Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD
rw |
RTOEN
rw |
ABRMOD
rw |
ABREN
rw |
MSBFIRST
rw |
DATAINV
rw |
TXINV
rw |
RXINV
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWAP
rw |
LINEN
rw |
STOP
rw |
CLKEN
rw |
CPOL
rw |
CPHA
rw |
LBCL
rw |
LBDIE
rw |
LBDL
rw |
ADDM7
rw |
DIS_NSS
rw |
SLVEN
rw |
Bit 0: Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled
Bit 3: NSS pin enable When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored
Bit 4: 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 326 and Figure 327) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1.
Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled
Bits 12-13: Stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled
Bits 24-31: Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wakeup from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wakeup from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0)..
Allowed values: 0x0-0xff
USART control register 3
Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode
Bit 3: Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled
Bit 6: DMA enable receiver This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception
Bit 7: DMA enable transmitter This bit is set/reset by software.
Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission
Bit 8: RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer
Bit 9: CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted
Bit 10: CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0)..
Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method
Bit 12: Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register
Bit 13: DMA Disable on reception error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0x7
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register
Bit 23: TXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG
Bit 24: Transmission complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full
Bit 28: RXFIFO threshold interrupt enable This bit is set and cleared by software..
Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty
USART baud rate register
Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BRR
rw |
USART guard time and prescaler register
Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
Bits 0-7: Prescaler value.
Allowed values: 0x0-0xff
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values: 0x0-0xff
USART receiver timeout register
Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BLEN
rw |
RTO
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTO
rw |
Bits 0-23: Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character..
Allowed values: 0x0-0xffffff
Bits 24-31: Block length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block..
Allowed values: 0x0-0xff
USART request register
Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available
Bit 2: Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag..
Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag
Bit 3: Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition..
Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition
Bit 4: Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data
USART interrupt and status register
Offset: 0x1c, size: 32, reset: 0x008000C0, access: Unspecified
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TXFT
r |
RXFT
r |
TCBGT
r |
RXFF
r |
TXFE
r |
REACK
r |
TEACK
r |
WUF
r |
RWU
r |
SBKF
r |
CMF
r |
BUSY
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ABRF
r |
ABRE
r |
UDR
r |
EOBF
r |
RTOF
r |
CTS
r |
CTSIF
r |
LBDF
r |
TXFNF
r |
TC
r |
RXFNE
r |
IDLE
r |
ORE
r |
NE
r |
FE
r |
PE
r |
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No parity error
1: Error: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 33.5.8: Tolerance of the USART receiver to clock deviation on page 1055). Note: This error is associated with the character in the USART_RDR..
Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set..
Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register..
Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). Note: This bit is used during single buffer transmission..
Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line
Bit 10: CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register..
Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register..
Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.
Bit 25: Transmission complete before guard time flag.
Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101 , RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.
USART interrupt flag clear register
Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified
15/15 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WUCF
w1c |
CMCF
w1c |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UDRCF
w1c |
EOBCF
w1c |
RTOCF
w1c |
CTSCF
w1c |
LBDCF
w1c |
TCBGTCF
w1c |
TCCF
w1c |
TXFECF
w1c |
IDLECF
w1c |
ORECF
w1c |
NECF
w1c |
FECF
w1c |
PECF
w1c |
Bit 0: Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the PE flag in the ISR register
Bit 1: Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the FE flag in the ISR register
Bit 2: Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the NF flag in the ISR register
Bit 3: Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the ORE flag in the ISR register
Bit 4: Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the IDLE flag in the ISR register
Bit 5: TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TXFE flag in the ISR register
Bit 6: Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the TC flag in the ISR register
Bit 7: Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register..
Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register
Bit 8: LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the LBDF flag in the ISR register
Bit 9: CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register
Bit 11: Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the RTOF flag in the ISR register
Bit 12: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the EOBF flag in the ISR register
Bit 13: SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038.
Allowed values:
1: Clear: Clear the UDR flag in the ISR register
Bit 17: Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register..
Allowed values:
1: Clear: Clears the CMF flag in the ISR register
Bit 20: Wakeup from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 33.4: USART implementation on page 1038..
Allowed values:
1: Clear: Clears the WUF flag in the ISR register
USART receive data register
Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDR
r |
Bits 0-8: Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 320). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit..
Allowed values: 0x0-0x1ff
USART transmit data register
Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDR
rw |
Bits 0-8: Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 320). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1..
Allowed values: 0x0-0x1ff
USART prescaler register
Offset: 0x2c, size: 32, reset: 0x00000000, access: Unspecified
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRESCALER
rw |
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256
0x40010030: Voltage reference buffer
1/5 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 | CSR | ||||||||||||||||||||||||||||||||
0x4 | CCR |
VREF control and status register
Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified
1/4 fields covered.
calibration control register
Offset: 0x4, size: 32, reset: 0x00000000, access: read-write
0/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TRIM
rw |
0x40002c00: System window watchdog
6/6 fields covered.
Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0x0 (16-bit) | CR | ||||||||||||||||||||||||||||||||
0x4 (16-bit) | CFR | ||||||||||||||||||||||||||||||||
0x8 (16-bit) | SR |
Control register
Offset: 0x0, size: 16, reset: 0x0000007F, access: read-write
2/2 fields covered.
Configuration register
Offset: 0x4, size: 16, reset: 0x0000007F, access: read-write
3/3 fields covered.
Bits 0-6: 7-bit window value.
Allowed values: 0x0-0x7f
Bits 7-8: Timer base.
Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8
Bit 9: Early wakeup interrupt.
Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40
Status register
Offset: 0x8, size: 16, reset: 0x00000000, access: read-write
1/1 fields covered.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EWIF
r/w0c |