Overall: 4514/13097 fields covered

ADC1

0x50040000: Analog-to-Digital Converter

6/130 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		DEEPPWD
rw 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw 		AWDCH1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		DMACFG
rw 		DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 3-4: RES.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWDCH1CH

Bits 26-30: AWDCH1CH.

JQDIS

Bit 31: Injected Queue disable.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw 		TROVS
rw 		OVSS
rw 		OVSR
rw 		JOVSE
rw 		ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

JOVSE

Bit 1: DMACFG.

OVSR

Bits 2-4: RES.

OVSS

Bits 5-8: ALIGN.

TROVS

Bit 9: Triggered Regular Oversampling.

ROVSM

Bit 10: EXTEN.

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMPPLUS
rw 		SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

SMPPLUS

Bit 31: Addition of one clock cycle to the sampling time.

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

HT2

Bits 16-23: HT2.

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

HT3

Bits 16-23: HT3.

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: Regular channel sequence length.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: Regular Data converted.

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-5: JEXTSEL.

JEXTEN

Bits 6-7: JEXTEN.

JSQ1

Bits 8-12: JSQ1.

JSQ2

Bits 14-18: JSQ2.

JSQ3

Bits 20-24: JSQ3.

JSQ4

Bits 26-30: JSQ4.

OFR1

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw 		OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-11: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

OFFSET1_EN

Bit 31: OFFSET1_EN.

OFR2

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw 		OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-11: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

OFFSET2_EN

Bit 31: OFFSET2_EN.

OFR3

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw 		OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-11: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

OFFSET3_EN

Bit 31: OFFSET3_EN.

OFR4

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw 		OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-11: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

OFFSET4_EN

Bit 31: OFFSET4_EN.

JDR1

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA1
r
Toggle fields

JDATA1

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA2
r
Toggle fields

JDATA2

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA3
r
Toggle fields

JDATA3

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA4
r
Toggle fields

JDATA4

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle fields

AWD2CH

Bits 0-17: AWD2CH.

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle fields

AWD3CH

Bits 0-17: AWD3CH.

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_16_18
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_1_15
rw
Toggle fields

DIFSEL_1_15

Bits 1-15: Differential mode for channels 15 to 1.

DIFSEL_16_18

Bits 16-18: Differential mode for channels 18 to 16.

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

CALFACT_D

Bits 16-22: CALFACT_D.

ADC_Common

0x50040300: Analog-to-Digital Converter

24/33 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x8 CCR
0xc CDR
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQOVF_SLV
r 		AWD3_SLV
r 		AWD2_SLV
r 		AWD1_SLV
r 		JEOS_SLV
r 		JEOC_SLV
r 		OVR_SLV
r 		EOS_SLV
r 		EOC_SLV
r 		EOSMP_SLV
r 		ADRDY_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF_MST
r 		AWD3_MST
r 		AWD2_MST
r 		AWD1_MST
r 		JEOS_MST
r 		JEOC_MST
r 		OVR_MST
r 		EOS_MST
r 		EOC_MST
r 		EOSMP_MST
r 		ADDRDY_MST
r
Toggle fields

ADDRDY_MST

Bit 0: ADDRDY_MST.

EOSMP_MST

Bit 1: EOSMP_MST.

EOC_MST

Bit 2: EOC_MST.

EOS_MST

Bit 3: EOS_MST.

OVR_MST

Bit 4: OVR_MST.

JEOC_MST

Bit 5: JEOC_MST.

JEOS_MST

Bit 6: JEOS_MST.

AWD1_MST

Bit 7: AWD1_MST.

AWD2_MST

Bit 8: AWD2_MST.

AWD3_MST

Bit 9: AWD3_MST.

JQOVF_MST

Bit 10: JQOVF_MST.

ADRDY_SLV

Bit 16: ADRDY_SLV.

EOSMP_SLV

Bit 17: EOSMP_SLV.

EOC_SLV

Bit 18: End of regular conversion of the slave ADC.

EOS_SLV

Bit 19: End of regular sequence flag of the slave ADC.

OVR_SLV

Bit 20: Overrun flag of the slave ADC.

JEOC_SLV

Bit 21: End of injected conversion flag of the slave ADC.

JEOS_SLV

Bit 22: End of injected sequence flag of the slave ADC.

AWD1_SLV

Bit 23: Analog watchdog 1 flag of the slave ADC.

AWD2_SLV

Bit 24: Analog watchdog 2 flag of the slave ADC.

AWD3_SLV

Bit 25: Analog watchdog 3 flag of the slave ADC.

JQOVF_SLV

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH18SEL
rw 		CH17SEL
rw 		VREFEN
rw 		PRESC
rw 		CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMA
rw 		DMACFG
rw 		DELAY
rw 		DUAL
rw
Toggle fields

DUAL

Bits 0-4: Dual ADC mode selection.

DELAY

Bits 8-11: Delay between 2 sampling phases.

DMACFG

Bit 13: DMA configuration (for multi-ADC mode).

MDMA

Bits 14-15: Direct memory access mode for multi ADC mode.

CKMODE

Bits 16-17: ADC clock mode.

PRESC

Bits 18-21: ADC prescaler.

VREFEN

Bit 22: VREFINT enable.

CH17SEL

Bit 23: CH17 selection.

CH18SEL

Bit 24: CH18 selection.

CDR

ADC common regular data register for dual and triple modes

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle fields

RDATA_MST

Bits 0-15: Regular data of the master ADC.

RDATA_SLV

Bits 16-31: Regular data of the slave ADC.

AES

0x50060000: Advanced encryption standard hardware accelerator

4/23 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DINR
0xc DOUTR
0x10 KEYR0
0x14 KEYR1
0x18 KEYR2
0x1c KEYR3
0x20 IVR0
0x24 IVR1
0x28 IVR2
0x2c IVR3
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAOUTEN
rw 		DMAINEN
rw 		ERRIE
rw 		CCFIE
rw 		ERRC
rw 		CCFC
rw 		CHMOD
rw 		MODE
rw 		DATATYPE
rw 		EN
rw
Toggle fields

EN

Bit 0: AES enable.

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

MODE

Bits 3-4: AES operating mode.

CHMOD

Bits 5-6: AES chaining mode.

CCFC

Bit 7: Computation Complete Flag Clear.

ERRC

Bit 8: Error clear.

CCFIE

Bit 9: CCF flag interrupt enable.

ERRIE

Bit 10: Error interrupt enable.

DMAINEN

Bit 11: Enable DMA management of data input phase.

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRERR
r 		RDERR
r 		CCF
r
Toggle fields

CCF

Bit 0: Computation complete flag.

RDERR

Bit 1: Read error flag.

WRERR

Bit 2: Write error flag.

DINR

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_DINR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_DINR
rw
Toggle fields

AES_DINR

Bits 0-31: Data Input Register.

DOUTR

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_DOUTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_DOUTR
r
Toggle fields

AES_DOUTR

Bits 0-31: Data output register.

KEYR0

key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR0
rw
Toggle fields

AES_KEYR0

Bits 0-31: Data Output Register (LSB key [31:0]).

KEYR1

key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR1
rw
Toggle fields

AES_KEYR1

Bits 0-31: AES key register (key [63:32]).

KEYR2

key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR2
rw
Toggle fields

AES_KEYR2

Bits 0-31: AES key register (key [95:64]).

KEYR3

key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR3
rw
Toggle fields

AES_KEYR3

Bits 0-31: AES key register (MSB key [127:96]).

IVR0

initialization vector register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR0
rw
Toggle fields

AES_IVR0

Bits 0-31: initialization vector register (LSB IVR [31:0]).

IVR1

initialization vector register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR1
rw
Toggle fields

AES_IVR1

Bits 0-31: Initialization Vector Register (IVR [63:32]).

IVR2

initialization vector register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR2
rw
Toggle fields

AES_IVR2

Bits 0-31: Initialization Vector Register (IVR [95:64]).

IVR3

initialization vector register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR3
rw
Toggle fields

AES_IVR3

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

CAN1

0x40006400: Controller area network

82/323 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MCR
0x4 MSR
0x8 TSR
0xc RF[0]R
0x10 RF[1]R
0x14 IER
0x18 ESR
0x1c BTR
0x180 TIR [0]
0x184 TDTR [0]
0x188 TDLR [0]
0x18c TDHR [0]
0x190 TIR [1]
0x194 TDTR [1]
0x198 TDLR [1]
0x19c TDHR [1]
0x1a0 TIR [2]
0x1a4 TDTR [2]
0x1a8 TDLR [2]
0x1ac TDHR [2]
0x1b0 RIR [0]
0x1b4 RDTR [0]
0x1b8 RDLR [0]
0x1bc RDHR [0]
0x1c0 RIR [1]
0x1c4 RDTR [1]
0x1c8 RDLR [1]
0x1cc RDHR [1]
0x200 FMR
0x204 FM1R
0x20c FS1R
0x214 FFA1R
0x21c FA1R
0x240 FR1 [0]
0x244 FR2 [0]
0x248 FR1 [1]
0x24c FR2 [1]
0x250 FR1 [2]
0x254 FR2 [2]
0x258 FR1 [3]
0x25c FR2 [3]
0x260 FR1 [4]
0x264 FR2 [4]
0x268 FR1 [5]
0x26c FR2 [5]
0x270 FR1 [6]
0x274 FR2 [6]
0x278 FR1 [7]
0x27c FR2 [7]
0x280 FR1 [8]
0x284 FR2 [8]
0x288 FR1 [9]
0x28c FR2 [9]
0x290 FR1 [10]
0x294 FR2 [10]
0x298 FR1 [11]
0x29c FR2 [11]
0x2a0 FR1 [12]
0x2a4 FR2 [12]
0x2a8 FR1 [13]
0x2ac FR2 [13]
0x2b0 FR1 [14]
0x2b4 FR2 [14]
0x2b8 FR1 [15]
0x2bc FR2 [15]
0x2c0 FR1 [16]
0x2c4 FR2 [16]
0x2c8 FR1 [17]
0x2cc FR2 [17]
0x2d0 FR1 [18]
0x2d4 FR2 [18]
0x2d8 FR1 [19]
0x2dc FR2 [19]
0x2e0 FR1 [20]
0x2e4 FR2 [20]
0x2e8 FR1 [21]
0x2ec FR2 [21]
0x2f0 FR1 [22]
0x2f4 FR2 [22]
0x2f8 FR1 [23]
0x2fc FR2 [23]
0x300 FR1 [24]
0x304 FR2 [24]
0x308 FR1 [25]
0x30c FR2 [25]
0x310 FR1 [26]
0x314 FR2 [26]
0x318 FR1 [27]
0x31c FR2 [27]
Toggle registers

MCR

master control register

Offset: 0x0, size: 32, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
rw 		TTCM
rw 		ABOM
rw 		AWUM
rw 		NART
rw 		RFLM
rw 		TXFP
rw 		SLEEP
rw 		INRQ
rw
Toggle fields

INRQ

Bit 0: INRQ.

SLEEP

Bit 1: SLEEP.

TXFP

Bit 2: TXFP.

RFLM

Bit 3: RFLM.

NART

Bit 4: NART.

AWUM

Bit 5: AWUM.

ABOM

Bit 6: ABOM.

TTCM

Bit 7: TTCM.

RESET

Bit 15: RESET.

DBF

Bit 16: DBF.

MSR

master status register

Offset: 0x4, size: 32, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r 		SAMP
r 		RXM
r 		TXM
r 		SLAKI
rw 		WKUI
rw 		ERRI
rw 		SLAK
r 		INAK
r
Toggle fields

INAK

Bit 0: INAK.

SLAK

Bit 1: SLAK.

ERRI

Bit 2: ERRI.

WKUI

Bit 3: WKUI.

SLAKI

Bit 4: SLAKI.

TXM

Bit 8: TXM.

RXM

Bit 9: RXM.

SAMP

Bit 10: SAMP.

RX

Bit 11: RX.

TSR

transmit status register

Offset: 0x8, size: 32, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOW[2]
r 		LOW[1]
r 		LOW[0]
r 		TME[2]
r 		TME[1]
r 		TME[0]
r 		CODE
r 		ABRQ2
rw 		TERR2
rw 		ALST2
rw 		TXOK2
rw 		RQCP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRQ1
rw 		TERR1
rw 		ALST1
rw 		TXOK1
rw 		RQCP1
rw 		ABRQ0
rw 		TERR0
rw 		ALST0
rw 		TXOK0
rw 		RQCP0
rw
Toggle fields

RQCP0

Bit 0: RQCP0.

TXOK0

Bit 1: TXOK0.

ALST0

Bit 2: ALST0.

TERR0

Bit 3: TERR0.

ABRQ0

Bit 7: ABRQ0.

RQCP1

Bit 8: RQCP1.

TXOK1

Bit 9: TXOK1.

ALST1

Bit 10: ALST1.

TERR1

Bit 11: TERR1.

ABRQ1

Bit 15: ABRQ1.

RQCP2

Bit 16: RQCP2.

TXOK2

Bit 17: TXOK2.

ALST2

Bit 18: ALST2.

TERR2

Bit 19: TERR2.

ABRQ2

Bit 23: ABRQ2.

CODE

Bits 24-25: CODE.

TME[0]

Bit 26: Lowest priority flag for mailbox 0.

TME[1]

Bit 27: Lowest priority flag for mailbox 1.

TME[2]

Bit 28: Lowest priority flag for mailbox 2.

LOW[0]

Bit 29: Lowest priority flag for mailbox 0.

LOW[1]

Bit 30: Lowest priority flag for mailbox 1.

LOW[2]

Bit 31: Lowest priority flag for mailbox 2.

RF[0]R

receive FIFO 0 register

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM
rw 		FOVR
rw 		FULL
rw 		FMP
r
Toggle fields

FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

RF[1]R

receive FIFO 1 register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM
rw 		FOVR
rw 		FULL
rw 		FMP
r
Toggle fields

FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

IER

interrupt enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw 		WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		LECIE
rw 		BOFIE
rw 		EPVIE
rw 		EWGIE
rw 		FOVIE1
rw 		FFIE1
rw 		FMPIE1
rw 		FOVIE0
rw 		FFIE0
rw 		FMPIE0
rw 		TMEIE
rw
Toggle fields

TMEIE

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

FMPIE0

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE0

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE0

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

FMPIE1

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE1

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE1

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

EWGIE

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

EPVIE

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

BOFIE

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

LECIE

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

ERRIE

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

WKUIE

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

SLKIE

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

ESR

interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r 		TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw 		BOFF
r 		EPVF
r 		EWGF
r
Toggle fields

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

bit timing register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw 		LBKM
rw 		SJW
rw 		TS2
rw 		TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle fields

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SILM

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

TIR [0]

TX mailbox identifier register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [0]

mailbox data length control and time stamp register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [0]

mailbox data low register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
rw 		DATA[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
rw 		DATA[0]
rw
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [0]

mailbox data high register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
rw 		DATA[6]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
rw 		DATA[4]
rw
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

TIR [1]

TX mailbox identifier register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [1]

mailbox data length control and time stamp register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [1]

mailbox data low register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
rw 		DATA[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
rw 		DATA[0]
rw
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [1]

mailbox data high register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
rw 		DATA[6]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
rw 		DATA[4]
rw
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

TIR [2]

TX mailbox identifier register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
rw 		EXID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
rw 		IDE
rw 		RTR
rw 		TXRQ
rw
Toggle fields

TXRQ

Bit 0: TXRQ.

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

TDTR [2]

mailbox data length control and time stamp register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGT
rw 		DLC
rw
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

TGT

Bit 8: TGT.

TIME

Bits 16-31: TIME.

TDLR [2]

mailbox data low register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
rw 		DATA[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
rw 		DATA[0]
rw
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

TDHR [2]

mailbox data high register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
rw 		DATA[6]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
rw 		DATA[4]
rw
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

RIR [0]

receive FIFO mailbox identifier register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
r 		EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r 		IDE
r 		RTR
r
Toggle fields

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDTR [0]

mailbox data high register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMI
r 		DLC
r
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDLR [0]

mailbox data high register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
r 		DATA[2]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
r 		DATA[0]
r
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

RDHR [0]

receive FIFO mailbox data high register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
r 		DATA[6]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
r 		DATA[4]
r
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

RIR [1]

receive FIFO mailbox identifier register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STID
r 		EXID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXID
r 		IDE
r 		RTR
r
Toggle fields

RTR

Bit 1: RTR.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

IDE

Bit 2: IDE.

Allowed values:
0: Standard: Standard identifier
1: Extended: Extended identifier

EXID

Bits 3-20: EXID.

STID

Bits 21-31: STID.

RDTR [1]

mailbox data high register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMI
r 		DLC
r
Toggle fields

DLC

Bits 0-3: DLC.

Allowed values: 0x0-0x8

FMI

Bits 8-15: FMI.

TIME

Bits 16-31: TIME.

RDLR [1]

mailbox data high register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[3]
r 		DATA[2]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[1]
r 		DATA[0]
r
Toggle fields

DATA[0]

Bits 0-7: DATA0.

DATA[1]

Bits 8-15: DATA1.

DATA[2]

Bits 16-23: DATA2.

DATA[3]

Bits 24-31: DATA3.

RDHR [1]

receive FIFO mailbox data high register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[7]
r 		DATA[6]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[5]
r 		DATA[4]
r
Toggle fields

DATA[4]

Bits 0-7: DATA4.

DATA[5]

Bits 8-15: DATA5.

DATA[6]

Bits 16-23: DATA6.

DATA[7]

Bits 24-31: DATA7.

FMR

filter master register

Offset: 0x200, size: 32, reset: 0x2A1C0E01, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CANSB
rw 		FINIT
rw
Toggle fields

FINIT

Bit 0: Filter initialization mode.

CANSB

Bits 8-13: CAN start bank.

FM1R

filter mode register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBM[27]
rw 		FBM[26]
rw 		FBM[25]
rw 		FBM[24]
rw 		FBM[23]
rw 		FBM[22]
rw 		FBM[21]
rw 		FBM[20]
rw 		FBM[19]
rw 		FBM[18]
rw 		FBM[17]
rw 		FBM[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM[15]
rw 		FBM[14]
rw 		FBM[13]
rw 		FBM[12]
rw 		FBM[11]
rw 		FBM[10]
rw 		FBM[9]
rw 		FBM[8]
rw 		FBM[7]
rw 		FBM[6]
rw 		FBM[5]
rw 		FBM[4]
rw 		FBM[3]
rw 		FBM[2]
rw 		FBM[1]
rw 		FBM[0]
rw
Toggle fields

FBM[0]

Bit 0: Filter mode.

FBM[1]

Bit 1: Filter mode.

FBM[2]

Bit 2: Filter mode.

FBM[3]

Bit 3: Filter mode.

FBM[4]

Bit 4: Filter mode.

FBM[5]

Bit 5: Filter mode.

FBM[6]

Bit 6: Filter mode.

FBM[7]

Bit 7: Filter mode.

FBM[8]

Bit 8: Filter mode.

FBM[9]

Bit 9: Filter mode.

FBM[10]

Bit 10: Filter mode.

FBM[11]

Bit 11: Filter mode.

FBM[12]

Bit 12: Filter mode.

FBM[13]

Bit 13: Filter mode.

FBM[14]

Bit 14: Filter mode.

FBM[15]

Bit 15: Filter mode.

FBM[16]

Bit 16: Filter mode.

FBM[17]

Bit 17: Filter mode.

FBM[18]

Bit 18: Filter mode.

FBM[19]

Bit 19: Filter mode.

FBM[20]

Bit 20: Filter mode.

FBM[21]

Bit 21: Filter mode.

FBM[22]

Bit 22: Filter mode.

FBM[23]

Bit 23: Filter mode.

FBM[24]

Bit 24: Filter mode.

FBM[25]

Bit 25: Filter mode.

FBM[26]

Bit 26: Filter mode.

FBM[27]

Bit 27: Filter mode.

FS1R

filter scale register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSC[27]
rw 		FSC[26]
rw 		FSC[25]
rw 		FSC[24]
rw 		FSC[23]
rw 		FSC[22]
rw 		FSC[21]
rw 		FSC[20]
rw 		FSC[19]
rw 		FSC[18]
rw 		FSC[17]
rw 		FSC[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC[15]
rw 		FSC[14]
rw 		FSC[13]
rw 		FSC[12]
rw 		FSC[11]
rw 		FSC[10]
rw 		FSC[9]
rw 		FSC[8]
rw 		FSC[7]
rw 		FSC[6]
rw 		FSC[5]
rw 		FSC[4]
rw 		FSC[3]
rw 		FSC[2]
rw 		FSC[1]
rw 		FSC[0]
rw
Toggle fields

FSC[0]

Bit 0: Filter scale configuration.

FSC[1]

Bit 1: Filter scale configuration.

FSC[2]

Bit 2: Filter scale configuration.

FSC[3]

Bit 3: Filter scale configuration.

FSC[4]

Bit 4: Filter scale configuration.

FSC[5]

Bit 5: Filter scale configuration.

FSC[6]

Bit 6: Filter scale configuration.

FSC[7]

Bit 7: Filter scale configuration.

FSC[8]

Bit 8: Filter scale configuration.

FSC[9]

Bit 9: Filter scale configuration.

FSC[10]

Bit 10: Filter scale configuration.

FSC[11]

Bit 11: Filter scale configuration.

FSC[12]

Bit 12: Filter scale configuration.

FSC[13]

Bit 13: Filter scale configuration.

FSC[14]

Bit 14: Filter scale configuration.

FSC[15]

Bit 15: Filter scale configuration.

FSC[16]

Bit 16: Filter scale configuration.

FSC[17]

Bit 17: Filter scale configuration.

FSC[18]

Bit 18: Filter scale configuration.

FSC[19]

Bit 19: Filter scale configuration.

FSC[20]

Bit 20: Filter scale configuration.

FSC[21]

Bit 21: Filter scale configuration.

FSC[22]

Bit 22: Filter scale configuration.

FSC[23]

Bit 23: Filter scale configuration.

FSC[24]

Bit 24: Filter scale configuration.

FSC[25]

Bit 25: Filter scale configuration.

FSC[26]

Bit 26: Filter scale configuration.

FSC[27]

Bit 27: Filter scale configuration.

FFA1R

filter FIFO assignment register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FFA[27]
rw 		FFA[26]
rw 		FFA[25]
rw 		FFA[24]
rw 		FFA[23]
rw 		FFA[22]
rw 		FFA[21]
rw 		FFA[20]
rw 		FFA[19]
rw 		FFA[18]
rw 		FFA[17]
rw 		FFA[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA[15]
rw 		FFA[14]
rw 		FFA[13]
rw 		FFA[12]
rw 		FFA[11]
rw 		FFA[10]
rw 		FFA[9]
rw 		FFA[8]
rw 		FFA[7]
rw 		FFA[6]
rw 		FFA[5]
rw 		FFA[4]
rw 		FFA[3]
rw 		FFA[2]
rw 		FFA[1]
rw 		FFA[0]
rw
Toggle fields

FFA[0]

Bit 0: Filter FIFO assignment for filter 0.

FFA[1]

Bit 1: Filter FIFO assignment for filter 1.

FFA[2]

Bit 2: Filter FIFO assignment for filter 2.

FFA[3]

Bit 3: Filter FIFO assignment for filter 3.

FFA[4]

Bit 4: Filter FIFO assignment for filter 4.

FFA[5]

Bit 5: Filter FIFO assignment for filter 5.

FFA[6]

Bit 6: Filter FIFO assignment for filter 6.

FFA[7]

Bit 7: Filter FIFO assignment for filter 7.

FFA[8]

Bit 8: Filter FIFO assignment for filter 8.

FFA[9]

Bit 9: Filter FIFO assignment for filter 9.

FFA[10]

Bit 10: Filter FIFO assignment for filter 10.

FFA[11]

Bit 11: Filter FIFO assignment for filter 11.

FFA[12]

Bit 12: Filter FIFO assignment for filter 12.

FFA[13]

Bit 13: Filter FIFO assignment for filter 13.

FFA[14]

Bit 14: Filter FIFO assignment for filter 14.

FFA[15]

Bit 15: Filter FIFO assignment for filter 15.

FFA[16]

Bit 16: Filter FIFO assignment for filter 16.

FFA[17]

Bit 17: Filter FIFO assignment for filter 17.

FFA[18]

Bit 18: Filter FIFO assignment for filter 18.

FFA[19]

Bit 19: Filter FIFO assignment for filter 19.

FFA[20]

Bit 20: Filter FIFO assignment for filter 20.

FFA[21]

Bit 21: Filter FIFO assignment for filter 21.

FFA[22]

Bit 22: Filter FIFO assignment for filter 22.

FFA[23]

Bit 23: Filter FIFO assignment for filter 23.

FFA[24]

Bit 24: Filter FIFO assignment for filter 24.

FFA[25]

Bit 25: Filter FIFO assignment for filter 25.

FFA[26]

Bit 26: Filter FIFO assignment for filter 26.

FFA[27]

Bit 27: Filter FIFO assignment for filter 27.

FA1R

filter activation register

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FACT[27]
rw 		FACT[26]
rw 		FACT[25]
rw 		FACT[24]
rw 		FACT[23]
rw 		FACT[22]
rw 		FACT[21]
rw 		FACT[20]
rw 		FACT[19]
rw 		FACT[18]
rw 		FACT[17]
rw 		FACT[16]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT[15]
rw 		FACT[14]
rw 		FACT[13]
rw 		FACT[12]
rw 		FACT[11]
rw 		FACT[10]
rw 		FACT[9]
rw 		FACT[8]
rw 		FACT[7]
rw 		FACT[6]
rw 		FACT[5]
rw 		FACT[4]
rw 		FACT[3]
rw 		FACT[2]
rw 		FACT[1]
rw 		FACT[0]
rw
Toggle fields

FACT[0]

Bit 0: Filter active.

FACT[1]

Bit 1: Filter active.

FACT[2]

Bit 2: Filter active.

FACT[3]

Bit 3: Filter active.

FACT[4]

Bit 4: Filter active.

FACT[5]

Bit 5: Filter active.

FACT[6]

Bit 6: Filter active.

FACT[7]

Bit 7: Filter active.

FACT[8]

Bit 8: Filter active.

FACT[9]

Bit 9: Filter active.

FACT[10]

Bit 10: Filter active.

FACT[11]

Bit 11: Filter active.

FACT[12]

Bit 12: Filter active.

FACT[13]

Bit 13: Filter active.

FACT[14]

Bit 14: Filter active.

FACT[15]

Bit 15: Filter active.

FACT[16]

Bit 16: Filter active.

FACT[17]

Bit 17: Filter active.

FACT[18]

Bit 18: Filter active.

FACT[19]

Bit 19: Filter active.

FACT[20]

Bit 20: Filter active.

FACT[21]

Bit 21: Filter active.

FACT[22]

Bit 22: Filter active.

FACT[23]

Bit 23: Filter active.

FACT[24]

Bit 24: Filter active.

FACT[25]

Bit 25: Filter active.

FACT[26]

Bit 26: Filter active.

FACT[27]

Bit 27: Filter active.

FR1 [0]

Filter bank x register 1

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [0]

Filter bank x register 2

Offset: 0x244, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [1]

Filter bank x register 1

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [1]

Filter bank x register 2

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [2]

Filter bank x register 1

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [2]

Filter bank x register 2

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [3]

Filter bank x register 1

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [3]

Filter bank x register 2

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [4]

Filter bank x register 1

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [4]

Filter bank x register 2

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [5]

Filter bank x register 1

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [5]

Filter bank x register 2

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [6]

Filter bank x register 1

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [6]

Filter bank x register 2

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [7]

Filter bank x register 1

Offset: 0x278, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [7]

Filter bank x register 2

Offset: 0x27c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [8]

Filter bank x register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [8]

Filter bank x register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [9]

Filter bank x register 1

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [9]

Filter bank x register 2

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [10]

Filter bank x register 1

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [10]

Filter bank x register 2

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [11]

Filter bank x register 1

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [11]

Filter bank x register 2

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [12]

Filter bank x register 1

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [12]

Filter bank x register 2

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [13]

Filter bank x register 1

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [13]

Filter bank x register 2

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [14]

Filter bank x register 1

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [14]

Filter bank x register 2

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [15]

Filter bank x register 1

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [15]

Filter bank x register 2

Offset: 0x2bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [16]

Filter bank x register 1

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [16]

Filter bank x register 2

Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [17]

Filter bank x register 1

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [17]

Filter bank x register 2

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [18]

Filter bank x register 1

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [18]

Filter bank x register 2

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [19]

Filter bank x register 1

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [19]

Filter bank x register 2

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [20]

Filter bank x register 1

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [20]

Filter bank x register 2

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [21]

Filter bank x register 1

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [21]

Filter bank x register 2

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [22]

Filter bank x register 1

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [22]

Filter bank x register 2

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [23]

Filter bank x register 1

Offset: 0x2f8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [23]

Filter bank x register 2

Offset: 0x2fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [24]

Filter bank x register 1

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [24]

Filter bank x register 2

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [25]

Filter bank x register 1

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [25]

Filter bank x register 2

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [26]

Filter bank x register 1

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [26]

Filter bank x register 2

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR1 [27]

Filter bank x register 1

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

FR2 [27]

Filter bank x register 2

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB
rw
Toggle fields

FB

Bits 0-31: Filter bits.

COMP

0x40010200: Comparator

2/23 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 COMP1_CSR
0x4 COMP2_CSR
Toggle registers

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP1_LOCK
w 		COMP1_VALUE
r 		COMP1_SCALEN
rw 		COMP1_BRGEN
rw 		COMP1_BLANKING
rw 		COMP1_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP1_POLARITY
rw 		COMP1_INPSEL
rw 		COMP1_INMSEL
rw 		COMP1_PWRMODE
rw 		COMP1_EN
rw
Toggle fields

COMP1_EN

Bit 0: Comparator 1 enable bit.

COMP1_PWRMODE

Bits 2-3: Power Mode of the comparator 1.

COMP1_INMSEL

Bits 4-6: Comparator 1 Input Minus connection configuration bit.

COMP1_INPSEL

Bit 7: Comparator1 input plus selection bit.

COMP1_POLARITY

Bit 15: Comparator 1 polarity selection bit.

COMP1_HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

COMP1_BLANKING

Bits 18-20: Comparator 1 blanking source selection bits.

COMP1_BRGEN

Bit 22: Scaler bridge enable.

COMP1_SCALEN

Bit 23: Voltage scaler enable bit.

COMP1_VALUE

Bit 30: Comparator 1 output status bit.

COMP1_LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP2_LOCK
w 		COMP2_VALUE
r 		COMP2_SCALEN
rw 		COMP2_BRGEN
rw 		COMP2_BLANKING
rw 		COMP2_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP2_POLARITY
rw 		COMP2_WINMODE
rw 		COMP2_INPSEL
rw 		COMP2_INMSEL
rw 		COMP2_PWRMODE
rw 		COMP2_EN
rw
Toggle fields

COMP2_EN

Bit 0: Comparator 2 enable bit.

COMP2_PWRMODE

Bits 2-3: Power Mode of the comparator 2.

COMP2_INMSEL

Bits 4-6: Comparator 2 Input Minus connection configuration bit.

COMP2_INPSEL

Bit 7: Comparator 2 Input Plus connection configuration bit.

COMP2_WINMODE

Bit 9: Windows mode selection bit.

COMP2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COMP2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

COMP2_BRGEN

Bit 22: Scaler bridge enable.

COMP2_SCALEN

Bit 23: Voltage scaler enable bit.

COMP2_VALUE

Bit 30: Comparator 2 output status bit.

COMP2_LOCK

Bit 31: COMP2_CSR register lock bit.

CRC

0x40023000: Cyclic redundancy check calculation unit

10/10 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x0 (16-bit) DR16
0x0 (8-bit) DR8
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data register bits.

Allowed values: 0x0-0xffffffff

DR16

Data register - half-word sized

Offset: 0x0, size: 16, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR16
rw
Toggle fields

DR16

Bits 0-15: Data register bits.

Allowed values: 0x0-0xffff

DR8

Data register - byte sized

Offset: 0x0, size: 8, reset: 0x000000FF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR8
rw
Toggle fields

DR8

Bits 0-7: Data register bits.

Allowed values: 0x0-0xff

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-7: General-purpose 8-bit data register bits.

Allowed values: 0x0-0xff

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
w
Toggle fields

RESET

Bit 0: RESET bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

POLYSIZE

Bits 3-4: Polynomial size.

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

REV_IN

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw
Toggle fields

INIT

Bits 0-31: Programmable initial CRC value.

Allowed values: 0x0-0xffffffff

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle fields

POL

Bits 0-31: Programmable polynomial.

Allowed values: 0x0-0xffffffff

CRS

0x40006000: Clock recovery system

9/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 ISR
0xc ICR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00002000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw 		SWSYNC
rw 		AUTOTRIMEN
rw 		CEN
rw 		ESYNCIE
rw 		ERRIE
rw 		SYNCWARNIE
rw 		SYNCOKIE
rw
Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-13: HSI48 oscillator smooth trimming.

CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL
rw 		SYNCSRC
rw 		SYNCDIV
rw 		FELIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEDIR
r 		TRIMOVF
r 		SYNCMISS
r 		SYNCERR
r 		ESYNCF
r 		ERRF
r 		SYNCWARNF
r 		SYNCOKF
r
Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ESYNCC
rw 		ERRC
rw 		SYNCWARNC
rw 		SYNCOKC
rw
Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

DAC

0x40007400: Digital-to-analog converter

6/48 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRIGR
0x8 DHR12R1
0xc DHR12L1
0x10 DHR8R1
0x14 DHR12R2
0x18 DHR12L2
0x1c DHR8R2
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR1
0x30 DOR2
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR1
0x44 SHSR2
0x48 SHHR
0x4c SHRR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN2
rw 		DMAUDRIE2
rw 		DMAEN2
rw 		MAMP2
rw 		WAVE2
rw 		TSEL2
rw 		TEN2
rw 		EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEN1
rw 		DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL1
rw 		TEN1
rw 		EN1
rw
Toggle fields

EN1

Bit 0: DAC channel1 enable.

TEN1

Bit 2: DAC channel1 trigger enable.

TSEL1

Bits 3-5: DAC channel1 trigger selection.

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

DMAEN1

Bit 12: DAC channel1 DMA enable.

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

CEN1

Bit 14: DAC Channel 1 calibration enable.

EN2

Bit 16: DAC channel2 enable.

TEN2

Bit 18: DAC channel2 trigger enable.

TSEL2

Bits 19-21: DAC channel2 trigger selection.

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

DMAEN2

Bit 28: DAC channel2 DMA enable.

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

CEN2

Bit 30: DAC Channel 2 calibration enable.

SWTRIGR

software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w 		SWTRIG1
w
Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger.

SWTRIG2

Bit 1: DAC channel2 software trigger.

DHR12R1

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DHR12L1

channel1 12-bit left-aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DHR8R1

channel1 8-bit right-aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DHR12R2

channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

DHR12L2

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

DHR8R2

channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw 		DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

DOR1

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output.

SR

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST2
r 		CAL_FLAG2
r 		DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST1
r 		CAL_FLAG1
r 		DMAUDR1
rw
Toggle fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

CAL_FLAG1

Bit 14: DAC Channel 1 calibration offset status.

BWST1

Bit 15: DAC Channel 1 busy writing sample time flag.

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

CAL_FLAG2

Bit 30: DAC Channel 2 calibration offset status.

BWST2

Bit 31: DAC Channel 2 busy writing sample time flag.

CCR

calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM1
rw
Toggle fields

OTRIM1

Bits 0-4: DAC Channel 1 offset trimming value.

OTRIM2

Bits 16-20: DAC Channel 2 offset trimming value.

MCR

mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE1
rw
Toggle fields

MODE1

Bits 0-2: DAC Channel 1 mode.

MODE2

Bits 16-18: DAC Channel 2 mode.

SHSR1

Sample and Hold sample time register 1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE1
rw
Toggle fields

TSAMPLE1

Bits 0-9: DAC Channel 1 sample Time.

SHSR2

Sample and Hold sample time register 2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE2
rw
Toggle fields

TSAMPLE2

Bits 0-9: DAC Channel 2 sample Time.

SHHR

Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD1
rw
Toggle fields

THOLD1

Bits 0-9: DAC Channel 1 hold Time.

THOLD2

Bits 16-25: DAC Channel 2 hold time.

SHRR

Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00000001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH1
rw
Toggle fields

TREFRESH1

Bits 0-7: DAC Channel 1 refresh Time.

TREFRESH2

Bits 16-23: DAC Channel 2 refresh Time.

DBGMCU

0xe0042000: Debug support

2/27 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IDCODE
0x4 CR
0x8 APB1FZR1
0xc APB1FZR2
0x10 APB2FZR
Toggle registers

IDCODE

MCU Device ID Code Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle fields

DEV_ID

Bits 0-15: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

CR

Debug MCU Configuration Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw 		TRACE_IOEN
rw 		DBG_STANDBY
rw 		DBG_STOP
rw 		DBG_SLEEP
rw
Toggle fields

DBG_SLEEP

Bit 0: Debug Sleep Mode.

DBG_STOP

Bit 1: Debug Stop Mode.

DBG_STANDBY

Bit 2: Debug Standby Mode.

TRACE_IOEN

Bit 5: Trace pin assignment control.

TRACE_MODE

Bits 6-7: Trace pin assignment control.

APB1FZR1

APB Low Freeze Register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIMER_STOP
rw 		DBG_CAN_STOP
rw 		DBG_I2C3_STOP
rw 		DBG_I2C2_STOP
rw 		DBG_I2C1_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw 		DBG_WWDG_STOP
rw 		DBG_RTC_STOP
rw 		DBG_TIM7_STOP
rw 		DBG_TIMER6_STOP
rw 		DBG_TIM5_STOP
rw 		DBG_TIM4_STOP
rw 		DBG_TIM3_STOP
rw 		DBG_TIMER2_STOP
rw
Toggle fields

DBG_TIMER2_STOP

Bit 0: Debug Timer 2 stopped when Core is halted.

DBG_TIM3_STOP

Bit 1: TIM3 counter stopped when core is halted.

DBG_TIM4_STOP

Bit 2: TIM4 counter stopped when core is halted.

DBG_TIM5_STOP

Bit 3: TIM5 counter stopped when core is halted.

DBG_TIMER6_STOP

Bit 4: Debug Timer 6 stopped when Core is halted.

DBG_TIM7_STOP

Bit 5: TIM7 counter stopped when core is halted.

DBG_RTC_STOP

Bit 10: Debug RTC stopped when Core is halted.

DBG_WWDG_STOP

Bit 11: Debug Window Wachdog stopped when Core is halted.

DBG_IWDG_STOP

Bit 12: Debug Independent Wachdog stopped when Core is halted.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout mode stopped when core is halted.

DBG_I2C2_STOP

Bit 22: I2C2 SMBUS timeout mode stopped when core is halted.

DBG_I2C3_STOP

Bit 23: I2C3 SMBUS timeout counter stopped when core is halted.

DBG_CAN_STOP

Bit 25: bxCAN stopped when core is halted.

DBG_LPTIMER_STOP

Bit 31: LPTIM1 counter stopped when core is halted.

APB1FZR2

APB Low Freeze Register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_LPTIM2_STOP
rw
Toggle fields

DBG_LPTIM2_STOP

Bit 5: LPTIM2 counter stopped when core is halted.

APB2FZR

APB High Freeze Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM17_STOP
rw 		DBG_TIM16_STOP
rw 		DBG_TIM15_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM8_STOP
rw 		DBG_TIM1_STOP
rw
Toggle fields

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM8_STOP

Bit 13: TIM8 counter stopped when core is halted.

DBG_TIM15_STOP

Bit 16: TIM15 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DBG_TIM17_STOP

Bit 18: TIM17 counter stopped when core is halted.

DCMI

0x50050000: Digital camera interface

17/54 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 RIS
0xc IER
0x10 MIS
0x14 ICR
0x18 ESCR
0x1c ESUR
0x20 CWSTRT
0x24 CWSIZE
0x28 DR
Toggle registers

CR

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OELS
rw 		LSM
rw 		OEBS
rw 		BSM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE
rw 		EDM
rw 		FCRC
rw 		VSPOL
rw 		HSPOL
rw 		PCKPOL
rw 		ESS
rw 		JPEG
rw 		CROP
rw 		CM
rw 		CAPTURE
rw
Toggle fields

CAPTURE

Bit 0: Capture enable.

CM

Bit 1: Capture mode.

CROP

Bit 2: Crop feature.

JPEG

Bit 3: JPEG format.

ESS

Bit 4: Embedded synchronization select.

PCKPOL

Bit 5: Pixel clock polarity.

HSPOL

Bit 6: Horizontal synchronization polarity.

VSPOL

Bit 7: Vertical synchronization polarity.

FCRC

Bits 8-9: Frame capture rate control.

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: DCMI enable.

BSM

Bits 16-17: Byte Select mode.

OEBS

Bit 18: Odd/Even Byte Select (Byte Select Start).

LSM

Bit 19: Line Select mode.

OELS

Bit 20: Odd/Even Line Select (Line Select Start).

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNE
r 		VSYNC
r 		HSYNC
r
Toggle fields

HSYNC

Bit 0: HSYNC.

VSYNC

Bit 1: VSYNC.

FNE

Bit 2: FIFO not empty.

RIS

raw interrupt status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_RIS
r 		VSYNC_RIS
r 		ERR_RIS
r 		OVR_RIS
r 		FRAME_RIS
r
Toggle fields

FRAME_RIS

Bit 0: Capture complete raw interrupt status.

OVR_RIS

Bit 1: Overrun raw interrupt status.

ERR_RIS

Bit 2: Synchronization error raw interrupt status.

VSYNC_RIS

Bit 3: VSYNC raw interrupt status.

LINE_RIS

Bit 4: Line raw interrupt status.

IER

interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_IE
rw 		VSYNC_IE
rw 		ERR_IE
rw 		OVR_IE
rw 		FRAME_IE
rw
Toggle fields

FRAME_IE

Bit 0: Capture complete interrupt enable.

OVR_IE

Bit 1: Overrun interrupt enable.

ERR_IE

Bit 2: Synchronization error interrupt enable.

VSYNC_IE

Bit 3: VSYNC interrupt enable.

LINE_IE

Bit 4: Line interrupt enable.

MIS

masked interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_MIS
r 		VSYNC_MIS
r 		ERR_MIS
r 		OVR_MIS
r 		FRAME_MIS
r
Toggle fields

FRAME_MIS

Bit 0: Capture complete masked interrupt status.

OVR_MIS

Bit 1: Overrun masked interrupt status.

ERR_MIS

Bit 2: Synchronization error masked interrupt status.

VSYNC_MIS

Bit 3: VSYNC masked interrupt status.

LINE_MIS

Bit 4: Line masked interrupt status.

ICR

interrupt clear register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_ISC
w 		VSYNC_ISC
w 		ERR_ISC
w 		OVR_ISC
w 		FRAME_ISC
w
Toggle fields

FRAME_ISC

Bit 0: Capture complete interrupt status clear.

OVR_ISC

Bit 1: Overrun interrupt status clear.

ERR_ISC

Bit 2: Synchronization error interrupt status clear.

VSYNC_ISC

Bit 3: Vertical synch interrupt status clear.

LINE_ISC

Bit 4: line interrupt status clear.

ESCR

embedded synchronization code register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
rw 		LEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSC
rw 		FSC
rw
Toggle fields

FSC

Bits 0-7: Frame start delimiter code.

LSC

Bits 8-15: Line start delimiter code.

LEC

Bits 16-23: Line end delimiter code.

FEC

Bits 24-31: Frame end delimiter code.

ESUR

embedded synchronization unmask register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEU
rw 		LEU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSU
rw 		FSU
rw
Toggle fields

FSU

Bits 0-7: Frame start delimiter unmask.

LSU

Bits 8-15: Line start delimiter unmask.

LEU

Bits 16-23: Line end delimiter unmask.

FEU

Bits 24-31: Frame end delimiter unmask.

CWSTRT

crop window start

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HOFFCNT
rw
Toggle fields

HOFFCNT

Bits 0-13: Horizontal offset count.

VST

Bits 16-28: Vertical start line count.

CWSIZE

crop window size

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLINE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCNT
rw
Toggle fields

CAPCNT

Bits 0-13: Capture count.

VLINE

Bits 16-29: Vertical line count.

DR

data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Byte3
r 		Byte2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Byte1
r 		Byte0
r
Toggle fields

Byte0

Bits 0-7: Data byte 0.

Byte1

Bits 8-15: Data byte 1.

Byte2

Bits 16-23: Data byte 2.

Byte3

Bits 24-31: Data byte 3.

DFSDM1

0x40016000: Digital filter for sigma delta modulators

84/379 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CH0CFGR1
0x4 CH0CFGR2
0x8 CH0AWSCDR
0xc CH0WDATR
0x10 CH0DATINR
0x14 CH0DLYR
0x20 CH1CFGR1
0x24 CH1CFGR2
0x28 CH1AWSCDR
0x2c CH1WDATR
0x30 CH1DATINR
0x34 CH1DLYR
0x40 CH2CFGR1
0x44 CH2CFGR2
0x48 CH2AWSCDR
0x4c CH2WDATR
0x50 CH2DATINR
0x54 CH2DLYR
0x60 CH3CFGR1
0x64 CH3CFGR2
0x68 CH3AWSCDR
0x6c CH3WDATR
0x70 CH3DATINR
0x74 CH3DLYR
0x80 CH4CFGR1
0x84 CH4CFGR2
0x88 CH4AWSCDR
0x8c CH4WDATR
0x90 CH4DATINR
0x94 CH4DLYR
0xa0 CH5CFGR1
0xa4 CH5CFGR2
0xa8 CH5AWSCDR
0xac CH5WDATR
0xb0 CH5DATINR
0xb4 CH5DLYR
0xc0 CH6CFGR1
0xc4 CH6CFGR2
0xc8 CH6AWSCDR
0xcc CH6WDATR
0xd0 CH6DATINR
0xd4 CH6DLYR
0xe0 CH7CFGR1
0xe4 CH7CFGR2
0xe8 CH7AWSCDR
0xec CH7WDATR
0xf0 CH7DATINR
0xf4 CH7DLYR
0x100 DFSDM_FLT0CR1
0x104 DFSDM_FLT0CR2
0x108 DFSDM_FLT0ISR
0x10c DFSDM_FLT0ICR
0x110 DFSDM_FLT0JCHGR
0x114 DFSDM_FLT0FCR
0x118 DFSDM_FLT0JDATAR
0x11c DFSDM_FLT0RDATAR
0x120 DFSDM_FLT0AWHTR
0x124 DFSDM_FLT0AWLTR
0x128 DFSDM_FLT0AWSR
0x12c DFSDM_FLT0AWCFR
0x130 DFSDM_FLT0EXMAX
0x134 DFSDM_FLT0EXMIN
0x138 DFSDM_FLT0CNVTIMR
0x180 DFSDM_FLT1CR1
0x184 DFSDM_FLT1CR2
0x188 DFSDM_FLT1ISR
0x18c DFSDM_FLT1ICR
0x190 DFSDM_FLT1CHGR
0x194 DFSDM_FLT1FCR
0x198 DFSDM_FLT1JDATAR
0x19c DFSDM_FLT1RDATAR
0x1a0 DFSDM_FLT1AWHTR
0x1a4 DFSDM_FLT1AWLTR
0x1a8 DFSDM_FLT1AWSR
0x1ac DFSDM_FLT1AWCFR
0x1b0 DFSDM_FLT1EXMAX
0x1b4 DFSDM_FLT1EXMIN
0x1b8 DFSDM_FLT1CNVTIMR
0x200 DFSDM_FLT2CR1
0x204 DFSDM_FLT2CR2
0x208 DFSDM_FLT2ISR
0x20c DFSDM_FLT2ICR
0x210 DFSDM_FLT2JCHGR
0x214 DFSDM_FLT2FCR
0x218 DFSDM_FLT2JDATAR
0x21c DFSDM_FLT2RDATAR
0x220 DFSDM_FLT2AWHTR
0x224 DFSDM_FLT2AWLTR
0x228 DFSDM_FLT2AWSR
0x22c DFSDM_FLT2AWCFR
0x230 DFSDM_FLT2EXMAX
0x234 DFSDM_FLT2EXMIN
0x238 DFSDM_FLT2CNVTIMR
0x280 DFSDM_FLT3CR1
0x284 DFSDM_FLT3CR2
0x288 DFSDM_FLT3ISR
0x28c DFSDM_FLT3ICR
0x290 DFSDM_FLT3JCHGR
0x294 DFSDM_FLT3FCR
0x298 DFSDM_FLT3JDATAR
0x29c DFSDM_FLT3RDATAR
0x2a0 DFSDM_FLT3AWHTR
0x2a4 DFSDM_FLT3AWLTR
0x2a8 DFSDM_FLT3AWSR
0x2ac DFSDM_FLT3AWCFR
0x2b0 DFSDM_FLT3EXMAX
0x2b4 DFSDM_FLT3EXMIN
0x2b8 DFSDM_FLT3CNVTIMR
Toggle registers

CH0CFGR1

channel configuration y register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH0CFGR2

channel configuration y register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH0AWSCDR

analog watchdog and short-circuit detector register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH0WDATR

channel watchdog filter data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH0DATINR

channel data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH0DLYR

channel y delay register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH1CFGR1

CH1CFGR1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CH1CFGR2

CH1CFGR2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH1AWSCDR

CH1AWSCDR

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH1WDATR

CH1WDATR

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH1DATINR

CH1DATINR

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH1DLYR

channel y delay register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH2CFGR1

CH2CFGR1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CH2CFGR2

CH2CFGR2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH2AWSCDR

CH2AWSCDR

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH2WDATR

CH2WDATR

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH2DATINR

CH2DATINR

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH2DLYR

channel y delay register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH3CFGR1

CH3CFGR1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CH3CFGR2

CH3CFGR2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH3AWSCDR

CH3AWSCDR

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH3WDATR

CH3WDATR

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH3DATINR

CH3DATINR

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH3DLYR

channel y delay register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH4CFGR1

CH4CFGR1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CH4CFGR2

CH4CFGR2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH4AWSCDR

CH4AWSCDR

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH4WDATR

CH4WDATR

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH4DATINR

CH4DATINR

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH4DLYR

channel y delay register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH5CFGR1

CH5CFGR1

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CH5CFGR2

CH5CFGR2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH5AWSCDR

CH5AWSCDR

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH5WDATR

CH5WDATR

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH5DATINR

CH5DATINR

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH5DLYR

channel y delay register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH6CFGR1

CH6CFGR1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CH6CFGR2

CH6CFGR2

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH6AWSCDR

CH6AWSCDR

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH6WDATR

CH6WDATR

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH6DATINR

CH6DATINR

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH6DLYR

channel y delay register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH7CFGR1

CH7CFGR1

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CH7CFGR2

CH7CFGR2

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH7AWSCDR

CH7AWSCDR

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH7WDATR

CH7WDATR

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH7DATINR

CH7DATINR

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH7DLYR

channel y delay register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

DFSDM_FLT0CR1

control register 1

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

DFSDM_FLT0CR2

control register 2

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

DFSDM_FLT0ISR

interrupt and status register

Offset: 0x108, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

DFSDM_FLT0ICR

interrupt flag clear register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

DFSDM_FLT0JCHGR

injected channel group selection register

Offset: 0x110, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

DFSDM_FLT0FCR

filter control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

DFSDM_FLT0JDATAR

data register for injected group

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

DFSDM_FLT0RDATAR

data register for the regular channel

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

DFSDM_FLT0AWHTR

analog watchdog high threshold register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

DFSDM_FLT0AWLTR

analog watchdog low threshold register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

DFSDM_FLT0AWSR

analog watchdog status register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

DFSDM_FLT0AWCFR

analog watchdog clear flag register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

DFSDM_FLT0EXMAX

Extremes detector maximum register

Offset: 0x130, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

DFSDM_FLT0EXMIN

Extremes detector minimum register

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

DFSDM_FLT0CNVTIMR

conversion timer register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

DFSDM_FLT1CR1

control register 1

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

DFSDM_FLT1CR2

control register 2

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

DFSDM_FLT1ISR

interrupt and status register

Offset: 0x188, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

DFSDM_FLT1ICR

interrupt flag clear register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

DFSDM_FLT1CHGR

injected channel group selection register

Offset: 0x190, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

DFSDM_FLT1FCR

filter control register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

DFSDM_FLT1JDATAR

data register for injected group

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

DFSDM_FLT1RDATAR

data register for the regular channel

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

DFSDM_FLT1AWHTR

analog watchdog high threshold register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

DFSDM_FLT1AWLTR

analog watchdog low threshold register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

DFSDM_FLT1AWSR

analog watchdog status register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

DFSDM_FLT1AWCFR

analog watchdog clear flag register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

DFSDM_FLT1EXMAX

Extremes detector maximum register

Offset: 0x1b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

DFSDM_FLT1EXMIN

Extremes detector minimum register

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

DFSDM_FLT1CNVTIMR

conversion timer register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

DFSDM_FLT2CR1

control register 1

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

DFSDM_FLT2CR2

control register 2

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

DFSDM_FLT2ISR

interrupt and status register

Offset: 0x208, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

DFSDM_FLT2ICR

interrupt flag clear register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

DFSDM_FLT2JCHGR

injected channel group selection register

Offset: 0x210, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

DFSDM_FLT2FCR

filter control register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

DFSDM_FLT2JDATAR

data register for injected group

Offset: 0x218, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

DFSDM_FLT2RDATAR

data register for the regular channel

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

DFSDM_FLT2AWHTR

analog watchdog high threshold register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

DFSDM_FLT2AWLTR

analog watchdog low threshold register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

DFSDM_FLT2AWSR

analog watchdog status register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

DFSDM_FLT2AWCFR

analog watchdog clear flag register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

DFSDM_FLT2EXMAX

Extremes detector maximum register

Offset: 0x230, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

DFSDM_FLT2EXMIN

Extremes detector minimum register

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

DFSDM_FLT2CNVTIMR

conversion timer register

Offset: 0x238, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

DFSDM_FLT3CR1

control register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

DFSDM_FLT3CR2

control register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

DFSDM_FLT3ISR

interrupt and status register

Offset: 0x288, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

DFSDM_FLT3ICR

interrupt flag clear register

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

DFSDM_FLT3JCHGR

injected channel group selection register

Offset: 0x290, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

DFSDM_FLT3FCR

filter control register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

DFSDM_FLT3JDATAR

data register for injected group

Offset: 0x298, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

DFSDM_FLT3RDATAR

data register for the regular channel

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

DFSDM_FLT3AWHTR

analog watchdog high threshold register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

DFSDM_FLT3AWLTR

analog watchdog low threshold register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

DFSDM_FLT3AWSR

analog watchdog status register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

DFSDM_FLT3AWCFR

analog watchdog clear flag register

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

DFSDM_FLT3EXMAX

Extremes detector maximum register

Offset: 0x2b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

DFSDM_FLT3EXMIN

Extremes detector minimum register

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

DFSDM_FLT3CNVTIMR

conversion timer register

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

DMA1

0x40020000: Direct memory access controller

147/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 MAR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 MAR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c MAR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 MAR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 MAR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 MAR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c MAR [7]
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF[7]
r 		HTIF[7]
r 		TCIF[7]
r 		GIF[7]
r 		TEIF[6]
r 		HTIF[6]
r 		TCIF[6]
r 		GIF[6]
r 		TEIF[5]
r 		HTIF[5]
r 		TCIF[5]
r 		GIF[5]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF[4]
r 		HTIF[4]
r 		TCIF[4]
r 		GIF[4]
r 		TEIF[3]
r 		HTIF[3]
r 		TCIF[3]
r 		GIF[3]
r 		TEIF[2]
r 		HTIF[2]
r 		TCIF[2]
r 		GIF[2]
r 		TEIF[1]
r 		HTIF[1]
r 		TCIF[1]
r 		GIF[1]
r
Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF[7]
w 		CHTIF[7]
w 		CTCIF[7]
w 		CGIF[7]
w 		CTEIF[6]
w 		CHTIF[6]
w 		CTCIF[6]
w 		CGIF[6]
w 		CTEIF[5]
w 		CHTIF[5]
w 		CTCIF[5]
w 		CGIF[5]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF[4]
w 		CHTIF[4]
w 		CTCIF[4]
w 		CGIF[4]
w 		CTEIF[3]
w 		CHTIF[3]
w 		CTCIF[3]
w 		CGIF[3]
w 		CTEIF[2]
w 		CHTIF[2]
w 		CTCIF[2]
w 		CGIF[2]
w 		CTEIF[1]
w 		CHTIF[1]
w 		CTCIF[1]
w 		CGIF[1]
w
Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

DMA2

0x40020400: Direct memory access controller

147/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 MAR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 MAR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c MAR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 MAR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 MAR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 MAR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c MAR [7]
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF[7]
r 		HTIF[7]
r 		TCIF[7]
r 		GIF[7]
r 		TEIF[6]
r 		HTIF[6]
r 		TCIF[6]
r 		GIF[6]
r 		TEIF[5]
r 		HTIF[5]
r 		TCIF[5]
r 		GIF[5]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF[4]
r 		HTIF[4]
r 		TCIF[4]
r 		GIF[4]
r 		TEIF[3]
r 		HTIF[3]
r 		TCIF[3]
r 		GIF[3]
r 		TEIF[2]
r 		HTIF[2]
r 		TCIF[2]
r 		GIF[2]
r 		TEIF[1]
r 		HTIF[1]
r 		TCIF[1]
r 		GIF[1]
r
Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF[7]
w 		CHTIF[7]
w 		CTCIF[7]
w 		CGIF[7]
w 		CTEIF[6]
w 		CHTIF[6]
w 		CTCIF[6]
w 		CGIF[6]
w 		CTEIF[5]
w 		CHTIF[5]
w 		CTCIF[5]
w 		CGIF[5]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF[4]
w 		CHTIF[4]
w 		CTCIF[4]
w 		CGIF[4]
w 		CTEIF[3]
w 		CHTIF[3]
w 		CTCIF[3]
w 		CGIF[3]
w 		CTEIF[2]
w 		CHTIF[2]
w 		CTCIF[2]
w 		CGIF[2]
w 		CTEIF[1]
w 		CHTIF[1]
w 		CTCIF[1]
w 		CGIF[1]
w
Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

MAR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

DMA2D

0x4002b000: DMA2D controller

48/72 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ISR
0x8 IFCR
0xc FGMAR
0x10 FGOR
0x14 BGMAR
0x18 BGOR
0x1c FGPFCCR
0x20 FGCOLR
0x24 BGPFCCR
0x28 BGCOLR
0x2c FGCMAR
0x30 BGCMAR
0x34 OPFCCR
0x38 OCOLR
0x3c OMAR
0x40 OOR
0x44 NLR
0x48 LWR
0x4c AMTCR
0x400 FGCLUT
0x800 BGCLUT
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEIE
rw 		CTCIE
rw 		CAEIE
rw 		TWIE
rw 		TCIE
rw 		TEIE
rw 		ABORT
rw 		SUSP
rw 		START
rw
Toggle fields

START

Bit 0: Start.

Allowed values:
1: Start: Launch the DMA2D

SUSP

Bit 1: Suspend.

Allowed values:
0: NotSuspended: Transfer not suspended
1: Suspended: Transfer suspended

ABORT

Bit 2: Abort.

Allowed values:
1: AbortRequest: Transfer abort requested

TEIE

Bit 8: Transfer error interrupt enable.

Allowed values:
0: Disabled: TE interrupt disabled
1: Enabled: TE interrupt enabled

TCIE

Bit 9: Transfer complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TWIE

Bit 10: Transfer watermark interrupt enable.

Allowed values:
0: Disabled: TW interrupt disabled
1: Enabled: TW interrupt enabled

CAEIE

Bit 11: CLUT access error interrupt enable.

Allowed values:
0: Disabled: CAE interrupt disabled
1: Enabled: CAE interrupt enabled

CTCIE

Bit 12: CLUT transfer complete interrupt enable.

Allowed values:
0: Disabled: CTC interrupt disabled
1: Enabled: CTC interrupt enabled

CEIE

Bit 13: Configuration Error Interrupt Enable.

Allowed values:
0: Disabled: CE interrupt disabled
1: Enabled: CE interrupt enabled

MODE

Bits 16-17: DMA2D mode.

Allowed values:
0: MemoryToMemory: Memory-to-memory (FG fetch only)
1: MemoryToMemoryPFC: Memory-to-memory with PFC (FG fetch only with FG PFC active)
2: MemoryToMemoryPFCBlending: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
3: RegisterToMemory: Register-to-memory

ISR

Interrupt Status Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEIF
r 		CTCIF
r 		CAEIF
r 		TWIF
r 		TCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: Transfer error interrupt flag.

TCIF

Bit 1: Transfer complete interrupt flag.

TWIF

Bit 2: Transfer watermark interrupt flag.

CAEIF

Bit 3: CLUT access error interrupt flag.

CTCIF

Bit 4: CLUT transfer complete interrupt flag.

CEIF

Bit 5: Configuration error interrupt flag.

IFCR

interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCEIF
rw 		CCTCIF
rw 		CAECIF
rw 		CTWIF
rw 		CTCIF
rw 		CTEIF
rw
Toggle fields

CTEIF

Bit 0: Clear Transfer error interrupt flag.

Allowed values:
1: Clear: Clear the TEIF flag in the ISR register

CTCIF

Bit 1: Clear transfer complete interrupt flag.

Allowed values:
1: Clear: Clear the TCIF flag in the ISR register

CTWIF

Bit 2: Clear transfer watermark interrupt flag.

Allowed values:
1: Clear: Clear the TWIF flag in the ISR register

CAECIF

Bit 3: Clear CLUT access error interrupt flag.

Allowed values:
1: Clear: Clear the CAEIF flag in the ISR register

CCTCIF

Bit 4: Clear CLUT transfer complete interrupt flag.

Allowed values:
1: Clear: Clear the CTCIF flag in the ISR register

CCEIF

Bit 5: Clear configuration error interrupt flag.

Allowed values:
1: Clear: Clear the CEIF flag in the ISR register

FGMAR

foreground memory address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

FGOR

foreground offset register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-13: Line offset.

Allowed values: 0x0-0x3fff

BGMAR

background memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

BGOR

background offset register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-13: Line offset.

Allowed values: 0x0-0x3fff

FGPFCCR

foreground PFC control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA
rw 		RBS
rw 		AI
rw 		AM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
rw 		START
rw 		CCM
rw 		CM
rw
Toggle fields

CM

Bits 0-3: Color mode.

Allowed values:
0: ARGB8888: Color mode ARGB8888
1: RGB888: Color mode RGB888
2: RGB565: Color mode RGB565
3: ARGB1555: Color mode ARGB1555
4: ARGB4444: Color mode ARGB4444
5: L8: Color mode L8
6: AL44: Color mode AL44
7: AL88: Color mode AL88
8: L4: Color mode L4
9: A8: Color mode A8
10: A4: Color mode A4

CCM

Bit 4: CLUT color mode.

Allowed values:
0: ARGB8888: CLUT color format ARGB8888
1: RGB888: CLUT color format RGB888

START

Bit 5: Start.

Allowed values:
1: Start: Start the automatic loading of the CLUT

CS

Bits 8-15: CLUT size.

Allowed values: 0x0-0xff

AM

Bits 16-17: Alpha mode.

Allowed values:
0: NoModify: No modification of alpha channel
1: Replace: Replace with value in ALPHA[7:0]
2: Multiply: Multiply with value in ALPHA[7:0]

AI

Bit 20: Alpha Inverted.

RBS

Bit 21: Red Blue Swap.

ALPHA

Bits 24-31: Alpha value.

Allowed values: 0x0-0xff

FGCOLR

foreground color register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value.

Allowed values: 0x0-0xff

GREEN

Bits 8-15: Green Value.

Allowed values: 0x0-0xff

RED

Bits 16-23: Red Value.

Allowed values: 0x0-0xff

BGPFCCR

background PFC control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALPHA
rw 		RBS
rw 		AI
rw 		AM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
rw 		START
rw 		CCM
rw 		CM
rw
Toggle fields

CM

Bits 0-3: Color mode.

Allowed values:
0: ARGB8888: Color mode ARGB8888
1: RGB888: Color mode RGB888
2: RGB565: Color mode RGB565
3: ARGB1555: Color mode ARGB1555
4: ARGB4444: Color mode ARGB4444
5: L8: Color mode L8
6: AL44: Color mode AL44
7: AL88: Color mode AL88
8: L4: Color mode L4
9: A8: Color mode A8
10: A4: Color mode A4

CCM

Bit 4: CLUT Color mode.

Allowed values:
0: ARGB8888: CLUT color format ARGB8888
1: RGB888: CLUT color format RGB888

START

Bit 5: Start.

Allowed values:
1: Start: Start the automatic loading of the CLUT

CS

Bits 8-15: CLUT size.

Allowed values: 0x0-0xff

AM

Bits 16-17: Alpha mode.

Allowed values:
0: NoModify: No modification of alpha channel
1: Replace: Replace with value in ALPHA[7:0]
2: Multiply: Multiply with value in ALPHA[7:0]

AI

Bit 20: Alpha Inverted.

RBS

Bit 21: Red Blue Swap.

ALPHA

Bits 24-31: Alpha value.

Allowed values: 0x0-0xff

BGCOLR

background color register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value.

Allowed values: 0x0-0xff

GREEN

Bits 8-15: Green Value.

Allowed values: 0x0-0xff

RED

Bits 16-23: Red Value.

Allowed values: 0x0-0xff

FGCMAR

foreground CLUT memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory Address.

BGCMAR

background CLUT memory address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

OPFCCR

output PFC control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBS
rw 		AI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CM
rw
Toggle fields

CM

Bits 0-2: Color mode.

Allowed values:
0: ARGB8888: ARGB8888
1: RGB888: RGB888
2: RGB565: RGB565
3: ARGB1555: ARGB1555
4: ARGB4444: ARGB4444

AI

Bit 20: Alpha Inverted.

RBS

Bit 21: Red Blue Swap.

OCOLR

output color register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APLHA
rw 		RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: Blue Value.

GREEN

Bits 8-15: Green Value.

RED

Bits 16-23: Red Value.

APLHA

Bits 24-31: Alpha Channel Value.

OMAR

output memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory Address.

OOR

output offset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 0-13: Line Offset.

Allowed values: 0x0-0x3fff

NLR

number of line register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NL
rw
Toggle fields

NL

Bits 0-15: Number of lines.

Allowed values: 0x0-0xffff

PL

Bits 16-29: Pixel per lines.

Allowed values: 0x0-0x3fff

LWR

line watermark register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LW
rw
Toggle fields

LW

Bits 0-15: Line watermark.

AMTCR

AHB master timer configuration register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

Allowed values:
0: Disabled: Disabled AHB/AXI dead-time functionality
1: Enabled: Enabled AHB/AXI dead-time functionality

DT

Bits 8-15: Dead Time.

Allowed values: 0x0-0xff

FGCLUT

FGCLUT

Offset: 0x400, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APLHA
rw 		RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: BLUE.

GREEN

Bits 8-15: GREEN.

RED

Bits 16-23: RED.

APLHA

Bits 24-31: APLHA.

BGCLUT

BGCLUT

Offset: 0x800, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APLHA
rw 		RED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
rw 		BLUE
rw
Toggle fields

BLUE

Bits 0-7: BLUE.

GREEN

Bits 8-15: GREEN.

RED

Bits 16-23: RED.

APLHA

Bits 24-31: APLHA.

DMAMUX1

0x40020800: DMA request multiplexer

18/154 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR[0]
0x4 CCR[1]
0x8 CCR[2]
0xc CCR[3]
0x10 CCR[4]
0x14 CCR[5]
0x18 CCR[6]
0x1c CCR[7]
0x20 CCR[8]
0x24 CCR[9]
0x28 CCR[10]
0x2c CCR[11]
0x30 CCR[12]
0x34 CCR[13]
0x80 CSR
0x84 CFR
0x100 RGCR[0]
0x104 RGCR[1]
0x108 RGCR[2]
0x10c RGCR[3]
0x140 RGSR
0x144 RGCFR
Toggle registers

CCR[0]

DMA Multiplexer Channel 0 Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[1]

DMA Multiplexer Channel 1 Control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[2]

DMA Multiplexer Channel 2 Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[3]

DMA Multiplexer Channel 3 Control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[4]

DMA Multiplexer Channel 4 Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[5]

DMA Multiplexer Channel 5 Control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[6]

DMA Multiplexer Channel 6 Control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[7]

DMA Multiplexer Channel 7 Control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[8]

DMA Multiplexer Channel 8 Control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[9]

DMA Multiplexer Channel 9 Control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[10]

DMA Multiplexer Channel 10 Control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[11]

DMA Multiplexer Channel 11 Control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[12]

DMA Multiplexer Channel 12 Control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CCR[13]

DMA Multiplexer Channel 13 Control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA request identification.

SOIE

Bit 8: Synchronization overrun interrupt enable.

EGE

Bit 9: Event generation enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Synchronization polarity.

NBREQ

Bits 19-23: Number of DMA requests minus 1 to forward.

SYNC_ID

Bits 24-28: Synchronization identification.

CSR

channel status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

14/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF13
r 		SOF12
r 		SOF11
r 		SOF10
r 		SOF9
r 		SOF8
r 		SOF7
r 		SOF6
r 		SOF5
r 		SOF4
r 		SOF3
r 		SOF2
r 		SOF1
r 		SOF0
r
Toggle fields

SOF0

Bit 0: Synchronization overrun event flag.

SOF1

Bit 1: Synchronization overrun event flag.

SOF2

Bit 2: Synchronization overrun event flag.

SOF3

Bit 3: Synchronization overrun event flag.

SOF4

Bit 4: Synchronization overrun event flag.

SOF5

Bit 5: Synchronization overrun event flag.

SOF6

Bit 6: Synchronization overrun event flag.

SOF7

Bit 7: Synchronization overrun event flag.

SOF8

Bit 8: Synchronization overrun event flag.

SOF9

Bit 9: Synchronization overrun event flag.

SOF10

Bit 10: Synchronization overrun event flag.

SOF11

Bit 11: Synchronization overrun event flag.

SOF12

Bit 12: Synchronization overrun event flag.

SOF13

Bit 13: Synchronization overrun event flag.

CFR

clear flag register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF13
w 		CSOF12
w 		CSOF11
w 		CSOF10
w 		CSOF9
w 		CSOF8
w 		CSOF7
w 		CSOF6
w 		CSOF5
w 		CSOF4
w 		CSOF3
w 		CSOF2
w 		CSOF1
w 		CSOF0
w
Toggle fields

CSOF0

Bit 0: Clear synchronization overrun event flag.

CSOF1

Bit 1: Clear synchronization overrun event flag.

CSOF2

Bit 2: Clear synchronization overrun event flag.

CSOF3

Bit 3: Clear synchronization overrun event flag.

CSOF4

Bit 4: Clear synchronization overrun event flag.

CSOF5

Bit 5: Clear synchronization overrun event flag.

CSOF6

Bit 6: Clear synchronization overrun event flag.

CSOF7

Bit 7: Clear synchronization overrun event flag.

CSOF8

Bit 8: Clear synchronization overrun event flag.

CSOF9

Bit 9: Clear synchronization overrun event flag.

CSOF10

Bit 10: Clear synchronization overrun event flag.

CSOF11

Bit 11: Clear synchronization overrun event flag.

CSOF12

Bit 12: Clear synchronization overrun event flag.

CSOF13

Bit 13: Clear synchronization overrun event flag.

RGCR[0]

request generator channel 0 configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal identification.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel 0 enable.

GPOL

Bits 17-18: DMA request generator trigger polarity.

GNBREQ

Bits 19-23: Number of DMA requests to be generated minus 1.

RGCR[1]

request generator channel 1 configuration register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal identification.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel 0 enable.

GPOL

Bits 17-18: DMA request generator trigger polarity.

GNBREQ

Bits 19-23: Number of DMA requests to be generated minus 1.

RGCR[2]

request generator channel 2 configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal identification.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel 0 enable.

GPOL

Bits 17-18: DMA request generator trigger polarity.

GNBREQ

Bits 19-23: Number of DMA requests to be generated minus 1.

RGCR[3]

request generator channel 3 configuration register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal identification.

OIE

Bit 8: Trigger overrun interrupt enable.

GE

Bit 16: DMA request generator channel 0 enable.

GPOL

Bits 17-18: DMA request generator trigger polarity.

GNBREQ

Bits 19-23: Number of DMA requests to be generated minus 1.

RGSR

request generator interrupt status register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF3
r 		OF2
r 		OF1
r 		OF0
r
Toggle fields

OF0

Bit 0: Trigger overrun event flag.

OF1

Bit 1: Trigger overrun event flag.

OF2

Bit 2: Trigger overrun event flag.

OF3

Bit 3: Trigger overrun event flag.

RGCFR

request generator interrupt clear flag register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF3
w 		COF2
w 		COF1
w 		COF0
w
Toggle fields

COF0

Bit 0: Clear trigger overrun event flag.

COF1

Bit 1: Clear trigger overrun event flag.

COF2

Bit 2: Clear trigger overrun event flag.

COF3

Bit 3: Clear trigger overrun event flag.

DSI

0x40016c00: DSI Host

82/303 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 VR
0x4 CR
0x8 CCR
0xc LVCIDR
0x10 LCOLCR
0x14 LPCR
0x18 LPMCR
0x2c PCR
0x30 GVCIDR
0x34 MCR
0x38 VMCR
0x3c VPCR
0x40 VCCR
0x44 VNPCR
0x48 VHSACR
0x4c VHBPCR
0x50 VLCR
0x54 VVSACR
0x58 VVBPCR
0x5c VVFPCR
0x60 VVACR
0x64 LCCR
0x68 CMCR
0x6c GHCR
0x70 GPDR
0x74 GPSR
0x78 TCCR0
0x7c TCCR1
0x80 TCCR2
0x84 TCCR3
0x88 TCCR4
0x8c TCCR5
0x94 CLCR
0x98 CLTCR
0x9c DLTRC
0xa0 PCTLR
0xa4 PCONFR
0xa8 PUCR
0xac PTTCR
0xb0 PSR
0xbc ISR0
0xc0 ISR1
0xc4 IER0
0xc8 IER1
0xd8 FIR0
0xdc FIR1
0x100 VSCR
0x10c LCVCIDR
0x110 LCCCR
0x118 LPMCCR
0x138 VMCCR
0x13c VPCCR
0x140 VCCCR
0x144 VNPCCR
0x148 VHSACCR
0x14c VHBPCCR
0x150 VLCCR
0x154 VVSACCR
0x158 VVBPCCR
0x15c VVFPCCR
0x160 VVACCR
0x400 WCFGR
0x404 WCR
0x408 WIER
0x40c WISR
0x410 WIFCR
0x418 WPCR0
0x41c WPCR1
0x420 WPCR2
0x424 WPCR3
0x428 WPCR4
0x430 WRPCR
Toggle registers

VR

DSI Host Version Register

Offset: 0x0, size: 32, reset: 0x3133302A, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VERSION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VERSION
r
Toggle fields

VERSION

Bits 0-31: Version of the DSI Host.

CR

DSI Host Control Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN
rw
Toggle fields

EN

Bit 0: Enable.

CCR

DSI HOST Clock Control Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOCKDIV
rw 		TXECKDIV
rw
Toggle fields

TXECKDIV

Bits 0-7: TX Escape Clock Division.

TOCKDIV

Bits 8-15: Timeout Clock Division.

LVCIDR

DSI Host LTDC VCID Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VCID
rw
Toggle fields

VCID

Bits 0-1: Virtual Channel ID.

LCOLCR

DSI Host LTDC Color Coding Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPE
rw 		COLC
rw
Toggle fields

COLC

Bits 0-3: Color Coding.

LPE

Bit 8: Loosely Packet Enable.

LPCR

DSI Host LTDC Polarity Configuration Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSP
rw 		VSP
rw 		DEP
rw
Toggle fields

DEP

Bit 0: Data Enable Polarity.

VSP

Bit 1: VSYNC Polarity.

HSP

Bit 2: HSYNC Polarity.

LPMCR

DSI Host Low-Power mode Configuration Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLPSIZE
rw
Toggle fields

VLPSIZE

Bits 0-7: VACT Largest Packet Size.

LPSIZE

Bits 16-23: Largest Packet Size.

PCR

DSI Host Protocol Configuration Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRXE
rw 		ECCRXE
rw 		BTAE
rw 		ETRXE
rw 		ETTXE
rw
Toggle fields

ETTXE

Bit 0: EoTp Transmission Enable.

ETRXE

Bit 1: EoTp Reception Enable.

BTAE

Bit 2: Bus Turn Around Enable.

ECCRXE

Bit 3: ECC Reception Enable.

CRCRXE

Bit 4: CRC Reception Enable.

GVCIDR

DSI Host Generic VCID Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VCID
rw
Toggle fields

VCID

Bits 0-1: Virtual Channel ID.

MCR

DSI Host mode Configuration Register

Offset: 0x34, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDM
rw
Toggle fields

CMDM

Bit 0: Command mode.

VMCR

DSI Host Video mode Configuration Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PGO
rw 		PGM
rw 		PGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPCE
rw 		FBTAAE
rw 		LPHFPE
rw 		LPHBPE
rw 		LPVAE
rw 		LPVFPE
rw 		LPVBPE
rw 		LPVSAE
rw 		VMT
rw
Toggle fields

VMT

Bits 0-1: Video mode Type.

LPVSAE

Bit 8: Low-Power Vertical Sync Active Enable.

LPVBPE

Bit 9: Low-power Vertical Back-Porch Enable.

LPVFPE

Bit 10: Low-power Vertical Front-porch Enable.

LPVAE

Bit 11: Low-Power Vertical Active Enable.

LPHBPE

Bit 12: Low-Power Horizontal Back-Porch Enable.

LPHFPE

Bit 13: Low-Power Horizontal Front-Porch Enable.

FBTAAE

Bit 14: Frame Bus-Turn-Around Acknowledge Enable.

LPCE

Bit 15: Low-Power Command Enable.

PGE

Bit 16: Pattern Generator Enable.

PGM

Bit 20: Pattern Generator mode.

PGO

Bit 24: Pattern Generator Orientation.

VPCR

DSI Host Video Packet Configuration Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPSIZE
rw
Toggle fields

VPSIZE

Bits 0-13: Video Packet Size.

VCCR

DSI Host Video Chunks Configuration Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NUMC
rw
Toggle fields

NUMC

Bits 0-12: Number of Chunks.

VNPCR

DSI Host Video Null Packet Configuration Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPSIZE
rw
Toggle fields

NPSIZE

Bits 0-12: Null Packet Size.

VHSACR

DSI Host Video HSA Configuration Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSA
rw
Toggle fields

HSA

Bits 0-11: Horizontal Synchronism Active duration.

VHBPCR

DSI Host Video HBP Configuration Register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HBP
rw
Toggle fields

HBP

Bits 0-11: Horizontal Back-Porch duration.

VLCR

DSI Host Video Line Configuration Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLINE
rw
Toggle fields

HLINE

Bits 0-14: Horizontal Line duration.

VVSACR

DSI Host Video VSA Configuration Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSA
rw
Toggle fields

VSA

Bits 0-9: Vertical Synchronism Active duration.

VVBPCR

DSI Host Video VBP Configuration Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBP
rw
Toggle fields

VBP

Bits 0-9: Vertical Back-Porch duration.

VVFPCR

DSI Host Video VFP Configuration Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VFP
rw
Toggle fields

VFP

Bits 0-9: Vertical Front-Porch duration.

VVACR

DSI Host Video VA Configuration Register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VA
rw
Toggle fields

VA

Bits 0-13: Vertical Active duration.

LCCR

DSI Host LTDC Command Configuration Register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDSIZE
rw
Toggle fields

CMDSIZE

Bits 0-15: Command Size.

CMCR

DSI Host Command mode Configuration Register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MRDPS
rw 		DLWTX
rw 		DSR0TX
rw 		DSW1TX
rw 		DSW0TX
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GLWTX
rw 		GSR2TX
rw 		GSR1TX
rw 		GSR0TX
rw 		GSW2TX
rw 		GSW1TX
rw 		GSW0TX
rw 		ARE
rw 		TEARE
rw
Toggle fields

TEARE

Bit 0: Tearing Effect Acknowledge Request Enable.

ARE

Bit 1: Acknowledge Request Enable.

GSW0TX

Bit 8: Generic Short Write Zero parameters Transmission.

GSW1TX

Bit 9: Generic Short Write One parameters Transmission.

GSW2TX

Bit 10: Generic Short Write Two parameters Transmission.

GSR0TX

Bit 11: Generic Short Read Zero parameters Transmission.

GSR1TX

Bit 12: Generic Short Read One parameters Transmission.

GSR2TX

Bit 13: Generic Short Read Two parameters Transmission.

GLWTX

Bit 14: Generic Long Write Transmission.

DSW0TX

Bit 16: DCS Short Write Zero parameter Transmission.

DSW1TX

Bit 17: DCS Short Read One parameter Transmission.

DSR0TX

Bit 18: DCS Short Read Zero parameter Transmission.

DLWTX

Bit 19: DCS Long Write Transmission.

MRDPS

Bit 24: Maximum Read Packet Size.

GHCR

DSI Host Generic Header Configuration Register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WCMSB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WCLSB
rw 		VCID
rw 		DT
rw
Toggle fields

DT

Bits 0-5: Type.

VCID

Bits 6-7: Channel.

WCLSB

Bits 8-15: WordCount LSB.

WCMSB

Bits 16-23: WordCount MSB.

GPDR

DSI Host Generic Payload Data Register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA4
rw 		DATA3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA2
rw 		DATA1
rw
Toggle fields

DATA1

Bits 0-7: Payload Byte 1.

DATA2

Bits 8-15: Payload Byte 2.

DATA3

Bits 16-23: Payload Byte 3.

DATA4

Bits 24-31: Payload Byte 4.

GPSR

DSI Host Generic Packet Status Register

Offset: 0x74, size: 32, reset: 0x00000015, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCB
r 		PRDFF
r 		PRDFE
r 		PWRFF
r 		PWRFE
r 		CMDFF
r 		CMDFE
r
Toggle fields

CMDFE

Bit 0: Command FIFO Empty.

CMDFF

Bit 1: Command FIFO Full.

PWRFE

Bit 2: Payload Write FIFO Empty.

PWRFF

Bit 3: Payload Write FIFO Full.

PRDFE

Bit 4: Payload Read FIFO Empty.

PRDFF

Bit 5: Payload Read FIFO Full.

RCB

Bit 6: Read Command Busy.

TCCR0

DSI Host Timeout Counter Configuration Register 0

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSTX_TOCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPRX_TOCNT
rw
Toggle fields

LPRX_TOCNT

Bits 0-15: Low-power Reception Timeout Counter.

HSTX_TOCNT

Bits 16-31: High-Speed Transmission Timeout Counter.

TCCR1

DSI Host Timeout Counter Configuration Register 1

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSRD_TOCNT
rw
Toggle fields

HSRD_TOCNT

Bits 0-15: High-Speed Read Timeout Counter.

TCCR2

DSI Host Timeout Counter Configuration Register 2

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPRD_TOCNT
rw
Toggle fields

LPRD_TOCNT

Bits 0-15: Low-Power Read Timeout Counter.

TCCR3

DSI Host Timeout Counter Configuration Register 3

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSWR_TOCNT
rw
Toggle fields

HSWR_TOCNT

Bits 0-15: High-Speed Write Timeout Counter.

PM

Bit 24: Presp mode.

TCCR4

DSI Host Timeout Counter Configuration Register 4

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSWR_TOCNT
rw
Toggle fields

LSWR_TOCNT

Bits 0-15: Low-Power Write Timeout Counter.

TCCR5

DSI Host Timeout Counter Configuration Register 5

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTA_TOCNT
rw
Toggle fields

BTA_TOCNT

Bits 0-15: Bus-Turn-Around Timeout Counter.

CLCR

DSI Host Clock Lane Configuration Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACR
rw 		DPCC
rw
Toggle fields

DPCC

Bit 0: D-PHY Clock Control.

ACR

Bit 1: Automatic Clock lane Control.

CLTCR

DSI Host Clock Lane Timer Configuration Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HS2LP_TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LP2HS_TIME
rw
Toggle fields

LP2HS_TIME

Bits 0-9: Low-Power to High-Speed Time.

HS2LP_TIME

Bits 16-25: High-Speed to Low-Power Time.

DLTRC

DSI Host Data Lane Timer Configuration Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HS2LP_TIME
rw 		LP2HS_TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MRD_TIME
rw
Toggle fields

MRD_TIME

Bits 0-14: Maximum Read Time.

LP2HS_TIME

Bits 16-23: Low-Power To High-Speed Time.

HS2LP_TIME

Bits 24-31: High-Speed To Low-Power Time.

PCTLR

DSI Host PHY Control Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKE
rw 		DEN
rw
Toggle fields

DEN

Bit 1: Digital Enable.

CKE

Bit 2: Clock Enable.

PCONFR

DSI Host PHY Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000001, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SW_TIME
rw 		NL
rw
Toggle fields

NL

Bits 0-1: Number of Lanes.

SW_TIME

Bits 8-15: Stop Wait Time.

PUCR

DSI Host PHY ULPS Control Register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEDL
rw 		URDL
rw 		UECL
rw 		URCL
rw
Toggle fields

URCL

Bit 0: ULPS Request on Clock Lane.

UECL

Bit 1: ULPS Exit on Clock Lane.

URDL

Bit 2: ULPS Request on Data Lane.

UEDL

Bit 3: ULPS Exit on Data Lane.

PTTCR

DSI Host PHY TX Triggers Configuration Register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_TRIG
rw
Toggle fields

TX_TRIG

Bits 0-3: Transmission Trigger.

PSR

DSI Host PHY Status Register

Offset: 0xb0, size: 32, reset: 0x00001528, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UAN1
r 		PSS1
r 		RUE0
r 		UAN0
r 		PSS0
r 		UANC
r 		PSSC
r 		PD
r
Toggle fields

PD

Bit 1: PHY Direction.

PSSC

Bit 2: PHY Stop State Clock lane.

UANC

Bit 3: ULPS Active Not Clock lane.

PSS0

Bit 4: PHY Stop State lane 0.

UAN0

Bit 5: ULPS Active Not lane 1.

RUE0

Bit 6: RX ULPS Escape lane 0.

PSS1

Bit 7: PHY Stop State lane 1.

UAN1

Bit 8: ULPS Active Not lane 1.

ISR0

DSI Host Interrupt & Status Register 0

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PE[4]
r 		PE[3]
r 		PE[2]
r 		PE[1]
r 		PE[0]
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AE[15]
r 		AE[14]
r 		AE[13]
r 		AE[12]
r 		AE[11]
r 		AE[10]
r 		AE[9]
r 		AE[8]
r 		AE[7]
r 		AE[6]
r 		AE[5]
r 		AE[4]
r 		AE[3]
r 		AE[2]
r 		AE[1]
r 		AE[0]
r
Toggle fields

AE[0]

Bit 0: Acknowledge Error 0.

AE[1]

Bit 1: Acknowledge Error 1.

AE[2]

Bit 2: Acknowledge Error 2.

AE[3]

Bit 3: Acknowledge Error 3.

AE[4]

Bit 4: Acknowledge Error 4.

AE[5]

Bit 5: Acknowledge Error 5.

AE[6]

Bit 6: Acknowledge Error 6.

AE[7]

Bit 7: Acknowledge Error 7.

AE[8]

Bit 8: Acknowledge Error 8.

AE[9]

Bit 9: Acknowledge Error 9.

AE[10]

Bit 10: Acknowledge Error 10.

AE[11]

Bit 11: Acknowledge Error 11.

AE[12]

Bit 12: Acknowledge Error 12.

AE[13]

Bit 13: Acknowledge Error 13.

AE[14]

Bit 14: Acknowledge Error 14.

AE[15]

Bit 15: Acknowledge Error 15.

PE[0]

Bit 16: PHY Error 0.

PE[1]

Bit 17: PHY Error 1.

PE[2]

Bit 18: PHY Error 2.

PE[3]

Bit 19: PHY Error 3.

PE[4]

Bit 20: PHY Error 4.

ISR1

DSI Host Interrupt & Status Register 1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPRXE
r 		GPRDE
r 		GPTXE
r 		GPWRE
r 		GCWRE
r 		LPWRE
r 		EOTPE
r 		PSE
r 		CRCE
r 		ECCME
r 		ECCSE
r 		TOLPRX
r 		TOHSTX
r
Toggle fields

TOHSTX

Bit 0: Timeout High-Speed Transmission.

TOLPRX

Bit 1: Timeout Low-Power Reception.

ECCSE

Bit 2: ECC Single-bit Error.

ECCME

Bit 3: ECC Multi-bit Error.

CRCE

Bit 4: CRC Error.

PSE

Bit 5: Packet Size Error.

EOTPE

Bit 6: EoTp Error.

LPWRE

Bit 7: LTDC Payload Write Error.

GCWRE

Bit 8: Generic Command Write Error.

GPWRE

Bit 9: Generic Payload Write Error.

GPTXE

Bit 10: Generic Payload Transmit Error.

GPRDE

Bit 11: Generic Payload Read Error.

GPRXE

Bit 12: Generic Payload Receive Error.

IER0

DSI Host Interrupt Enable Register 0

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PE[4]IE
rw 		PE[3]IE
rw 		PE[2]IE
rw 		PE[1]IE
rw 		PE[0]IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AE[15]IE
rw 		AE[14]IE
rw 		AE[13]IE
rw 		AE[12]IE
rw 		AE[11]IE
rw 		AE[10]IE
rw 		AE[9]IE
rw 		AE[8]IE
rw 		AE[7]IE
rw 		AE[6]IE
rw 		AE[5]IE
rw 		AE[4]IE
rw 		AE[3]IE
rw 		AE[2]IE
rw 		AE[1]IE
rw 		AE[0]IE
rw
Toggle fields

AE[0]IE

Bit 0: Acknowledge Error 0 Interrupt Enable.

AE[1]IE

Bit 1: Acknowledge Error 1 Interrupt Enable.

AE[2]IE

Bit 2: Acknowledge Error 2 Interrupt Enable.

AE[3]IE

Bit 3: Acknowledge Error 3 Interrupt Enable.

AE[4]IE

Bit 4: Acknowledge Error 4 Interrupt Enable.

AE[5]IE

Bit 5: Acknowledge Error 5 Interrupt Enable.

AE[6]IE

Bit 6: Acknowledge Error 6 Interrupt Enable.

AE[7]IE

Bit 7: Acknowledge Error 7 Interrupt Enable.

AE[8]IE

Bit 8: Acknowledge Error 8 Interrupt Enable.

AE[9]IE

Bit 9: Acknowledge Error 9 Interrupt Enable.

AE[10]IE

Bit 10: Acknowledge Error 10 Interrupt Enable.

AE[11]IE

Bit 11: Acknowledge Error 11 Interrupt Enable.

AE[12]IE

Bit 12: Acknowledge Error 12 Interrupt Enable.

AE[13]IE

Bit 13: Acknowledge Error 13 Interrupt Enable.

AE[14]IE

Bit 14: Acknowledge Error 14 Interrupt Enable.

AE[15]IE

Bit 15: Acknowledge Error 15 Interrupt Enable.

PE[0]IE

Bit 16: PHY Error 0 Interrupt Enable.

PE[1]IE

Bit 17: PHY Error 1 Interrupt Enable.

PE[2]IE

Bit 18: PHY Error 2 Interrupt Enable.

PE[3]IE

Bit 19: PHY Error 3 Interrupt Enable.

PE[4]IE

Bit 20: PHY Error 4 Interrupt Enable.

IER1

DSI Host Interrupt Enable Register 1

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPRXEIE
rw 		GPRDEIE
rw 		GPTXEIE
rw 		GPWREIE
rw 		GCWREIE
rw 		LPWREIE
rw 		EOTPEIE
rw 		PSEIE
rw 		CRCEIE
rw 		ECCMEIE
rw 		ECCSEIE
rw 		TOLPRXIE
rw 		TOHSTXIE
rw
Toggle fields

TOHSTXIE

Bit 0: Timeout High-Speed Transmission Interrupt Enable.

TOLPRXIE

Bit 1: Timeout Low-Power Reception Interrupt Enable.

ECCSEIE

Bit 2: ECC Single-bit Error Interrupt Enable.

ECCMEIE

Bit 3: ECC Multi-bit Error Interrupt Enable.

CRCEIE

Bit 4: CRC Error Interrupt Enable.

PSEIE

Bit 5: Packet Size Error Interrupt Enable.

EOTPEIE

Bit 6: EoTp Error Interrupt Enable.

LPWREIE

Bit 7: LTDC Payload Write Error Interrupt Enable.

GCWREIE

Bit 8: Generic Command Write Error Interrupt Enable.

GPWREIE

Bit 9: Generic Payload Write Error Interrupt Enable.

GPTXEIE

Bit 10: Generic Payload Transmit Error Interrupt Enable.

GPRDEIE

Bit 11: Generic Payload Read Error Interrupt Enable.

GPRXEIE

Bit 12: Generic Payload Receive Error Interrupt Enable.

FIR0

DSI Host Force Interrupt Register 0

Offset: 0xd8, size: 32, reset: 0x00000000, access: write-only

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPE[4]
w 		FPE[3]
w 		FPE[2]
w 		FPE[1]
w 		FPE[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAE[15]
w 		FAE[14]
w 		FAE[13]
w 		FAE[12]
w 		FAE[11]
w 		FAE[10]
w 		FAE[9]
w 		FAE[8]
w 		FAE[7]
w 		FAE[6]
w 		FAE[5]
w 		FAE[4]
w 		FAE[3]
w 		FAE[2]
w 		FAE[1]
w 		FAE[0]
w
Toggle fields

FAE[0]

Bit 0: Force Acknowledge Error 0.

FAE[1]

Bit 1: Force Acknowledge Error 1.

FAE[2]

Bit 2: Force Acknowledge Error 2.

FAE[3]

Bit 3: Force Acknowledge Error 3.

FAE[4]

Bit 4: Force Acknowledge Error 4.

FAE[5]

Bit 5: Force Acknowledge Error 5.

FAE[6]

Bit 6: Force Acknowledge Error 6.

FAE[7]

Bit 7: Force Acknowledge Error 7.

FAE[8]

Bit 8: Force Acknowledge Error 8.

FAE[9]

Bit 9: Force Acknowledge Error 9.

FAE[10]

Bit 10: Force Acknowledge Error 10.

FAE[11]

Bit 11: Force Acknowledge Error 11.

FAE[12]

Bit 12: Force Acknowledge Error 12.

FAE[13]

Bit 13: Force Acknowledge Error 13.

FAE[14]

Bit 14: Force Acknowledge Error 14.

FAE[15]

Bit 15: Force Acknowledge Error 15.

FPE[0]

Bit 16: Force PHY Error 0.

FPE[1]

Bit 17: Force PHY Error 1.

FPE[2]

Bit 18: Force PHY Error 2.

FPE[3]

Bit 19: Force PHY Error 3.

FPE[4]

Bit 20: Force PHY Error 4.

FIR1

DSI Host Force Interrupt Register 1

Offset: 0xdc, size: 32, reset: 0x00000000, access: write-only

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FGPRXE
w 		FGPRDE
w 		FGPTXE
w 		FGPWRE
w 		FGCWRE
w 		FLPWRE
w 		FEOTPE
w 		FPSE
w 		FCRCE
w 		FECCME
w 		FECCSE
w 		FTOLPRX
w 		FTOHSTX
w
Toggle fields

FTOHSTX

Bit 0: Force Timeout High-Speed Transmission.

FTOLPRX

Bit 1: Force Timeout Low-Power Reception.

FECCSE

Bit 2: Force ECC Single-bit Error.

FECCME

Bit 3: Force ECC Multi-bit Error.

FCRCE

Bit 4: Force CRC Error.

FPSE

Bit 5: Force Packet Size Error.

FEOTPE

Bit 6: Force EoTp Error.

FLPWRE

Bit 7: Force LTDC Payload Write Error.

FGCWRE

Bit 8: Force Generic Command Write Error.

FGPWRE

Bit 9: Force Generic Payload Write Error.

FGPTXE

Bit 10: Force Generic Payload Transmit Error.

FGPRDE

Bit 11: Force Generic Payload Read Error.

FGPRXE

Bit 12: Force Generic Payload Receive Error.

VSCR

DSI Host Video Shadow Control Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UR
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

UR

Bit 8: Update Register.

LCVCIDR

DSI Host LTDC Current VCID Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VCID
r
Toggle fields

VCID

Bits 0-1: Virtual Channel ID.

LCCCR

DSI Host LTDC Current Color Coding Register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPE
r 		COLC
r
Toggle fields

COLC

Bits 0-3: Color Coding.

LPE

Bit 8: Loosely Packed Enable.

LPMCCR

DSI Host Low-Power mode Current Configuration Register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLPSIZE
r
Toggle fields

VLPSIZE

Bits 0-7: VACT Largest Packet Size.

LPSIZE

Bits 16-23: Largest Packet Size.

VMCCR

DSI Host Video mode Current Configuration Register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPCE
r 		FBTAAE
r 		LPHFE
r 		LPHBPE
r 		LPVAE
r 		LPVFPE
r 		LPVBPE
r 		LPVSAE
r 		VMT
r
Toggle fields

VMT

Bits 0-1: Video mode Type.

LPVSAE

Bit 2: Low-Power Vertical Sync time Enable.

LPVBPE

Bit 3: Low-power Vertical Back-Porch Enable.

LPVFPE

Bit 4: Low-power Vertical Front-Porch Enable.

LPVAE

Bit 5: Low-Power Vertical Active Enable.

LPHBPE

Bit 6: Low-power Horizontal Back-Porch Enable.

LPHFE

Bit 7: Low-Power Horizontal Front-Porch Enable.

FBTAAE

Bit 8: Frame BTA Acknowledge Enable.

LPCE

Bit 9: Low-Power Command Enable.

VPCCR

DSI Host Video Packet Current Configuration Register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPSIZE
r
Toggle fields

VPSIZE

Bits 0-13: Video Packet Size.

VCCCR

DSI Host Video Chunks Current Configuration Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NUMC
r
Toggle fields

NUMC

Bits 0-12: Number of Chunks.

VNPCCR

DSI Host Video Null Packet Current Configuration Register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPSIZE
r
Toggle fields

NPSIZE

Bits 0-12: Null Packet Size.

VHSACCR

DSI Host Video HSA Current Configuration Register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSA
r
Toggle fields

HSA

Bits 0-11: Horizontal Synchronism Active duration.

VHBPCCR

DSI Host Video HBP Current Configuration Register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HBP
r
Toggle fields

HBP

Bits 0-11: Horizontal Back-Porch duration.

VLCCR

DSI Host Video Line Current Configuration Register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLINE
r
Toggle fields

HLINE

Bits 0-14: Horizontal Line duration.

VVSACCR

DSI Host Video VSA Current Configuration Register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSA
r
Toggle fields

VSA

Bits 0-9: Vertical Synchronism Active duration.

VVBPCCR

DSI Host Video VBP Current Configuration Register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBP
r
Toggle fields

VBP

Bits 0-9: Vertical Back-Porch duration.

VVFPCCR

DSI Host Video VFP Current Configuration Register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VFP
r
Toggle fields

VFP

Bits 0-9: Vertical Front-Porch duration.

VVACCR

DSI Host Video VA Current Configuration Register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VA
r
Toggle fields

VA

Bits 0-13: Vertical Active duration.

WCFGR

DSI Wrapper Configuration Register

Offset: 0x400, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSPOL
rw 		AR
rw 		TEPOL
rw 		TESRC
rw 		COLMUX
rw 		DSIM
rw
Toggle fields

DSIM

Bit 0: DSI Mode.

COLMUX

Bits 1-3: Color Multiplexing.

TESRC

Bit 4: TE Source.

TEPOL

Bit 5: TE Polarity.

AR

Bit 6: Automatic Refresh.

VSPOL

Bit 7: VSync Polarity.

WCR

DSI Wrapper Control Register

Offset: 0x404, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSIEN
rw 		LTDCEN
rw 		SHTDN
rw 		COLM
rw
Toggle fields

COLM

Bit 0: Color Mode.

SHTDN

Bit 1: Shutdown.

LTDCEN

Bit 2: LTDC Enable.

DSIEN

Bit 3: DSI Enable.

WIER

DSI Wrapper Interrupt Enable Register

Offset: 0x408, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIE
rw 		PLLUIE
rw 		PLLLIE
rw 		ERIE
rw 		TEIE
rw
Toggle fields

TEIE

Bit 0: Tearing Effect Interrupt Enable.

ERIE

Bit 1: End of Refresh Interrupt Enable.

PLLLIE

Bit 9: PLL Lock Interrupt Enable.

PLLUIE

Bit 10: PLL Unlock Interrupt Enable.

RRIE

Bit 13: Regulator Ready Interrupt Enable.

WISR

DSI Wrapper Interrupt & Status Register

Offset: 0x40c, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIF
r 		RRS
r 		PLLUIF
r 		PLLLIF
r 		PLLLS
r 		BUSY
r 		ERIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: Tearing Effect Interrupt Flag.

ERIF

Bit 1: End of Refresh Interrupt Flag.

BUSY

Bit 2: Busy Flag.

PLLLS

Bit 8: PLL Lock Status.

PLLLIF

Bit 9: PLL Lock Interrupt Flag.

PLLUIF

Bit 10: PLL Unlock Interrupt Flag.

RRS

Bit 12: Regulator Ready Status.

RRIF

Bit 13: Regulator Ready Interrupt Flag.

WIFCR

DSI Wrapper Interrupt Flag Clear Register

Offset: 0x410, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRRIF
rw 		CPLLUIF
rw 		CPLLLIF
rw 		CERIF
rw 		CTEIF
rw
Toggle fields

CTEIF

Bit 0: Clear Tearing Effect Interrupt Flag.

CERIF

Bit 1: Clear End of Refresh Interrupt Flag.

CPLLLIF

Bit 9: Clear PLL Lock Interrupt Flag.

CPLLUIF

Bit 10: Clear PLL Unlock Interrupt Flag.

CRRIF

Bit 13: Clear Regulator Ready Interrupt Flag.

WPCR0

DSI Wrapper PHY Configuration Register 0

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCLKPOSTEN
rw 		TLPXCEN
rw 		THSEXITEN
rw 		TLPXDEN
rw 		THSZEROEN
rw 		THSTRAILEN
rw 		THSPREPEN
rw 		TCLKZEROEN
rw 		TCLKPREPEN
rw 		PDEN
rw 		TDDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CDOFFDL
rw 		FTXSMDL
rw 		FTXSMCL
rw 		HSIDL1
rw 		HSIDL0
rw 		HSICL
rw 		SWDL1
rw 		SWDL0
rw 		SWCL
rw 		UIX4
rw
Toggle fields

UIX4

Bits 0-5: Unit Interval multiplied by 4.

SWCL

Bit 6: Swap Clock Lane pins.

SWDL0

Bit 7: Swap Data Lane 0 pins.

SWDL1

Bit 8: Swap Data Lane 1 pins.

HSICL

Bit 9: Invert Hight-Speed data signal on Clock Lane.

HSIDL0

Bit 10: Invert the Hight-Speed data signal on Data Lane 0.

HSIDL1

Bit 11: Invert the High-Speed data signal on Data Lane 1.

FTXSMCL

Bit 12: Force in TX Stop Mode the Clock Lane.

FTXSMDL

Bit 13: Force in TX Stop Mode the Data Lanes.

CDOFFDL

Bit 14: Contention Detection OFF on Data Lanes.

TDDL

Bit 16: Turn Disable Data Lanes.

PDEN

Bit 18: Pull-Down Enable.

TCLKPREPEN

Bit 19: custom time for tCLK-PREPARE Enable.

TCLKZEROEN

Bit 20: custom time for tCLK-ZERO Enable.

THSPREPEN

Bit 21: custom time for tHS-PREPARE Enable.

THSTRAILEN

Bit 22: custom time for tHS-TRAIL Enable.

THSZEROEN

Bit 23: custom time for tHS-ZERO Enable.

TLPXDEN

Bit 24: custom time for tLPX for Data lanes Enable.

THSEXITEN

Bit 25: custom time for tHS-EXIT Enable.

TLPXCEN

Bit 26: custom time for tLPX for Clock lane Enable.

TCLKPOSTEN

Bit 27: custom time for tCLK-POST Enable.

WPCR1

DSI Wrapper PHY Configuration Register 1

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPRXFT
rw 		FLPRXLPM
rw 		HSTXSRCDL
rw 		HSTXSRCCL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDCC
rw 		LPSRDL
rw 		LPSRCL
rw 		HSTXDLL
rw 		HSTXDCL
rw
Toggle fields

HSTXDCL

Bits 0-1: High-Speed Transmission Delay on Clock Lane.

HSTXDLL

Bits 2-3: High-Speed Transmission Delay on Data Lanes.

LPSRCL

Bits 6-7: Low-Power transmission Slew Rate Compensation on Clock Lane.

LPSRDL

Bits 8-9: Low-Power transmission Slew Rate Compensation on Data Lanes.

SDCC

Bit 12: SDD Control.

HSTXSRCCL

Bits 16-17: High-Speed Transmission Slew Rate Control on Clock Lane.

HSTXSRCDL

Bits 18-19: High-Speed Transmission Slew Rate Control on Data Lanes.

FLPRXLPM

Bit 22: Forces LP Receiver in Low-Power Mode.

LPRXFT

Bits 25-26: Low-Power RX low-pass Filtering Tuning.

WPCR2

DSI Wrapper PHY Configuration Register 2

Offset: 0x420, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THSTRAIL
rw 		THSPREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCLKZEO
rw 		TCLKPREP
rw
Toggle fields

TCLKPREP

Bits 0-7: tCLK-PREPARE.

TCLKZEO

Bits 8-15: tCLK-ZERO.

THSPREP

Bits 16-23: tHS-PREPARE.

THSTRAIL

Bits 24-31: tHSTRAIL.

WPCR3

DSI_WPCR3

Offset: 0x424, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLPXC
rw 		THSEXIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLPXD
rw 		THSZERO
rw
Toggle fields

THSZERO

Bits 0-7: tHS-ZERO.

TLPXD

Bits 8-15: tLPX for Data lanes.

THSEXIT

Bits 16-23: tHSEXIT.

TLPXC

Bits 24-31: tLPXC for Clock lane.

WPCR4

DSI Wrapper PHY Configuration Register 4

Offset: 0x428, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THSZERO
rw
Toggle fields

THSZERO

Bits 0-7: tCLK-POST.

WRPCR

DSI Wrapper Regulator and PLL Control Register

Offset: 0x430, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGEN
rw 		ODF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDF
rw 		NDIV
rw 		PLLEN
rw
Toggle fields

PLLEN

Bit 0: PLL Enable.

NDIV

Bits 2-8: PLL Loop Division Factor.

IDF

Bits 11-14: PLL Input Division Factor.

ODF

Bits 16-17: PLL Output Division Factor.

REGEN

Bit 24: Regulator Enable.

EXTI

0x40010400: External interrupt/event controller

184/184 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IMR1
0x4 EMR1
0x8 RTSR1
0xc FTSR1
0x10 SWIER1
0x14 PR1
0x20 IMR2
0x24 EMR2
0x28 RTSR2
0x2c FTSR2
0x30 SWIER2
0x34 PR2
Toggle registers

IMR1

Interrupt mask register

Offset: 0x0, size: 32, reset: 0xFF820000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw 		MR30
rw 		MR29
rw 		MR28
rw 		MR27
rw 		MR26
rw 		MR25
rw 		MR24
rw 		MR23
rw 		MR22
rw 		MR21
rw 		MR20
rw 		MR19
rw 		MR18
rw 		MR17
rw 		MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw 		MR14
rw 		MR13
rw 		MR12
rw 		MR11
rw 		MR10
rw 		MR9
rw 		MR8
rw 		MR7
rw 		MR6
rw 		MR5
rw 		MR4
rw 		MR3
rw 		MR2
rw 		MR1
rw 		MR0
rw
Toggle fields

MR0

Bit 0: Interrupt Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Interrupt Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Interrupt Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Interrupt Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Interrupt Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Interrupt Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Interrupt Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Interrupt Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Interrupt Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Interrupt Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Interrupt Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Interrupt Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Interrupt Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Interrupt Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Interrupt Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Interrupt Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Interrupt Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Interrupt Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Interrupt Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Interrupt Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Interrupt Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Interrupt Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Interrupt Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR23

Bit 23: Interrupt Mask on line 23.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR24

Bit 24: Interrupt Mask on line 24.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: Interrupt Mask on line 25.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR26

Bit 26: Interrupt Mask on line 26.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR27

Bit 27: Interrupt Mask on line 27.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR28

Bit 28: Interrupt Mask on line 28.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR29

Bit 29: Interrupt Mask on line 29.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR30

Bit 30: Interrupt Mask on line 30.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR31

Bit 31: Interrupt Mask on line 31.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR1

Event mask register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw 		MR30
rw 		MR29
rw 		MR28
rw 		MR27
rw 		MR26
rw 		MR25
rw 		MR24
rw 		MR23
rw 		MR22
rw 		MR21
rw 		MR20
rw 		MR19
rw 		MR18
rw 		MR17
rw 		MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw 		MR14
rw 		MR13
rw 		MR12
rw 		MR11
rw 		MR10
rw 		MR9
rw 		MR8
rw 		MR7
rw 		MR6
rw 		MR5
rw 		MR4
rw 		MR3
rw 		MR2
rw 		MR1
rw 		MR0
rw
Toggle fields

MR0

Bit 0: Event Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Event Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Event Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Event Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Event Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Event Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Event Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Event Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Event Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Event Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Event Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Event Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Event Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Event Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Event Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Event Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Event Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Event Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Event Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Event Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Event Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Event Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Event Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR23

Bit 23: Event Mask on line 23.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR24

Bit 24: Event Mask on line 24.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: Event Mask on line 25.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR26

Bit 26: Event Mask on line 26.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR27

Bit 27: Event Mask on line 27.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR28

Bit 28: Event Mask on line 28.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR29

Bit 29: Event Mask on line 29.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR30

Bit 30: Event Mask on line 30.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR31

Bit 31: Event Mask on line 31.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR1

Rising Trigger selection register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw 		TR21
rw 		TR20
rw 		TR19
rw 		TR18
rw 		TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw 		TR14
rw 		TR13
rw 		TR12
rw 		TR11
rw 		TR10
rw 		TR9
rw 		TR8
rw 		TR7
rw 		TR6
rw 		TR5
rw 		TR4
rw 		TR3
rw 		TR2
rw 		TR1
rw 		TR0
rw
Toggle fields

TR0

Bit 0: Rising trigger event configuration of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR19

Bit 19: Rising trigger event configuration of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR20

Bit 20: Rising trigger event configuration of line 20.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR21

Bit 21: Rising trigger event configuration of line 21.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR22

Bit 22: Rising trigger event configuration of line 22.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR1

Falling Trigger selection register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw 		TR21
rw 		TR20
rw 		TR19
rw 		TR18
rw 		TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw 		TR14
rw 		TR13
rw 		TR12
rw 		TR11
rw 		TR10
rw 		TR9
rw 		TR8
rw 		TR7
rw 		TR6
rw 		TR5
rw 		TR4
rw 		TR3
rw 		TR2
rw 		TR1
rw 		TR0
rw
Toggle fields

TR0

Bit 0: Falling trigger event configuration of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Falling trigger event configuration of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Falling trigger event configuration of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Falling trigger event configuration of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Falling trigger event configuration of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Falling trigger event configuration of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Falling trigger event configuration of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Falling trigger event configuration of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Falling trigger event configuration of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Falling trigger event configuration of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Falling trigger event configuration of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Falling trigger event configuration of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Falling trigger event configuration of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Falling trigger event configuration of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Falling trigger event configuration of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Falling trigger event configuration of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Falling trigger event configuration of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Falling trigger event configuration of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR19

Bit 19: Falling trigger event configuration of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR20

Bit 20: Falling trigger event configuration of line 20.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR21

Bit 21: Falling trigger event configuration of line 21.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR22

Bit 22: Falling trigger event configuration of line 22.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER1

Software interrupt event register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER22
rw 		SWIER21
rw 		SWIER20
rw 		SWIER19
rw 		SWIER18
rw 		SWIER16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER15
rw 		SWIER14
rw 		SWIER13
rw 		SWIER12
rw 		SWIER11
rw 		SWIER10
rw 		SWIER9
rw 		SWIER8
rw 		SWIER7
rw 		SWIER6
rw 		SWIER5
rw 		SWIER4
rw 		SWIER3
rw 		SWIER2
rw 		SWIER1
rw 		SWIER0
rw
Toggle fields

SWIER0

Bit 0: Software Interrupt on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Software Interrupt on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Software Interrupt on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Software Interrupt on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Software Interrupt on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Software Interrupt on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Software Interrupt on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Software Interrupt on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Software Interrupt on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Software Interrupt on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Software Interrupt on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Software Interrupt on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Software Interrupt on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Software Interrupt on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Software Interrupt on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Software Interrupt on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Software Interrupt on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Software Interrupt on line 18.

Allowed values:
1: Pend: Generates an interrupt request

SWIER19

Bit 19: Software Interrupt on line 19.

Allowed values:
1: Pend: Generates an interrupt request

SWIER20

Bit 20: Software Interrupt on line 20.

Allowed values:
1: Pend: Generates an interrupt request

SWIER21

Bit 21: Software Interrupt on line 21.

Allowed values:
1: Pend: Generates an interrupt request

SWIER22

Bit 22: Software Interrupt on line 22.

Allowed values:
1: Pend: Generates an interrupt request

PR1

Pending register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR22
rw 		PR21
rw 		PR20
rw 		PR19
rw 		PR18
rw 		PR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15
rw 		PR14
rw 		PR13
rw 		PR12
rw 		PR11
rw 		PR10
rw 		PR9
rw 		PR8
rw 		PR7
rw 		PR6
rw 		PR5
rw 		PR4
rw 		PR3
rw 		PR2
rw 		PR1
rw 		PR0
rw
Toggle fields

PR0

Bit 0: Pending bit 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: Pending bit 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: Pending bit 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: Pending bit 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: Pending bit 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: Pending bit 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: Pending bit 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: Pending bit 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: Pending bit 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: Pending bit 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: Pending bit 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: Pending bit 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: Pending bit 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: Pending bit 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: Pending bit 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: Pending bit 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: Pending bit 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR18

Bit 18: Pending bit 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR19

Bit 19: Pending bit 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR20

Bit 20: Pending bit 20.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR21

Bit 21: Pending bit 21.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR22

Bit 22: Pending bit 22.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

IMR2

Interrupt mask register

Offset: 0x20, size: 32, reset: 0xFFFFFF87, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR39
rw 		MR38
rw 		MR37
rw 		MR36
rw 		MR35
rw 		MR34
rw 		MR33
rw 		MR32
rw
Toggle fields

MR32

Bit 0: Interrupt Mask on external/internal line 32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR33

Bit 1: Interrupt Mask on external/internal line 33.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR34

Bit 2: Interrupt Mask on external/internal line 34.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR35

Bit 3: Interrupt Mask on external/internal line 35.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR36

Bit 4: Interrupt Mask on external/internal line 36.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR37

Bit 5: Interrupt Mask on external/internal line 37.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR38

Bit 6: Interrupt Mask on external/internal line 38.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR39

Bit 7: Interrupt Mask on external/internal line 39.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR2

Event mask register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR39
rw 		MR38
rw 		MR37
rw 		MR36
rw 		MR35
rw 		MR34
rw 		MR33
rw 		MR32
rw
Toggle fields

MR32

Bit 0: Event mask on external/internal line 32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR33

Bit 1: Event mask on external/internal line 33.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR34

Bit 2: Event mask on external/internal line 34.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR35

Bit 3: Event mask on external/internal line 35.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR36

Bit 4: Event mask on external/internal line 36.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR37

Bit 5: Event mask on external/internal line 37.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR38

Bit 6: Event mask on external/internal line 38.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR39

Bit 7: Event mask on external/internal line 39.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR2

Rising Trigger selection register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT38
rw 		RT37
rw 		RT36
rw 		RT35
rw
Toggle fields

RT35

Bit 3: Rising trigger event configuration bit of line 35.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT36

Bit 4: Rising trigger event configuration bit of line 36.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT37

Bit 5: Rising trigger event configuration bit of line 37.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT38

Bit 6: Rising trigger event configuration bit of line 38.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR2

Falling Trigger selection register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT38
rw 		FT37
rw 		FT36
rw 		FT35
rw
Toggle fields

FT35

Bit 3: Falling trigger event configuration bit of line 35.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT36

Bit 4: Falling trigger event configuration bit of line 36.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT37

Bit 5: Falling trigger event configuration bit of line 37.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT38

Bit 6: Falling trigger event configuration bit of line 38.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER2

Software interrupt event register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI38
rw 		SWI37
rw 		SWI36
rw 		SWI35
rw
Toggle fields

SWI35

Bit 3: Software interrupt on line 35.

Allowed values:
1: Pend: Generates an interrupt request

SWI36

Bit 4: Software interrupt on line 36.

Allowed values:
1: Pend: Generates an interrupt request

SWI37

Bit 5: Software interrupt on line 37.

Allowed values:
1: Pend: Generates an interrupt request

SWI38

Bit 6: Software interrupt on line 38.

Allowed values:
1: Pend: Generates an interrupt request

PR2

Pending register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIF38
rw 		PIF37
rw 		PIF36
rw 		PIF35
rw
Toggle fields

PIF35

Bit 3: Pending interrupt flag on line 35.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF36

Bit 4: Pending interrupt flag on line 36.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF37

Bit 5: Pending interrupt flag on line 37.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF38

Bit 6: Pending interrupt flag on line 38.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FIREWALL

0x40011c00: Firewall

9/9 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSSA
0x4 CSL
0x8 NVDSSA
0xc NVDSL
0x10 VDSSA
0x14 VDSL
0x20 CR
Toggle registers

CSSA

Code segment start address

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD
rw
Toggle fields

ADD

Bits 8-23: code segment start address.

Allowed values: 0x0-0xffff

CSL

Code segment length

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LENG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENG
rw
Toggle fields

LENG

Bits 8-21: code segment length.

Allowed values: 0x0-0x3fff

NVDSSA

Non-volatile data segment start address

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD
rw
Toggle fields

ADD

Bits 8-23: Non-volatile data segment start address.

Allowed values: 0x0-0xffff

NVDSL

Non-volatile data segment length

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LENG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENG
rw
Toggle fields

LENG

Bits 8-21: Non-volatile data segment length.

Allowed values: 0x0-0x3fff

VDSSA

Volatile data segment start address

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD
rw
Toggle fields

ADD

Bits 6-15: Volatile data segment start address.

Allowed values: 0x0-0x3ff

VDSL

Volatile data segment length

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENG
rw
Toggle fields

LENG

Bits 6-15: Non-volatile data segment length.

Allowed values: 0x0-0x3ff

CR

Configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDE
rw 		VDS
rw 		FPA
rw
Toggle fields

FPA

Bit 0: Firewall pre alarm.

Allowed values:
0: PreArmReset: Any code executed outside the protected segment when the Firewall is opened will generate a system reset
1: PreArmSet: Any code executed outside the protected segment will close the Firewall

VDS

Bit 1: Volatile data shared.

Allowed values:
0: NotShared: Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed
1: Shared: Volatile data segment is shared with non protected application code

VDE

Bit 2: Volatile data execution.

Allowed values:
0: NotExecutable: Volatile data segment cannot be executed if VDS = 0
1: Executable: Volatile data segment is declared executable whatever VDS bit value

FLASH

0x40022000: Flash

4/72 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 PDKEYR
0x8 KEYR
0xc OPTKEYR
0x10 SR
0x14 CR
0x18 ECCR
0x20 OPTR
0x24 PCROP1SR
0x28 PCROP1ER
0x2c WRP1AR
0x30 WRP1BR
0x44 PCROP2SR
0x48 PCROP2ER
0x4c WRP2AR
0x50 WRP2BR
Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000600, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLEEP_PD
rw 		RUN_PD
rw 		DCRST
rw 		ICRST
rw 		DCEN
rw 		ICEN
rw 		PRFTEN
rw 		LATENCY
rw
Toggle fields

LATENCY

Bits 0-2: Latency.

PRFTEN

Bit 8: Prefetch enable.

ICEN

Bit 9: Instruction cache enable.

DCEN

Bit 10: Data cache enable.

ICRST

Bit 11: Instruction cache reset.

DCRST

Bit 12: Data cache reset.

RUN_PD

Bit 13: Flash Power-down mode during Low-power run mode.

SLEEP_PD

Bit 14: Flash Power-down mode during Low-power sleep mode.

PDKEYR

Power down key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR
w
Toggle fields

PDKEYR

Bits 0-31: RUN_PD in FLASH_ACR key.

KEYR

Flash key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYR
w
Toggle fields

KEYR

Bits 0-31: KEYR.

OPTKEYR

Option byte key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle fields

OPTKEYR

Bits 0-31: Option byte key.

SR

Status register

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR
rw 		RDERR
rw 		FASTERR
rw 		MISERR
rw 		PGSERR
rw 		SIZERR
rw 		PGAERR
rw 		WRPERR
rw 		PROGERR
rw 		OPERR
rw 		EOP
rw
Toggle fields

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: Write protected error.

PGAERR

Bit 5: Programming alignment error.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

RDERR

Bit 14: PCROP read error.

OPTVERR

Bit 15: Option validity error.

BSY

Bit 16: Busy.

CR

Flash control register

Offset: 0x14, size: 32, reset: 0xC0000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw 		OPTLOCK
rw 		OBL_LAUNCH
rw 		RDERRIE
rw 		ERRIE
rw 		EOPIE
rw 		FSTPG
rw 		OPTSTRT
rw 		START
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MER2
rw 		BKER
rw 		PNB
rw 		MER1
rw 		PER
rw 		PG
rw
Toggle fields

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER1

Bit 2: Bank 1 Mass erase.

PNB

Bits 3-10: Page number.

BKER

Bit 11: Bank erase.

MER2

Bit 15: Bank 2 Mass erase.

START

Bit 16: Start.

OPTSTRT

Bit 17: Options modification start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: PCROP read error interrupt enable.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

LOCK

Bit 31: FLASH_CR Lock.

ECCR

Flash ECC register

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD
rw 		ECCC
rw 		ECCIE
rw 		SYSF_ECC
r 		BK_ECC
r 		ADDR_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC
r
Toggle fields

ADDR_ECC

Bits 0-18: ECC fail address.

BK_ECC

Bit 19: ECC fail bank.

SYSF_ECC

Bit 20: System Flash ECC fail.

ECCIE

Bit 24: ECC correction interrupt enable.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x20, size: 32, reset: 0xF0000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
nBOOT0
rw 		nSWBOOT0
rw 		SRAM2_RST
rw 		SRAM2_PE
rw 		nBOOT1
rw 		DUALBANK
rw 		BFB2
rw 		WWDG_SW
rw 		IWDG_STDBY
rw 		IWDG_STOP
rw 		IDWG_SW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_STDBY
rw 		nRST_STOP
rw 		BOR_LEV
rw 		RDP
rw
Toggle fields

RDP

Bits 0-7: Read protection level.

BOR_LEV

Bits 8-10: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

IDWG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

BFB2

Bit 20: Dual-bank boot.

DUALBANK

Bit 21: Dual-Bank on 512 KB or 256 KB Flash memory devices.

nBOOT1

Bit 23: Boot configuration.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: Software BOOT0.

nBOOT0

Bit 27: nBOOT0 option bit.

PCROP1SR

Flash Bank 1 PCROP Start address register

Offset: 0x24, size: 32, reset: 0xFFFF0000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1_STRT
rw
Toggle fields

PCROP1_STRT

Bits 0-15: Bank 1 PCROP area start offset.

PCROP1ER

Flash Bank 1 PCROP End address register

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCROP_RDP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1_END
rw
Toggle fields

PCROP1_END

Bits 0-15: Bank 1 PCROP area end offset.

PCROP_RDP

Bit 31: PCROP area preserved when RDP level decreased.

WRP1AR

Flash Bank 1 WRP area A address register

Offset: 0x2c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1A_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1A_STRT
rw
Toggle fields

WRP1A_STRT

Bits 0-7: Bank 1 WRP first area start offset.

WRP1A_END

Bits 16-23: Bank 1 WRP first area A end offset.

WRP1BR

Flash Bank 1 WRP area B address register

Offset: 0x30, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1B_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1B_STRT
rw
Toggle fields

WRP1B_STRT

Bits 0-7: Bank 1 WRP second area B start offset.

WRP1B_END

Bits 16-23: Bank 1 WRP second area B end offset.

PCROP2SR

Flash Bank 2 PCROP Start address register

Offset: 0x44, size: 32, reset: 0xFFFF0000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2_STRT
rw
Toggle fields

PCROP2_STRT

Bits 0-15: Bank 2 PCROP area start offset.

PCROP2ER

Flash Bank 2 PCROP End address register

Offset: 0x48, size: 32, reset: 0xFFFF0000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2_END
rw
Toggle fields

PCROP2_END

Bits 0-15: Bank 2 PCROP area end offset.

WRP2AR

Flash Bank 2 WRP area A address register

Offset: 0x4c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2A_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2A_STRT
rw
Toggle fields

WRP2A_STRT

Bits 0-7: Bank 2 WRP first area A start offset.

WRP2A_END

Bits 16-23: Bank 2 WRP first area A end offset.

WRP2BR

Flash Bank 2 WRP area B address register

Offset: 0x50, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2B_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2B_STRT
rw
Toggle fields

WRP2B_STRT

Bits 0-7: Bank 2 WRP second area B start offset.

WRP2B_END

Bits 16-23: Bank 2 WRP second area B end offset.

FMC

0xa0000000: Flexible memory controller

2/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BCR1
0x4 BTR1
0x8 BCR2
0xc BTR2
0x10 BCR3
0x14 BTR3
0x18 BCR4
0x1c BTR4
0x80 PCR
0x84 SR
0x88 PMEM
0x8c PATT
0x94 ECCR
0x104 BWTR1
0x10c BWTR2
0x114 BWTR3
0x11c BWTR4
Toggle registers

BCR1

SRAM/NOR-Flash chip-select control register 1

Offset: 0x0, size: 32, reset: 0x000030D0, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CBURSTRW

Bit 19: CBURSTRW.

CCLKEN

Bit 20: CCLKEN.

WFDIS

Bit 21: Write FIFO Disable.

BTR1

SRAM/NOR-Flash chip-select timing register 1

Offset: 0x4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BCR2

SRAM/NOR-Flash chip-select control register 2

Offset: 0x8, size: 32, reset: 0x000030D0, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CBURSTRW

Bit 19: CBURSTRW.

BTR2

SRAM/NOR-Flash chip-select timing register 2

Offset: 0xc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BCR3

SRAM/NOR-Flash chip-select control register 3

Offset: 0x10, size: 32, reset: 0x000030D0, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CBURSTRW

Bit 19: CBURSTRW.

BTR3

SRAM/NOR-Flash chip-select timing register 3

Offset: 0x14, size: 32, reset: 0xFFFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BCR4

SRAM/NOR-Flash chip-select control register 4

Offset: 0x18, size: 32, reset: 0x000030D0, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WRAPMOD
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CBURSTRW

Bit 19: CBURSTRW.

BTR4

SRAM/NOR-Flash chip-select timing register 4

Offset: 0x1c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

PCR

PC Card/NAND Flash control register 3

Offset: 0x80, size: 32, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw 		TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw 		TCLR
rw 		ECCEN
rw 		PWID
rw 		PTYP
rw 		PBKEN
rw 		PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: PWAITEN.

PBKEN

Bit 2: PBKEN.

PTYP

Bit 3: PTYP.

PWID

Bits 4-5: PWID.

ECCEN

Bit 6: ECCEN.

TCLR

Bits 9-12: TCLR.

TAR

Bits 13-16: TAR.

ECCPS

Bits 17-19: ECCPS.

SR

FIFO status and interrupt register 3

Offset: 0x84, size: 32, reset: 0x00000040, access: Unspecified

1/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r 		IFEN
rw 		ILEN
rw 		IREN
rw 		IFS
rw 		ILS
rw 		IRS
rw
Toggle fields

IRS

Bit 0: IRS.

ILS

Bit 1: ILS.

IFS

Bit 2: IFS.

IREN

Bit 3: IREN.

ILEN

Bit 4: ILEN.

IFEN

Bit 5: IFEN.

FEMPT

Bit 6: FEMPT.

PMEM

Common memory space timing register 3

Offset: 0x88, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZx
rw 		MEMHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAITx
rw 		MEMSETx
rw
Toggle fields

MEMSETx

Bits 0-7: MEMSETx.

MEMWAITx

Bits 8-15: MEMWAITx.

MEMHOLDx

Bits 16-23: MEMHOLDx.

MEMHIZx

Bits 24-31: MEMHIZx.

PATT

Attribute memory space timing register 3

Offset: 0x8c, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZx
rw 		ATTHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAITx
rw 		ATTSETx
rw
Toggle fields

ATTSETx

Bits 0-7: ATTSETx.

ATTWAITx

Bits 8-15: ATTWAITx.

ATTHOLDx

Bits 16-23: ATTHOLDx.

ATTHIZx

Bits 24-31: ATTHIZx.

ECCR

ECC result register 3

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCx
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECCx
r
Toggle fields

ECCx

Bits 0-31: ECCx.

BWTR1

SRAM/NOR-Flash write timing registers 1

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BWTR2

SRAM/NOR-Flash write timing registers 2

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BWTR3

SRAM/NOR-Flash write timing registers 3

Offset: 0x114, size: 32, reset: 0x0FFFFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

BWTR4

SRAM/NOR-Flash write timing registers 4

Offset: 0x11c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

FPU

0xe000ef34: Floting point unit

0/24 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FPCCR
0x4 FPCAR
0x8 FPSCR
Toggle registers

FPCCR

Floating-point context control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASPEN
rw 		LSPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MONRDY
rw 		BFRDY
rw 		MMRDY
rw 		HFRDY
rw 		THREAD
rw 		USER
rw 		LSPACT
rw
Toggle fields

LSPACT

Bit 0: LSPACT.

USER

Bit 1: USER.

THREAD

Bit 3: THREAD.

HFRDY

Bit 4: HFRDY.

MMRDY

Bit 5: MMRDY.

BFRDY

Bit 6: BFRDY.

MONRDY

Bit 8: MONRDY.

LSPEN

Bit 30: LSPEN.

ASPEN

Bit 31: ASPEN.

FPCAR

Floating-point context address register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 3-31: Location of unpopulated floating-point.

FPSCR

Floating-point status control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
N
rw 		Z
rw 		C
rw 		V
rw 		AHP
rw 		DN
rw 		FZ
rw 		RMode
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDC
rw 		IXC
rw 		UFC
rw 		OFC
rw 		DZC
rw 		IOC
rw
Toggle fields

IOC

Bit 0: Invalid operation cumulative exception bit.

DZC

Bit 1: Division by zero cumulative exception bit..

OFC

Bit 2: Overflow cumulative exception bit.

UFC

Bit 3: Underflow cumulative exception bit.

IXC

Bit 4: Inexact cumulative exception bit.

IDC

Bit 7: Input denormal cumulative exception bit..

RMode

Bits 22-23: Rounding Mode control field.

FZ

Bit 24: Flush-to-zero mode control bit:.

DN

Bit 25: Default NaN mode control bit.

AHP

Bit 26: Alternative half-precision control bit.

V

Bit 28: Overflow condition code flag.

C

Bit 29: Carry condition code flag.

Z

Bit 30: Zero condition code flag.

N

Bit 31: Negative condition code flag.

FPU_CPACR

0xe000ed88: Floating point unit CPACR

0/1 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CPACR
Toggle registers

CPACR

Coprocessor access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CP

Bits 20-23: CP.

GFXMMU

0x4002c000: Graphic MMU

9/4125 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 FCR
0x10 DVR
0x20 B0CR
0x24 B1CR
0x28 B2CR
0x2c B3CR
0xff4 VERR
0xff8 IPIDR
0xffc SIDR
0x1000 LUTL [0]
0x1004 LUTH [0]
0x1008 LUTL [1]
0x100c LUTH [1]
0x1010 LUTL [2]
0x1014 LUTH [2]
0x1018 LUTL [3]
0x101c LUTH [3]
0x1020 LUTL [4]
0x1024 LUTH [4]
0x1028 LUTL [5]
0x102c LUTH [5]
0x1030 LUTL [6]
0x1034 LUTH [6]
0x1038 LUTL [7]
0x103c LUTH [7]
0x1040 LUTL [8]
0x1044 LUTH [8]
0x1048 LUTL [9]
0x104c LUTH [9]
0x1050 LUTL [10]
0x1054 LUTH [10]
0x1058 LUTL [11]
0x105c LUTH [11]
0x1060 LUTL [12]
0x1064 LUTH [12]
0x1068 LUTL [13]
0x106c LUTH [13]
0x1070 LUTL [14]
0x1074 LUTH [14]
0x1078 LUTL [15]
0x107c LUTH [15]
0x1080 LUTL [16]
0x1084 LUTH [16]
0x1088 LUTL [17]
0x108c LUTH [17]
0x1090 LUTL [18]
0x1094 LUTH [18]
0x1098 LUTL [19]
0x109c LUTH [19]
0x10a0 LUTL [20]
0x10a4 LUTH [20]
0x10a8 LUTL [21]
0x10ac LUTH [21]
0x10b0 LUTL [22]
0x10b4 LUTH [22]
0x10b8 LUTL [23]
0x10bc LUTH [23]
0x10c0 LUTL [24]
0x10c4 LUTH [24]
0x10c8 LUTL [25]
0x10cc LUTH [25]
0x10d0 LUTL [26]
0x10d4 LUTH [26]
0x10d8 LUTL [27]
0x10dc LUTH [27]
0x10e0 LUTL [28]
0x10e4 LUTH [28]
0x10e8 LUTL [29]
0x10ec LUTH [29]
0x10f0 LUTL [30]
0x10f4 LUTH [30]
0x10f8 LUTL [31]
0x10fc LUTH [31]
0x1100 LUTL [32]
0x1104 LUTH [32]
0x1108 LUTL [33]
0x110c LUTH [33]
0x1110 LUTL [34]
0x1114 LUTH [34]
0x1118 LUTL [35]
0x111c LUTH [35]
0x1120 LUTL [36]
0x1124 LUTH [36]
0x1128 LUTL [37]
0x112c LUTH [37]
0x1130 LUTL [38]
0x1134 LUTH [38]
0x1138 LUTL [39]
0x113c LUTH [39]
0x1140 LUTL [40]
0x1144 LUTH [40]
0x1148 LUTL [41]
0x114c LUTH [41]
0x1150 LUTL [42]
0x1154 LUTH [42]
0x1158 LUTL [43]
0x115c LUTH [43]
0x1160 LUTL [44]
0x1164 LUTH [44]
0x1168 LUTL [45]
0x116c LUTH [45]
0x1170 LUTL [46]
0x1174 LUTH [46]
0x1178 LUTL [47]
0x117c LUTH [47]
0x1180 LUTL [48]
0x1184 LUTH [48]
0x1188 LUTL [49]
0x118c LUTH [49]
0x1190 LUTL [50]
0x1194 LUTH [50]
0x1198 LUTL [51]
0x119c LUTH [51]
0x11a0 LUTL [52]
0x11a4 LUTH [52]
0x11a8 LUTL [53]
0x11ac LUTH [53]
0x11b0 LUTL [54]
0x11b4 LUTH [54]
0x11b8 LUTL [55]
0x11bc LUTH [55]
0x11c0 LUTL [56]
0x11c4 LUTH [56]
0x11c8 LUTL [57]
0x11cc LUTH [57]
0x11d0 LUTL [58]
0x11d4 LUTH [58]
0x11d8 LUTL [59]
0x11dc LUTH [59]
0x11e0 LUTL [60]
0x11e4 LUTH [60]
0x11e8 LUTL [61]
0x11ec LUTH [61]
0x11f0 LUTL [62]
0x11f4 LUTH [62]
0x11f8 LUTL [63]
0x11fc LUTH [63]
0x1200 LUTL [64]
0x1204 LUTH [64]
0x1208 LUTL [65]
0x120c LUTH [65]
0x1210 LUTL [66]
0x1214 LUTH [66]
0x1218 LUTL [67]
0x121c LUTH [67]
0x1220 LUTL [68]
0x1224 LUTH [68]
0x1228 LUTL [69]
0x122c LUTH [69]
0x1230 LUTL [70]
0x1234 LUTH [70]
0x1238 LUTL [71]
0x123c LUTH [71]
0x1240 LUTL [72]
0x1244 LUTH [72]
0x1248 LUTL [73]
0x124c LUTH [73]
0x1250 LUTL [74]
0x1254 LUTH [74]
0x1258 LUTL [75]
0x125c LUTH [75]
0x1260 LUTL [76]
0x1264 LUTH [76]
0x1268 LUTL [77]
0x126c LUTH [77]
0x1270 LUTL [78]
0x1274 LUTH [78]
0x1278 LUTL [79]
0x127c LUTH [79]
0x1280 LUTL [80]
0x1284 LUTH [80]
0x1288 LUTL [81]
0x128c LUTH [81]
0x1290 LUTL [82]
0x1294 LUTH [82]
0x1298 LUTL [83]
0x129c LUTH [83]
0x12a0 LUTL [84]
0x12a4 LUTH [84]
0x12a8 LUTL [85]
0x12ac LUTH [85]
0x12b0 LUTL [86]
0x12b4 LUTH [86]
0x12b8 LUTL [87]
0x12bc LUTH [87]
0x12c0 LUTL [88]
0x12c4 LUTH [88]
0x12c8 LUTL [89]
0x12cc LUTH [89]
0x12d0 LUTL [90]
0x12d4 LUTH [90]
0x12d8 LUTL [91]
0x12dc LUTH [91]
0x12e0 LUTL [92]
0x12e4 LUTH [92]
0x12e8 LUTL [93]
0x12ec LUTH [93]
0x12f0 LUTL [94]
0x12f4 LUTH [94]
0x12f8 LUTL [95]
0x12fc LUTH [95]
0x1300 LUTL [96]
0x1304 LUTH [96]
0x1308 LUTL [97]
0x130c LUTH [97]
0x1310 LUTL [98]
0x1314 LUTH [98]
0x1318 LUTL [99]
0x131c LUTH [99]
0x1320 LUTL [100]
0x1324 LUTH [100]
0x1328 LUTL [101]
0x132c LUTH [101]
0x1330 LUTL [102]
0x1334 LUTH [102]
0x1338 LUTL [103]
0x133c LUTH [103]
0x1340 LUTL [104]
0x1344 LUTH [104]
0x1348 LUTL [105]
0x134c LUTH [105]
0x1350 LUTL [106]
0x1354 LUTH [106]
0x1358 LUTL [107]
0x135c LUTH [107]
0x1360 LUTL [108]
0x1364 LUTH [108]
0x1368 LUTL [109]
0x136c LUTH [109]
0x1370 LUTL [110]
0x1374 LUTH [110]
0x1378 LUTL [111]
0x137c LUTH [111]
0x1380 LUTL [112]
0x1384 LUTH [112]
0x1388 LUTL [113]
0x138c LUTH [113]
0x1390 LUTL [114]
0x1394 LUTH [114]
0x1398 LUTL [115]
0x139c LUTH [115]
0x13a0 LUTL [116]
0x13a4 LUTH [116]
0x13a8 LUTL [117]
0x13ac LUTH [117]
0x13b0 LUTL [118]
0x13b4 LUTH [118]
0x13b8 LUTL [119]
0x13bc LUTH [119]
0x13c0 LUTL [120]
0x13c4 LUTH [120]
0x13c8 LUTL [121]
0x13cc LUTH [121]
0x13d0 LUTL [122]
0x13d4 LUTH [122]
0x13d8 LUTL [123]
0x13dc LUTH [123]
0x13e0 LUTL [124]
0x13e4 LUTH [124]
0x13e8 LUTL [125]
0x13ec LUTH [125]
0x13f0 LUTL [126]
0x13f4 LUTH [126]
0x13f8 LUTL [127]
0x13fc LUTH [127]
0x1400 LUTL [128]
0x1404 LUTH [128]
0x1408 LUTL [129]
0x140c LUTH [129]
0x1410 LUTL [130]
0x1414 LUTH [130]
0x1418 LUTL [131]
0x141c LUTH [131]
0x1420 LUTL [132]
0x1424 LUTH [132]
0x1428 LUTL [133]
0x142c LUTH [133]
0x1430 LUTL [134]
0x1434 LUTH [134]
0x1438 LUTL [135]
0x143c LUTH [135]
0x1440 LUTL [136]
0x1444 LUTH [136]
0x1448 LUTL [137]
0x144c LUTH [137]
0x1450 LUTL [138]
0x1454 LUTH [138]
0x1458 LUTL [139]
0x145c LUTH [139]
0x1460 LUTL [140]
0x1464 LUTH [140]
0x1468 LUTL [141]
0x146c LUTH [141]
0x1470 LUTL [142]
0x1474 LUTH [142]
0x1478 LUTL [143]
0x147c LUTH [143]
0x1480 LUTL [144]
0x1484 LUTH [144]
0x1488 LUTL [145]
0x148c LUTH [145]
0x1490 LUTL [146]
0x1494 LUTH [146]
0x1498 LUTL [147]
0x149c LUTH [147]
0x14a0 LUTL [148]
0x14a4 LUTH [148]
0x14a8 LUTL [149]
0x14ac LUTH [149]
0x14b0 LUTL [150]
0x14b4 LUTH [150]
0x14b8 LUTL [151]
0x14bc LUTH [151]
0x14c0 LUTL [152]
0x14c4 LUTH [152]
0x14c8 LUTL [153]
0x14cc LUTH [153]
0x14d0 LUTL [154]
0x14d4 LUTH [154]
0x14d8 LUTL [155]
0x14dc LUTH [155]
0x14e0 LUTL [156]
0x14e4 LUTH [156]
0x14e8 LUTL [157]
0x14ec LUTH [157]
0x14f0 LUTL [158]
0x14f4 LUTH [158]
0x14f8 LUTL [159]
0x14fc LUTH [159]
0x1500 LUTL [160]
0x1504 LUTH [160]
0x1508 LUTL [161]
0x150c LUTH [161]
0x1510 LUTL [162]
0x1514 LUTH [162]
0x1518 LUTL [163]
0x151c LUTH [163]
0x1520 LUTL [164]
0x1524 LUTH [164]
0x1528 LUTL [165]
0x152c LUTH [165]
0x1530 LUTL [166]
0x1534 LUTH [166]
0x1538 LUTL [167]
0x153c LUTH [167]
0x1540 LUTL [168]
0x1544 LUTH [168]
0x1548 LUTL [169]
0x154c LUTH [169]
0x1550 LUTL [170]
0x1554 LUTH [170]
0x1558 LUTL [171]
0x155c LUTH [171]
0x1560 LUTL [172]
0x1564 LUTH [172]
0x1568 LUTL [173]
0x156c LUTH [173]
0x1570 LUTL [174]
0x1574 LUTH [174]
0x1578 LUTL [175]
0x157c LUTH [175]
0x1580 LUTL [176]
0x1584 LUTH [176]
0x1588 LUTL [177]
0x158c LUTH [177]
0x1590 LUTL [178]
0x1594 LUTH [178]
0x1598 LUTL [179]
0x159c LUTH [179]
0x15a0 LUTL [180]
0x15a4 LUTH [180]
0x15a8 LUTL [181]
0x15ac LUTH [181]
0x15b0 LUTL [182]
0x15b4 LUTH [182]
0x15b8 LUTL [183]
0x15bc LUTH [183]
0x15c0 LUTL [184]
0x15c4 LUTH [184]
0x15c8 LUTL [185]
0x15cc LUTH [185]
0x15d0 LUTL [186]
0x15d4 LUTH [186]
0x15d8 LUTL [187]
0x15dc LUTH [187]
0x15e0 LUTL [188]
0x15e4 LUTH [188]
0x15e8 LUTL [189]
0x15ec LUTH [189]
0x15f0 LUTL [190]
0x15f4 LUTH [190]
0x15f8 LUTL [191]
0x15fc LUTH [191]
0x1600 LUTL [192]
0x1604 LUTH [192]
0x1608 LUTL [193]
0x160c LUTH [193]
0x1610 LUTL [194]
0x1614 LUTH [194]
0x1618 LUTL [195]
0x161c LUTH [195]
0x1620 LUTL [196]
0x1624 LUTH [196]
0x1628 LUTL [197]
0x162c LUTH [197]
0x1630 LUTL [198]
0x1634 LUTH [198]
0x1638 LUTL [199]
0x163c LUTH [199]
0x1640 LUTL [200]
0x1644 LUTH [200]
0x1648 LUTL [201]
0x164c LUTH [201]
0x1650 LUTL [202]
0x1654 LUTH [202]
0x1658 LUTL [203]
0x165c LUTH [203]
0x1660 LUTL [204]
0x1664 LUTH [204]
0x1668 LUTL [205]
0x166c LUTH [205]
0x1670 LUTL [206]
0x1674 LUTH [206]
0x1678 LUTL [207]
0x167c LUTH [207]
0x1680 LUTL [208]
0x1684 LUTH [208]
0x1688 LUTL [209]
0x168c LUTH [209]
0x1690 LUTL [210]
0x1694 LUTH [210]
0x1698 LUTL [211]
0x169c LUTH [211]
0x16a0 LUTL [212]
0x16a4 LUTH [212]
0x16a8 LUTL [213]
0x16ac LUTH [213]
0x16b0 LUTL [214]
0x16b4 LUTH [214]
0x16b8 LUTL [215]
0x16bc LUTH [215]
0x16c0 LUTL [216]
0x16c4 LUTH [216]
0x16c8 LUTL [217]
0x16cc LUTH [217]
0x16d0 LUTL [218]
0x16d4 LUTH [218]
0x16d8 LUTL [219]
0x16dc LUTH [219]
0x16e0 LUTL [220]
0x16e4 LUTH [220]
0x16e8 LUTL [221]
0x16ec LUTH [221]
0x16f0 LUTL [222]
0x16f4 LUTH [222]
0x16f8 LUTL [223]
0x16fc LUTH [223]
0x1700 LUTL [224]
0x1704 LUTH [224]
0x1708 LUTL [225]
0x170c LUTH [225]
0x1710 LUTL [226]
0x1714 LUTH [226]
0x1718 LUTL [227]
0x171c LUTH [227]
0x1720 LUTL [228]
0x1724 LUTH [228]
0x1728 LUTL [229]
0x172c LUTH [229]
0x1730 LUTL [230]
0x1734 LUTH [230]
0x1738 LUTL [231]
0x173c LUTH [231]
0x1740 LUTL [232]
0x1744 LUTH [232]
0x1748 LUTL [233]
0x174c LUTH [233]
0x1750 LUTL [234]
0x1754 LUTH [234]
0x1758 LUTL [235]
0x175c LUTH [235]
0x1760 LUTL [236]
0x1764 LUTH [236]
0x1768 LUTL [237]
0x176c LUTH [237]
0x1770 LUTL [238]
0x1774 LUTH [238]
0x1778 LUTL [239]
0x177c LUTH [239]
0x1780 LUTL [240]
0x1784 LUTH [240]
0x1788 LUTL [241]
0x178c LUTH [241]
0x1790 LUTL [242]
0x1794 LUTH [242]
0x1798 LUTL [243]
0x179c LUTH [243]
0x17a0 LUTL [244]
0x17a4 LUTH [244]
0x17a8 LUTL [245]
0x17ac LUTH [245]
0x17b0 LUTL [246]
0x17b4 LUTH [246]
0x17b8 LUTL [247]
0x17bc LUTH [247]
0x17c0 LUTL [248]
0x17c4 LUTH [248]
0x17c8 LUTL [249]
0x17cc LUTH [249]
0x17d0 LUTL [250]
0x17d4 LUTH [250]
0x17d8 LUTL [251]
0x17dc LUTH [251]
0x17e0 LUTL [252]
0x17e4 LUTH [252]
0x17e8 LUTL [253]
0x17ec LUTH [253]
0x17f0 LUTL [254]
0x17f4 LUTH [254]
0x17f8 LUTL [255]
0x17fc LUTH [255]
0x1800 LUTL [256]
0x1804 LUTH [256]
0x1808 LUTL [257]
0x180c LUTH [257]
0x1810 LUTL [258]
0x1814 LUTH [258]
0x1818 LUTL [259]
0x181c LUTH [259]
0x1820 LUTL [260]
0x1824 LUTH [260]
0x1828 LUTL [261]
0x182c LUTH [261]
0x1830 LUTL [262]
0x1834 LUTH [262]
0x1838 LUTL [263]
0x183c LUTH [263]
0x1840 LUTL [264]
0x1844 LUTH [264]
0x1848 LUTL [265]
0x184c LUTH [265]
0x1850 LUTL [266]
0x1854 LUTH [266]
0x1858 LUTL [267]
0x185c LUTH [267]
0x1860 LUTL [268]
0x1864 LUTH [268]
0x1868 LUTL [269]
0x186c LUTH [269]
0x1870 LUTL [270]
0x1874 LUTH [270]
0x1878 LUTL [271]
0x187c LUTH [271]
0x1880 LUTL [272]
0x1884 LUTH [272]
0x1888 LUTL [273]
0x188c LUTH [273]
0x1890 LUTL [274]
0x1894 LUTH [274]
0x1898 LUTL [275]
0x189c LUTH [275]
0x18a0 LUTL [276]
0x18a4 LUTH [276]
0x18a8 LUTL [277]
0x18ac LUTH [277]
0x18b0 LUTL [278]
0x18b4 LUTH [278]
0x18b8 LUTL [279]
0x18bc LUTH [279]
0x18c0 LUTL [280]
0x18c4 LUTH [280]
0x18c8 LUTL [281]
0x18cc LUTH [281]
0x18d0 LUTL [282]
0x18d4 LUTH [282]
0x18d8 LUTL [283]
0x18dc LUTH [283]
0x18e0 LUTL [284]
0x18e4 LUTH [284]
0x18e8 LUTL [285]
0x18ec LUTH [285]
0x18f0 LUTL [286]
0x18f4 LUTH [286]
0x18f8 LUTL [287]
0x18fc LUTH [287]
0x1900 LUTL [288]
0x1904 LUTH [288]
0x1908 LUTL [289]
0x190c LUTH [289]
0x1910 LUTL [290]
0x1914 LUTH [290]
0x1918 LUTL [291]
0x191c LUTH [291]
0x1920 LUTL [292]
0x1924 LUTH [292]
0x1928 LUTL [293]
0x192c LUTH [293]
0x1930 LUTL [294]
0x1934 LUTH [294]
0x1938 LUTL [295]
0x193c LUTH [295]
0x1940 LUTL [296]
0x1944 LUTH [296]
0x1948 LUTL [297]
0x194c LUTH [297]
0x1950 LUTL [298]
0x1954 LUTH [298]
0x1958 LUTL [299]
0x195c LUTH [299]
0x1960 LUTL [300]
0x1964 LUTH [300]
0x1968 LUTL [301]
0x196c LUTH [301]
0x1970 LUTL [302]
0x1974 LUTH [302]
0x1978 LUTL [303]
0x197c LUTH [303]
0x1980 LUTL [304]
0x1984 LUTH [304]
0x1988 LUTL [305]
0x198c LUTH [305]
0x1990 LUTL [306]
0x1994 LUTH [306]
0x1998 LUTL [307]
0x199c LUTH [307]
0x19a0 LUTL [308]
0x19a4 LUTH [308]
0x19a8 LUTL [309]
0x19ac LUTH [309]
0x19b0 LUTL [310]
0x19b4 LUTH [310]
0x19b8 LUTL [311]
0x19bc LUTH [311]
0x19c0 LUTL [312]
0x19c4 LUTH [312]
0x19c8 LUTL [313]
0x19cc LUTH [313]
0x19d0 LUTL [314]
0x19d4 LUTH [314]
0x19d8 LUTL [315]
0x19dc LUTH [315]
0x19e0 LUTL [316]
0x19e4 LUTH [316]
0x19e8 LUTL [317]
0x19ec LUTH [317]
0x19f0 LUTL [318]
0x19f4 LUTH [318]
0x19f8 LUTL [319]
0x19fc LUTH [319]
0x1a00 LUTL [320]
0x1a04 LUTH [320]
0x1a08 LUTL [321]
0x1a0c LUTH [321]
0x1a10 LUTL [322]
0x1a14 LUTH [322]
0x1a18 LUTL [323]
0x1a1c LUTH [323]
0x1a20 LUTL [324]
0x1a24 LUTH [324]
0x1a28 LUTL [325]
0x1a2c LUTH [325]
0x1a30 LUTL [326]
0x1a34 LUTH [326]
0x1a38 LUTL [327]
0x1a3c LUTH [327]
0x1a40 LUTL [328]
0x1a44 LUTH [328]
0x1a48 LUTL [329]
0x1a4c LUTH [329]
0x1a50 LUTL [330]
0x1a54 LUTH [330]
0x1a58 LUTL [331]
0x1a5c LUTH [331]
0x1a60 LUTL [332]
0x1a64 LUTH [332]
0x1a68 LUTL [333]
0x1a6c LUTH [333]
0x1a70 LUTL [334]
0x1a74 LUTH [334]
0x1a78 LUTL [335]
0x1a7c LUTH [335]
0x1a80 LUTL [336]
0x1a84 LUTH [336]
0x1a88 LUTL [337]
0x1a8c LUTH [337]
0x1a90 LUTL [338]
0x1a94 LUTH [338]
0x1a98 LUTL [339]
0x1a9c LUTH [339]
0x1aa0 LUTL [340]
0x1aa4 LUTH [340]
0x1aa8 LUTL [341]
0x1aac LUTH [341]
0x1ab0 LUTL [342]
0x1ab4 LUTH [342]
0x1ab8 LUTL [343]
0x1abc LUTH [343]
0x1ac0 LUTL [344]
0x1ac4 LUTH [344]
0x1ac8 LUTL [345]
0x1acc LUTH [345]
0x1ad0 LUTL [346]
0x1ad4 LUTH [346]
0x1ad8 LUTL [347]
0x1adc LUTH [347]
0x1ae0 LUTL [348]
0x1ae4 LUTH [348]
0x1ae8 LUTL [349]
0x1aec LUTH [349]
0x1af0 LUTL [350]
0x1af4 LUTH [350]
0x1af8 LUTL [351]
0x1afc LUTH [351]
0x1b00 LUTL [352]
0x1b04 LUTH [352]
0x1b08 LUTL [353]
0x1b0c LUTH [353]
0x1b10 LUTL [354]
0x1b14 LUTH [354]
0x1b18 LUTL [355]
0x1b1c LUTH [355]
0x1b20 LUTL [356]
0x1b24 LUTH [356]
0x1b28 LUTL [357]
0x1b2c LUTH [357]
0x1b30 LUTL [358]
0x1b34 LUTH [358]
0x1b38 LUTL [359]
0x1b3c LUTH [359]
0x1b40 LUTL [360]
0x1b44 LUTH [360]
0x1b48 LUTL [361]
0x1b4c LUTH [361]
0x1b50 LUTL [362]
0x1b54 LUTH [362]
0x1b58 LUTL [363]
0x1b5c LUTH [363]
0x1b60 LUTL [364]
0x1b64 LUTH [364]
0x1b68 LUTL [365]
0x1b6c LUTH [365]
0x1b70 LUTL [366]
0x1b74 LUTH [366]
0x1b78 LUTL [367]
0x1b7c LUTH [367]
0x1b80 LUTL [368]
0x1b84 LUTH [368]
0x1b88 LUTL [369]
0x1b8c LUTH [369]
0x1b90 LUTL [370]
0x1b94 LUTH [370]
0x1b98 LUTL [371]
0x1b9c LUTH [371]
0x1ba0 LUTL [372]
0x1ba4 LUTH [372]
0x1ba8 LUTL [373]
0x1bac LUTH [373]
0x1bb0 LUTL [374]
0x1bb4 LUTH [374]
0x1bb8 LUTL [375]
0x1bbc LUTH [375]
0x1bc0 LUTL [376]
0x1bc4 LUTH [376]
0x1bc8 LUTL [377]
0x1bcc LUTH [377]
0x1bd0 LUTL [378]
0x1bd4 LUTH [378]
0x1bd8 LUTL [379]
0x1bdc LUTH [379]
0x1be0 LUTL [380]
0x1be4 LUTH [380]
0x1be8 LUTL [381]
0x1bec LUTH [381]
0x1bf0 LUTL [382]
0x1bf4 LUTH [382]
0x1bf8 LUTL [383]
0x1bfc LUTH [383]
0x1c00 LUTL [384]
0x1c04 LUTH [384]
0x1c08 LUTL [385]
0x1c0c LUTH [385]
0x1c10 LUTL [386]
0x1c14 LUTH [386]
0x1c18 LUTL [387]
0x1c1c LUTH [387]
0x1c20 LUTL [388]
0x1c24 LUTH [388]
0x1c28 LUTL [389]
0x1c2c LUTH [389]
0x1c30 LUTL [390]
0x1c34 LUTH [390]
0x1c38 LUTL [391]
0x1c3c LUTH [391]
0x1c40 LUTL [392]
0x1c44 LUTH [392]
0x1c48 LUTL [393]
0x1c4c LUTH [393]
0x1c50 LUTL [394]
0x1c54 LUTH [394]
0x1c58 LUTL [395]
0x1c5c LUTH [395]
0x1c60 LUTL [396]
0x1c64 LUTH [396]
0x1c68 LUTL [397]
0x1c6c LUTH [397]
0x1c70 LUTL [398]
0x1c74 LUTH [398]
0x1c78 LUTL [399]
0x1c7c LUTH [399]
0x1c80 LUTL [400]
0x1c84 LUTH [400]
0x1c88 LUTL [401]
0x1c8c LUTH [401]
0x1c90 LUTL [402]
0x1c94 LUTH [402]
0x1c98 LUTL [403]
0x1c9c LUTH [403]
0x1ca0 LUTL [404]
0x1ca4 LUTH [404]
0x1ca8 LUTL [405]
0x1cac LUTH [405]
0x1cb0 LUTL [406]
0x1cb4 LUTH [406]
0x1cb8 LUTL [407]
0x1cbc LUTH [407]
0x1cc0 LUTL [408]
0x1cc4 LUTH [408]
0x1cc8 LUTL [409]
0x1ccc LUTH [409]
0x1cd0 LUTL [410]
0x1cd4 LUTH [410]
0x1cd8 LUTL [411]
0x1cdc LUTH [411]
0x1ce0 LUTL [412]
0x1ce4 LUTH [412]
0x1ce8 LUTL [413]
0x1cec LUTH [413]
0x1cf0 LUTL [414]
0x1cf4 LUTH [414]
0x1cf8 LUTL [415]
0x1cfc LUTH [415]
0x1d00 LUTL [416]
0x1d04 LUTH [416]
0x1d08 LUTL [417]
0x1d0c LUTH [417]
0x1d10 LUTL [418]
0x1d14 LUTH [418]
0x1d18 LUTL [419]
0x1d1c LUTH [419]
0x1d20 LUTL [420]
0x1d24 LUTH [420]
0x1d28 LUTL [421]
0x1d2c LUTH [421]
0x1d30 LUTL [422]
0x1d34 LUTH [422]
0x1d38 LUTL [423]
0x1d3c LUTH [423]
0x1d40 LUTL [424]
0x1d44 LUTH [424]
0x1d48 LUTL [425]
0x1d4c LUTH [425]
0x1d50 LUTL [426]
0x1d54 LUTH [426]
0x1d58 LUTL [427]
0x1d5c LUTH [427]
0x1d60 LUTL [428]
0x1d64 LUTH [428]
0x1d68 LUTL [429]
0x1d6c LUTH [429]
0x1d70 LUTL [430]
0x1d74 LUTH [430]
0x1d78 LUTL [431]
0x1d7c LUTH [431]
0x1d80 LUTL [432]
0x1d84 LUTH [432]
0x1d88 LUTL [433]
0x1d8c LUTH [433]
0x1d90 LUTL [434]
0x1d94 LUTH [434]
0x1d98 LUTL [435]
0x1d9c LUTH [435]
0x1da0 LUTL [436]
0x1da4 LUTH [436]
0x1da8 LUTL [437]
0x1dac LUTH [437]
0x1db0 LUTL [438]
0x1db4 LUTH [438]
0x1db8 LUTL [439]
0x1dbc LUTH [439]
0x1dc0 LUTL [440]
0x1dc4 LUTH [440]
0x1dc8 LUTL [441]
0x1dcc LUTH [441]
0x1dd0 LUTL [442]
0x1dd4 LUTH [442]
0x1dd8 LUTL [443]
0x1ddc LUTH [443]
0x1de0 LUTL [444]
0x1de4 LUTH [444]
0x1de8 LUTL [445]
0x1dec LUTH [445]
0x1df0 LUTL [446]
0x1df4 LUTH [446]
0x1df8 LUTL [447]
0x1dfc LUTH [447]
0x1e00 LUTL [448]
0x1e04 LUTH [448]
0x1e08 LUTL [449]
0x1e0c LUTH [449]
0x1e10 LUTL [450]
0x1e14 LUTH [450]
0x1e18 LUTL [451]
0x1e1c LUTH [451]
0x1e20 LUTL [452]
0x1e24 LUTH [452]
0x1e28 LUTL [453]
0x1e2c LUTH [453]
0x1e30 LUTL [454]
0x1e34 LUTH [454]
0x1e38 LUTL [455]
0x1e3c LUTH [455]
0x1e40 LUTL [456]
0x1e44 LUTH [456]
0x1e48 LUTL [457]
0x1e4c LUTH [457]
0x1e50 LUTL [458]
0x1e54 LUTH [458]
0x1e58 LUTL [459]
0x1e5c LUTH [459]
0x1e60 LUTL [460]
0x1e64 LUTH [460]
0x1e68 LUTL [461]
0x1e6c LUTH [461]
0x1e70 LUTL [462]
0x1e74 LUTH [462]
0x1e78 LUTL [463]
0x1e7c LUTH [463]
0x1e80 LUTL [464]
0x1e84 LUTH [464]
0x1e88 LUTL [465]
0x1e8c LUTH [465]
0x1e90 LUTL [466]
0x1e94 LUTH [466]
0x1e98 LUTL [467]
0x1e9c LUTH [467]
0x1ea0 LUTL [468]
0x1ea4 LUTH [468]
0x1ea8 LUTL [469]
0x1eac LUTH [469]
0x1eb0 LUTL [470]
0x1eb4 LUTH [470]
0x1eb8 LUTL [471]
0x1ebc LUTH [471]
0x1ec0 LUTL [472]
0x1ec4 LUTH [472]
0x1ec8 LUTL [473]
0x1ecc LUTH [473]
0x1ed0 LUTL [474]
0x1ed4 LUTH [474]
0x1ed8 LUTL [475]
0x1edc LUTH [475]
0x1ee0 LUTL [476]
0x1ee4 LUTH [476]
0x1ee8 LUTL [477]
0x1eec LUTH [477]
0x1ef0 LUTL [478]
0x1ef4 LUTH [478]
0x1ef8 LUTL [479]
0x1efc LUTH [479]
0x1f00 LUTL [480]
0x1f04 LUTH [480]
0x1f08 LUTL [481]
0x1f0c LUTH [481]
0x1f10 LUTL [482]
0x1f14 LUTH [482]
0x1f18 LUTL [483]
0x1f1c LUTH [483]
0x1f20 LUTL [484]
0x1f24 LUTH [484]
0x1f28 LUTL [485]
0x1f2c LUTH [485]
0x1f30 LUTL [486]
0x1f34 LUTH [486]
0x1f38 LUTL [487]
0x1f3c LUTH [487]
0x1f40 LUTL [488]
0x1f44 LUTH [488]
0x1f48 LUTL [489]
0x1f4c LUTH [489]
0x1f50 LUTL [490]
0x1f54 LUTH [490]
0x1f58 LUTL [491]
0x1f5c LUTH [491]
0x1f60 LUTL [492]
0x1f64 LUTH [492]
0x1f68 LUTL [493]
0x1f6c LUTH [493]
0x1f70 LUTL [494]
0x1f74 LUTH [494]
0x1f78 LUTL [495]
0x1f7c LUTH [495]
0x1f80 LUTL [496]
0x1f84 LUTH [496]
0x1f88 LUTL [497]
0x1f8c LUTH [497]
0x1f90 LUTL [498]
0x1f94 LUTH [498]
0x1f98 LUTL [499]
0x1f9c LUTH [499]
0x1fa0 LUTL [500]
0x1fa4 LUTH [500]
0x1fa8 LUTL [501]
0x1fac LUTH [501]
0x1fb0 LUTL [502]
0x1fb4 LUTH [502]
0x1fb8 LUTL [503]
0x1fbc LUTH [503]
0x1fc0 LUTL [504]
0x1fc4 LUTH [504]
0x1fc8 LUTL [505]
0x1fcc LUTH [505]
0x1fd0 LUTL [506]
0x1fd4 LUTH [506]
0x1fd8 LUTL [507]
0x1fdc LUTH [507]
0x1fe0 LUTL [508]
0x1fe4 LUTH [508]
0x1fe8 LUTL [509]
0x1fec LUTH [509]
0x1ff0 LUTL [510]
0x1ff4 LUTH [510]
0x1ff8 LUTL [511]
0x1ffc LUTH [511]
0x2000 LUTL [512]
0x2004 LUTH [512]
0x2008 LUTL [513]
0x200c LUTH [513]
0x2010 LUTL [514]
0x2014 LUTH [514]
0x2018 LUTL [515]
0x201c LUTH [515]
0x2020 LUTL [516]
0x2024 LUTH [516]
0x2028 LUTL [517]
0x202c LUTH [517]
0x2030 LUTL [518]
0x2034 LUTH [518]
0x2038 LUTL [519]
0x203c LUTH [519]
0x2040 LUTL [520]
0x2044 LUTH [520]
0x2048 LUTL [521]
0x204c LUTH [521]
0x2050 LUTL [522]
0x2054 LUTH [522]
0x2058 LUTL [523]
0x205c LUTH [523]
0x2060 LUTL [524]
0x2064 LUTH [524]
0x2068 LUTL [525]
0x206c LUTH [525]
0x2070 LUTL [526]
0x2074 LUTH [526]
0x2078 LUTL [527]
0x207c LUTH [527]
0x2080 LUTL [528]
0x2084 LUTH [528]
0x2088 LUTL [529]
0x208c LUTH [529]
0x2090 LUTL [530]
0x2094 LUTH [530]
0x2098 LUTL [531]
0x209c LUTH [531]
0x20a0 LUTL [532]
0x20a4 LUTH [532]
0x20a8 LUTL [533]
0x20ac LUTH [533]
0x20b0 LUTL [534]
0x20b4 LUTH [534]
0x20b8 LUTL [535]
0x20bc LUTH [535]
0x20c0 LUTL [536]
0x20c4 LUTH [536]
0x20c8 LUTL [537]
0x20cc LUTH [537]
0x20d0 LUTL [538]
0x20d4 LUTH [538]
0x20d8 LUTL [539]
0x20dc LUTH [539]
0x20e0 LUTL [540]
0x20e4 LUTH [540]
0x20e8 LUTL [541]
0x20ec LUTH [541]
0x20f0 LUTL [542]
0x20f4 LUTH [542]
0x20f8 LUTL [543]
0x20fc LUTH [543]
0x2100 LUTL [544]
0x2104 LUTH [544]
0x2108 LUTL [545]
0x210c LUTH [545]
0x2110 LUTL [546]
0x2114 LUTH [546]
0x2118 LUTL [547]
0x211c LUTH [547]
0x2120 LUTL [548]
0x2124 LUTH [548]
0x2128 LUTL [549]
0x212c LUTH [549]
0x2130 LUTL [550]
0x2134 LUTH [550]
0x2138 LUTL [551]
0x213c LUTH [551]
0x2140 LUTL [552]
0x2144 LUTH [552]
0x2148 LUTL [553]
0x214c LUTH [553]
0x2150 LUTL [554]
0x2154 LUTH [554]
0x2158 LUTL [555]
0x215c LUTH [555]
0x2160 LUTL [556]
0x2164 LUTH [556]
0x2168 LUTL [557]
0x216c LUTH [557]
0x2170 LUTL [558]
0x2174 LUTH [558]
0x2178 LUTL [559]
0x217c LUTH [559]
0x2180 LUTL [560]
0x2184 LUTH [560]
0x2188 LUTL [561]
0x218c LUTH [561]
0x2190 LUTL [562]
0x2194 LUTH [562]
0x2198 LUTL [563]
0x219c LUTH [563]
0x21a0 LUTL [564]
0x21a4 LUTH [564]
0x21a8 LUTL [565]
0x21ac LUTH [565]
0x21b0 LUTL [566]
0x21b4 LUTH [566]
0x21b8 LUTL [567]
0x21bc LUTH [567]
0x21c0 LUTL [568]
0x21c4 LUTH [568]
0x21c8 LUTL [569]
0x21cc LUTH [569]
0x21d0 LUTL [570]
0x21d4 LUTH [570]
0x21d8 LUTL [571]
0x21dc LUTH [571]
0x21e0 LUTL [572]
0x21e4 LUTH [572]
0x21e8 LUTL [573]
0x21ec LUTH [573]
0x21f0 LUTL [574]
0x21f4 LUTH [574]
0x21f8 LUTL [575]
0x21fc LUTH [575]
0x2200 LUTL [576]
0x2204 LUTH [576]
0x2208 LUTL [577]
0x220c LUTH [577]
0x2210 LUTL [578]
0x2214 LUTH [578]
0x2218 LUTL [579]
0x221c LUTH [579]
0x2220 LUTL [580]
0x2224 LUTH [580]
0x2228 LUTL [581]
0x222c LUTH [581]
0x2230 LUTL [582]
0x2234 LUTH [582]
0x2238 LUTL [583]
0x223c LUTH [583]
0x2240 LUTL [584]
0x2244 LUTH [584]
0x2248 LUTL [585]
0x224c LUTH [585]
0x2250 LUTL [586]
0x2254 LUTH [586]
0x2258 LUTL [587]
0x225c LUTH [587]
0x2260 LUTL [588]
0x2264 LUTH [588]
0x2268 LUTL [589]
0x226c LUTH [589]
0x2270 LUTL [590]
0x2274 LUTH [590]
0x2278 LUTL [591]
0x227c LUTH [591]
0x2280 LUTL [592]
0x2284 LUTH [592]
0x2288 LUTL [593]
0x228c LUTH [593]
0x2290 LUTL [594]
0x2294 LUTH [594]
0x2298 LUTL [595]
0x229c LUTH [595]
0x22a0 LUTL [596]
0x22a4 LUTH [596]
0x22a8 LUTL [597]
0x22ac LUTH [597]
0x22b0 LUTL [598]
0x22b4 LUTH [598]
0x22b8 LUTL [599]
0x22bc LUTH [599]
0x22c0 LUTL [600]
0x22c4 LUTH [600]
0x22c8 LUTL [601]
0x22cc LUTH [601]
0x22d0 LUTL [602]
0x22d4 LUTH [602]
0x22d8 LUTL [603]
0x22dc LUTH [603]
0x22e0 LUTL [604]
0x22e4 LUTH [604]
0x22e8 LUTL [605]
0x22ec LUTH [605]
0x22f0 LUTL [606]
0x22f4 LUTH [606]
0x22f8 LUTL [607]
0x22fc LUTH [607]
0x2300 LUTL [608]
0x2304 LUTH [608]
0x2308 LUTL [609]
0x230c LUTH [609]
0x2310 LUTL [610]
0x2314 LUTH [610]
0x2318 LUTL [611]
0x231c LUTH [611]
0x2320 LUTL [612]
0x2324 LUTH [612]
0x2328 LUTL [613]
0x232c LUTH [613]
0x2330 LUTL [614]
0x2334 LUTH [614]
0x2338 LUTL [615]
0x233c LUTH [615]
0x2340 LUTL [616]
0x2344 LUTH [616]
0x2348 LUTL [617]
0x234c LUTH [617]
0x2350 LUTL [618]
0x2354 LUTH [618]
0x2358 LUTL [619]
0x235c LUTH [619]
0x2360 LUTL [620]
0x2364 LUTH [620]
0x2368 LUTL [621]
0x236c LUTH [621]
0x2370 LUTL [622]
0x2374 LUTH [622]
0x2378 LUTL [623]
0x237c LUTH [623]
0x2380 LUTL [624]
0x2384 LUTH [624]
0x2388 LUTL [625]
0x238c LUTH [625]
0x2390 LUTL [626]
0x2394 LUTH [626]
0x2398 LUTL [627]
0x239c LUTH [627]
0x23a0 LUTL [628]
0x23a4 LUTH [628]
0x23a8 LUTL [629]
0x23ac LUTH [629]
0x23b0 LUTL [630]
0x23b4 LUTH [630]
0x23b8 LUTL [631]
0x23bc LUTH [631]
0x23c0 LUTL [632]
0x23c4 LUTH [632]
0x23c8 LUTL [633]
0x23cc LUTH [633]
0x23d0 LUTL [634]
0x23d4 LUTH [634]
0x23d8 LUTL [635]
0x23dc LUTH [635]
0x23e0 LUTL [636]
0x23e4 LUTH [636]
0x23e8 LUTL [637]
0x23ec LUTH [637]
0x23f0 LUTL [638]
0x23f4 LUTH [638]
0x23f8 LUTL [639]
0x23fc LUTH [639]
0x2400 LUTL [640]
0x2404 LUTH [640]
0x2408 LUTL [641]
0x240c LUTH [641]
0x2410 LUTL [642]
0x2414 LUTH [642]
0x2418 LUTL [643]
0x241c LUTH [643]
0x2420 LUTL [644]
0x2424 LUTH [644]
0x2428 LUTL [645]
0x242c LUTH [645]
0x2430 LUTL [646]
0x2434 LUTH [646]
0x2438 LUTL [647]
0x243c LUTH [647]
0x2440 LUTL [648]
0x2444 LUTH [648]
0x2448 LUTL [649]
0x244c LUTH [649]
0x2450 LUTL [650]
0x2454 LUTH [650]
0x2458 LUTL [651]
0x245c LUTH [651]
0x2460 LUTL [652]
0x2464 LUTH [652]
0x2468 LUTL [653]
0x246c LUTH [653]
0x2470 LUTL [654]
0x2474 LUTH [654]
0x2478 LUTL [655]
0x247c LUTH [655]
0x2480 LUTL [656]
0x2484 LUTH [656]
0x2488 LUTL [657]
0x248c LUTH [657]
0x2490 LUTL [658]
0x2494 LUTH [658]
0x2498 LUTL [659]
0x249c LUTH [659]
0x24a0 LUTL [660]
0x24a4 LUTH [660]
0x24a8 LUTL [661]
0x24ac LUTH [661]
0x24b0 LUTL [662]
0x24b4 LUTH [662]
0x24b8 LUTL [663]
0x24bc LUTH [663]
0x24c0 LUTL [664]
0x24c4 LUTH [664]
0x24c8 LUTL [665]
0x24cc LUTH [665]
0x24d0 LUTL [666]
0x24d4 LUTH [666]
0x24d8 LUTL [667]
0x24dc LUTH [667]
0x24e0 LUTL [668]
0x24e4 LUTH [668]
0x24e8 LUTL [669]
0x24ec LUTH [669]
0x24f0 LUTL [670]
0x24f4 LUTH [670]
0x24f8 LUTL [671]
0x24fc LUTH [671]
0x2500 LUTL [672]
0x2504 LUTH [672]
0x2508 LUTL [673]
0x250c LUTH [673]
0x2510 LUTL [674]
0x2514 LUTH [674]
0x2518 LUTL [675]
0x251c LUTH [675]
0x2520 LUTL [676]
0x2524 LUTH [676]
0x2528 LUTL [677]
0x252c LUTH [677]
0x2530 LUTL [678]
0x2534 LUTH [678]
0x2538 LUTL [679]
0x253c LUTH [679]
0x2540 LUTL [680]
0x2544 LUTH [680]
0x2548 LUTL [681]
0x254c LUTH [681]
0x2550 LUTL [682]
0x2554 LUTH [682]
0x2558 LUTL [683]
0x255c LUTH [683]
0x2560 LUTL [684]
0x2564 LUTH [684]
0x2568 LUTL [685]
0x256c LUTH [685]
0x2570 LUTL [686]
0x2574 LUTH [686]
0x2578 LUTL [687]
0x257c LUTH [687]
0x2580 LUTL [688]
0x2584 LUTH [688]
0x2588 LUTL [689]
0x258c LUTH [689]
0x2590 LUTL [690]
0x2594 LUTH [690]
0x2598 LUTL [691]
0x259c LUTH [691]
0x25a0 LUTL [692]
0x25a4 LUTH [692]
0x25a8 LUTL [693]
0x25ac LUTH [693]
0x25b0 LUTL [694]
0x25b4 LUTH [694]
0x25b8 LUTL [695]
0x25bc LUTH [695]
0x25c0 LUTL [696]
0x25c4 LUTH [696]
0x25c8 LUTL [697]
0x25cc LUTH [697]
0x25d0 LUTL [698]
0x25d4 LUTH [698]
0x25d8 LUTL [699]
0x25dc LUTH [699]
0x25e0 LUTL [700]
0x25e4 LUTH [700]
0x25e8 LUTL [701]
0x25ec LUTH [701]
0x25f0 LUTL [702]
0x25f4 LUTH [702]
0x25f8 LUTL [703]
0x25fc LUTH [703]
0x2600 LUTL [704]
0x2604 LUTH [704]
0x2608 LUTL [705]
0x260c LUTH [705]
0x2610 LUTL [706]
0x2614 LUTH [706]
0x2618 LUTL [707]
0x261c LUTH [707]
0x2620 LUTL [708]
0x2624 LUTH [708]
0x2628 LUTL [709]
0x262c LUTH [709]
0x2630 LUTL [710]
0x2634 LUTH [710]
0x2638 LUTL [711]
0x263c LUTH [711]
0x2640 LUTL [712]
0x2644 LUTH [712]
0x2648 LUTL [713]
0x264c LUTH [713]
0x2650 LUTL [714]
0x2654 LUTH [714]
0x2658 LUTL [715]
0x265c LUTH [715]
0x2660 LUTL [716]
0x2664 LUTH [716]
0x2668 LUTL [717]
0x266c LUTH [717]
0x2670 LUTL [718]
0x2674 LUTH [718]
0x2678 LUTL [719]
0x267c LUTH [719]
0x2680 LUTL [720]
0x2684 LUTH [720]
0x2688 LUTL [721]
0x268c LUTH [721]
0x2690 LUTL [722]
0x2694 LUTH [722]
0x2698 LUTL [723]
0x269c LUTH [723]
0x26a0 LUTL [724]
0x26a4 LUTH [724]
0x26a8 LUTL [725]
0x26ac LUTH [725]
0x26b0 LUTL [726]
0x26b4 LUTH [726]
0x26b8 LUTL [727]
0x26bc LUTH [727]
0x26c0 LUTL [728]
0x26c4 LUTH [728]
0x26c8 LUTL [729]
0x26cc LUTH [729]
0x26d0 LUTL [730]
0x26d4 LUTH [730]
0x26d8 LUTL [731]
0x26dc LUTH [731]
0x26e0 LUTL [732]
0x26e4 LUTH [732]
0x26e8 LUTL [733]
0x26ec LUTH [733]
0x26f0 LUTL [734]
0x26f4 LUTH [734]
0x26f8 LUTL [735]
0x26fc LUTH [735]
0x2700 LUTL [736]
0x2704 LUTH [736]
0x2708 LUTL [737]
0x270c LUTH [737]
0x2710 LUTL [738]
0x2714 LUTH [738]
0x2718 LUTL [739]
0x271c LUTH [739]
0x2720 LUTL [740]
0x2724 LUTH [740]
0x2728 LUTL [741]
0x272c LUTH [741]
0x2730 LUTL [742]
0x2734 LUTH [742]
0x2738 LUTL [743]
0x273c LUTH [743]
0x2740 LUTL [744]
0x2744 LUTH [744]
0x2748 LUTL [745]
0x274c LUTH [745]
0x2750 LUTL [746]
0x2754 LUTH [746]
0x2758 LUTL [747]
0x275c LUTH [747]
0x2760 LUTL [748]
0x2764 LUTH [748]
0x2768 LUTL [749]
0x276c LUTH [749]
0x2770 LUTL [750]
0x2774 LUTH [750]
0x2778 LUTL [751]
0x277c LUTH [751]
0x2780 LUTL [752]
0x2784 LUTH [752]
0x2788 LUTL [753]
0x278c LUTH [753]
0x2790 LUTL [754]
0x2794 LUTH [754]
0x2798 LUTL [755]
0x279c LUTH [755]
0x27a0 LUTL [756]
0x27a4 LUTH [756]
0x27a8 LUTL [757]
0x27ac LUTH [757]
0x27b0 LUTL [758]
0x27b4 LUTH [758]
0x27b8 LUTL [759]
0x27bc LUTH [759]
0x27c0 LUTL [760]
0x27c4 LUTH [760]
0x27c8 LUTL [761]
0x27cc LUTH [761]
0x27d0 LUTL [762]
0x27d4 LUTH [762]
0x27d8 LUTL [763]
0x27dc LUTH [763]
0x27e0 LUTL [764]
0x27e4 LUTH [764]
0x27e8 LUTL [765]
0x27ec LUTH [765]
0x27f0 LUTL [766]
0x27f4 LUTH [766]
0x27f8 LUTL [767]
0x27fc LUTH [767]
0x2800 LUTL [768]
0x2804 LUTH [768]
0x2808 LUTL [769]
0x280c LUTH [769]
0x2810 LUTL [770]
0x2814 LUTH [770]
0x2818 LUTL [771]
0x281c LUTH [771]
0x2820 LUTL [772]
0x2824 LUTH [772]
0x2828 LUTL [773]
0x282c LUTH [773]
0x2830 LUTL [774]
0x2834 LUTH [774]
0x2838 LUTL [775]
0x283c LUTH [775]
0x2840 LUTL [776]
0x2844 LUTH [776]
0x2848 LUTL [777]
0x284c LUTH [777]
0x2850 LUTL [778]
0x2854 LUTH [778]
0x2858 LUTL [779]
0x285c LUTH [779]
0x2860 LUTL [780]
0x2864 LUTH [780]
0x2868 LUTL [781]
0x286c LUTH [781]
0x2870 LUTL [782]
0x2874 LUTH [782]
0x2878 LUTL [783]
0x287c LUTH [783]
0x2880 LUTL [784]
0x2884 LUTH [784]
0x2888 LUTL [785]
0x288c LUTH [785]
0x2890 LUTL [786]
0x2894 LUTH [786]
0x2898 LUTL [787]
0x289c LUTH [787]
0x28a0 LUTL [788]
0x28a4 LUTH [788]
0x28a8 LUTL [789]
0x28ac LUTH [789]
0x28b0 LUTL [790]
0x28b4 LUTH [790]
0x28b8 LUTL [791]
0x28bc LUTH [791]
0x28c0 LUTL [792]
0x28c4 LUTH [792]
0x28c8 LUTL [793]
0x28cc LUTH [793]
0x28d0 LUTL [794]
0x28d4 LUTH [794]
0x28d8 LUTL [795]
0x28dc LUTH [795]
0x28e0 LUTL [796]
0x28e4 LUTH [796]
0x28e8 LUTL [797]
0x28ec LUTH [797]
0x28f0 LUTL [798]
0x28f4 LUTH [798]
0x28f8 LUTL [799]
0x28fc LUTH [799]
0x2900 LUTL [800]
0x2904 LUTH [800]
0x2908 LUTL [801]
0x290c LUTH [801]
0x2910 LUTL [802]
0x2914 LUTH [802]
0x2918 LUTL [803]
0x291c LUTH [803]
0x2920 LUTL [804]
0x2924 LUTH [804]
0x2928 LUTL [805]
0x292c LUTH [805]
0x2930 LUTL [806]
0x2934 LUTH [806]
0x2938 LUTL [807]
0x293c LUTH [807]
0x2940 LUTL [808]
0x2944 LUTH [808]
0x2948 LUTL [809]
0x294c LUTH [809]
0x2950 LUTL [810]
0x2954 LUTH [810]
0x2958 LUTL [811]
0x295c LUTH [811]
0x2960 LUTL [812]
0x2964 LUTH [812]
0x2968 LUTL [813]
0x296c LUTH [813]
0x2970 LUTL [814]
0x2974 LUTH [814]
0x2978 LUTL [815]
0x297c LUTH [815]
0x2980 LUTL [816]
0x2984 LUTH [816]
0x2988 LUTL [817]
0x298c LUTH [817]
0x2990 LUTL [818]
0x2994 LUTH [818]
0x2998 LUTL [819]
0x299c LUTH [819]
0x29a0 LUTL [820]
0x29a4 LUTH [820]
0x29a8 LUTL [821]
0x29ac LUTH [821]
0x29b0 LUTL [822]
0x29b4 LUTH [822]
0x29b8 LUTL [823]
0x29bc LUTH [823]
0x29c0 LUTL [824]
0x29c4 LUTH [824]
0x29c8 LUTL [825]
0x29cc LUTH [825]
0x29d0 LUTL [826]
0x29d4 LUTH [826]
0x29d8 LUTL [827]
0x29dc LUTH [827]
0x29e0 LUTL [828]
0x29e4 LUTH [828]
0x29e8 LUTL [829]
0x29ec LUTH [829]
0x29f0 LUTL [830]
0x29f4 LUTH [830]
0x29f8 LUTL [831]
0x29fc LUTH [831]
0x2a00 LUTL [832]
0x2a04 LUTH [832]
0x2a08 LUTL [833]
0x2a0c LUTH [833]
0x2a10 LUTL [834]
0x2a14 LUTH [834]
0x2a18 LUTL [835]
0x2a1c LUTH [835]
0x2a20 LUTL [836]
0x2a24 LUTH [836]
0x2a28 LUTL [837]
0x2a2c LUTH [837]
0x2a30 LUTL [838]
0x2a34 LUTH [838]
0x2a38 LUTL [839]
0x2a3c LUTH [839]
0x2a40 LUTL [840]
0x2a44 LUTH [840]
0x2a48 LUTL [841]
0x2a4c LUTH [841]
0x2a50 LUTL [842]
0x2a54 LUTH [842]
0x2a58 LUTL [843]
0x2a5c LUTH [843]
0x2a60 LUTL [844]
0x2a64 LUTH [844]
0x2a68 LUTL [845]
0x2a6c LUTH [845]
0x2a70 LUTL [846]
0x2a74 LUTH [846]
0x2a78 LUTL [847]
0x2a7c LUTH [847]
0x2a80 LUTL [848]
0x2a84 LUTH [848]
0x2a88 LUTL [849]
0x2a8c LUTH [849]
0x2a90 LUTL [850]
0x2a94 LUTH [850]
0x2a98 LUTL [851]
0x2a9c LUTH [851]
0x2aa0 LUTL [852]
0x2aa4 LUTH [852]
0x2aa8 LUTL [853]
0x2aac LUTH [853]
0x2ab0 LUTL [854]
0x2ab4 LUTH [854]
0x2ab8 LUTL [855]
0x2abc LUTH [855]
0x2ac0 LUTL [856]
0x2ac4 LUTH [856]
0x2ac8 LUTL [857]
0x2acc LUTH [857]
0x2ad0 LUTL [858]
0x2ad4 LUTH [858]
0x2ad8 LUTL [859]
0x2adc LUTH [859]
0x2ae0 LUTL [860]
0x2ae4 LUTH [860]
0x2ae8 LUTL [861]
0x2aec LUTH [861]
0x2af0 LUTL [862]
0x2af4 LUTH [862]
0x2af8 LUTL [863]
0x2afc LUTH [863]
0x2b00 LUTL [864]
0x2b04 LUTH [864]
0x2b08 LUTL [865]
0x2b0c LUTH [865]
0x2b10 LUTL [866]
0x2b14 LUTH [866]
0x2b18 LUTL [867]
0x2b1c LUTH [867]
0x2b20 LUTL [868]
0x2b24 LUTH [868]
0x2b28 LUTL [869]
0x2b2c LUTH [869]
0x2b30 LUTL [870]
0x2b34 LUTH [870]
0x2b38 LUTL [871]
0x2b3c LUTH [871]
0x2b40 LUTL [872]
0x2b44 LUTH [872]
0x2b48 LUTL [873]
0x2b4c LUTH [873]
0x2b50 LUTL [874]
0x2b54 LUTH [874]
0x2b58 LUTL [875]
0x2b5c LUTH [875]
0x2b60 LUTL [876]
0x2b64 LUTH [876]
0x2b68 LUTL [877]
0x2b6c LUTH [877]
0x2b70 LUTL [878]
0x2b74 LUTH [878]
0x2b78 LUTL [879]
0x2b7c LUTH [879]
0x2b80 LUTL [880]
0x2b84 LUTH [880]
0x2b88 LUTL [881]
0x2b8c LUTH [881]
0x2b90 LUTL [882]
0x2b94 LUTH [882]
0x2b98 LUTL [883]
0x2b9c LUTH [883]
0x2ba0 LUTL [884]
0x2ba4 LUTH [884]
0x2ba8 LUTL [885]
0x2bac LUTH [885]
0x2bb0 LUTL [886]
0x2bb4 LUTH [886]
0x2bb8 LUTL [887]
0x2bbc LUTH [887]
0x2bc0 LUTL [888]
0x2bc4 LUTH [888]
0x2bc8 LUTL [889]
0x2bcc LUTH [889]
0x2bd0 LUTL [890]
0x2bd4 LUTH [890]
0x2bd8 LUTL [891]
0x2bdc LUTH [891]
0x2be0 LUTL [892]
0x2be4 LUTH [892]
0x2be8 LUTL [893]
0x2bec LUTH [893]
0x2bf0 LUTL [894]
0x2bf4 LUTH [894]
0x2bf8 LUTL [895]
0x2bfc LUTH [895]
0x2c00 LUTL [896]
0x2c04 LUTH [896]
0x2c08 LUTL [897]
0x2c0c LUTH [897]
0x2c10 LUTL [898]
0x2c14 LUTH [898]
0x2c18 LUTL [899]
0x2c1c LUTH [899]
0x2c20 LUTL [900]
0x2c24 LUTH [900]
0x2c28 LUTL [901]
0x2c2c LUTH [901]
0x2c30 LUTL [902]
0x2c34 LUTH [902]
0x2c38 LUTL [903]
0x2c3c LUTH [903]
0x2c40 LUTL [904]
0x2c44 LUTH [904]
0x2c48 LUTL [905]
0x2c4c LUTH [905]
0x2c50 LUTL [906]
0x2c54 LUTH [906]
0x2c58 LUTL [907]
0x2c5c LUTH [907]
0x2c60 LUTL [908]
0x2c64 LUTH [908]
0x2c68 LUTL [909]
0x2c6c LUTH [909]
0x2c70 LUTL [910]
0x2c74 LUTH [910]
0x2c78 LUTL [911]
0x2c7c LUTH [911]
0x2c80 LUTL [912]
0x2c84 LUTH [912]
0x2c88 LUTL [913]
0x2c8c LUTH [913]
0x2c90 LUTL [914]
0x2c94 LUTH [914]
0x2c98 LUTL [915]
0x2c9c LUTH [915]
0x2ca0 LUTL [916]
0x2ca4 LUTH [916]
0x2ca8 LUTL [917]
0x2cac LUTH [917]
0x2cb0 LUTL [918]
0x2cb4 LUTH [918]
0x2cb8 LUTL [919]
0x2cbc LUTH [919]
0x2cc0 LUTL [920]
0x2cc4 LUTH [920]
0x2cc8 LUTL [921]
0x2ccc LUTH [921]
0x2cd0 LUTL [922]
0x2cd4 LUTH [922]
0x2cd8 LUTL [923]
0x2cdc LUTH [923]
0x2ce0 LUTL [924]
0x2ce4 LUTH [924]
0x2ce8 LUTL [925]
0x2cec LUTH [925]
0x2cf0 LUTL [926]
0x2cf4 LUTH [926]
0x2cf8 LUTL [927]
0x2cfc LUTH [927]
0x2d00 LUTL [928]
0x2d04 LUTH [928]
0x2d08 LUTL [929]
0x2d0c LUTH [929]
0x2d10 LUTL [930]
0x2d14 LUTH [930]
0x2d18 LUTL [931]
0x2d1c LUTH [931]
0x2d20 LUTL [932]
0x2d24 LUTH [932]
0x2d28 LUTL [933]
0x2d2c LUTH [933]
0x2d30 LUTL [934]
0x2d34 LUTH [934]
0x2d38 LUTL [935]
0x2d3c LUTH [935]
0x2d40 LUTL [936]
0x2d44 LUTH [936]
0x2d48 LUTL [937]
0x2d4c LUTH [937]
0x2d50 LUTL [938]
0x2d54 LUTH [938]
0x2d58 LUTL [939]
0x2d5c LUTH [939]
0x2d60 LUTL [940]
0x2d64 LUTH [940]
0x2d68 LUTL [941]
0x2d6c LUTH [941]
0x2d70 LUTL [942]
0x2d74 LUTH [942]
0x2d78 LUTL [943]
0x2d7c LUTH [943]
0x2d80 LUTL [944]
0x2d84 LUTH [944]
0x2d88 LUTL [945]
0x2d8c LUTH [945]
0x2d90 LUTL [946]
0x2d94 LUTH [946]
0x2d98 LUTL [947]
0x2d9c LUTH [947]
0x2da0 LUTL [948]
0x2da4 LUTH [948]
0x2da8 LUTL [949]
0x2dac LUTH [949]
0x2db0 LUTL [950]
0x2db4 LUTH [950]
0x2db8 LUTL [951]
0x2dbc LUTH [951]
0x2dc0 LUTL [952]
0x2dc4 LUTH [952]
0x2dc8 LUTL [953]
0x2dcc LUTH [953]
0x2dd0 LUTL [954]
0x2dd4 LUTH [954]
0x2dd8 LUTL [955]
0x2ddc LUTH [955]
0x2de0 LUTL [956]
0x2de4 LUTH [956]
0x2de8 LUTL [957]
0x2dec LUTH [957]
0x2df0 LUTL [958]
0x2df4 LUTH [958]
0x2df8 LUTL [959]
0x2dfc LUTH [959]
0x2e00 LUTL [960]
0x2e04 LUTH [960]
0x2e08 LUTL [961]
0x2e0c LUTH [961]
0x2e10 LUTL [962]
0x2e14 LUTH [962]
0x2e18 LUTL [963]
0x2e1c LUTH [963]
0x2e20 LUTL [964]
0x2e24 LUTH [964]
0x2e28 LUTL [965]
0x2e2c LUTH [965]
0x2e30 LUTL [966]
0x2e34 LUTH [966]
0x2e38 LUTL [967]
0x2e3c LUTH [967]
0x2e40 LUTL [968]
0x2e44 LUTH [968]
0x2e48 LUTL [969]
0x2e4c LUTH [969]
0x2e50 LUTL [970]
0x2e54 LUTH [970]
0x2e58 LUTL [971]
0x2e5c LUTH [971]
0x2e60 LUTL [972]
0x2e64 LUTH [972]
0x2e68 LUTL [973]
0x2e6c LUTH [973]
0x2e70 LUTL [974]
0x2e74 LUTH [974]
0x2e78 LUTL [975]
0x2e7c LUTH [975]
0x2e80 LUTL [976]
0x2e84 LUTH [976]
0x2e88 LUTL [977]
0x2e8c LUTH [977]
0x2e90 LUTL [978]
0x2e94 LUTH [978]
0x2e98 LUTL [979]
0x2e9c LUTH [979]
0x2ea0 LUTL [980]
0x2ea4 LUTH [980]
0x2ea8 LUTL [981]
0x2eac LUTH [981]
0x2eb0 LUTL [982]
0x2eb4 LUTH [982]
0x2eb8 LUTL [983]
0x2ebc LUTH [983]
0x2ec0 LUTL [984]
0x2ec4 LUTH [984]
0x2ec8 LUTL [985]
0x2ecc LUTH [985]
0x2ed0 LUTL [986]
0x2ed4 LUTH [986]
0x2ed8 LUTL [987]
0x2edc LUTH [987]
0x2ee0 LUTL [988]
0x2ee4 LUTH [988]
0x2ee8 LUTL [989]
0x2eec LUTH [989]
0x2ef0 LUTL [990]
0x2ef4 LUTH [990]
0x2ef8 LUTL [991]
0x2efc LUTH [991]
0x2f00 LUTL [992]
0x2f04 LUTH [992]
0x2f08 LUTL [993]
0x2f0c LUTH [993]
0x2f10 LUTL [994]
0x2f14 LUTH [994]
0x2f18 LUTL [995]
0x2f1c LUTH [995]
0x2f20 LUTL [996]
0x2f24 LUTH [996]
0x2f28 LUTL [997]
0x2f2c LUTH [997]
0x2f30 LUTL [998]
0x2f34 LUTH [998]
0x2f38 LUTL [999]
0x2f3c LUTH [999]
0x2f40 LUTL [1000]
0x2f44 LUTH [1000]
0x2f48 LUTL [1001]
0x2f4c LUTH [1001]
0x2f50 LUTL [1002]
0x2f54 LUTH [1002]
0x2f58 LUTL [1003]
0x2f5c LUTH [1003]
0x2f60 LUTL [1004]
0x2f64 LUTH [1004]
0x2f68 LUTL [1005]
0x2f6c LUTH [1005]
0x2f70 LUTL [1006]
0x2f74 LUTH [1006]
0x2f78 LUTL [1007]
0x2f7c LUTH [1007]
0x2f80 LUTL [1008]
0x2f84 LUTH [1008]
0x2f88 LUTL [1009]
0x2f8c LUTH [1009]
0x2f90 LUTL [1010]
0x2f94 LUTH [1010]
0x2f98 LUTL [1011]
0x2f9c LUTH [1011]
0x2fa0 LUTL [1012]
0x2fa4 LUTH [1012]
0x2fa8 LUTL [1013]
0x2fac LUTH [1013]
0x2fb0 LUTL [1014]
0x2fb4 LUTH [1014]
0x2fb8 LUTL [1015]
0x2fbc LUTH [1015]
0x2fc0 LUTL [1016]
0x2fc4 LUTH [1016]
0x2fc8 LUTL [1017]
0x2fcc LUTH [1017]
0x2fd0 LUTL [1018]
0x2fd4 LUTH [1018]
0x2fd8 LUTL [1019]
0x2fdc LUTH [1019]
0x2fe0 LUTL [1020]
0x2fe4 LUTH [1020]
0x2fe8 LUTL [1021]
0x2fec LUTH [1021]
0x2ff0 LUTL [1022]
0x2ff4 LUTH [1022]
0x2ff8 LUTL [1023]
0x2ffc LUTH [1023]
Toggle registers

CR

Graphic MMU configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BM192
rw 		AMEIE
rw 		B3OIE
rw 		B2OIE
rw 		B1OIE
rw 		B0OIE
rw
Toggle fields

B0OIE

Bit 0: Buffer 0 overflow interrupt enable.

B1OIE

Bit 1: Buffer 1 overflow interrupt enable.

B2OIE

Bit 2: Buffer 2 overflow interrupt enable.

B3OIE

Bit 3: Buffer 3 overflow interrupt enable.

AMEIE

Bit 4: AHB master error interrupt enable.

BM192

Bit 6: 192 Block mode.

SR

Graphic MMU status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AMEF
r 		B3OF
r 		B2OF
r 		B1OF
r 		B0OF
r
Toggle fields

B0OF

Bit 0: Buffer 0 overflow flag.

B1OF

Bit 1: Buffer 1 overflow flag.

B2OF

Bit 2: Buffer 2 overflow flag.

B3OF

Bit 3: Buffer 3 overflow flag.

AMEF

Bit 4: AHB master error flag.

FCR

Graphic MMU flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAMEF
w 		CB3OF
w 		CB2OF
w 		CB1OF
w 		CB0OF
w
Toggle fields

CB0OF

Bit 0: Clear buffer 0 overflow flag.

CB1OF

Bit 1: Clear buffer 1 overflow flag.

CB2OF

Bit 2: Clear buffer 2 overflow flag.

CB3OF

Bit 3: Clear buffer 3 overflow flag.

CAMEF

Bit 4: Clear AHB master error flag.

DVR

Graphic MMU default value register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DV
rw
Toggle fields

DV

Bits 0-31: Default value.

B0CR

Graphic MMU buffer 0 configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBBA
rw 		PBO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBO
rw
Toggle fields

PBO

Bits 4-22: Physical buffer offset.

PBBA

Bits 23-31: Physical buffer base address.

B1CR

Graphic MMU buffer 1 configuration register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBBA
rw 		PBO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBO
rw
Toggle fields

PBO

Bits 4-22: Physical buffer offset.

PBBA

Bits 23-31: Physical buffer base address.

B2CR

Graphic MMU buffer 2 configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBBA
rw 		PBO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBO
rw
Toggle fields

PBO

Bits 4-22: Physical buffer offset.

PBBA

Bits 23-31: Physical buffer base address.

B3CR

Graphic MMU buffer 3 configuration register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBBA
rw 		PBO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBO
rw
Toggle fields

PBO

Bits 4-22: Physical buffer offset.

PBBA

Bits 23-31: Physical buffer base address.

VERR

Graphic MMU version register

Offset: 0xff4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor revision.

MAJREV

Bits 4-7: Major revision.

IPIDR

Graphic MMU identification register

Offset: 0xff8, size: 32, reset: 0x00160061, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: Identification Code.

SIDR

Graphic MMU size identification register

Offset: 0xffc, size: 32, reset: 0xA3C5DD04, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size and ID.

LUTL [0]

Graphic MMU LUT entry x low

Offset: 0x1000, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [0]

Graphic MMU LUT entry x high

Offset: 0x1004, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1]

Graphic MMU LUT entry x low

Offset: 0x1008, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1]

Graphic MMU LUT entry x high

Offset: 0x100c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [2]

Graphic MMU LUT entry x low

Offset: 0x1010, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [2]

Graphic MMU LUT entry x high

Offset: 0x1014, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [3]

Graphic MMU LUT entry x low

Offset: 0x1018, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [3]

Graphic MMU LUT entry x high

Offset: 0x101c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [4]

Graphic MMU LUT entry x low

Offset: 0x1020, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [4]

Graphic MMU LUT entry x high

Offset: 0x1024, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [5]

Graphic MMU LUT entry x low

Offset: 0x1028, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [5]

Graphic MMU LUT entry x high

Offset: 0x102c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [6]

Graphic MMU LUT entry x low

Offset: 0x1030, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [6]

Graphic MMU LUT entry x high

Offset: 0x1034, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [7]

Graphic MMU LUT entry x low

Offset: 0x1038, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [7]

Graphic MMU LUT entry x high

Offset: 0x103c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [8]

Graphic MMU LUT entry x low

Offset: 0x1040, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [8]

Graphic MMU LUT entry x high

Offset: 0x1044, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [9]

Graphic MMU LUT entry x low

Offset: 0x1048, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [9]

Graphic MMU LUT entry x high

Offset: 0x104c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [10]

Graphic MMU LUT entry x low

Offset: 0x1050, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [10]

Graphic MMU LUT entry x high

Offset: 0x1054, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [11]

Graphic MMU LUT entry x low

Offset: 0x1058, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [11]

Graphic MMU LUT entry x high

Offset: 0x105c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [12]

Graphic MMU LUT entry x low

Offset: 0x1060, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [12]

Graphic MMU LUT entry x high

Offset: 0x1064, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [13]

Graphic MMU LUT entry x low

Offset: 0x1068, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [13]

Graphic MMU LUT entry x high

Offset: 0x106c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [14]

Graphic MMU LUT entry x low

Offset: 0x1070, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [14]

Graphic MMU LUT entry x high

Offset: 0x1074, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [15]

Graphic MMU LUT entry x low

Offset: 0x1078, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [15]

Graphic MMU LUT entry x high

Offset: 0x107c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [16]

Graphic MMU LUT entry x low

Offset: 0x1080, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [16]

Graphic MMU LUT entry x high

Offset: 0x1084, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [17]

Graphic MMU LUT entry x low

Offset: 0x1088, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [17]

Graphic MMU LUT entry x high

Offset: 0x108c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [18]

Graphic MMU LUT entry x low

Offset: 0x1090, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [18]

Graphic MMU LUT entry x high

Offset: 0x1094, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [19]

Graphic MMU LUT entry x low

Offset: 0x1098, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [19]

Graphic MMU LUT entry x high

Offset: 0x109c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [20]

Graphic MMU LUT entry x low

Offset: 0x10a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [20]

Graphic MMU LUT entry x high

Offset: 0x10a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [21]

Graphic MMU LUT entry x low

Offset: 0x10a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [21]

Graphic MMU LUT entry x high

Offset: 0x10ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [22]

Graphic MMU LUT entry x low

Offset: 0x10b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [22]

Graphic MMU LUT entry x high

Offset: 0x10b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [23]

Graphic MMU LUT entry x low

Offset: 0x10b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [23]

Graphic MMU LUT entry x high

Offset: 0x10bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [24]

Graphic MMU LUT entry x low

Offset: 0x10c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [24]

Graphic MMU LUT entry x high

Offset: 0x10c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [25]

Graphic MMU LUT entry x low

Offset: 0x10c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [25]

Graphic MMU LUT entry x high

Offset: 0x10cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [26]

Graphic MMU LUT entry x low

Offset: 0x10d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [26]

Graphic MMU LUT entry x high

Offset: 0x10d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [27]

Graphic MMU LUT entry x low

Offset: 0x10d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [27]

Graphic MMU LUT entry x high

Offset: 0x10dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [28]

Graphic MMU LUT entry x low

Offset: 0x10e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [28]

Graphic MMU LUT entry x high

Offset: 0x10e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [29]

Graphic MMU LUT entry x low

Offset: 0x10e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [29]

Graphic MMU LUT entry x high

Offset: 0x10ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [30]

Graphic MMU LUT entry x low

Offset: 0x10f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [30]

Graphic MMU LUT entry x high

Offset: 0x10f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [31]

Graphic MMU LUT entry x low

Offset: 0x10f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [31]

Graphic MMU LUT entry x high

Offset: 0x10fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [32]

Graphic MMU LUT entry x low

Offset: 0x1100, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [32]

Graphic MMU LUT entry x high

Offset: 0x1104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [33]

Graphic MMU LUT entry x low

Offset: 0x1108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [33]

Graphic MMU LUT entry x high

Offset: 0x110c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [34]

Graphic MMU LUT entry x low

Offset: 0x1110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [34]

Graphic MMU LUT entry x high

Offset: 0x1114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [35]

Graphic MMU LUT entry x low

Offset: 0x1118, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [35]

Graphic MMU LUT entry x high

Offset: 0x111c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [36]

Graphic MMU LUT entry x low

Offset: 0x1120, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [36]

Graphic MMU LUT entry x high

Offset: 0x1124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [37]

Graphic MMU LUT entry x low

Offset: 0x1128, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [37]

Graphic MMU LUT entry x high

Offset: 0x112c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [38]

Graphic MMU LUT entry x low

Offset: 0x1130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [38]

Graphic MMU LUT entry x high

Offset: 0x1134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [39]

Graphic MMU LUT entry x low

Offset: 0x1138, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [39]

Graphic MMU LUT entry x high

Offset: 0x113c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [40]

Graphic MMU LUT entry x low

Offset: 0x1140, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [40]

Graphic MMU LUT entry x high

Offset: 0x1144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [41]

Graphic MMU LUT entry x low

Offset: 0x1148, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [41]

Graphic MMU LUT entry x high

Offset: 0x114c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [42]

Graphic MMU LUT entry x low

Offset: 0x1150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [42]

Graphic MMU LUT entry x high

Offset: 0x1154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [43]

Graphic MMU LUT entry x low

Offset: 0x1158, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [43]

Graphic MMU LUT entry x high

Offset: 0x115c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [44]

Graphic MMU LUT entry x low

Offset: 0x1160, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [44]

Graphic MMU LUT entry x high

Offset: 0x1164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [45]

Graphic MMU LUT entry x low

Offset: 0x1168, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [45]

Graphic MMU LUT entry x high

Offset: 0x116c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [46]

Graphic MMU LUT entry x low

Offset: 0x1170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [46]

Graphic MMU LUT entry x high

Offset: 0x1174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [47]

Graphic MMU LUT entry x low

Offset: 0x1178, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [47]

Graphic MMU LUT entry x high

Offset: 0x117c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [48]

Graphic MMU LUT entry x low

Offset: 0x1180, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [48]

Graphic MMU LUT entry x high

Offset: 0x1184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [49]

Graphic MMU LUT entry x low

Offset: 0x1188, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [49]

Graphic MMU LUT entry x high

Offset: 0x118c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [50]

Graphic MMU LUT entry x low

Offset: 0x1190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [50]

Graphic MMU LUT entry x high

Offset: 0x1194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [51]

Graphic MMU LUT entry x low

Offset: 0x1198, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [51]

Graphic MMU LUT entry x high

Offset: 0x119c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [52]

Graphic MMU LUT entry x low

Offset: 0x11a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [52]

Graphic MMU LUT entry x high

Offset: 0x11a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [53]

Graphic MMU LUT entry x low

Offset: 0x11a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [53]

Graphic MMU LUT entry x high

Offset: 0x11ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [54]

Graphic MMU LUT entry x low

Offset: 0x11b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [54]

Graphic MMU LUT entry x high

Offset: 0x11b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [55]

Graphic MMU LUT entry x low

Offset: 0x11b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [55]

Graphic MMU LUT entry x high

Offset: 0x11bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [56]

Graphic MMU LUT entry x low

Offset: 0x11c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [56]

Graphic MMU LUT entry x high

Offset: 0x11c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [57]

Graphic MMU LUT entry x low

Offset: 0x11c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [57]

Graphic MMU LUT entry x high

Offset: 0x11cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [58]

Graphic MMU LUT entry x low

Offset: 0x11d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [58]

Graphic MMU LUT entry x high

Offset: 0x11d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [59]

Graphic MMU LUT entry x low

Offset: 0x11d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [59]

Graphic MMU LUT entry x high

Offset: 0x11dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [60]

Graphic MMU LUT entry x low

Offset: 0x11e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [60]

Graphic MMU LUT entry x high

Offset: 0x11e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [61]

Graphic MMU LUT entry x low

Offset: 0x11e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [61]

Graphic MMU LUT entry x high

Offset: 0x11ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [62]

Graphic MMU LUT entry x low

Offset: 0x11f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [62]

Graphic MMU LUT entry x high

Offset: 0x11f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [63]

Graphic MMU LUT entry x low

Offset: 0x11f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [63]

Graphic MMU LUT entry x high

Offset: 0x11fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [64]

Graphic MMU LUT entry x low

Offset: 0x1200, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [64]

Graphic MMU LUT entry x high

Offset: 0x1204, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [65]

Graphic MMU LUT entry x low

Offset: 0x1208, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [65]

Graphic MMU LUT entry x high

Offset: 0x120c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [66]

Graphic MMU LUT entry x low

Offset: 0x1210, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [66]

Graphic MMU LUT entry x high

Offset: 0x1214, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [67]

Graphic MMU LUT entry x low

Offset: 0x1218, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [67]

Graphic MMU LUT entry x high

Offset: 0x121c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [68]

Graphic MMU LUT entry x low

Offset: 0x1220, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [68]

Graphic MMU LUT entry x high

Offset: 0x1224, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [69]

Graphic MMU LUT entry x low

Offset: 0x1228, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [69]

Graphic MMU LUT entry x high

Offset: 0x122c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [70]

Graphic MMU LUT entry x low

Offset: 0x1230, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [70]

Graphic MMU LUT entry x high

Offset: 0x1234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [71]

Graphic MMU LUT entry x low

Offset: 0x1238, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [71]

Graphic MMU LUT entry x high

Offset: 0x123c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [72]

Graphic MMU LUT entry x low

Offset: 0x1240, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [72]

Graphic MMU LUT entry x high

Offset: 0x1244, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [73]

Graphic MMU LUT entry x low

Offset: 0x1248, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [73]

Graphic MMU LUT entry x high

Offset: 0x124c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [74]

Graphic MMU LUT entry x low

Offset: 0x1250, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [74]

Graphic MMU LUT entry x high

Offset: 0x1254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [75]

Graphic MMU LUT entry x low

Offset: 0x1258, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [75]

Graphic MMU LUT entry x high

Offset: 0x125c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [76]

Graphic MMU LUT entry x low

Offset: 0x1260, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [76]

Graphic MMU LUT entry x high

Offset: 0x1264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [77]

Graphic MMU LUT entry x low

Offset: 0x1268, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [77]

Graphic MMU LUT entry x high

Offset: 0x126c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [78]

Graphic MMU LUT entry x low

Offset: 0x1270, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [78]

Graphic MMU LUT entry x high

Offset: 0x1274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [79]

Graphic MMU LUT entry x low

Offset: 0x1278, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [79]

Graphic MMU LUT entry x high

Offset: 0x127c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [80]

Graphic MMU LUT entry x low

Offset: 0x1280, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [80]

Graphic MMU LUT entry x high

Offset: 0x1284, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [81]

Graphic MMU LUT entry x low

Offset: 0x1288, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [81]

Graphic MMU LUT entry x high

Offset: 0x128c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [82]

Graphic MMU LUT entry x low

Offset: 0x1290, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [82]

Graphic MMU LUT entry x high

Offset: 0x1294, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [83]

Graphic MMU LUT entry x low

Offset: 0x1298, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [83]

Graphic MMU LUT entry x high

Offset: 0x129c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [84]

Graphic MMU LUT entry x low

Offset: 0x12a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [84]

Graphic MMU LUT entry x high

Offset: 0x12a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [85]

Graphic MMU LUT entry x low

Offset: 0x12a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [85]

Graphic MMU LUT entry x high

Offset: 0x12ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [86]

Graphic MMU LUT entry x low

Offset: 0x12b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [86]

Graphic MMU LUT entry x high

Offset: 0x12b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [87]

Graphic MMU LUT entry x low

Offset: 0x12b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [87]

Graphic MMU LUT entry x high

Offset: 0x12bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [88]

Graphic MMU LUT entry x low

Offset: 0x12c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [88]

Graphic MMU LUT entry x high

Offset: 0x12c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [89]

Graphic MMU LUT entry x low

Offset: 0x12c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [89]

Graphic MMU LUT entry x high

Offset: 0x12cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [90]

Graphic MMU LUT entry x low

Offset: 0x12d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [90]

Graphic MMU LUT entry x high

Offset: 0x12d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [91]

Graphic MMU LUT entry x low

Offset: 0x12d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [91]

Graphic MMU LUT entry x high

Offset: 0x12dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [92]

Graphic MMU LUT entry x low

Offset: 0x12e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [92]

Graphic MMU LUT entry x high

Offset: 0x12e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [93]

Graphic MMU LUT entry x low

Offset: 0x12e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [93]

Graphic MMU LUT entry x high

Offset: 0x12ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [94]

Graphic MMU LUT entry x low

Offset: 0x12f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [94]

Graphic MMU LUT entry x high

Offset: 0x12f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [95]

Graphic MMU LUT entry x low

Offset: 0x12f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [95]

Graphic MMU LUT entry x high

Offset: 0x12fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [96]

Graphic MMU LUT entry x low

Offset: 0x1300, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [96]

Graphic MMU LUT entry x high

Offset: 0x1304, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [97]

Graphic MMU LUT entry x low

Offset: 0x1308, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [97]

Graphic MMU LUT entry x high

Offset: 0x130c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [98]

Graphic MMU LUT entry x low

Offset: 0x1310, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [98]

Graphic MMU LUT entry x high

Offset: 0x1314, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [99]

Graphic MMU LUT entry x low

Offset: 0x1318, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [99]

Graphic MMU LUT entry x high

Offset: 0x131c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [100]

Graphic MMU LUT entry x low

Offset: 0x1320, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [100]

Graphic MMU LUT entry x high

Offset: 0x1324, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [101]

Graphic MMU LUT entry x low

Offset: 0x1328, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [101]

Graphic MMU LUT entry x high

Offset: 0x132c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [102]

Graphic MMU LUT entry x low

Offset: 0x1330, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [102]

Graphic MMU LUT entry x high

Offset: 0x1334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [103]

Graphic MMU LUT entry x low

Offset: 0x1338, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [103]

Graphic MMU LUT entry x high

Offset: 0x133c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [104]

Graphic MMU LUT entry x low

Offset: 0x1340, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [104]

Graphic MMU LUT entry x high

Offset: 0x1344, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [105]

Graphic MMU LUT entry x low

Offset: 0x1348, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [105]

Graphic MMU LUT entry x high

Offset: 0x134c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [106]

Graphic MMU LUT entry x low

Offset: 0x1350, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [106]

Graphic MMU LUT entry x high

Offset: 0x1354, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [107]

Graphic MMU LUT entry x low

Offset: 0x1358, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [107]

Graphic MMU LUT entry x high

Offset: 0x135c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [108]

Graphic MMU LUT entry x low

Offset: 0x1360, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [108]

Graphic MMU LUT entry x high

Offset: 0x1364, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [109]

Graphic MMU LUT entry x low

Offset: 0x1368, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [109]

Graphic MMU LUT entry x high

Offset: 0x136c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [110]

Graphic MMU LUT entry x low

Offset: 0x1370, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [110]

Graphic MMU LUT entry x high

Offset: 0x1374, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [111]

Graphic MMU LUT entry x low

Offset: 0x1378, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [111]

Graphic MMU LUT entry x high

Offset: 0x137c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [112]

Graphic MMU LUT entry x low

Offset: 0x1380, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [112]

Graphic MMU LUT entry x high

Offset: 0x1384, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [113]

Graphic MMU LUT entry x low

Offset: 0x1388, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [113]

Graphic MMU LUT entry x high

Offset: 0x138c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [114]

Graphic MMU LUT entry x low

Offset: 0x1390, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [114]

Graphic MMU LUT entry x high

Offset: 0x1394, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [115]

Graphic MMU LUT entry x low

Offset: 0x1398, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [115]

Graphic MMU LUT entry x high

Offset: 0x139c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [116]

Graphic MMU LUT entry x low

Offset: 0x13a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [116]

Graphic MMU LUT entry x high

Offset: 0x13a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [117]

Graphic MMU LUT entry x low

Offset: 0x13a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [117]

Graphic MMU LUT entry x high

Offset: 0x13ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [118]

Graphic MMU LUT entry x low

Offset: 0x13b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [118]

Graphic MMU LUT entry x high

Offset: 0x13b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [119]

Graphic MMU LUT entry x low

Offset: 0x13b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [119]

Graphic MMU LUT entry x high

Offset: 0x13bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [120]

Graphic MMU LUT entry x low

Offset: 0x13c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [120]

Graphic MMU LUT entry x high

Offset: 0x13c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [121]

Graphic MMU LUT entry x low

Offset: 0x13c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [121]

Graphic MMU LUT entry x high

Offset: 0x13cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [122]

Graphic MMU LUT entry x low

Offset: 0x13d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [122]

Graphic MMU LUT entry x high

Offset: 0x13d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [123]

Graphic MMU LUT entry x low

Offset: 0x13d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [123]

Graphic MMU LUT entry x high

Offset: 0x13dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [124]

Graphic MMU LUT entry x low

Offset: 0x13e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [124]

Graphic MMU LUT entry x high

Offset: 0x13e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [125]

Graphic MMU LUT entry x low

Offset: 0x13e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [125]

Graphic MMU LUT entry x high

Offset: 0x13ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [126]

Graphic MMU LUT entry x low

Offset: 0x13f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [126]

Graphic MMU LUT entry x high

Offset: 0x13f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [127]

Graphic MMU LUT entry x low

Offset: 0x13f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [127]

Graphic MMU LUT entry x high

Offset: 0x13fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [128]

Graphic MMU LUT entry x low

Offset: 0x1400, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [128]

Graphic MMU LUT entry x high

Offset: 0x1404, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [129]

Graphic MMU LUT entry x low

Offset: 0x1408, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [129]

Graphic MMU LUT entry x high

Offset: 0x140c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [130]

Graphic MMU LUT entry x low

Offset: 0x1410, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [130]

Graphic MMU LUT entry x high

Offset: 0x1414, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [131]

Graphic MMU LUT entry x low

Offset: 0x1418, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [131]

Graphic MMU LUT entry x high

Offset: 0x141c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [132]

Graphic MMU LUT entry x low

Offset: 0x1420, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [132]

Graphic MMU LUT entry x high

Offset: 0x1424, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [133]

Graphic MMU LUT entry x low

Offset: 0x1428, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [133]

Graphic MMU LUT entry x high

Offset: 0x142c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [134]

Graphic MMU LUT entry x low

Offset: 0x1430, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [134]

Graphic MMU LUT entry x high

Offset: 0x1434, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [135]

Graphic MMU LUT entry x low

Offset: 0x1438, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [135]

Graphic MMU LUT entry x high

Offset: 0x143c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [136]

Graphic MMU LUT entry x low

Offset: 0x1440, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [136]

Graphic MMU LUT entry x high

Offset: 0x1444, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [137]

Graphic MMU LUT entry x low

Offset: 0x1448, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [137]

Graphic MMU LUT entry x high

Offset: 0x144c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [138]

Graphic MMU LUT entry x low

Offset: 0x1450, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [138]

Graphic MMU LUT entry x high

Offset: 0x1454, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [139]

Graphic MMU LUT entry x low

Offset: 0x1458, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [139]

Graphic MMU LUT entry x high

Offset: 0x145c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [140]

Graphic MMU LUT entry x low

Offset: 0x1460, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [140]

Graphic MMU LUT entry x high

Offset: 0x1464, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [141]

Graphic MMU LUT entry x low

Offset: 0x1468, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [141]

Graphic MMU LUT entry x high

Offset: 0x146c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [142]

Graphic MMU LUT entry x low

Offset: 0x1470, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [142]

Graphic MMU LUT entry x high

Offset: 0x1474, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [143]

Graphic MMU LUT entry x low

Offset: 0x1478, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [143]

Graphic MMU LUT entry x high

Offset: 0x147c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [144]

Graphic MMU LUT entry x low

Offset: 0x1480, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [144]

Graphic MMU LUT entry x high

Offset: 0x1484, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [145]

Graphic MMU LUT entry x low

Offset: 0x1488, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [145]

Graphic MMU LUT entry x high

Offset: 0x148c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [146]

Graphic MMU LUT entry x low

Offset: 0x1490, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [146]

Graphic MMU LUT entry x high

Offset: 0x1494, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [147]

Graphic MMU LUT entry x low

Offset: 0x1498, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [147]

Graphic MMU LUT entry x high

Offset: 0x149c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [148]

Graphic MMU LUT entry x low

Offset: 0x14a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [148]

Graphic MMU LUT entry x high

Offset: 0x14a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [149]

Graphic MMU LUT entry x low

Offset: 0x14a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [149]

Graphic MMU LUT entry x high

Offset: 0x14ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [150]

Graphic MMU LUT entry x low

Offset: 0x14b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [150]

Graphic MMU LUT entry x high

Offset: 0x14b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [151]

Graphic MMU LUT entry x low

Offset: 0x14b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [151]

Graphic MMU LUT entry x high

Offset: 0x14bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [152]

Graphic MMU LUT entry x low

Offset: 0x14c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [152]

Graphic MMU LUT entry x high

Offset: 0x14c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [153]

Graphic MMU LUT entry x low

Offset: 0x14c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [153]

Graphic MMU LUT entry x high

Offset: 0x14cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [154]

Graphic MMU LUT entry x low

Offset: 0x14d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [154]

Graphic MMU LUT entry x high

Offset: 0x14d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [155]

Graphic MMU LUT entry x low

Offset: 0x14d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [155]

Graphic MMU LUT entry x high

Offset: 0x14dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [156]

Graphic MMU LUT entry x low

Offset: 0x14e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [156]

Graphic MMU LUT entry x high

Offset: 0x14e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [157]

Graphic MMU LUT entry x low

Offset: 0x14e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [157]

Graphic MMU LUT entry x high

Offset: 0x14ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [158]

Graphic MMU LUT entry x low

Offset: 0x14f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [158]

Graphic MMU LUT entry x high

Offset: 0x14f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [159]

Graphic MMU LUT entry x low

Offset: 0x14f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [159]

Graphic MMU LUT entry x high

Offset: 0x14fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [160]

Graphic MMU LUT entry x low

Offset: 0x1500, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [160]

Graphic MMU LUT entry x high

Offset: 0x1504, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [161]

Graphic MMU LUT entry x low

Offset: 0x1508, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [161]

Graphic MMU LUT entry x high

Offset: 0x150c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [162]

Graphic MMU LUT entry x low

Offset: 0x1510, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [162]

Graphic MMU LUT entry x high

Offset: 0x1514, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [163]

Graphic MMU LUT entry x low

Offset: 0x1518, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [163]

Graphic MMU LUT entry x high

Offset: 0x151c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [164]

Graphic MMU LUT entry x low

Offset: 0x1520, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [164]

Graphic MMU LUT entry x high

Offset: 0x1524, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [165]

Graphic MMU LUT entry x low

Offset: 0x1528, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [165]

Graphic MMU LUT entry x high

Offset: 0x152c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [166]

Graphic MMU LUT entry x low

Offset: 0x1530, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [166]

Graphic MMU LUT entry x high

Offset: 0x1534, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [167]

Graphic MMU LUT entry x low

Offset: 0x1538, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [167]

Graphic MMU LUT entry x high

Offset: 0x153c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [168]

Graphic MMU LUT entry x low

Offset: 0x1540, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [168]

Graphic MMU LUT entry x high

Offset: 0x1544, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [169]

Graphic MMU LUT entry x low

Offset: 0x1548, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [169]

Graphic MMU LUT entry x high

Offset: 0x154c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [170]

Graphic MMU LUT entry x low

Offset: 0x1550, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [170]

Graphic MMU LUT entry x high

Offset: 0x1554, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [171]

Graphic MMU LUT entry x low

Offset: 0x1558, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [171]

Graphic MMU LUT entry x high

Offset: 0x155c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [172]

Graphic MMU LUT entry x low

Offset: 0x1560, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [172]

Graphic MMU LUT entry x high

Offset: 0x1564, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [173]

Graphic MMU LUT entry x low

Offset: 0x1568, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [173]

Graphic MMU LUT entry x high

Offset: 0x156c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [174]

Graphic MMU LUT entry x low

Offset: 0x1570, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [174]

Graphic MMU LUT entry x high

Offset: 0x1574, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [175]

Graphic MMU LUT entry x low

Offset: 0x1578, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [175]

Graphic MMU LUT entry x high

Offset: 0x157c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [176]

Graphic MMU LUT entry x low

Offset: 0x1580, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [176]

Graphic MMU LUT entry x high

Offset: 0x1584, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [177]

Graphic MMU LUT entry x low

Offset: 0x1588, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [177]

Graphic MMU LUT entry x high

Offset: 0x158c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [178]

Graphic MMU LUT entry x low

Offset: 0x1590, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [178]

Graphic MMU LUT entry x high

Offset: 0x1594, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [179]

Graphic MMU LUT entry x low

Offset: 0x1598, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [179]

Graphic MMU LUT entry x high

Offset: 0x159c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [180]

Graphic MMU LUT entry x low

Offset: 0x15a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [180]

Graphic MMU LUT entry x high

Offset: 0x15a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [181]

Graphic MMU LUT entry x low

Offset: 0x15a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [181]

Graphic MMU LUT entry x high

Offset: 0x15ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [182]

Graphic MMU LUT entry x low

Offset: 0x15b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [182]

Graphic MMU LUT entry x high

Offset: 0x15b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [183]

Graphic MMU LUT entry x low

Offset: 0x15b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [183]

Graphic MMU LUT entry x high

Offset: 0x15bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [184]

Graphic MMU LUT entry x low

Offset: 0x15c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [184]

Graphic MMU LUT entry x high

Offset: 0x15c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [185]

Graphic MMU LUT entry x low

Offset: 0x15c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [185]

Graphic MMU LUT entry x high

Offset: 0x15cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [186]

Graphic MMU LUT entry x low

Offset: 0x15d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [186]

Graphic MMU LUT entry x high

Offset: 0x15d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [187]

Graphic MMU LUT entry x low

Offset: 0x15d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [187]

Graphic MMU LUT entry x high

Offset: 0x15dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [188]

Graphic MMU LUT entry x low

Offset: 0x15e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [188]

Graphic MMU LUT entry x high

Offset: 0x15e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [189]

Graphic MMU LUT entry x low

Offset: 0x15e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [189]

Graphic MMU LUT entry x high

Offset: 0x15ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [190]

Graphic MMU LUT entry x low

Offset: 0x15f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [190]

Graphic MMU LUT entry x high

Offset: 0x15f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [191]

Graphic MMU LUT entry x low

Offset: 0x15f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [191]

Graphic MMU LUT entry x high

Offset: 0x15fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [192]

Graphic MMU LUT entry x low

Offset: 0x1600, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [192]

Graphic MMU LUT entry x high

Offset: 0x1604, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [193]

Graphic MMU LUT entry x low

Offset: 0x1608, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [193]

Graphic MMU LUT entry x high

Offset: 0x160c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [194]

Graphic MMU LUT entry x low

Offset: 0x1610, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [194]

Graphic MMU LUT entry x high

Offset: 0x1614, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [195]

Graphic MMU LUT entry x low

Offset: 0x1618, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [195]

Graphic MMU LUT entry x high

Offset: 0x161c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [196]

Graphic MMU LUT entry x low

Offset: 0x1620, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [196]

Graphic MMU LUT entry x high

Offset: 0x1624, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [197]

Graphic MMU LUT entry x low

Offset: 0x1628, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [197]

Graphic MMU LUT entry x high

Offset: 0x162c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [198]

Graphic MMU LUT entry x low

Offset: 0x1630, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [198]

Graphic MMU LUT entry x high

Offset: 0x1634, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [199]

Graphic MMU LUT entry x low

Offset: 0x1638, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [199]

Graphic MMU LUT entry x high

Offset: 0x163c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [200]

Graphic MMU LUT entry x low

Offset: 0x1640, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [200]

Graphic MMU LUT entry x high

Offset: 0x1644, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [201]

Graphic MMU LUT entry x low

Offset: 0x1648, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [201]

Graphic MMU LUT entry x high

Offset: 0x164c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [202]

Graphic MMU LUT entry x low

Offset: 0x1650, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [202]

Graphic MMU LUT entry x high

Offset: 0x1654, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [203]

Graphic MMU LUT entry x low

Offset: 0x1658, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [203]

Graphic MMU LUT entry x high

Offset: 0x165c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [204]

Graphic MMU LUT entry x low

Offset: 0x1660, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [204]

Graphic MMU LUT entry x high

Offset: 0x1664, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [205]

Graphic MMU LUT entry x low

Offset: 0x1668, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [205]

Graphic MMU LUT entry x high

Offset: 0x166c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [206]

Graphic MMU LUT entry x low

Offset: 0x1670, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [206]

Graphic MMU LUT entry x high

Offset: 0x1674, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [207]

Graphic MMU LUT entry x low

Offset: 0x1678, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [207]

Graphic MMU LUT entry x high

Offset: 0x167c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [208]

Graphic MMU LUT entry x low

Offset: 0x1680, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [208]

Graphic MMU LUT entry x high

Offset: 0x1684, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [209]

Graphic MMU LUT entry x low

Offset: 0x1688, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [209]

Graphic MMU LUT entry x high

Offset: 0x168c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [210]

Graphic MMU LUT entry x low

Offset: 0x1690, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [210]

Graphic MMU LUT entry x high

Offset: 0x1694, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [211]

Graphic MMU LUT entry x low

Offset: 0x1698, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [211]

Graphic MMU LUT entry x high

Offset: 0x169c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [212]

Graphic MMU LUT entry x low

Offset: 0x16a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [212]

Graphic MMU LUT entry x high

Offset: 0x16a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [213]

Graphic MMU LUT entry x low

Offset: 0x16a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [213]

Graphic MMU LUT entry x high

Offset: 0x16ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [214]

Graphic MMU LUT entry x low

Offset: 0x16b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [214]

Graphic MMU LUT entry x high

Offset: 0x16b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [215]

Graphic MMU LUT entry x low

Offset: 0x16b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [215]

Graphic MMU LUT entry x high

Offset: 0x16bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [216]

Graphic MMU LUT entry x low

Offset: 0x16c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [216]

Graphic MMU LUT entry x high

Offset: 0x16c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [217]

Graphic MMU LUT entry x low

Offset: 0x16c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [217]

Graphic MMU LUT entry x high

Offset: 0x16cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [218]

Graphic MMU LUT entry x low

Offset: 0x16d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [218]

Graphic MMU LUT entry x high

Offset: 0x16d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [219]

Graphic MMU LUT entry x low

Offset: 0x16d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [219]

Graphic MMU LUT entry x high

Offset: 0x16dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [220]

Graphic MMU LUT entry x low

Offset: 0x16e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [220]

Graphic MMU LUT entry x high

Offset: 0x16e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [221]

Graphic MMU LUT entry x low

Offset: 0x16e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [221]

Graphic MMU LUT entry x high

Offset: 0x16ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [222]

Graphic MMU LUT entry x low

Offset: 0x16f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [222]

Graphic MMU LUT entry x high

Offset: 0x16f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [223]

Graphic MMU LUT entry x low

Offset: 0x16f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [223]

Graphic MMU LUT entry x high

Offset: 0x16fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [224]

Graphic MMU LUT entry x low

Offset: 0x1700, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [224]

Graphic MMU LUT entry x high

Offset: 0x1704, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [225]

Graphic MMU LUT entry x low

Offset: 0x1708, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [225]

Graphic MMU LUT entry x high

Offset: 0x170c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [226]

Graphic MMU LUT entry x low

Offset: 0x1710, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [226]

Graphic MMU LUT entry x high

Offset: 0x1714, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [227]

Graphic MMU LUT entry x low

Offset: 0x1718, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [227]

Graphic MMU LUT entry x high

Offset: 0x171c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [228]

Graphic MMU LUT entry x low

Offset: 0x1720, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [228]

Graphic MMU LUT entry x high

Offset: 0x1724, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [229]

Graphic MMU LUT entry x low

Offset: 0x1728, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [229]

Graphic MMU LUT entry x high

Offset: 0x172c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [230]

Graphic MMU LUT entry x low

Offset: 0x1730, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [230]

Graphic MMU LUT entry x high

Offset: 0x1734, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [231]

Graphic MMU LUT entry x low

Offset: 0x1738, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [231]

Graphic MMU LUT entry x high

Offset: 0x173c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [232]

Graphic MMU LUT entry x low

Offset: 0x1740, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [232]

Graphic MMU LUT entry x high

Offset: 0x1744, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [233]

Graphic MMU LUT entry x low

Offset: 0x1748, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [233]

Graphic MMU LUT entry x high

Offset: 0x174c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [234]

Graphic MMU LUT entry x low

Offset: 0x1750, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [234]

Graphic MMU LUT entry x high

Offset: 0x1754, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [235]

Graphic MMU LUT entry x low

Offset: 0x1758, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [235]

Graphic MMU LUT entry x high

Offset: 0x175c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [236]

Graphic MMU LUT entry x low

Offset: 0x1760, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [236]

Graphic MMU LUT entry x high

Offset: 0x1764, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [237]

Graphic MMU LUT entry x low

Offset: 0x1768, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [237]

Graphic MMU LUT entry x high

Offset: 0x176c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [238]

Graphic MMU LUT entry x low

Offset: 0x1770, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [238]

Graphic MMU LUT entry x high

Offset: 0x1774, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [239]

Graphic MMU LUT entry x low

Offset: 0x1778, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [239]

Graphic MMU LUT entry x high

Offset: 0x177c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [240]

Graphic MMU LUT entry x low

Offset: 0x1780, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [240]

Graphic MMU LUT entry x high

Offset: 0x1784, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [241]

Graphic MMU LUT entry x low

Offset: 0x1788, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [241]

Graphic MMU LUT entry x high

Offset: 0x178c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [242]

Graphic MMU LUT entry x low

Offset: 0x1790, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [242]

Graphic MMU LUT entry x high

Offset: 0x1794, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [243]

Graphic MMU LUT entry x low

Offset: 0x1798, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [243]

Graphic MMU LUT entry x high

Offset: 0x179c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [244]

Graphic MMU LUT entry x low

Offset: 0x17a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [244]

Graphic MMU LUT entry x high

Offset: 0x17a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [245]

Graphic MMU LUT entry x low

Offset: 0x17a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [245]

Graphic MMU LUT entry x high

Offset: 0x17ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [246]

Graphic MMU LUT entry x low

Offset: 0x17b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [246]

Graphic MMU LUT entry x high

Offset: 0x17b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [247]

Graphic MMU LUT entry x low

Offset: 0x17b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [247]

Graphic MMU LUT entry x high

Offset: 0x17bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [248]

Graphic MMU LUT entry x low

Offset: 0x17c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [248]

Graphic MMU LUT entry x high

Offset: 0x17c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [249]

Graphic MMU LUT entry x low

Offset: 0x17c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [249]

Graphic MMU LUT entry x high

Offset: 0x17cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [250]

Graphic MMU LUT entry x low

Offset: 0x17d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [250]

Graphic MMU LUT entry x high

Offset: 0x17d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [251]

Graphic MMU LUT entry x low

Offset: 0x17d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [251]

Graphic MMU LUT entry x high

Offset: 0x17dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [252]

Graphic MMU LUT entry x low

Offset: 0x17e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [252]

Graphic MMU LUT entry x high

Offset: 0x17e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [253]

Graphic MMU LUT entry x low

Offset: 0x17e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [253]

Graphic MMU LUT entry x high

Offset: 0x17ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [254]

Graphic MMU LUT entry x low

Offset: 0x17f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [254]

Graphic MMU LUT entry x high

Offset: 0x17f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [255]

Graphic MMU LUT entry x low

Offset: 0x17f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [255]

Graphic MMU LUT entry x high

Offset: 0x17fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [256]

Graphic MMU LUT entry x low

Offset: 0x1800, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [256]

Graphic MMU LUT entry x high

Offset: 0x1804, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [257]

Graphic MMU LUT entry x low

Offset: 0x1808, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [257]

Graphic MMU LUT entry x high

Offset: 0x180c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [258]

Graphic MMU LUT entry x low

Offset: 0x1810, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [258]

Graphic MMU LUT entry x high

Offset: 0x1814, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [259]

Graphic MMU LUT entry x low

Offset: 0x1818, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [259]

Graphic MMU LUT entry x high

Offset: 0x181c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [260]

Graphic MMU LUT entry x low

Offset: 0x1820, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [260]

Graphic MMU LUT entry x high

Offset: 0x1824, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [261]

Graphic MMU LUT entry x low

Offset: 0x1828, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [261]

Graphic MMU LUT entry x high

Offset: 0x182c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [262]

Graphic MMU LUT entry x low

Offset: 0x1830, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [262]

Graphic MMU LUT entry x high

Offset: 0x1834, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [263]

Graphic MMU LUT entry x low

Offset: 0x1838, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [263]

Graphic MMU LUT entry x high

Offset: 0x183c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [264]

Graphic MMU LUT entry x low

Offset: 0x1840, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [264]

Graphic MMU LUT entry x high

Offset: 0x1844, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [265]

Graphic MMU LUT entry x low

Offset: 0x1848, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [265]

Graphic MMU LUT entry x high

Offset: 0x184c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [266]

Graphic MMU LUT entry x low

Offset: 0x1850, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [266]

Graphic MMU LUT entry x high

Offset: 0x1854, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [267]

Graphic MMU LUT entry x low

Offset: 0x1858, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [267]

Graphic MMU LUT entry x high

Offset: 0x185c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [268]

Graphic MMU LUT entry x low

Offset: 0x1860, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [268]

Graphic MMU LUT entry x high

Offset: 0x1864, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [269]

Graphic MMU LUT entry x low

Offset: 0x1868, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [269]

Graphic MMU LUT entry x high

Offset: 0x186c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [270]

Graphic MMU LUT entry x low

Offset: 0x1870, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [270]

Graphic MMU LUT entry x high

Offset: 0x1874, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [271]

Graphic MMU LUT entry x low

Offset: 0x1878, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [271]

Graphic MMU LUT entry x high

Offset: 0x187c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [272]

Graphic MMU LUT entry x low

Offset: 0x1880, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [272]

Graphic MMU LUT entry x high

Offset: 0x1884, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [273]

Graphic MMU LUT entry x low

Offset: 0x1888, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [273]

Graphic MMU LUT entry x high

Offset: 0x188c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [274]

Graphic MMU LUT entry x low

Offset: 0x1890, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [274]

Graphic MMU LUT entry x high

Offset: 0x1894, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [275]

Graphic MMU LUT entry x low

Offset: 0x1898, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [275]

Graphic MMU LUT entry x high

Offset: 0x189c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [276]

Graphic MMU LUT entry x low

Offset: 0x18a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [276]

Graphic MMU LUT entry x high

Offset: 0x18a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [277]

Graphic MMU LUT entry x low

Offset: 0x18a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [277]

Graphic MMU LUT entry x high

Offset: 0x18ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [278]

Graphic MMU LUT entry x low

Offset: 0x18b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [278]

Graphic MMU LUT entry x high

Offset: 0x18b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [279]

Graphic MMU LUT entry x low

Offset: 0x18b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [279]

Graphic MMU LUT entry x high

Offset: 0x18bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [280]

Graphic MMU LUT entry x low

Offset: 0x18c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [280]

Graphic MMU LUT entry x high

Offset: 0x18c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [281]

Graphic MMU LUT entry x low

Offset: 0x18c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [281]

Graphic MMU LUT entry x high

Offset: 0x18cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [282]

Graphic MMU LUT entry x low

Offset: 0x18d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [282]

Graphic MMU LUT entry x high

Offset: 0x18d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [283]

Graphic MMU LUT entry x low

Offset: 0x18d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [283]

Graphic MMU LUT entry x high

Offset: 0x18dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [284]

Graphic MMU LUT entry x low

Offset: 0x18e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [284]

Graphic MMU LUT entry x high

Offset: 0x18e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [285]

Graphic MMU LUT entry x low

Offset: 0x18e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [285]

Graphic MMU LUT entry x high

Offset: 0x18ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [286]

Graphic MMU LUT entry x low

Offset: 0x18f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [286]

Graphic MMU LUT entry x high

Offset: 0x18f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [287]

Graphic MMU LUT entry x low

Offset: 0x18f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [287]

Graphic MMU LUT entry x high

Offset: 0x18fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [288]

Graphic MMU LUT entry x low

Offset: 0x1900, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [288]

Graphic MMU LUT entry x high

Offset: 0x1904, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [289]

Graphic MMU LUT entry x low

Offset: 0x1908, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [289]

Graphic MMU LUT entry x high

Offset: 0x190c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [290]

Graphic MMU LUT entry x low

Offset: 0x1910, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [290]

Graphic MMU LUT entry x high

Offset: 0x1914, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [291]

Graphic MMU LUT entry x low

Offset: 0x1918, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [291]

Graphic MMU LUT entry x high

Offset: 0x191c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [292]

Graphic MMU LUT entry x low

Offset: 0x1920, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [292]

Graphic MMU LUT entry x high

Offset: 0x1924, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [293]

Graphic MMU LUT entry x low

Offset: 0x1928, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [293]

Graphic MMU LUT entry x high

Offset: 0x192c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [294]

Graphic MMU LUT entry x low

Offset: 0x1930, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [294]

Graphic MMU LUT entry x high

Offset: 0x1934, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [295]

Graphic MMU LUT entry x low

Offset: 0x1938, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [295]

Graphic MMU LUT entry x high

Offset: 0x193c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [296]

Graphic MMU LUT entry x low

Offset: 0x1940, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [296]

Graphic MMU LUT entry x high

Offset: 0x1944, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [297]

Graphic MMU LUT entry x low

Offset: 0x1948, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [297]

Graphic MMU LUT entry x high

Offset: 0x194c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [298]

Graphic MMU LUT entry x low

Offset: 0x1950, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [298]

Graphic MMU LUT entry x high

Offset: 0x1954, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [299]

Graphic MMU LUT entry x low

Offset: 0x1958, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [299]

Graphic MMU LUT entry x high

Offset: 0x195c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [300]

Graphic MMU LUT entry x low

Offset: 0x1960, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [300]

Graphic MMU LUT entry x high

Offset: 0x1964, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [301]

Graphic MMU LUT entry x low

Offset: 0x1968, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [301]

Graphic MMU LUT entry x high

Offset: 0x196c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [302]

Graphic MMU LUT entry x low

Offset: 0x1970, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [302]

Graphic MMU LUT entry x high

Offset: 0x1974, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [303]

Graphic MMU LUT entry x low

Offset: 0x1978, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [303]

Graphic MMU LUT entry x high

Offset: 0x197c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [304]

Graphic MMU LUT entry x low

Offset: 0x1980, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [304]

Graphic MMU LUT entry x high

Offset: 0x1984, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [305]

Graphic MMU LUT entry x low

Offset: 0x1988, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [305]

Graphic MMU LUT entry x high

Offset: 0x198c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [306]

Graphic MMU LUT entry x low

Offset: 0x1990, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [306]

Graphic MMU LUT entry x high

Offset: 0x1994, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [307]

Graphic MMU LUT entry x low

Offset: 0x1998, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [307]

Graphic MMU LUT entry x high

Offset: 0x199c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [308]

Graphic MMU LUT entry x low

Offset: 0x19a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [308]

Graphic MMU LUT entry x high

Offset: 0x19a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [309]

Graphic MMU LUT entry x low

Offset: 0x19a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [309]

Graphic MMU LUT entry x high

Offset: 0x19ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [310]

Graphic MMU LUT entry x low

Offset: 0x19b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [310]

Graphic MMU LUT entry x high

Offset: 0x19b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [311]

Graphic MMU LUT entry x low

Offset: 0x19b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [311]

Graphic MMU LUT entry x high

Offset: 0x19bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [312]

Graphic MMU LUT entry x low

Offset: 0x19c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [312]

Graphic MMU LUT entry x high

Offset: 0x19c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [313]

Graphic MMU LUT entry x low

Offset: 0x19c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [313]

Graphic MMU LUT entry x high

Offset: 0x19cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [314]

Graphic MMU LUT entry x low

Offset: 0x19d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [314]

Graphic MMU LUT entry x high

Offset: 0x19d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [315]

Graphic MMU LUT entry x low

Offset: 0x19d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [315]

Graphic MMU LUT entry x high

Offset: 0x19dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [316]

Graphic MMU LUT entry x low

Offset: 0x19e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [316]

Graphic MMU LUT entry x high

Offset: 0x19e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [317]

Graphic MMU LUT entry x low

Offset: 0x19e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [317]

Graphic MMU LUT entry x high

Offset: 0x19ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [318]

Graphic MMU LUT entry x low

Offset: 0x19f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [318]

Graphic MMU LUT entry x high

Offset: 0x19f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [319]

Graphic MMU LUT entry x low

Offset: 0x19f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [319]

Graphic MMU LUT entry x high

Offset: 0x19fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [320]

Graphic MMU LUT entry x low

Offset: 0x1a00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [320]

Graphic MMU LUT entry x high

Offset: 0x1a04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [321]

Graphic MMU LUT entry x low

Offset: 0x1a08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [321]

Graphic MMU LUT entry x high

Offset: 0x1a0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [322]

Graphic MMU LUT entry x low

Offset: 0x1a10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [322]

Graphic MMU LUT entry x high

Offset: 0x1a14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [323]

Graphic MMU LUT entry x low

Offset: 0x1a18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [323]

Graphic MMU LUT entry x high

Offset: 0x1a1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [324]

Graphic MMU LUT entry x low

Offset: 0x1a20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [324]

Graphic MMU LUT entry x high

Offset: 0x1a24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [325]

Graphic MMU LUT entry x low

Offset: 0x1a28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [325]

Graphic MMU LUT entry x high

Offset: 0x1a2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [326]

Graphic MMU LUT entry x low

Offset: 0x1a30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [326]

Graphic MMU LUT entry x high

Offset: 0x1a34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [327]

Graphic MMU LUT entry x low

Offset: 0x1a38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [327]

Graphic MMU LUT entry x high

Offset: 0x1a3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [328]

Graphic MMU LUT entry x low

Offset: 0x1a40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [328]

Graphic MMU LUT entry x high

Offset: 0x1a44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [329]

Graphic MMU LUT entry x low

Offset: 0x1a48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [329]

Graphic MMU LUT entry x high

Offset: 0x1a4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [330]

Graphic MMU LUT entry x low

Offset: 0x1a50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [330]

Graphic MMU LUT entry x high

Offset: 0x1a54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [331]

Graphic MMU LUT entry x low

Offset: 0x1a58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [331]

Graphic MMU LUT entry x high

Offset: 0x1a5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [332]

Graphic MMU LUT entry x low

Offset: 0x1a60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [332]

Graphic MMU LUT entry x high

Offset: 0x1a64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [333]

Graphic MMU LUT entry x low

Offset: 0x1a68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [333]

Graphic MMU LUT entry x high

Offset: 0x1a6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [334]

Graphic MMU LUT entry x low

Offset: 0x1a70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [334]

Graphic MMU LUT entry x high

Offset: 0x1a74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [335]

Graphic MMU LUT entry x low

Offset: 0x1a78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [335]

Graphic MMU LUT entry x high

Offset: 0x1a7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [336]

Graphic MMU LUT entry x low

Offset: 0x1a80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [336]

Graphic MMU LUT entry x high

Offset: 0x1a84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [337]

Graphic MMU LUT entry x low

Offset: 0x1a88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [337]

Graphic MMU LUT entry x high

Offset: 0x1a8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [338]

Graphic MMU LUT entry x low

Offset: 0x1a90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [338]

Graphic MMU LUT entry x high

Offset: 0x1a94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [339]

Graphic MMU LUT entry x low

Offset: 0x1a98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [339]

Graphic MMU LUT entry x high

Offset: 0x1a9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [340]

Graphic MMU LUT entry x low

Offset: 0x1aa0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [340]

Graphic MMU LUT entry x high

Offset: 0x1aa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [341]

Graphic MMU LUT entry x low

Offset: 0x1aa8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [341]

Graphic MMU LUT entry x high

Offset: 0x1aac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [342]

Graphic MMU LUT entry x low

Offset: 0x1ab0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [342]

Graphic MMU LUT entry x high

Offset: 0x1ab4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [343]

Graphic MMU LUT entry x low

Offset: 0x1ab8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [343]

Graphic MMU LUT entry x high

Offset: 0x1abc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [344]

Graphic MMU LUT entry x low

Offset: 0x1ac0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [344]

Graphic MMU LUT entry x high

Offset: 0x1ac4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [345]

Graphic MMU LUT entry x low

Offset: 0x1ac8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [345]

Graphic MMU LUT entry x high

Offset: 0x1acc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [346]

Graphic MMU LUT entry x low

Offset: 0x1ad0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [346]

Graphic MMU LUT entry x high

Offset: 0x1ad4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [347]

Graphic MMU LUT entry x low

Offset: 0x1ad8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [347]

Graphic MMU LUT entry x high

Offset: 0x1adc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [348]

Graphic MMU LUT entry x low

Offset: 0x1ae0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [348]

Graphic MMU LUT entry x high

Offset: 0x1ae4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [349]

Graphic MMU LUT entry x low

Offset: 0x1ae8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [349]

Graphic MMU LUT entry x high

Offset: 0x1aec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [350]

Graphic MMU LUT entry x low

Offset: 0x1af0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [350]

Graphic MMU LUT entry x high

Offset: 0x1af4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [351]

Graphic MMU LUT entry x low

Offset: 0x1af8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [351]

Graphic MMU LUT entry x high

Offset: 0x1afc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [352]

Graphic MMU LUT entry x low

Offset: 0x1b00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [352]

Graphic MMU LUT entry x high

Offset: 0x1b04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [353]

Graphic MMU LUT entry x low

Offset: 0x1b08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [353]

Graphic MMU LUT entry x high

Offset: 0x1b0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [354]

Graphic MMU LUT entry x low

Offset: 0x1b10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [354]

Graphic MMU LUT entry x high

Offset: 0x1b14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [355]

Graphic MMU LUT entry x low

Offset: 0x1b18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [355]

Graphic MMU LUT entry x high

Offset: 0x1b1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [356]

Graphic MMU LUT entry x low

Offset: 0x1b20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [356]

Graphic MMU LUT entry x high

Offset: 0x1b24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [357]

Graphic MMU LUT entry x low

Offset: 0x1b28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [357]

Graphic MMU LUT entry x high

Offset: 0x1b2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [358]

Graphic MMU LUT entry x low

Offset: 0x1b30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [358]

Graphic MMU LUT entry x high

Offset: 0x1b34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [359]

Graphic MMU LUT entry x low

Offset: 0x1b38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [359]

Graphic MMU LUT entry x high

Offset: 0x1b3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [360]

Graphic MMU LUT entry x low

Offset: 0x1b40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [360]

Graphic MMU LUT entry x high

Offset: 0x1b44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [361]

Graphic MMU LUT entry x low

Offset: 0x1b48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [361]

Graphic MMU LUT entry x high

Offset: 0x1b4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [362]

Graphic MMU LUT entry x low

Offset: 0x1b50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [362]

Graphic MMU LUT entry x high

Offset: 0x1b54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [363]

Graphic MMU LUT entry x low

Offset: 0x1b58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [363]

Graphic MMU LUT entry x high

Offset: 0x1b5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [364]

Graphic MMU LUT entry x low

Offset: 0x1b60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [364]

Graphic MMU LUT entry x high

Offset: 0x1b64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [365]

Graphic MMU LUT entry x low

Offset: 0x1b68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [365]

Graphic MMU LUT entry x high

Offset: 0x1b6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [366]

Graphic MMU LUT entry x low

Offset: 0x1b70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [366]

Graphic MMU LUT entry x high

Offset: 0x1b74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [367]

Graphic MMU LUT entry x low

Offset: 0x1b78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [367]

Graphic MMU LUT entry x high

Offset: 0x1b7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [368]

Graphic MMU LUT entry x low

Offset: 0x1b80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [368]

Graphic MMU LUT entry x high

Offset: 0x1b84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [369]

Graphic MMU LUT entry x low

Offset: 0x1b88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [369]

Graphic MMU LUT entry x high

Offset: 0x1b8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [370]

Graphic MMU LUT entry x low

Offset: 0x1b90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [370]

Graphic MMU LUT entry x high

Offset: 0x1b94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [371]

Graphic MMU LUT entry x low

Offset: 0x1b98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [371]

Graphic MMU LUT entry x high

Offset: 0x1b9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [372]

Graphic MMU LUT entry x low

Offset: 0x1ba0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [372]

Graphic MMU LUT entry x high

Offset: 0x1ba4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [373]

Graphic MMU LUT entry x low

Offset: 0x1ba8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [373]

Graphic MMU LUT entry x high

Offset: 0x1bac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [374]

Graphic MMU LUT entry x low

Offset: 0x1bb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [374]

Graphic MMU LUT entry x high

Offset: 0x1bb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [375]

Graphic MMU LUT entry x low

Offset: 0x1bb8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [375]

Graphic MMU LUT entry x high

Offset: 0x1bbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [376]

Graphic MMU LUT entry x low

Offset: 0x1bc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [376]

Graphic MMU LUT entry x high

Offset: 0x1bc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [377]

Graphic MMU LUT entry x low

Offset: 0x1bc8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [377]

Graphic MMU LUT entry x high

Offset: 0x1bcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [378]

Graphic MMU LUT entry x low

Offset: 0x1bd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [378]

Graphic MMU LUT entry x high

Offset: 0x1bd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [379]

Graphic MMU LUT entry x low

Offset: 0x1bd8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [379]

Graphic MMU LUT entry x high

Offset: 0x1bdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [380]

Graphic MMU LUT entry x low

Offset: 0x1be0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [380]

Graphic MMU LUT entry x high

Offset: 0x1be4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [381]

Graphic MMU LUT entry x low

Offset: 0x1be8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [381]

Graphic MMU LUT entry x high

Offset: 0x1bec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [382]

Graphic MMU LUT entry x low

Offset: 0x1bf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [382]

Graphic MMU LUT entry x high

Offset: 0x1bf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [383]

Graphic MMU LUT entry x low

Offset: 0x1bf8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [383]

Graphic MMU LUT entry x high

Offset: 0x1bfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [384]

Graphic MMU LUT entry x low

Offset: 0x1c00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [384]

Graphic MMU LUT entry x high

Offset: 0x1c04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [385]

Graphic MMU LUT entry x low

Offset: 0x1c08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [385]

Graphic MMU LUT entry x high

Offset: 0x1c0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [386]

Graphic MMU LUT entry x low

Offset: 0x1c10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [386]

Graphic MMU LUT entry x high

Offset: 0x1c14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [387]

Graphic MMU LUT entry x low

Offset: 0x1c18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [387]

Graphic MMU LUT entry x high

Offset: 0x1c1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [388]

Graphic MMU LUT entry x low

Offset: 0x1c20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [388]

Graphic MMU LUT entry x high

Offset: 0x1c24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [389]

Graphic MMU LUT entry x low

Offset: 0x1c28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [389]

Graphic MMU LUT entry x high

Offset: 0x1c2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [390]

Graphic MMU LUT entry x low

Offset: 0x1c30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [390]

Graphic MMU LUT entry x high

Offset: 0x1c34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [391]

Graphic MMU LUT entry x low

Offset: 0x1c38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [391]

Graphic MMU LUT entry x high

Offset: 0x1c3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [392]

Graphic MMU LUT entry x low

Offset: 0x1c40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [392]

Graphic MMU LUT entry x high

Offset: 0x1c44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [393]

Graphic MMU LUT entry x low

Offset: 0x1c48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [393]

Graphic MMU LUT entry x high

Offset: 0x1c4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [394]

Graphic MMU LUT entry x low

Offset: 0x1c50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [394]

Graphic MMU LUT entry x high

Offset: 0x1c54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [395]

Graphic MMU LUT entry x low

Offset: 0x1c58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [395]

Graphic MMU LUT entry x high

Offset: 0x1c5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [396]

Graphic MMU LUT entry x low

Offset: 0x1c60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [396]

Graphic MMU LUT entry x high

Offset: 0x1c64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [397]

Graphic MMU LUT entry x low

Offset: 0x1c68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [397]

Graphic MMU LUT entry x high

Offset: 0x1c6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [398]

Graphic MMU LUT entry x low

Offset: 0x1c70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [398]

Graphic MMU LUT entry x high

Offset: 0x1c74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [399]

Graphic MMU LUT entry x low

Offset: 0x1c78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [399]

Graphic MMU LUT entry x high

Offset: 0x1c7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [400]

Graphic MMU LUT entry x low

Offset: 0x1c80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [400]

Graphic MMU LUT entry x high

Offset: 0x1c84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [401]

Graphic MMU LUT entry x low

Offset: 0x1c88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [401]

Graphic MMU LUT entry x high

Offset: 0x1c8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [402]

Graphic MMU LUT entry x low

Offset: 0x1c90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [402]

Graphic MMU LUT entry x high

Offset: 0x1c94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [403]

Graphic MMU LUT entry x low

Offset: 0x1c98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [403]

Graphic MMU LUT entry x high

Offset: 0x1c9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [404]

Graphic MMU LUT entry x low

Offset: 0x1ca0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [404]

Graphic MMU LUT entry x high

Offset: 0x1ca4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [405]

Graphic MMU LUT entry x low

Offset: 0x1ca8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [405]

Graphic MMU LUT entry x high

Offset: 0x1cac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [406]

Graphic MMU LUT entry x low

Offset: 0x1cb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [406]

Graphic MMU LUT entry x high

Offset: 0x1cb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [407]

Graphic MMU LUT entry x low

Offset: 0x1cb8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [407]

Graphic MMU LUT entry x high

Offset: 0x1cbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [408]

Graphic MMU LUT entry x low

Offset: 0x1cc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [408]

Graphic MMU LUT entry x high

Offset: 0x1cc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [409]

Graphic MMU LUT entry x low

Offset: 0x1cc8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [409]

Graphic MMU LUT entry x high

Offset: 0x1ccc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [410]

Graphic MMU LUT entry x low

Offset: 0x1cd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [410]

Graphic MMU LUT entry x high

Offset: 0x1cd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [411]

Graphic MMU LUT entry x low

Offset: 0x1cd8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [411]

Graphic MMU LUT entry x high

Offset: 0x1cdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [412]

Graphic MMU LUT entry x low

Offset: 0x1ce0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [412]

Graphic MMU LUT entry x high

Offset: 0x1ce4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [413]

Graphic MMU LUT entry x low

Offset: 0x1ce8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [413]

Graphic MMU LUT entry x high

Offset: 0x1cec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [414]

Graphic MMU LUT entry x low

Offset: 0x1cf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [414]

Graphic MMU LUT entry x high

Offset: 0x1cf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [415]

Graphic MMU LUT entry x low

Offset: 0x1cf8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [415]

Graphic MMU LUT entry x high

Offset: 0x1cfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [416]

Graphic MMU LUT entry x low

Offset: 0x1d00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [416]

Graphic MMU LUT entry x high

Offset: 0x1d04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [417]

Graphic MMU LUT entry x low

Offset: 0x1d08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [417]

Graphic MMU LUT entry x high

Offset: 0x1d0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [418]

Graphic MMU LUT entry x low

Offset: 0x1d10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [418]

Graphic MMU LUT entry x high

Offset: 0x1d14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [419]

Graphic MMU LUT entry x low

Offset: 0x1d18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [419]

Graphic MMU LUT entry x high

Offset: 0x1d1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [420]

Graphic MMU LUT entry x low

Offset: 0x1d20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [420]

Graphic MMU LUT entry x high

Offset: 0x1d24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [421]

Graphic MMU LUT entry x low

Offset: 0x1d28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [421]

Graphic MMU LUT entry x high

Offset: 0x1d2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [422]

Graphic MMU LUT entry x low

Offset: 0x1d30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [422]

Graphic MMU LUT entry x high

Offset: 0x1d34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [423]

Graphic MMU LUT entry x low

Offset: 0x1d38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [423]

Graphic MMU LUT entry x high

Offset: 0x1d3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [424]

Graphic MMU LUT entry x low

Offset: 0x1d40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [424]

Graphic MMU LUT entry x high

Offset: 0x1d44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [425]

Graphic MMU LUT entry x low

Offset: 0x1d48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [425]

Graphic MMU LUT entry x high

Offset: 0x1d4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [426]

Graphic MMU LUT entry x low

Offset: 0x1d50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [426]

Graphic MMU LUT entry x high

Offset: 0x1d54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [427]

Graphic MMU LUT entry x low

Offset: 0x1d58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [427]

Graphic MMU LUT entry x high

Offset: 0x1d5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [428]

Graphic MMU LUT entry x low

Offset: 0x1d60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [428]

Graphic MMU LUT entry x high

Offset: 0x1d64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [429]

Graphic MMU LUT entry x low

Offset: 0x1d68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [429]

Graphic MMU LUT entry x high

Offset: 0x1d6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [430]

Graphic MMU LUT entry x low

Offset: 0x1d70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [430]

Graphic MMU LUT entry x high

Offset: 0x1d74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [431]

Graphic MMU LUT entry x low

Offset: 0x1d78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [431]

Graphic MMU LUT entry x high

Offset: 0x1d7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [432]

Graphic MMU LUT entry x low

Offset: 0x1d80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [432]

Graphic MMU LUT entry x high

Offset: 0x1d84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [433]

Graphic MMU LUT entry x low

Offset: 0x1d88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [433]

Graphic MMU LUT entry x high

Offset: 0x1d8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [434]

Graphic MMU LUT entry x low

Offset: 0x1d90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [434]

Graphic MMU LUT entry x high

Offset: 0x1d94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [435]

Graphic MMU LUT entry x low

Offset: 0x1d98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [435]

Graphic MMU LUT entry x high

Offset: 0x1d9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [436]

Graphic MMU LUT entry x low

Offset: 0x1da0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [436]

Graphic MMU LUT entry x high

Offset: 0x1da4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [437]

Graphic MMU LUT entry x low

Offset: 0x1da8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [437]

Graphic MMU LUT entry x high

Offset: 0x1dac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [438]

Graphic MMU LUT entry x low

Offset: 0x1db0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [438]

Graphic MMU LUT entry x high

Offset: 0x1db4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [439]

Graphic MMU LUT entry x low

Offset: 0x1db8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [439]

Graphic MMU LUT entry x high

Offset: 0x1dbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [440]

Graphic MMU LUT entry x low

Offset: 0x1dc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [440]

Graphic MMU LUT entry x high

Offset: 0x1dc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [441]

Graphic MMU LUT entry x low

Offset: 0x1dc8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [441]

Graphic MMU LUT entry x high

Offset: 0x1dcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [442]

Graphic MMU LUT entry x low

Offset: 0x1dd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [442]

Graphic MMU LUT entry x high

Offset: 0x1dd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [443]

Graphic MMU LUT entry x low

Offset: 0x1dd8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [443]

Graphic MMU LUT entry x high

Offset: 0x1ddc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [444]

Graphic MMU LUT entry x low

Offset: 0x1de0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [444]

Graphic MMU LUT entry x high

Offset: 0x1de4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [445]

Graphic MMU LUT entry x low

Offset: 0x1de8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [445]

Graphic MMU LUT entry x high

Offset: 0x1dec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [446]

Graphic MMU LUT entry x low

Offset: 0x1df0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [446]

Graphic MMU LUT entry x high

Offset: 0x1df4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [447]

Graphic MMU LUT entry x low

Offset: 0x1df8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [447]

Graphic MMU LUT entry x high

Offset: 0x1dfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [448]

Graphic MMU LUT entry x low

Offset: 0x1e00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [448]

Graphic MMU LUT entry x high

Offset: 0x1e04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [449]

Graphic MMU LUT entry x low

Offset: 0x1e08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [449]

Graphic MMU LUT entry x high

Offset: 0x1e0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [450]

Graphic MMU LUT entry x low

Offset: 0x1e10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [450]

Graphic MMU LUT entry x high

Offset: 0x1e14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [451]

Graphic MMU LUT entry x low

Offset: 0x1e18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [451]

Graphic MMU LUT entry x high

Offset: 0x1e1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [452]

Graphic MMU LUT entry x low

Offset: 0x1e20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [452]

Graphic MMU LUT entry x high

Offset: 0x1e24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [453]

Graphic MMU LUT entry x low

Offset: 0x1e28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [453]

Graphic MMU LUT entry x high

Offset: 0x1e2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [454]

Graphic MMU LUT entry x low

Offset: 0x1e30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [454]

Graphic MMU LUT entry x high

Offset: 0x1e34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [455]

Graphic MMU LUT entry x low

Offset: 0x1e38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [455]

Graphic MMU LUT entry x high

Offset: 0x1e3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [456]

Graphic MMU LUT entry x low

Offset: 0x1e40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [456]

Graphic MMU LUT entry x high

Offset: 0x1e44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [457]

Graphic MMU LUT entry x low

Offset: 0x1e48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [457]

Graphic MMU LUT entry x high

Offset: 0x1e4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [458]

Graphic MMU LUT entry x low

Offset: 0x1e50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [458]

Graphic MMU LUT entry x high

Offset: 0x1e54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [459]

Graphic MMU LUT entry x low

Offset: 0x1e58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [459]

Graphic MMU LUT entry x high

Offset: 0x1e5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [460]

Graphic MMU LUT entry x low

Offset: 0x1e60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [460]

Graphic MMU LUT entry x high

Offset: 0x1e64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [461]

Graphic MMU LUT entry x low

Offset: 0x1e68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [461]

Graphic MMU LUT entry x high

Offset: 0x1e6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [462]

Graphic MMU LUT entry x low

Offset: 0x1e70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [462]

Graphic MMU LUT entry x high

Offset: 0x1e74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [463]

Graphic MMU LUT entry x low

Offset: 0x1e78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [463]

Graphic MMU LUT entry x high

Offset: 0x1e7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [464]

Graphic MMU LUT entry x low

Offset: 0x1e80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [464]

Graphic MMU LUT entry x high

Offset: 0x1e84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [465]

Graphic MMU LUT entry x low

Offset: 0x1e88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [465]

Graphic MMU LUT entry x high

Offset: 0x1e8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [466]

Graphic MMU LUT entry x low

Offset: 0x1e90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [466]

Graphic MMU LUT entry x high

Offset: 0x1e94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [467]

Graphic MMU LUT entry x low

Offset: 0x1e98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [467]

Graphic MMU LUT entry x high

Offset: 0x1e9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [468]

Graphic MMU LUT entry x low

Offset: 0x1ea0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [468]

Graphic MMU LUT entry x high

Offset: 0x1ea4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [469]

Graphic MMU LUT entry x low

Offset: 0x1ea8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [469]

Graphic MMU LUT entry x high

Offset: 0x1eac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [470]

Graphic MMU LUT entry x low

Offset: 0x1eb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [470]

Graphic MMU LUT entry x high

Offset: 0x1eb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [471]

Graphic MMU LUT entry x low

Offset: 0x1eb8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [471]

Graphic MMU LUT entry x high

Offset: 0x1ebc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [472]

Graphic MMU LUT entry x low

Offset: 0x1ec0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [472]

Graphic MMU LUT entry x high

Offset: 0x1ec4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [473]

Graphic MMU LUT entry x low

Offset: 0x1ec8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [473]

Graphic MMU LUT entry x high

Offset: 0x1ecc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [474]

Graphic MMU LUT entry x low

Offset: 0x1ed0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [474]

Graphic MMU LUT entry x high

Offset: 0x1ed4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [475]

Graphic MMU LUT entry x low

Offset: 0x1ed8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [475]

Graphic MMU LUT entry x high

Offset: 0x1edc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [476]

Graphic MMU LUT entry x low

Offset: 0x1ee0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [476]

Graphic MMU LUT entry x high

Offset: 0x1ee4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [477]

Graphic MMU LUT entry x low

Offset: 0x1ee8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [477]

Graphic MMU LUT entry x high

Offset: 0x1eec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [478]

Graphic MMU LUT entry x low

Offset: 0x1ef0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [478]

Graphic MMU LUT entry x high

Offset: 0x1ef4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [479]

Graphic MMU LUT entry x low

Offset: 0x1ef8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [479]

Graphic MMU LUT entry x high

Offset: 0x1efc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [480]

Graphic MMU LUT entry x low

Offset: 0x1f00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [480]

Graphic MMU LUT entry x high

Offset: 0x1f04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [481]

Graphic MMU LUT entry x low

Offset: 0x1f08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [481]

Graphic MMU LUT entry x high

Offset: 0x1f0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [482]

Graphic MMU LUT entry x low

Offset: 0x1f10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [482]

Graphic MMU LUT entry x high

Offset: 0x1f14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [483]

Graphic MMU LUT entry x low

Offset: 0x1f18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [483]

Graphic MMU LUT entry x high

Offset: 0x1f1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [484]

Graphic MMU LUT entry x low

Offset: 0x1f20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [484]

Graphic MMU LUT entry x high

Offset: 0x1f24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [485]

Graphic MMU LUT entry x low

Offset: 0x1f28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [485]

Graphic MMU LUT entry x high

Offset: 0x1f2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [486]

Graphic MMU LUT entry x low

Offset: 0x1f30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [486]

Graphic MMU LUT entry x high

Offset: 0x1f34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [487]

Graphic MMU LUT entry x low

Offset: 0x1f38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [487]

Graphic MMU LUT entry x high

Offset: 0x1f3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [488]

Graphic MMU LUT entry x low

Offset: 0x1f40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [488]

Graphic MMU LUT entry x high

Offset: 0x1f44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [489]

Graphic MMU LUT entry x low

Offset: 0x1f48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [489]

Graphic MMU LUT entry x high

Offset: 0x1f4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [490]

Graphic MMU LUT entry x low

Offset: 0x1f50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [490]

Graphic MMU LUT entry x high

Offset: 0x1f54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [491]

Graphic MMU LUT entry x low

Offset: 0x1f58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [491]

Graphic MMU LUT entry x high

Offset: 0x1f5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [492]

Graphic MMU LUT entry x low

Offset: 0x1f60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [492]

Graphic MMU LUT entry x high

Offset: 0x1f64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [493]

Graphic MMU LUT entry x low

Offset: 0x1f68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [493]

Graphic MMU LUT entry x high

Offset: 0x1f6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [494]

Graphic MMU LUT entry x low

Offset: 0x1f70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [494]

Graphic MMU LUT entry x high

Offset: 0x1f74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [495]

Graphic MMU LUT entry x low

Offset: 0x1f78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [495]

Graphic MMU LUT entry x high

Offset: 0x1f7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [496]

Graphic MMU LUT entry x low

Offset: 0x1f80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [496]

Graphic MMU LUT entry x high

Offset: 0x1f84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [497]

Graphic MMU LUT entry x low

Offset: 0x1f88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [497]

Graphic MMU LUT entry x high

Offset: 0x1f8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [498]

Graphic MMU LUT entry x low

Offset: 0x1f90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [498]

Graphic MMU LUT entry x high

Offset: 0x1f94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [499]

Graphic MMU LUT entry x low

Offset: 0x1f98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [499]

Graphic MMU LUT entry x high

Offset: 0x1f9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [500]

Graphic MMU LUT entry x low

Offset: 0x1fa0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [500]

Graphic MMU LUT entry x high

Offset: 0x1fa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [501]

Graphic MMU LUT entry x low

Offset: 0x1fa8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [501]

Graphic MMU LUT entry x high

Offset: 0x1fac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [502]

Graphic MMU LUT entry x low

Offset: 0x1fb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [502]

Graphic MMU LUT entry x high

Offset: 0x1fb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [503]

Graphic MMU LUT entry x low

Offset: 0x1fb8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [503]

Graphic MMU LUT entry x high

Offset: 0x1fbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [504]

Graphic MMU LUT entry x low

Offset: 0x1fc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [504]

Graphic MMU LUT entry x high

Offset: 0x1fc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [505]

Graphic MMU LUT entry x low

Offset: 0x1fc8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [505]

Graphic MMU LUT entry x high

Offset: 0x1fcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [506]

Graphic MMU LUT entry x low

Offset: 0x1fd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [506]

Graphic MMU LUT entry x high

Offset: 0x1fd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [507]

Graphic MMU LUT entry x low

Offset: 0x1fd8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [507]

Graphic MMU LUT entry x high

Offset: 0x1fdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [508]

Graphic MMU LUT entry x low

Offset: 0x1fe0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [508]

Graphic MMU LUT entry x high

Offset: 0x1fe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [509]

Graphic MMU LUT entry x low

Offset: 0x1fe8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [509]

Graphic MMU LUT entry x high

Offset: 0x1fec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [510]

Graphic MMU LUT entry x low

Offset: 0x1ff0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [510]

Graphic MMU LUT entry x high

Offset: 0x1ff4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [511]

Graphic MMU LUT entry x low

Offset: 0x1ff8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [511]

Graphic MMU LUT entry x high

Offset: 0x1ffc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [512]

Graphic MMU LUT entry x low

Offset: 0x2000, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [512]

Graphic MMU LUT entry x high

Offset: 0x2004, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [513]

Graphic MMU LUT entry x low

Offset: 0x2008, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [513]

Graphic MMU LUT entry x high

Offset: 0x200c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [514]

Graphic MMU LUT entry x low

Offset: 0x2010, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [514]

Graphic MMU LUT entry x high

Offset: 0x2014, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [515]

Graphic MMU LUT entry x low

Offset: 0x2018, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [515]

Graphic MMU LUT entry x high

Offset: 0x201c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [516]

Graphic MMU LUT entry x low

Offset: 0x2020, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [516]

Graphic MMU LUT entry x high

Offset: 0x2024, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [517]

Graphic MMU LUT entry x low

Offset: 0x2028, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [517]

Graphic MMU LUT entry x high

Offset: 0x202c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [518]

Graphic MMU LUT entry x low

Offset: 0x2030, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [518]

Graphic MMU LUT entry x high

Offset: 0x2034, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [519]

Graphic MMU LUT entry x low

Offset: 0x2038, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [519]

Graphic MMU LUT entry x high

Offset: 0x203c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [520]

Graphic MMU LUT entry x low

Offset: 0x2040, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [520]

Graphic MMU LUT entry x high

Offset: 0x2044, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [521]

Graphic MMU LUT entry x low

Offset: 0x2048, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [521]

Graphic MMU LUT entry x high

Offset: 0x204c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [522]

Graphic MMU LUT entry x low

Offset: 0x2050, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [522]

Graphic MMU LUT entry x high

Offset: 0x2054, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [523]

Graphic MMU LUT entry x low

Offset: 0x2058, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [523]

Graphic MMU LUT entry x high

Offset: 0x205c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [524]

Graphic MMU LUT entry x low

Offset: 0x2060, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [524]

Graphic MMU LUT entry x high

Offset: 0x2064, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [525]

Graphic MMU LUT entry x low

Offset: 0x2068, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [525]

Graphic MMU LUT entry x high

Offset: 0x206c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [526]

Graphic MMU LUT entry x low

Offset: 0x2070, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [526]

Graphic MMU LUT entry x high

Offset: 0x2074, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [527]

Graphic MMU LUT entry x low

Offset: 0x2078, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [527]

Graphic MMU LUT entry x high

Offset: 0x207c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [528]

Graphic MMU LUT entry x low

Offset: 0x2080, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [528]

Graphic MMU LUT entry x high

Offset: 0x2084, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [529]

Graphic MMU LUT entry x low

Offset: 0x2088, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [529]

Graphic MMU LUT entry x high

Offset: 0x208c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [530]

Graphic MMU LUT entry x low

Offset: 0x2090, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [530]

Graphic MMU LUT entry x high

Offset: 0x2094, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [531]

Graphic MMU LUT entry x low

Offset: 0x2098, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [531]

Graphic MMU LUT entry x high

Offset: 0x209c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [532]

Graphic MMU LUT entry x low

Offset: 0x20a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [532]

Graphic MMU LUT entry x high

Offset: 0x20a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [533]

Graphic MMU LUT entry x low

Offset: 0x20a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [533]

Graphic MMU LUT entry x high

Offset: 0x20ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [534]

Graphic MMU LUT entry x low

Offset: 0x20b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [534]

Graphic MMU LUT entry x high

Offset: 0x20b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [535]

Graphic MMU LUT entry x low

Offset: 0x20b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [535]

Graphic MMU LUT entry x high

Offset: 0x20bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [536]

Graphic MMU LUT entry x low

Offset: 0x20c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [536]

Graphic MMU LUT entry x high

Offset: 0x20c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [537]

Graphic MMU LUT entry x low

Offset: 0x20c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [537]

Graphic MMU LUT entry x high

Offset: 0x20cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [538]

Graphic MMU LUT entry x low

Offset: 0x20d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [538]

Graphic MMU LUT entry x high

Offset: 0x20d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [539]

Graphic MMU LUT entry x low

Offset: 0x20d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [539]

Graphic MMU LUT entry x high

Offset: 0x20dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [540]

Graphic MMU LUT entry x low

Offset: 0x20e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [540]

Graphic MMU LUT entry x high

Offset: 0x20e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [541]

Graphic MMU LUT entry x low

Offset: 0x20e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [541]

Graphic MMU LUT entry x high

Offset: 0x20ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [542]

Graphic MMU LUT entry x low

Offset: 0x20f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [542]

Graphic MMU LUT entry x high

Offset: 0x20f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [543]

Graphic MMU LUT entry x low

Offset: 0x20f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [543]

Graphic MMU LUT entry x high

Offset: 0x20fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [544]

Graphic MMU LUT entry x low

Offset: 0x2100, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [544]

Graphic MMU LUT entry x high

Offset: 0x2104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [545]

Graphic MMU LUT entry x low

Offset: 0x2108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [545]

Graphic MMU LUT entry x high

Offset: 0x210c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [546]

Graphic MMU LUT entry x low

Offset: 0x2110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [546]

Graphic MMU LUT entry x high

Offset: 0x2114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [547]

Graphic MMU LUT entry x low

Offset: 0x2118, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [547]

Graphic MMU LUT entry x high

Offset: 0x211c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [548]

Graphic MMU LUT entry x low

Offset: 0x2120, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [548]

Graphic MMU LUT entry x high

Offset: 0x2124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [549]

Graphic MMU LUT entry x low

Offset: 0x2128, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [549]

Graphic MMU LUT entry x high

Offset: 0x212c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [550]

Graphic MMU LUT entry x low

Offset: 0x2130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [550]

Graphic MMU LUT entry x high

Offset: 0x2134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [551]

Graphic MMU LUT entry x low

Offset: 0x2138, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [551]

Graphic MMU LUT entry x high

Offset: 0x213c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [552]

Graphic MMU LUT entry x low

Offset: 0x2140, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [552]

Graphic MMU LUT entry x high

Offset: 0x2144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [553]

Graphic MMU LUT entry x low

Offset: 0x2148, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [553]

Graphic MMU LUT entry x high

Offset: 0x214c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [554]

Graphic MMU LUT entry x low

Offset: 0x2150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [554]

Graphic MMU LUT entry x high

Offset: 0x2154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [555]

Graphic MMU LUT entry x low

Offset: 0x2158, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [555]

Graphic MMU LUT entry x high

Offset: 0x215c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [556]

Graphic MMU LUT entry x low

Offset: 0x2160, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [556]

Graphic MMU LUT entry x high

Offset: 0x2164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [557]

Graphic MMU LUT entry x low

Offset: 0x2168, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [557]

Graphic MMU LUT entry x high

Offset: 0x216c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [558]

Graphic MMU LUT entry x low

Offset: 0x2170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [558]

Graphic MMU LUT entry x high

Offset: 0x2174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [559]

Graphic MMU LUT entry x low

Offset: 0x2178, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [559]

Graphic MMU LUT entry x high

Offset: 0x217c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [560]

Graphic MMU LUT entry x low

Offset: 0x2180, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [560]

Graphic MMU LUT entry x high

Offset: 0x2184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [561]

Graphic MMU LUT entry x low

Offset: 0x2188, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [561]

Graphic MMU LUT entry x high

Offset: 0x218c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [562]

Graphic MMU LUT entry x low

Offset: 0x2190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [562]

Graphic MMU LUT entry x high

Offset: 0x2194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [563]

Graphic MMU LUT entry x low

Offset: 0x2198, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [563]

Graphic MMU LUT entry x high

Offset: 0x219c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [564]

Graphic MMU LUT entry x low

Offset: 0x21a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [564]

Graphic MMU LUT entry x high

Offset: 0x21a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [565]

Graphic MMU LUT entry x low

Offset: 0x21a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [565]

Graphic MMU LUT entry x high

Offset: 0x21ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [566]

Graphic MMU LUT entry x low

Offset: 0x21b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [566]

Graphic MMU LUT entry x high

Offset: 0x21b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [567]

Graphic MMU LUT entry x low

Offset: 0x21b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [567]

Graphic MMU LUT entry x high

Offset: 0x21bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [568]

Graphic MMU LUT entry x low

Offset: 0x21c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [568]

Graphic MMU LUT entry x high

Offset: 0x21c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [569]

Graphic MMU LUT entry x low

Offset: 0x21c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [569]

Graphic MMU LUT entry x high

Offset: 0x21cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [570]

Graphic MMU LUT entry x low

Offset: 0x21d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [570]

Graphic MMU LUT entry x high

Offset: 0x21d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [571]

Graphic MMU LUT entry x low

Offset: 0x21d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [571]

Graphic MMU LUT entry x high

Offset: 0x21dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [572]

Graphic MMU LUT entry x low

Offset: 0x21e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [572]

Graphic MMU LUT entry x high

Offset: 0x21e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [573]

Graphic MMU LUT entry x low

Offset: 0x21e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [573]

Graphic MMU LUT entry x high

Offset: 0x21ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [574]

Graphic MMU LUT entry x low

Offset: 0x21f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [574]

Graphic MMU LUT entry x high

Offset: 0x21f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [575]

Graphic MMU LUT entry x low

Offset: 0x21f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [575]

Graphic MMU LUT entry x high

Offset: 0x21fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [576]

Graphic MMU LUT entry x low

Offset: 0x2200, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [576]

Graphic MMU LUT entry x high

Offset: 0x2204, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [577]

Graphic MMU LUT entry x low

Offset: 0x2208, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [577]

Graphic MMU LUT entry x high

Offset: 0x220c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [578]

Graphic MMU LUT entry x low

Offset: 0x2210, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [578]

Graphic MMU LUT entry x high

Offset: 0x2214, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [579]

Graphic MMU LUT entry x low

Offset: 0x2218, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [579]

Graphic MMU LUT entry x high

Offset: 0x221c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [580]

Graphic MMU LUT entry x low

Offset: 0x2220, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [580]

Graphic MMU LUT entry x high

Offset: 0x2224, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [581]

Graphic MMU LUT entry x low

Offset: 0x2228, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [581]

Graphic MMU LUT entry x high

Offset: 0x222c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [582]

Graphic MMU LUT entry x low

Offset: 0x2230, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [582]

Graphic MMU LUT entry x high

Offset: 0x2234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [583]

Graphic MMU LUT entry x low

Offset: 0x2238, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [583]

Graphic MMU LUT entry x high

Offset: 0x223c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [584]

Graphic MMU LUT entry x low

Offset: 0x2240, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [584]

Graphic MMU LUT entry x high

Offset: 0x2244, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [585]

Graphic MMU LUT entry x low

Offset: 0x2248, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [585]

Graphic MMU LUT entry x high

Offset: 0x224c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [586]

Graphic MMU LUT entry x low

Offset: 0x2250, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [586]

Graphic MMU LUT entry x high

Offset: 0x2254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [587]

Graphic MMU LUT entry x low

Offset: 0x2258, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [587]

Graphic MMU LUT entry x high

Offset: 0x225c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [588]

Graphic MMU LUT entry x low

Offset: 0x2260, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [588]

Graphic MMU LUT entry x high

Offset: 0x2264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [589]

Graphic MMU LUT entry x low

Offset: 0x2268, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [589]

Graphic MMU LUT entry x high

Offset: 0x226c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [590]

Graphic MMU LUT entry x low

Offset: 0x2270, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [590]

Graphic MMU LUT entry x high

Offset: 0x2274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [591]

Graphic MMU LUT entry x low

Offset: 0x2278, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [591]

Graphic MMU LUT entry x high

Offset: 0x227c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [592]

Graphic MMU LUT entry x low

Offset: 0x2280, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [592]

Graphic MMU LUT entry x high

Offset: 0x2284, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [593]

Graphic MMU LUT entry x low

Offset: 0x2288, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [593]

Graphic MMU LUT entry x high

Offset: 0x228c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [594]

Graphic MMU LUT entry x low

Offset: 0x2290, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [594]

Graphic MMU LUT entry x high

Offset: 0x2294, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [595]

Graphic MMU LUT entry x low

Offset: 0x2298, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [595]

Graphic MMU LUT entry x high

Offset: 0x229c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [596]

Graphic MMU LUT entry x low

Offset: 0x22a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [596]

Graphic MMU LUT entry x high

Offset: 0x22a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [597]

Graphic MMU LUT entry x low

Offset: 0x22a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [597]

Graphic MMU LUT entry x high

Offset: 0x22ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [598]

Graphic MMU LUT entry x low

Offset: 0x22b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [598]

Graphic MMU LUT entry x high

Offset: 0x22b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [599]

Graphic MMU LUT entry x low

Offset: 0x22b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [599]

Graphic MMU LUT entry x high

Offset: 0x22bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [600]

Graphic MMU LUT entry x low

Offset: 0x22c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [600]

Graphic MMU LUT entry x high

Offset: 0x22c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [601]

Graphic MMU LUT entry x low

Offset: 0x22c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [601]

Graphic MMU LUT entry x high

Offset: 0x22cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [602]

Graphic MMU LUT entry x low

Offset: 0x22d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [602]

Graphic MMU LUT entry x high

Offset: 0x22d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [603]

Graphic MMU LUT entry x low

Offset: 0x22d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [603]

Graphic MMU LUT entry x high

Offset: 0x22dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [604]

Graphic MMU LUT entry x low

Offset: 0x22e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [604]

Graphic MMU LUT entry x high

Offset: 0x22e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [605]

Graphic MMU LUT entry x low

Offset: 0x22e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [605]

Graphic MMU LUT entry x high

Offset: 0x22ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [606]

Graphic MMU LUT entry x low

Offset: 0x22f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [606]

Graphic MMU LUT entry x high

Offset: 0x22f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [607]

Graphic MMU LUT entry x low

Offset: 0x22f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [607]

Graphic MMU LUT entry x high

Offset: 0x22fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [608]

Graphic MMU LUT entry x low

Offset: 0x2300, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [608]

Graphic MMU LUT entry x high

Offset: 0x2304, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [609]

Graphic MMU LUT entry x low

Offset: 0x2308, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [609]

Graphic MMU LUT entry x high

Offset: 0x230c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [610]

Graphic MMU LUT entry x low

Offset: 0x2310, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [610]

Graphic MMU LUT entry x high

Offset: 0x2314, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [611]

Graphic MMU LUT entry x low

Offset: 0x2318, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [611]

Graphic MMU LUT entry x high

Offset: 0x231c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [612]

Graphic MMU LUT entry x low

Offset: 0x2320, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [612]

Graphic MMU LUT entry x high

Offset: 0x2324, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [613]

Graphic MMU LUT entry x low

Offset: 0x2328, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [613]

Graphic MMU LUT entry x high

Offset: 0x232c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [614]

Graphic MMU LUT entry x low

Offset: 0x2330, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [614]

Graphic MMU LUT entry x high

Offset: 0x2334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [615]

Graphic MMU LUT entry x low

Offset: 0x2338, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [615]

Graphic MMU LUT entry x high

Offset: 0x233c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [616]

Graphic MMU LUT entry x low

Offset: 0x2340, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [616]

Graphic MMU LUT entry x high

Offset: 0x2344, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [617]

Graphic MMU LUT entry x low

Offset: 0x2348, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [617]

Graphic MMU LUT entry x high

Offset: 0x234c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [618]

Graphic MMU LUT entry x low

Offset: 0x2350, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [618]

Graphic MMU LUT entry x high

Offset: 0x2354, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [619]

Graphic MMU LUT entry x low

Offset: 0x2358, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [619]

Graphic MMU LUT entry x high

Offset: 0x235c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [620]

Graphic MMU LUT entry x low

Offset: 0x2360, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [620]

Graphic MMU LUT entry x high

Offset: 0x2364, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [621]

Graphic MMU LUT entry x low

Offset: 0x2368, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [621]

Graphic MMU LUT entry x high

Offset: 0x236c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [622]

Graphic MMU LUT entry x low

Offset: 0x2370, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [622]

Graphic MMU LUT entry x high

Offset: 0x2374, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [623]

Graphic MMU LUT entry x low

Offset: 0x2378, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [623]

Graphic MMU LUT entry x high

Offset: 0x237c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [624]

Graphic MMU LUT entry x low

Offset: 0x2380, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [624]

Graphic MMU LUT entry x high

Offset: 0x2384, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [625]

Graphic MMU LUT entry x low

Offset: 0x2388, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [625]

Graphic MMU LUT entry x high

Offset: 0x238c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [626]

Graphic MMU LUT entry x low

Offset: 0x2390, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [626]

Graphic MMU LUT entry x high

Offset: 0x2394, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [627]

Graphic MMU LUT entry x low

Offset: 0x2398, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [627]

Graphic MMU LUT entry x high

Offset: 0x239c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [628]

Graphic MMU LUT entry x low

Offset: 0x23a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [628]

Graphic MMU LUT entry x high

Offset: 0x23a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [629]

Graphic MMU LUT entry x low

Offset: 0x23a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [629]

Graphic MMU LUT entry x high

Offset: 0x23ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [630]

Graphic MMU LUT entry x low

Offset: 0x23b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [630]

Graphic MMU LUT entry x high

Offset: 0x23b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [631]

Graphic MMU LUT entry x low

Offset: 0x23b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [631]

Graphic MMU LUT entry x high

Offset: 0x23bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [632]

Graphic MMU LUT entry x low

Offset: 0x23c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [632]

Graphic MMU LUT entry x high

Offset: 0x23c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [633]

Graphic MMU LUT entry x low

Offset: 0x23c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [633]

Graphic MMU LUT entry x high

Offset: 0x23cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [634]

Graphic MMU LUT entry x low

Offset: 0x23d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [634]

Graphic MMU LUT entry x high

Offset: 0x23d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [635]

Graphic MMU LUT entry x low

Offset: 0x23d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [635]

Graphic MMU LUT entry x high

Offset: 0x23dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [636]

Graphic MMU LUT entry x low

Offset: 0x23e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [636]

Graphic MMU LUT entry x high

Offset: 0x23e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [637]

Graphic MMU LUT entry x low

Offset: 0x23e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [637]

Graphic MMU LUT entry x high

Offset: 0x23ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [638]

Graphic MMU LUT entry x low

Offset: 0x23f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [638]

Graphic MMU LUT entry x high

Offset: 0x23f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [639]

Graphic MMU LUT entry x low

Offset: 0x23f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [639]

Graphic MMU LUT entry x high

Offset: 0x23fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [640]

Graphic MMU LUT entry x low

Offset: 0x2400, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [640]

Graphic MMU LUT entry x high

Offset: 0x2404, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [641]

Graphic MMU LUT entry x low

Offset: 0x2408, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [641]

Graphic MMU LUT entry x high

Offset: 0x240c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [642]

Graphic MMU LUT entry x low

Offset: 0x2410, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [642]

Graphic MMU LUT entry x high

Offset: 0x2414, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [643]

Graphic MMU LUT entry x low

Offset: 0x2418, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [643]

Graphic MMU LUT entry x high

Offset: 0x241c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [644]

Graphic MMU LUT entry x low

Offset: 0x2420, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [644]

Graphic MMU LUT entry x high

Offset: 0x2424, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [645]

Graphic MMU LUT entry x low

Offset: 0x2428, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [645]

Graphic MMU LUT entry x high

Offset: 0x242c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [646]

Graphic MMU LUT entry x low

Offset: 0x2430, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [646]

Graphic MMU LUT entry x high

Offset: 0x2434, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [647]

Graphic MMU LUT entry x low

Offset: 0x2438, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [647]

Graphic MMU LUT entry x high

Offset: 0x243c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [648]

Graphic MMU LUT entry x low

Offset: 0x2440, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [648]

Graphic MMU LUT entry x high

Offset: 0x2444, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [649]

Graphic MMU LUT entry x low

Offset: 0x2448, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [649]

Graphic MMU LUT entry x high

Offset: 0x244c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [650]

Graphic MMU LUT entry x low

Offset: 0x2450, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [650]

Graphic MMU LUT entry x high

Offset: 0x2454, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [651]

Graphic MMU LUT entry x low

Offset: 0x2458, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [651]

Graphic MMU LUT entry x high

Offset: 0x245c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [652]

Graphic MMU LUT entry x low

Offset: 0x2460, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [652]

Graphic MMU LUT entry x high

Offset: 0x2464, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [653]

Graphic MMU LUT entry x low

Offset: 0x2468, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [653]

Graphic MMU LUT entry x high

Offset: 0x246c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [654]

Graphic MMU LUT entry x low

Offset: 0x2470, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [654]

Graphic MMU LUT entry x high

Offset: 0x2474, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [655]

Graphic MMU LUT entry x low

Offset: 0x2478, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [655]

Graphic MMU LUT entry x high

Offset: 0x247c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [656]

Graphic MMU LUT entry x low

Offset: 0x2480, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [656]

Graphic MMU LUT entry x high

Offset: 0x2484, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [657]

Graphic MMU LUT entry x low

Offset: 0x2488, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [657]

Graphic MMU LUT entry x high

Offset: 0x248c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [658]

Graphic MMU LUT entry x low

Offset: 0x2490, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [658]

Graphic MMU LUT entry x high

Offset: 0x2494, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [659]

Graphic MMU LUT entry x low

Offset: 0x2498, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [659]

Graphic MMU LUT entry x high

Offset: 0x249c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [660]

Graphic MMU LUT entry x low

Offset: 0x24a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [660]

Graphic MMU LUT entry x high

Offset: 0x24a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [661]

Graphic MMU LUT entry x low

Offset: 0x24a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [661]

Graphic MMU LUT entry x high

Offset: 0x24ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [662]

Graphic MMU LUT entry x low

Offset: 0x24b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [662]

Graphic MMU LUT entry x high

Offset: 0x24b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [663]

Graphic MMU LUT entry x low

Offset: 0x24b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [663]

Graphic MMU LUT entry x high

Offset: 0x24bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [664]

Graphic MMU LUT entry x low

Offset: 0x24c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [664]

Graphic MMU LUT entry x high

Offset: 0x24c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [665]

Graphic MMU LUT entry x low

Offset: 0x24c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [665]

Graphic MMU LUT entry x high

Offset: 0x24cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [666]

Graphic MMU LUT entry x low

Offset: 0x24d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [666]

Graphic MMU LUT entry x high

Offset: 0x24d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [667]

Graphic MMU LUT entry x low

Offset: 0x24d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [667]

Graphic MMU LUT entry x high

Offset: 0x24dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [668]

Graphic MMU LUT entry x low

Offset: 0x24e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [668]

Graphic MMU LUT entry x high

Offset: 0x24e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [669]

Graphic MMU LUT entry x low

Offset: 0x24e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [669]

Graphic MMU LUT entry x high

Offset: 0x24ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [670]

Graphic MMU LUT entry x low

Offset: 0x24f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [670]

Graphic MMU LUT entry x high

Offset: 0x24f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [671]

Graphic MMU LUT entry x low

Offset: 0x24f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [671]

Graphic MMU LUT entry x high

Offset: 0x24fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [672]

Graphic MMU LUT entry x low

Offset: 0x2500, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [672]

Graphic MMU LUT entry x high

Offset: 0x2504, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [673]

Graphic MMU LUT entry x low

Offset: 0x2508, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [673]

Graphic MMU LUT entry x high

Offset: 0x250c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [674]

Graphic MMU LUT entry x low

Offset: 0x2510, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [674]

Graphic MMU LUT entry x high

Offset: 0x2514, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [675]

Graphic MMU LUT entry x low

Offset: 0x2518, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [675]

Graphic MMU LUT entry x high

Offset: 0x251c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [676]

Graphic MMU LUT entry x low

Offset: 0x2520, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [676]

Graphic MMU LUT entry x high

Offset: 0x2524, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [677]

Graphic MMU LUT entry x low

Offset: 0x2528, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [677]

Graphic MMU LUT entry x high

Offset: 0x252c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [678]

Graphic MMU LUT entry x low

Offset: 0x2530, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [678]

Graphic MMU LUT entry x high

Offset: 0x2534, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [679]

Graphic MMU LUT entry x low

Offset: 0x2538, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [679]

Graphic MMU LUT entry x high

Offset: 0x253c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [680]

Graphic MMU LUT entry x low

Offset: 0x2540, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [680]

Graphic MMU LUT entry x high

Offset: 0x2544, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [681]

Graphic MMU LUT entry x low

Offset: 0x2548, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [681]

Graphic MMU LUT entry x high

Offset: 0x254c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [682]

Graphic MMU LUT entry x low

Offset: 0x2550, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [682]

Graphic MMU LUT entry x high

Offset: 0x2554, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [683]

Graphic MMU LUT entry x low

Offset: 0x2558, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [683]

Graphic MMU LUT entry x high

Offset: 0x255c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [684]

Graphic MMU LUT entry x low

Offset: 0x2560, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [684]

Graphic MMU LUT entry x high

Offset: 0x2564, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [685]

Graphic MMU LUT entry x low

Offset: 0x2568, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [685]

Graphic MMU LUT entry x high

Offset: 0x256c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [686]

Graphic MMU LUT entry x low

Offset: 0x2570, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [686]

Graphic MMU LUT entry x high

Offset: 0x2574, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [687]

Graphic MMU LUT entry x low

Offset: 0x2578, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [687]

Graphic MMU LUT entry x high

Offset: 0x257c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [688]

Graphic MMU LUT entry x low

Offset: 0x2580, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [688]

Graphic MMU LUT entry x high

Offset: 0x2584, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [689]

Graphic MMU LUT entry x low

Offset: 0x2588, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [689]

Graphic MMU LUT entry x high

Offset: 0x258c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [690]

Graphic MMU LUT entry x low

Offset: 0x2590, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [690]

Graphic MMU LUT entry x high

Offset: 0x2594, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [691]

Graphic MMU LUT entry x low

Offset: 0x2598, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [691]

Graphic MMU LUT entry x high

Offset: 0x259c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [692]

Graphic MMU LUT entry x low

Offset: 0x25a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [692]

Graphic MMU LUT entry x high

Offset: 0x25a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [693]

Graphic MMU LUT entry x low

Offset: 0x25a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [693]

Graphic MMU LUT entry x high

Offset: 0x25ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [694]

Graphic MMU LUT entry x low

Offset: 0x25b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [694]

Graphic MMU LUT entry x high

Offset: 0x25b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [695]

Graphic MMU LUT entry x low

Offset: 0x25b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [695]

Graphic MMU LUT entry x high

Offset: 0x25bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [696]

Graphic MMU LUT entry x low

Offset: 0x25c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [696]

Graphic MMU LUT entry x high

Offset: 0x25c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [697]

Graphic MMU LUT entry x low

Offset: 0x25c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [697]

Graphic MMU LUT entry x high

Offset: 0x25cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [698]

Graphic MMU LUT entry x low

Offset: 0x25d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [698]

Graphic MMU LUT entry x high

Offset: 0x25d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [699]

Graphic MMU LUT entry x low

Offset: 0x25d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [699]

Graphic MMU LUT entry x high

Offset: 0x25dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [700]

Graphic MMU LUT entry x low

Offset: 0x25e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [700]

Graphic MMU LUT entry x high

Offset: 0x25e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [701]

Graphic MMU LUT entry x low

Offset: 0x25e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [701]

Graphic MMU LUT entry x high

Offset: 0x25ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [702]

Graphic MMU LUT entry x low

Offset: 0x25f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [702]

Graphic MMU LUT entry x high

Offset: 0x25f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [703]

Graphic MMU LUT entry x low

Offset: 0x25f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [703]

Graphic MMU LUT entry x high

Offset: 0x25fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [704]

Graphic MMU LUT entry x low

Offset: 0x2600, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [704]

Graphic MMU LUT entry x high

Offset: 0x2604, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [705]

Graphic MMU LUT entry x low

Offset: 0x2608, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [705]

Graphic MMU LUT entry x high

Offset: 0x260c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [706]

Graphic MMU LUT entry x low

Offset: 0x2610, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [706]

Graphic MMU LUT entry x high

Offset: 0x2614, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [707]

Graphic MMU LUT entry x low

Offset: 0x2618, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [707]

Graphic MMU LUT entry x high

Offset: 0x261c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [708]

Graphic MMU LUT entry x low

Offset: 0x2620, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [708]

Graphic MMU LUT entry x high

Offset: 0x2624, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [709]

Graphic MMU LUT entry x low

Offset: 0x2628, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [709]

Graphic MMU LUT entry x high

Offset: 0x262c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [710]

Graphic MMU LUT entry x low

Offset: 0x2630, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [710]

Graphic MMU LUT entry x high

Offset: 0x2634, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [711]

Graphic MMU LUT entry x low

Offset: 0x2638, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [711]

Graphic MMU LUT entry x high

Offset: 0x263c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [712]

Graphic MMU LUT entry x low

Offset: 0x2640, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [712]

Graphic MMU LUT entry x high

Offset: 0x2644, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [713]

Graphic MMU LUT entry x low

Offset: 0x2648, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [713]

Graphic MMU LUT entry x high

Offset: 0x264c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [714]

Graphic MMU LUT entry x low

Offset: 0x2650, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [714]

Graphic MMU LUT entry x high

Offset: 0x2654, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [715]

Graphic MMU LUT entry x low

Offset: 0x2658, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [715]

Graphic MMU LUT entry x high

Offset: 0x265c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [716]

Graphic MMU LUT entry x low

Offset: 0x2660, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [716]

Graphic MMU LUT entry x high

Offset: 0x2664, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [717]

Graphic MMU LUT entry x low

Offset: 0x2668, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [717]

Graphic MMU LUT entry x high

Offset: 0x266c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [718]

Graphic MMU LUT entry x low

Offset: 0x2670, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [718]

Graphic MMU LUT entry x high

Offset: 0x2674, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [719]

Graphic MMU LUT entry x low

Offset: 0x2678, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [719]

Graphic MMU LUT entry x high

Offset: 0x267c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [720]

Graphic MMU LUT entry x low

Offset: 0x2680, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [720]

Graphic MMU LUT entry x high

Offset: 0x2684, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [721]

Graphic MMU LUT entry x low

Offset: 0x2688, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [721]

Graphic MMU LUT entry x high

Offset: 0x268c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [722]

Graphic MMU LUT entry x low

Offset: 0x2690, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [722]

Graphic MMU LUT entry x high

Offset: 0x2694, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [723]

Graphic MMU LUT entry x low

Offset: 0x2698, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [723]

Graphic MMU LUT entry x high

Offset: 0x269c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [724]

Graphic MMU LUT entry x low

Offset: 0x26a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [724]

Graphic MMU LUT entry x high

Offset: 0x26a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [725]

Graphic MMU LUT entry x low

Offset: 0x26a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [725]

Graphic MMU LUT entry x high

Offset: 0x26ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [726]

Graphic MMU LUT entry x low

Offset: 0x26b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [726]

Graphic MMU LUT entry x high

Offset: 0x26b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [727]

Graphic MMU LUT entry x low

Offset: 0x26b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [727]

Graphic MMU LUT entry x high

Offset: 0x26bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [728]

Graphic MMU LUT entry x low

Offset: 0x26c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [728]

Graphic MMU LUT entry x high

Offset: 0x26c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [729]

Graphic MMU LUT entry x low

Offset: 0x26c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [729]

Graphic MMU LUT entry x high

Offset: 0x26cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [730]

Graphic MMU LUT entry x low

Offset: 0x26d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [730]

Graphic MMU LUT entry x high

Offset: 0x26d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [731]

Graphic MMU LUT entry x low

Offset: 0x26d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [731]

Graphic MMU LUT entry x high

Offset: 0x26dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [732]

Graphic MMU LUT entry x low

Offset: 0x26e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [732]

Graphic MMU LUT entry x high

Offset: 0x26e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [733]

Graphic MMU LUT entry x low

Offset: 0x26e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [733]

Graphic MMU LUT entry x high

Offset: 0x26ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [734]

Graphic MMU LUT entry x low

Offset: 0x26f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [734]

Graphic MMU LUT entry x high

Offset: 0x26f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [735]

Graphic MMU LUT entry x low

Offset: 0x26f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [735]

Graphic MMU LUT entry x high

Offset: 0x26fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [736]

Graphic MMU LUT entry x low

Offset: 0x2700, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [736]

Graphic MMU LUT entry x high

Offset: 0x2704, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [737]

Graphic MMU LUT entry x low

Offset: 0x2708, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [737]

Graphic MMU LUT entry x high

Offset: 0x270c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [738]

Graphic MMU LUT entry x low

Offset: 0x2710, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [738]

Graphic MMU LUT entry x high

Offset: 0x2714, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [739]

Graphic MMU LUT entry x low

Offset: 0x2718, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [739]

Graphic MMU LUT entry x high

Offset: 0x271c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [740]

Graphic MMU LUT entry x low

Offset: 0x2720, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [740]

Graphic MMU LUT entry x high

Offset: 0x2724, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [741]

Graphic MMU LUT entry x low

Offset: 0x2728, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [741]

Graphic MMU LUT entry x high

Offset: 0x272c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [742]

Graphic MMU LUT entry x low

Offset: 0x2730, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [742]

Graphic MMU LUT entry x high

Offset: 0x2734, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [743]

Graphic MMU LUT entry x low

Offset: 0x2738, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [743]

Graphic MMU LUT entry x high

Offset: 0x273c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [744]

Graphic MMU LUT entry x low

Offset: 0x2740, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [744]

Graphic MMU LUT entry x high

Offset: 0x2744, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [745]

Graphic MMU LUT entry x low

Offset: 0x2748, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [745]

Graphic MMU LUT entry x high

Offset: 0x274c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [746]

Graphic MMU LUT entry x low

Offset: 0x2750, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [746]

Graphic MMU LUT entry x high

Offset: 0x2754, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [747]

Graphic MMU LUT entry x low

Offset: 0x2758, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [747]

Graphic MMU LUT entry x high

Offset: 0x275c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [748]

Graphic MMU LUT entry x low

Offset: 0x2760, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [748]

Graphic MMU LUT entry x high

Offset: 0x2764, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [749]

Graphic MMU LUT entry x low

Offset: 0x2768, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [749]

Graphic MMU LUT entry x high

Offset: 0x276c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [750]

Graphic MMU LUT entry x low

Offset: 0x2770, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [750]

Graphic MMU LUT entry x high

Offset: 0x2774, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [751]

Graphic MMU LUT entry x low

Offset: 0x2778, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [751]

Graphic MMU LUT entry x high

Offset: 0x277c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [752]

Graphic MMU LUT entry x low

Offset: 0x2780, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [752]

Graphic MMU LUT entry x high

Offset: 0x2784, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [753]

Graphic MMU LUT entry x low

Offset: 0x2788, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [753]

Graphic MMU LUT entry x high

Offset: 0x278c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [754]

Graphic MMU LUT entry x low

Offset: 0x2790, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [754]

Graphic MMU LUT entry x high

Offset: 0x2794, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [755]

Graphic MMU LUT entry x low

Offset: 0x2798, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [755]

Graphic MMU LUT entry x high

Offset: 0x279c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [756]

Graphic MMU LUT entry x low

Offset: 0x27a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [756]

Graphic MMU LUT entry x high

Offset: 0x27a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [757]

Graphic MMU LUT entry x low

Offset: 0x27a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [757]

Graphic MMU LUT entry x high

Offset: 0x27ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [758]

Graphic MMU LUT entry x low

Offset: 0x27b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [758]

Graphic MMU LUT entry x high

Offset: 0x27b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [759]

Graphic MMU LUT entry x low

Offset: 0x27b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [759]

Graphic MMU LUT entry x high

Offset: 0x27bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [760]

Graphic MMU LUT entry x low

Offset: 0x27c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [760]

Graphic MMU LUT entry x high

Offset: 0x27c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [761]

Graphic MMU LUT entry x low

Offset: 0x27c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [761]

Graphic MMU LUT entry x high

Offset: 0x27cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [762]

Graphic MMU LUT entry x low

Offset: 0x27d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [762]

Graphic MMU LUT entry x high

Offset: 0x27d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [763]

Graphic MMU LUT entry x low

Offset: 0x27d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [763]

Graphic MMU LUT entry x high

Offset: 0x27dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [764]

Graphic MMU LUT entry x low

Offset: 0x27e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [764]

Graphic MMU LUT entry x high

Offset: 0x27e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [765]

Graphic MMU LUT entry x low

Offset: 0x27e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [765]

Graphic MMU LUT entry x high

Offset: 0x27ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [766]

Graphic MMU LUT entry x low

Offset: 0x27f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [766]

Graphic MMU LUT entry x high

Offset: 0x27f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [767]

Graphic MMU LUT entry x low

Offset: 0x27f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [767]

Graphic MMU LUT entry x high

Offset: 0x27fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [768]

Graphic MMU LUT entry x low

Offset: 0x2800, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [768]

Graphic MMU LUT entry x high

Offset: 0x2804, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [769]

Graphic MMU LUT entry x low

Offset: 0x2808, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [769]

Graphic MMU LUT entry x high

Offset: 0x280c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [770]

Graphic MMU LUT entry x low

Offset: 0x2810, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [770]

Graphic MMU LUT entry x high

Offset: 0x2814, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [771]

Graphic MMU LUT entry x low

Offset: 0x2818, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [771]

Graphic MMU LUT entry x high

Offset: 0x281c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [772]

Graphic MMU LUT entry x low

Offset: 0x2820, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [772]

Graphic MMU LUT entry x high

Offset: 0x2824, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [773]

Graphic MMU LUT entry x low

Offset: 0x2828, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [773]

Graphic MMU LUT entry x high

Offset: 0x282c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [774]

Graphic MMU LUT entry x low

Offset: 0x2830, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [774]

Graphic MMU LUT entry x high

Offset: 0x2834, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [775]

Graphic MMU LUT entry x low

Offset: 0x2838, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [775]

Graphic MMU LUT entry x high

Offset: 0x283c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [776]

Graphic MMU LUT entry x low

Offset: 0x2840, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [776]

Graphic MMU LUT entry x high

Offset: 0x2844, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [777]

Graphic MMU LUT entry x low

Offset: 0x2848, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [777]

Graphic MMU LUT entry x high

Offset: 0x284c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [778]

Graphic MMU LUT entry x low

Offset: 0x2850, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [778]

Graphic MMU LUT entry x high

Offset: 0x2854, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [779]

Graphic MMU LUT entry x low

Offset: 0x2858, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [779]

Graphic MMU LUT entry x high

Offset: 0x285c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [780]

Graphic MMU LUT entry x low

Offset: 0x2860, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [780]

Graphic MMU LUT entry x high

Offset: 0x2864, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [781]

Graphic MMU LUT entry x low

Offset: 0x2868, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [781]

Graphic MMU LUT entry x high

Offset: 0x286c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [782]

Graphic MMU LUT entry x low

Offset: 0x2870, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [782]

Graphic MMU LUT entry x high

Offset: 0x2874, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [783]

Graphic MMU LUT entry x low

Offset: 0x2878, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [783]

Graphic MMU LUT entry x high

Offset: 0x287c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [784]

Graphic MMU LUT entry x low

Offset: 0x2880, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [784]

Graphic MMU LUT entry x high

Offset: 0x2884, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [785]

Graphic MMU LUT entry x low

Offset: 0x2888, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [785]

Graphic MMU LUT entry x high

Offset: 0x288c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [786]

Graphic MMU LUT entry x low

Offset: 0x2890, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [786]

Graphic MMU LUT entry x high

Offset: 0x2894, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [787]

Graphic MMU LUT entry x low

Offset: 0x2898, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [787]

Graphic MMU LUT entry x high

Offset: 0x289c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [788]

Graphic MMU LUT entry x low

Offset: 0x28a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [788]

Graphic MMU LUT entry x high

Offset: 0x28a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [789]

Graphic MMU LUT entry x low

Offset: 0x28a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [789]

Graphic MMU LUT entry x high

Offset: 0x28ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [790]

Graphic MMU LUT entry x low

Offset: 0x28b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [790]

Graphic MMU LUT entry x high

Offset: 0x28b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [791]

Graphic MMU LUT entry x low

Offset: 0x28b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [791]

Graphic MMU LUT entry x high

Offset: 0x28bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [792]

Graphic MMU LUT entry x low

Offset: 0x28c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [792]

Graphic MMU LUT entry x high

Offset: 0x28c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [793]

Graphic MMU LUT entry x low

Offset: 0x28c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [793]

Graphic MMU LUT entry x high

Offset: 0x28cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [794]

Graphic MMU LUT entry x low

Offset: 0x28d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [794]

Graphic MMU LUT entry x high

Offset: 0x28d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [795]

Graphic MMU LUT entry x low

Offset: 0x28d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [795]

Graphic MMU LUT entry x high

Offset: 0x28dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [796]

Graphic MMU LUT entry x low

Offset: 0x28e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [796]

Graphic MMU LUT entry x high

Offset: 0x28e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [797]

Graphic MMU LUT entry x low

Offset: 0x28e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [797]

Graphic MMU LUT entry x high

Offset: 0x28ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [798]

Graphic MMU LUT entry x low

Offset: 0x28f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [798]

Graphic MMU LUT entry x high

Offset: 0x28f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [799]

Graphic MMU LUT entry x low

Offset: 0x28f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [799]

Graphic MMU LUT entry x high

Offset: 0x28fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [800]

Graphic MMU LUT entry x low

Offset: 0x2900, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [800]

Graphic MMU LUT entry x high

Offset: 0x2904, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [801]

Graphic MMU LUT entry x low

Offset: 0x2908, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [801]

Graphic MMU LUT entry x high

Offset: 0x290c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [802]

Graphic MMU LUT entry x low

Offset: 0x2910, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [802]

Graphic MMU LUT entry x high

Offset: 0x2914, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [803]

Graphic MMU LUT entry x low

Offset: 0x2918, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [803]

Graphic MMU LUT entry x high

Offset: 0x291c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [804]

Graphic MMU LUT entry x low

Offset: 0x2920, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [804]

Graphic MMU LUT entry x high

Offset: 0x2924, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [805]

Graphic MMU LUT entry x low

Offset: 0x2928, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [805]

Graphic MMU LUT entry x high

Offset: 0x292c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [806]

Graphic MMU LUT entry x low

Offset: 0x2930, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [806]

Graphic MMU LUT entry x high

Offset: 0x2934, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [807]

Graphic MMU LUT entry x low

Offset: 0x2938, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [807]

Graphic MMU LUT entry x high

Offset: 0x293c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [808]

Graphic MMU LUT entry x low

Offset: 0x2940, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [808]

Graphic MMU LUT entry x high

Offset: 0x2944, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [809]

Graphic MMU LUT entry x low

Offset: 0x2948, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [809]

Graphic MMU LUT entry x high

Offset: 0x294c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [810]

Graphic MMU LUT entry x low

Offset: 0x2950, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [810]

Graphic MMU LUT entry x high

Offset: 0x2954, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [811]

Graphic MMU LUT entry x low

Offset: 0x2958, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [811]

Graphic MMU LUT entry x high

Offset: 0x295c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [812]

Graphic MMU LUT entry x low

Offset: 0x2960, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [812]

Graphic MMU LUT entry x high

Offset: 0x2964, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [813]

Graphic MMU LUT entry x low

Offset: 0x2968, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [813]

Graphic MMU LUT entry x high

Offset: 0x296c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [814]

Graphic MMU LUT entry x low

Offset: 0x2970, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [814]

Graphic MMU LUT entry x high

Offset: 0x2974, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [815]

Graphic MMU LUT entry x low

Offset: 0x2978, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [815]

Graphic MMU LUT entry x high

Offset: 0x297c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [816]

Graphic MMU LUT entry x low

Offset: 0x2980, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [816]

Graphic MMU LUT entry x high

Offset: 0x2984, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [817]

Graphic MMU LUT entry x low

Offset: 0x2988, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [817]

Graphic MMU LUT entry x high

Offset: 0x298c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [818]

Graphic MMU LUT entry x low

Offset: 0x2990, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [818]

Graphic MMU LUT entry x high

Offset: 0x2994, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [819]

Graphic MMU LUT entry x low

Offset: 0x2998, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [819]

Graphic MMU LUT entry x high

Offset: 0x299c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [820]

Graphic MMU LUT entry x low

Offset: 0x29a0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [820]

Graphic MMU LUT entry x high

Offset: 0x29a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [821]

Graphic MMU LUT entry x low

Offset: 0x29a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [821]

Graphic MMU LUT entry x high

Offset: 0x29ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [822]

Graphic MMU LUT entry x low

Offset: 0x29b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [822]

Graphic MMU LUT entry x high

Offset: 0x29b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [823]

Graphic MMU LUT entry x low

Offset: 0x29b8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [823]

Graphic MMU LUT entry x high

Offset: 0x29bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [824]

Graphic MMU LUT entry x low

Offset: 0x29c0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [824]

Graphic MMU LUT entry x high

Offset: 0x29c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [825]

Graphic MMU LUT entry x low

Offset: 0x29c8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [825]

Graphic MMU LUT entry x high

Offset: 0x29cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [826]

Graphic MMU LUT entry x low

Offset: 0x29d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [826]

Graphic MMU LUT entry x high

Offset: 0x29d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [827]

Graphic MMU LUT entry x low

Offset: 0x29d8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [827]

Graphic MMU LUT entry x high

Offset: 0x29dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [828]

Graphic MMU LUT entry x low

Offset: 0x29e0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [828]

Graphic MMU LUT entry x high

Offset: 0x29e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [829]

Graphic MMU LUT entry x low

Offset: 0x29e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [829]

Graphic MMU LUT entry x high

Offset: 0x29ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [830]

Graphic MMU LUT entry x low

Offset: 0x29f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [830]

Graphic MMU LUT entry x high

Offset: 0x29f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [831]

Graphic MMU LUT entry x low

Offset: 0x29f8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [831]

Graphic MMU LUT entry x high

Offset: 0x29fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [832]

Graphic MMU LUT entry x low

Offset: 0x2a00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [832]

Graphic MMU LUT entry x high

Offset: 0x2a04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [833]

Graphic MMU LUT entry x low

Offset: 0x2a08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [833]

Graphic MMU LUT entry x high

Offset: 0x2a0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [834]

Graphic MMU LUT entry x low

Offset: 0x2a10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [834]

Graphic MMU LUT entry x high

Offset: 0x2a14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [835]

Graphic MMU LUT entry x low

Offset: 0x2a18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [835]

Graphic MMU LUT entry x high

Offset: 0x2a1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [836]

Graphic MMU LUT entry x low

Offset: 0x2a20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [836]

Graphic MMU LUT entry x high

Offset: 0x2a24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [837]

Graphic MMU LUT entry x low

Offset: 0x2a28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [837]

Graphic MMU LUT entry x high

Offset: 0x2a2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [838]

Graphic MMU LUT entry x low

Offset: 0x2a30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [838]

Graphic MMU LUT entry x high

Offset: 0x2a34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [839]

Graphic MMU LUT entry x low

Offset: 0x2a38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [839]

Graphic MMU LUT entry x high

Offset: 0x2a3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [840]

Graphic MMU LUT entry x low

Offset: 0x2a40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [840]

Graphic MMU LUT entry x high

Offset: 0x2a44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [841]

Graphic MMU LUT entry x low

Offset: 0x2a48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [841]

Graphic MMU LUT entry x high

Offset: 0x2a4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [842]

Graphic MMU LUT entry x low

Offset: 0x2a50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [842]

Graphic MMU LUT entry x high

Offset: 0x2a54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [843]

Graphic MMU LUT entry x low

Offset: 0x2a58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [843]

Graphic MMU LUT entry x high

Offset: 0x2a5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [844]

Graphic MMU LUT entry x low

Offset: 0x2a60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [844]

Graphic MMU LUT entry x high

Offset: 0x2a64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [845]

Graphic MMU LUT entry x low

Offset: 0x2a68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [845]

Graphic MMU LUT entry x high

Offset: 0x2a6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [846]

Graphic MMU LUT entry x low

Offset: 0x2a70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [846]

Graphic MMU LUT entry x high

Offset: 0x2a74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [847]

Graphic MMU LUT entry x low

Offset: 0x2a78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [847]

Graphic MMU LUT entry x high

Offset: 0x2a7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [848]

Graphic MMU LUT entry x low

Offset: 0x2a80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [848]

Graphic MMU LUT entry x high

Offset: 0x2a84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [849]

Graphic MMU LUT entry x low

Offset: 0x2a88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [849]

Graphic MMU LUT entry x high

Offset: 0x2a8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [850]

Graphic MMU LUT entry x low

Offset: 0x2a90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [850]

Graphic MMU LUT entry x high

Offset: 0x2a94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [851]

Graphic MMU LUT entry x low

Offset: 0x2a98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [851]

Graphic MMU LUT entry x high

Offset: 0x2a9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [852]

Graphic MMU LUT entry x low

Offset: 0x2aa0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [852]

Graphic MMU LUT entry x high

Offset: 0x2aa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [853]

Graphic MMU LUT entry x low

Offset: 0x2aa8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [853]

Graphic MMU LUT entry x high

Offset: 0x2aac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [854]

Graphic MMU LUT entry x low

Offset: 0x2ab0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [854]

Graphic MMU LUT entry x high

Offset: 0x2ab4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [855]

Graphic MMU LUT entry x low

Offset: 0x2ab8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [855]

Graphic MMU LUT entry x high

Offset: 0x2abc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [856]

Graphic MMU LUT entry x low

Offset: 0x2ac0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [856]

Graphic MMU LUT entry x high

Offset: 0x2ac4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [857]

Graphic MMU LUT entry x low

Offset: 0x2ac8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [857]

Graphic MMU LUT entry x high

Offset: 0x2acc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [858]

Graphic MMU LUT entry x low

Offset: 0x2ad0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [858]

Graphic MMU LUT entry x high

Offset: 0x2ad4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [859]

Graphic MMU LUT entry x low

Offset: 0x2ad8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [859]

Graphic MMU LUT entry x high

Offset: 0x2adc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [860]

Graphic MMU LUT entry x low

Offset: 0x2ae0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [860]

Graphic MMU LUT entry x high

Offset: 0x2ae4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [861]

Graphic MMU LUT entry x low

Offset: 0x2ae8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [861]

Graphic MMU LUT entry x high

Offset: 0x2aec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [862]

Graphic MMU LUT entry x low

Offset: 0x2af0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [862]

Graphic MMU LUT entry x high

Offset: 0x2af4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [863]

Graphic MMU LUT entry x low

Offset: 0x2af8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [863]

Graphic MMU LUT entry x high

Offset: 0x2afc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [864]

Graphic MMU LUT entry x low

Offset: 0x2b00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [864]

Graphic MMU LUT entry x high

Offset: 0x2b04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [865]

Graphic MMU LUT entry x low

Offset: 0x2b08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [865]

Graphic MMU LUT entry x high

Offset: 0x2b0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [866]

Graphic MMU LUT entry x low

Offset: 0x2b10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [866]

Graphic MMU LUT entry x high

Offset: 0x2b14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [867]

Graphic MMU LUT entry x low

Offset: 0x2b18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [867]

Graphic MMU LUT entry x high

Offset: 0x2b1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [868]

Graphic MMU LUT entry x low

Offset: 0x2b20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [868]

Graphic MMU LUT entry x high

Offset: 0x2b24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [869]

Graphic MMU LUT entry x low

Offset: 0x2b28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [869]

Graphic MMU LUT entry x high

Offset: 0x2b2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [870]

Graphic MMU LUT entry x low

Offset: 0x2b30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [870]

Graphic MMU LUT entry x high

Offset: 0x2b34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [871]

Graphic MMU LUT entry x low

Offset: 0x2b38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [871]

Graphic MMU LUT entry x high

Offset: 0x2b3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [872]

Graphic MMU LUT entry x low

Offset: 0x2b40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [872]

Graphic MMU LUT entry x high

Offset: 0x2b44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [873]

Graphic MMU LUT entry x low

Offset: 0x2b48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [873]

Graphic MMU LUT entry x high

Offset: 0x2b4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [874]

Graphic MMU LUT entry x low

Offset: 0x2b50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [874]

Graphic MMU LUT entry x high

Offset: 0x2b54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [875]

Graphic MMU LUT entry x low

Offset: 0x2b58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [875]

Graphic MMU LUT entry x high

Offset: 0x2b5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [876]

Graphic MMU LUT entry x low

Offset: 0x2b60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [876]

Graphic MMU LUT entry x high

Offset: 0x2b64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [877]

Graphic MMU LUT entry x low

Offset: 0x2b68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [877]

Graphic MMU LUT entry x high

Offset: 0x2b6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [878]

Graphic MMU LUT entry x low

Offset: 0x2b70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [878]

Graphic MMU LUT entry x high

Offset: 0x2b74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [879]

Graphic MMU LUT entry x low

Offset: 0x2b78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [879]

Graphic MMU LUT entry x high

Offset: 0x2b7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [880]

Graphic MMU LUT entry x low

Offset: 0x2b80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [880]

Graphic MMU LUT entry x high

Offset: 0x2b84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [881]

Graphic MMU LUT entry x low

Offset: 0x2b88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [881]

Graphic MMU LUT entry x high

Offset: 0x2b8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [882]

Graphic MMU LUT entry x low

Offset: 0x2b90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [882]

Graphic MMU LUT entry x high

Offset: 0x2b94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [883]

Graphic MMU LUT entry x low

Offset: 0x2b98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [883]

Graphic MMU LUT entry x high

Offset: 0x2b9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [884]

Graphic MMU LUT entry x low

Offset: 0x2ba0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [884]

Graphic MMU LUT entry x high

Offset: 0x2ba4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [885]

Graphic MMU LUT entry x low

Offset: 0x2ba8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [885]

Graphic MMU LUT entry x high

Offset: 0x2bac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [886]

Graphic MMU LUT entry x low

Offset: 0x2bb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [886]

Graphic MMU LUT entry x high

Offset: 0x2bb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [887]

Graphic MMU LUT entry x low

Offset: 0x2bb8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [887]

Graphic MMU LUT entry x high

Offset: 0x2bbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [888]

Graphic MMU LUT entry x low

Offset: 0x2bc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [888]

Graphic MMU LUT entry x high

Offset: 0x2bc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [889]

Graphic MMU LUT entry x low

Offset: 0x2bc8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [889]

Graphic MMU LUT entry x high

Offset: 0x2bcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [890]

Graphic MMU LUT entry x low

Offset: 0x2bd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [890]

Graphic MMU LUT entry x high

Offset: 0x2bd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [891]

Graphic MMU LUT entry x low

Offset: 0x2bd8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [891]

Graphic MMU LUT entry x high

Offset: 0x2bdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [892]

Graphic MMU LUT entry x low

Offset: 0x2be0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [892]

Graphic MMU LUT entry x high

Offset: 0x2be4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [893]

Graphic MMU LUT entry x low

Offset: 0x2be8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [893]

Graphic MMU LUT entry x high

Offset: 0x2bec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [894]

Graphic MMU LUT entry x low

Offset: 0x2bf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [894]

Graphic MMU LUT entry x high

Offset: 0x2bf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [895]

Graphic MMU LUT entry x low

Offset: 0x2bf8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [895]

Graphic MMU LUT entry x high

Offset: 0x2bfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [896]

Graphic MMU LUT entry x low

Offset: 0x2c00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [896]

Graphic MMU LUT entry x high

Offset: 0x2c04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [897]

Graphic MMU LUT entry x low

Offset: 0x2c08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [897]

Graphic MMU LUT entry x high

Offset: 0x2c0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [898]

Graphic MMU LUT entry x low

Offset: 0x2c10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [898]

Graphic MMU LUT entry x high

Offset: 0x2c14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [899]

Graphic MMU LUT entry x low

Offset: 0x2c18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [899]

Graphic MMU LUT entry x high

Offset: 0x2c1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [900]

Graphic MMU LUT entry x low

Offset: 0x2c20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [900]

Graphic MMU LUT entry x high

Offset: 0x2c24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [901]

Graphic MMU LUT entry x low

Offset: 0x2c28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [901]

Graphic MMU LUT entry x high

Offset: 0x2c2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [902]

Graphic MMU LUT entry x low

Offset: 0x2c30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [902]

Graphic MMU LUT entry x high

Offset: 0x2c34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [903]

Graphic MMU LUT entry x low

Offset: 0x2c38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [903]

Graphic MMU LUT entry x high

Offset: 0x2c3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [904]

Graphic MMU LUT entry x low

Offset: 0x2c40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [904]

Graphic MMU LUT entry x high

Offset: 0x2c44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [905]

Graphic MMU LUT entry x low

Offset: 0x2c48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [905]

Graphic MMU LUT entry x high

Offset: 0x2c4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [906]

Graphic MMU LUT entry x low

Offset: 0x2c50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [906]

Graphic MMU LUT entry x high

Offset: 0x2c54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [907]

Graphic MMU LUT entry x low

Offset: 0x2c58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [907]

Graphic MMU LUT entry x high

Offset: 0x2c5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [908]

Graphic MMU LUT entry x low

Offset: 0x2c60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [908]

Graphic MMU LUT entry x high

Offset: 0x2c64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [909]

Graphic MMU LUT entry x low

Offset: 0x2c68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [909]

Graphic MMU LUT entry x high

Offset: 0x2c6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [910]

Graphic MMU LUT entry x low

Offset: 0x2c70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [910]

Graphic MMU LUT entry x high

Offset: 0x2c74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [911]

Graphic MMU LUT entry x low

Offset: 0x2c78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [911]

Graphic MMU LUT entry x high

Offset: 0x2c7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [912]

Graphic MMU LUT entry x low

Offset: 0x2c80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [912]

Graphic MMU LUT entry x high

Offset: 0x2c84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [913]

Graphic MMU LUT entry x low

Offset: 0x2c88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [913]

Graphic MMU LUT entry x high

Offset: 0x2c8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [914]

Graphic MMU LUT entry x low

Offset: 0x2c90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [914]

Graphic MMU LUT entry x high

Offset: 0x2c94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [915]

Graphic MMU LUT entry x low

Offset: 0x2c98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [915]

Graphic MMU LUT entry x high

Offset: 0x2c9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [916]

Graphic MMU LUT entry x low

Offset: 0x2ca0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [916]

Graphic MMU LUT entry x high

Offset: 0x2ca4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [917]

Graphic MMU LUT entry x low

Offset: 0x2ca8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [917]

Graphic MMU LUT entry x high

Offset: 0x2cac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [918]

Graphic MMU LUT entry x low

Offset: 0x2cb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [918]

Graphic MMU LUT entry x high

Offset: 0x2cb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [919]

Graphic MMU LUT entry x low

Offset: 0x2cb8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [919]

Graphic MMU LUT entry x high

Offset: 0x2cbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [920]

Graphic MMU LUT entry x low

Offset: 0x2cc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [920]

Graphic MMU LUT entry x high

Offset: 0x2cc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [921]

Graphic MMU LUT entry x low

Offset: 0x2cc8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [921]

Graphic MMU LUT entry x high

Offset: 0x2ccc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [922]

Graphic MMU LUT entry x low

Offset: 0x2cd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [922]

Graphic MMU LUT entry x high

Offset: 0x2cd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [923]

Graphic MMU LUT entry x low

Offset: 0x2cd8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [923]

Graphic MMU LUT entry x high

Offset: 0x2cdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [924]

Graphic MMU LUT entry x low

Offset: 0x2ce0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [924]

Graphic MMU LUT entry x high

Offset: 0x2ce4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [925]

Graphic MMU LUT entry x low

Offset: 0x2ce8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [925]

Graphic MMU LUT entry x high

Offset: 0x2cec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [926]

Graphic MMU LUT entry x low

Offset: 0x2cf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [926]

Graphic MMU LUT entry x high

Offset: 0x2cf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [927]

Graphic MMU LUT entry x low

Offset: 0x2cf8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [927]

Graphic MMU LUT entry x high

Offset: 0x2cfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [928]

Graphic MMU LUT entry x low

Offset: 0x2d00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [928]

Graphic MMU LUT entry x high

Offset: 0x2d04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [929]

Graphic MMU LUT entry x low

Offset: 0x2d08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [929]

Graphic MMU LUT entry x high

Offset: 0x2d0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [930]

Graphic MMU LUT entry x low

Offset: 0x2d10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [930]

Graphic MMU LUT entry x high

Offset: 0x2d14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [931]

Graphic MMU LUT entry x low

Offset: 0x2d18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [931]

Graphic MMU LUT entry x high

Offset: 0x2d1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [932]

Graphic MMU LUT entry x low

Offset: 0x2d20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [932]

Graphic MMU LUT entry x high

Offset: 0x2d24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [933]

Graphic MMU LUT entry x low

Offset: 0x2d28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [933]

Graphic MMU LUT entry x high

Offset: 0x2d2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [934]

Graphic MMU LUT entry x low

Offset: 0x2d30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [934]

Graphic MMU LUT entry x high

Offset: 0x2d34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [935]

Graphic MMU LUT entry x low

Offset: 0x2d38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [935]

Graphic MMU LUT entry x high

Offset: 0x2d3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [936]

Graphic MMU LUT entry x low

Offset: 0x2d40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [936]

Graphic MMU LUT entry x high

Offset: 0x2d44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [937]

Graphic MMU LUT entry x low

Offset: 0x2d48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [937]

Graphic MMU LUT entry x high

Offset: 0x2d4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [938]

Graphic MMU LUT entry x low

Offset: 0x2d50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [938]

Graphic MMU LUT entry x high

Offset: 0x2d54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [939]

Graphic MMU LUT entry x low

Offset: 0x2d58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [939]

Graphic MMU LUT entry x high

Offset: 0x2d5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [940]

Graphic MMU LUT entry x low

Offset: 0x2d60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [940]

Graphic MMU LUT entry x high

Offset: 0x2d64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [941]

Graphic MMU LUT entry x low

Offset: 0x2d68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [941]

Graphic MMU LUT entry x high

Offset: 0x2d6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [942]

Graphic MMU LUT entry x low

Offset: 0x2d70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [942]

Graphic MMU LUT entry x high

Offset: 0x2d74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [943]

Graphic MMU LUT entry x low

Offset: 0x2d78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [943]

Graphic MMU LUT entry x high

Offset: 0x2d7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [944]

Graphic MMU LUT entry x low

Offset: 0x2d80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [944]

Graphic MMU LUT entry x high

Offset: 0x2d84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [945]

Graphic MMU LUT entry x low

Offset: 0x2d88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [945]

Graphic MMU LUT entry x high

Offset: 0x2d8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [946]

Graphic MMU LUT entry x low

Offset: 0x2d90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [946]

Graphic MMU LUT entry x high

Offset: 0x2d94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [947]

Graphic MMU LUT entry x low

Offset: 0x2d98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [947]

Graphic MMU LUT entry x high

Offset: 0x2d9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [948]

Graphic MMU LUT entry x low

Offset: 0x2da0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [948]

Graphic MMU LUT entry x high

Offset: 0x2da4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [949]

Graphic MMU LUT entry x low

Offset: 0x2da8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [949]

Graphic MMU LUT entry x high

Offset: 0x2dac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [950]

Graphic MMU LUT entry x low

Offset: 0x2db0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [950]

Graphic MMU LUT entry x high

Offset: 0x2db4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [951]

Graphic MMU LUT entry x low

Offset: 0x2db8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [951]

Graphic MMU LUT entry x high

Offset: 0x2dbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [952]

Graphic MMU LUT entry x low

Offset: 0x2dc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [952]

Graphic MMU LUT entry x high

Offset: 0x2dc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [953]

Graphic MMU LUT entry x low

Offset: 0x2dc8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [953]

Graphic MMU LUT entry x high

Offset: 0x2dcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [954]

Graphic MMU LUT entry x low

Offset: 0x2dd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [954]

Graphic MMU LUT entry x high

Offset: 0x2dd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [955]

Graphic MMU LUT entry x low

Offset: 0x2dd8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [955]

Graphic MMU LUT entry x high

Offset: 0x2ddc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [956]

Graphic MMU LUT entry x low

Offset: 0x2de0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [956]

Graphic MMU LUT entry x high

Offset: 0x2de4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [957]

Graphic MMU LUT entry x low

Offset: 0x2de8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [957]

Graphic MMU LUT entry x high

Offset: 0x2dec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [958]

Graphic MMU LUT entry x low

Offset: 0x2df0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [958]

Graphic MMU LUT entry x high

Offset: 0x2df4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [959]

Graphic MMU LUT entry x low

Offset: 0x2df8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [959]

Graphic MMU LUT entry x high

Offset: 0x2dfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [960]

Graphic MMU LUT entry x low

Offset: 0x2e00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [960]

Graphic MMU LUT entry x high

Offset: 0x2e04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [961]

Graphic MMU LUT entry x low

Offset: 0x2e08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [961]

Graphic MMU LUT entry x high

Offset: 0x2e0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [962]

Graphic MMU LUT entry x low

Offset: 0x2e10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [962]

Graphic MMU LUT entry x high

Offset: 0x2e14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [963]

Graphic MMU LUT entry x low

Offset: 0x2e18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [963]

Graphic MMU LUT entry x high

Offset: 0x2e1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [964]

Graphic MMU LUT entry x low

Offset: 0x2e20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [964]

Graphic MMU LUT entry x high

Offset: 0x2e24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [965]

Graphic MMU LUT entry x low

Offset: 0x2e28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [965]

Graphic MMU LUT entry x high

Offset: 0x2e2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [966]

Graphic MMU LUT entry x low

Offset: 0x2e30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [966]

Graphic MMU LUT entry x high

Offset: 0x2e34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [967]

Graphic MMU LUT entry x low

Offset: 0x2e38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [967]

Graphic MMU LUT entry x high

Offset: 0x2e3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [968]

Graphic MMU LUT entry x low

Offset: 0x2e40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [968]

Graphic MMU LUT entry x high

Offset: 0x2e44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [969]

Graphic MMU LUT entry x low

Offset: 0x2e48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [969]

Graphic MMU LUT entry x high

Offset: 0x2e4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [970]

Graphic MMU LUT entry x low

Offset: 0x2e50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [970]

Graphic MMU LUT entry x high

Offset: 0x2e54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [971]

Graphic MMU LUT entry x low

Offset: 0x2e58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [971]

Graphic MMU LUT entry x high

Offset: 0x2e5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [972]

Graphic MMU LUT entry x low

Offset: 0x2e60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [972]

Graphic MMU LUT entry x high

Offset: 0x2e64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [973]

Graphic MMU LUT entry x low

Offset: 0x2e68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [973]

Graphic MMU LUT entry x high

Offset: 0x2e6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [974]

Graphic MMU LUT entry x low

Offset: 0x2e70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [974]

Graphic MMU LUT entry x high

Offset: 0x2e74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [975]

Graphic MMU LUT entry x low

Offset: 0x2e78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [975]

Graphic MMU LUT entry x high

Offset: 0x2e7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [976]

Graphic MMU LUT entry x low

Offset: 0x2e80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [976]

Graphic MMU LUT entry x high

Offset: 0x2e84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [977]

Graphic MMU LUT entry x low

Offset: 0x2e88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [977]

Graphic MMU LUT entry x high

Offset: 0x2e8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [978]

Graphic MMU LUT entry x low

Offset: 0x2e90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [978]

Graphic MMU LUT entry x high

Offset: 0x2e94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [979]

Graphic MMU LUT entry x low

Offset: 0x2e98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [979]

Graphic MMU LUT entry x high

Offset: 0x2e9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [980]

Graphic MMU LUT entry x low

Offset: 0x2ea0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [980]

Graphic MMU LUT entry x high

Offset: 0x2ea4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [981]

Graphic MMU LUT entry x low

Offset: 0x2ea8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [981]

Graphic MMU LUT entry x high

Offset: 0x2eac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [982]

Graphic MMU LUT entry x low

Offset: 0x2eb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [982]

Graphic MMU LUT entry x high

Offset: 0x2eb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [983]

Graphic MMU LUT entry x low

Offset: 0x2eb8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [983]

Graphic MMU LUT entry x high

Offset: 0x2ebc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [984]

Graphic MMU LUT entry x low

Offset: 0x2ec0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [984]

Graphic MMU LUT entry x high

Offset: 0x2ec4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [985]

Graphic MMU LUT entry x low

Offset: 0x2ec8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [985]

Graphic MMU LUT entry x high

Offset: 0x2ecc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [986]

Graphic MMU LUT entry x low

Offset: 0x2ed0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [986]

Graphic MMU LUT entry x high

Offset: 0x2ed4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [987]

Graphic MMU LUT entry x low

Offset: 0x2ed8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [987]

Graphic MMU LUT entry x high

Offset: 0x2edc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [988]

Graphic MMU LUT entry x low

Offset: 0x2ee0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [988]

Graphic MMU LUT entry x high

Offset: 0x2ee4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [989]

Graphic MMU LUT entry x low

Offset: 0x2ee8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [989]

Graphic MMU LUT entry x high

Offset: 0x2eec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [990]

Graphic MMU LUT entry x low

Offset: 0x2ef0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [990]

Graphic MMU LUT entry x high

Offset: 0x2ef4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [991]

Graphic MMU LUT entry x low

Offset: 0x2ef8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [991]

Graphic MMU LUT entry x high

Offset: 0x2efc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [992]

Graphic MMU LUT entry x low

Offset: 0x2f00, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [992]

Graphic MMU LUT entry x high

Offset: 0x2f04, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [993]

Graphic MMU LUT entry x low

Offset: 0x2f08, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [993]

Graphic MMU LUT entry x high

Offset: 0x2f0c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [994]

Graphic MMU LUT entry x low

Offset: 0x2f10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [994]

Graphic MMU LUT entry x high

Offset: 0x2f14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [995]

Graphic MMU LUT entry x low

Offset: 0x2f18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [995]

Graphic MMU LUT entry x high

Offset: 0x2f1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [996]

Graphic MMU LUT entry x low

Offset: 0x2f20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [996]

Graphic MMU LUT entry x high

Offset: 0x2f24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [997]

Graphic MMU LUT entry x low

Offset: 0x2f28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [997]

Graphic MMU LUT entry x high

Offset: 0x2f2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [998]

Graphic MMU LUT entry x low

Offset: 0x2f30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [998]

Graphic MMU LUT entry x high

Offset: 0x2f34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [999]

Graphic MMU LUT entry x low

Offset: 0x2f38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [999]

Graphic MMU LUT entry x high

Offset: 0x2f3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1000]

Graphic MMU LUT entry x low

Offset: 0x2f40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1000]

Graphic MMU LUT entry x high

Offset: 0x2f44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1001]

Graphic MMU LUT entry x low

Offset: 0x2f48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1001]

Graphic MMU LUT entry x high

Offset: 0x2f4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1002]

Graphic MMU LUT entry x low

Offset: 0x2f50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1002]

Graphic MMU LUT entry x high

Offset: 0x2f54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1003]

Graphic MMU LUT entry x low

Offset: 0x2f58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1003]

Graphic MMU LUT entry x high

Offset: 0x2f5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1004]

Graphic MMU LUT entry x low

Offset: 0x2f60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1004]

Graphic MMU LUT entry x high

Offset: 0x2f64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1005]

Graphic MMU LUT entry x low

Offset: 0x2f68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1005]

Graphic MMU LUT entry x high

Offset: 0x2f6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1006]

Graphic MMU LUT entry x low

Offset: 0x2f70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1006]

Graphic MMU LUT entry x high

Offset: 0x2f74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1007]

Graphic MMU LUT entry x low

Offset: 0x2f78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1007]

Graphic MMU LUT entry x high

Offset: 0x2f7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1008]

Graphic MMU LUT entry x low

Offset: 0x2f80, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1008]

Graphic MMU LUT entry x high

Offset: 0x2f84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1009]

Graphic MMU LUT entry x low

Offset: 0x2f88, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1009]

Graphic MMU LUT entry x high

Offset: 0x2f8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1010]

Graphic MMU LUT entry x low

Offset: 0x2f90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1010]

Graphic MMU LUT entry x high

Offset: 0x2f94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1011]

Graphic MMU LUT entry x low

Offset: 0x2f98, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1011]

Graphic MMU LUT entry x high

Offset: 0x2f9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1012]

Graphic MMU LUT entry x low

Offset: 0x2fa0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1012]

Graphic MMU LUT entry x high

Offset: 0x2fa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1013]

Graphic MMU LUT entry x low

Offset: 0x2fa8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1013]

Graphic MMU LUT entry x high

Offset: 0x2fac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1014]

Graphic MMU LUT entry x low

Offset: 0x2fb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1014]

Graphic MMU LUT entry x high

Offset: 0x2fb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1015]

Graphic MMU LUT entry x low

Offset: 0x2fb8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1015]

Graphic MMU LUT entry x high

Offset: 0x2fbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1016]

Graphic MMU LUT entry x low

Offset: 0x2fc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1016]

Graphic MMU LUT entry x high

Offset: 0x2fc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1017]

Graphic MMU LUT entry x low

Offset: 0x2fc8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1017]

Graphic MMU LUT entry x high

Offset: 0x2fcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1018]

Graphic MMU LUT entry x low

Offset: 0x2fd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1018]

Graphic MMU LUT entry x high

Offset: 0x2fd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1019]

Graphic MMU LUT entry x low

Offset: 0x2fd8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1019]

Graphic MMU LUT entry x high

Offset: 0x2fdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1020]

Graphic MMU LUT entry x low

Offset: 0x2fe0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1020]

Graphic MMU LUT entry x high

Offset: 0x2fe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1021]

Graphic MMU LUT entry x low

Offset: 0x2fe8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1021]

Graphic MMU LUT entry x high

Offset: 0x2fec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1022]

Graphic MMU LUT entry x low

Offset: 0x2ff0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1022]

Graphic MMU LUT entry x high

Offset: 0x2ff4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

LUTL [1023]

Graphic MMU LUT entry x low

Offset: 0x2ff8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FVB
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

FVB

Bits 8-15: First Valid Block.

LVB

Bits 16-23: Last Valid Block.

LUTH [1023]

Graphic MMU LUT entry x high

Offset: 0x2ffc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LO
rw
Toggle fields

LO

Bits 4-21: Line offset.

GPIOA

0x48000000: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x2c ASCR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xA8000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

ASCR

GPIO port analog switch control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC15
rw 		ASC14
rw 		ASC13
rw 		ASC12
rw 		ASC11
rw 		ASC10
rw 		ASC9
rw 		ASC8
rw 		ASC7
rw 		ASC6
rw 		ASC5
rw 		ASC4
rw 		ASC3
rw 		ASC2
rw 		ASC1
rw 		ASC0
rw
Toggle fields

ASC0

Bit 0: Port analog switch control.

ASC1

Bit 1: Port analog switch control.

ASC2

Bit 2: Port analog switch control.

ASC3

Bit 3: Port analog switch control.

ASC4

Bit 4: Port analog switch control.

ASC5

Bit 5: Port analog switch control.

ASC6

Bit 6: Port analog switch control.

ASC7

Bit 7: Port analog switch control.

ASC8

Bit 8: Port analog switch control.

ASC9

Bit 9: Port analog switch control.

ASC10

Bit 10: Port analog switch control.

ASC11

Bit 11: Port analog switch control.

ASC12

Bit 12: Port analog switch control.

ASC13

Bit 13: Port analog switch control.

ASC14

Bit 14: Port analog switch control.

ASC15

Bit 15: Port analog switch control.

GPIOB

0x48000400: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x2c ASCR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000280, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x000000C0, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

ASCR

GPIO port analog switch control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC15
rw 		ASC14
rw 		ASC13
rw 		ASC12
rw 		ASC11
rw 		ASC10
rw 		ASC9
rw 		ASC8
rw 		ASC7
rw 		ASC6
rw 		ASC5
rw 		ASC4
rw 		ASC3
rw 		ASC2
rw 		ASC1
rw 		ASC0
rw
Toggle fields

ASC0

Bit 0: Port analog switch control.

ASC1

Bit 1: Port analog switch control.

ASC2

Bit 2: Port analog switch control.

ASC3

Bit 3: Port analog switch control.

ASC4

Bit 4: Port analog switch control.

ASC5

Bit 5: Port analog switch control.

ASC6

Bit 6: Port analog switch control.

ASC7

Bit 7: Port analog switch control.

ASC8

Bit 8: Port analog switch control.

ASC9

Bit 9: Port analog switch control.

ASC10

Bit 10: Port analog switch control.

ASC11

Bit 11: Port analog switch control.

ASC12

Bit 12: Port analog switch control.

ASC13

Bit 13: Port analog switch control.

ASC14

Bit 14: Port analog switch control.

ASC15

Bit 15: Port analog switch control.

GPIOC

0x48000800: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x2c ASCR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

ASCR

GPIO port analog switch control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC15
rw 		ASC14
rw 		ASC13
rw 		ASC12
rw 		ASC11
rw 		ASC10
rw 		ASC9
rw 		ASC8
rw 		ASC7
rw 		ASC6
rw 		ASC5
rw 		ASC4
rw 		ASC3
rw 		ASC2
rw 		ASC1
rw 		ASC0
rw
Toggle fields

ASC0

Bit 0: Port analog switch control.

ASC1

Bit 1: Port analog switch control.

ASC2

Bit 2: Port analog switch control.

ASC3

Bit 3: Port analog switch control.

ASC4

Bit 4: Port analog switch control.

ASC5

Bit 5: Port analog switch control.

ASC6

Bit 6: Port analog switch control.

ASC7

Bit 7: Port analog switch control.

ASC8

Bit 8: Port analog switch control.

ASC9

Bit 9: Port analog switch control.

ASC10

Bit 10: Port analog switch control.

ASC11

Bit 11: Port analog switch control.

ASC12

Bit 12: Port analog switch control.

ASC13

Bit 13: Port analog switch control.

ASC14

Bit 14: Port analog switch control.

ASC15

Bit 15: Port analog switch control.

GPIOD

0x48000c00: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x2c ASCR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

ASCR

GPIO port analog switch control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC15
rw 		ASC14
rw 		ASC13
rw 		ASC12
rw 		ASC11
rw 		ASC10
rw 		ASC9
rw 		ASC8
rw 		ASC7
rw 		ASC6
rw 		ASC5
rw 		ASC4
rw 		ASC3
rw 		ASC2
rw 		ASC1
rw 		ASC0
rw
Toggle fields

ASC0

Bit 0: Port analog switch control.

ASC1

Bit 1: Port analog switch control.

ASC2

Bit 2: Port analog switch control.

ASC3

Bit 3: Port analog switch control.

ASC4

Bit 4: Port analog switch control.

ASC5

Bit 5: Port analog switch control.

ASC6

Bit 6: Port analog switch control.

ASC7

Bit 7: Port analog switch control.

ASC8

Bit 8: Port analog switch control.

ASC9

Bit 9: Port analog switch control.

ASC10

Bit 10: Port analog switch control.

ASC11

Bit 11: Port analog switch control.

ASC12

Bit 12: Port analog switch control.

ASC13

Bit 13: Port analog switch control.

ASC14

Bit 14: Port analog switch control.

ASC15

Bit 15: Port analog switch control.

GPIOE

0x48001000: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x2c ASCR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

ASCR

GPIO port analog switch control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC15
rw 		ASC14
rw 		ASC13
rw 		ASC12
rw 		ASC11
rw 		ASC10
rw 		ASC9
rw 		ASC8
rw 		ASC7
rw 		ASC6
rw 		ASC5
rw 		ASC4
rw 		ASC3
rw 		ASC2
rw 		ASC1
rw 		ASC0
rw
Toggle fields

ASC0

Bit 0: Port analog switch control.

ASC1

Bit 1: Port analog switch control.

ASC2

Bit 2: Port analog switch control.

ASC3

Bit 3: Port analog switch control.

ASC4

Bit 4: Port analog switch control.

ASC5

Bit 5: Port analog switch control.

ASC6

Bit 6: Port analog switch control.

ASC7

Bit 7: Port analog switch control.

ASC8

Bit 8: Port analog switch control.

ASC9

Bit 9: Port analog switch control.

ASC10

Bit 10: Port analog switch control.

ASC11

Bit 11: Port analog switch control.

ASC12

Bit 12: Port analog switch control.

ASC13

Bit 13: Port analog switch control.

ASC14

Bit 14: Port analog switch control.

ASC15

Bit 15: Port analog switch control.

GPIOF

0x48001400: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x2c ASCR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

ASCR

GPIO port analog switch control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC15
rw 		ASC14
rw 		ASC13
rw 		ASC12
rw 		ASC11
rw 		ASC10
rw 		ASC9
rw 		ASC8
rw 		ASC7
rw 		ASC6
rw 		ASC5
rw 		ASC4
rw 		ASC3
rw 		ASC2
rw 		ASC1
rw 		ASC0
rw
Toggle fields

ASC0

Bit 0: Port analog switch control.

ASC1

Bit 1: Port analog switch control.

ASC2

Bit 2: Port analog switch control.

ASC3

Bit 3: Port analog switch control.

ASC4

Bit 4: Port analog switch control.

ASC5

Bit 5: Port analog switch control.

ASC6

Bit 6: Port analog switch control.

ASC7

Bit 7: Port analog switch control.

ASC8

Bit 8: Port analog switch control.

ASC9

Bit 9: Port analog switch control.

ASC10

Bit 10: Port analog switch control.

ASC11

Bit 11: Port analog switch control.

ASC12

Bit 12: Port analog switch control.

ASC13

Bit 13: Port analog switch control.

ASC14

Bit 14: Port analog switch control.

ASC15

Bit 15: Port analog switch control.

GPIOG

0x48001800: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x2c ASCR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

ASCR

GPIO port analog switch control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC15
rw 		ASC14
rw 		ASC13
rw 		ASC12
rw 		ASC11
rw 		ASC10
rw 		ASC9
rw 		ASC8
rw 		ASC7
rw 		ASC6
rw 		ASC5
rw 		ASC4
rw 		ASC3
rw 		ASC2
rw 		ASC1
rw 		ASC0
rw
Toggle fields

ASC0

Bit 0: Port analog switch control.

ASC1

Bit 1: Port analog switch control.

ASC2

Bit 2: Port analog switch control.

ASC3

Bit 3: Port analog switch control.

ASC4

Bit 4: Port analog switch control.

ASC5

Bit 5: Port analog switch control.

ASC6

Bit 6: Port analog switch control.

ASC7

Bit 7: Port analog switch control.

ASC8

Bit 8: Port analog switch control.

ASC9

Bit 9: Port analog switch control.

ASC10

Bit 10: Port analog switch control.

ASC11

Bit 11: Port analog switch control.

ASC12

Bit 12: Port analog switch control.

ASC13

Bit 13: Port analog switch control.

ASC14

Bit 14: Port analog switch control.

ASC15

Bit 15: Port analog switch control.

GPIOH

0x48001c00: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x2c ASCR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

ASCR

GPIO port analog switch control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC15
rw 		ASC14
rw 		ASC13
rw 		ASC12
rw 		ASC11
rw 		ASC10
rw 		ASC9
rw 		ASC8
rw 		ASC7
rw 		ASC6
rw 		ASC5
rw 		ASC4
rw 		ASC3
rw 		ASC2
rw 		ASC1
rw 		ASC0
rw
Toggle fields

ASC0

Bit 0: Port analog switch control.

ASC1

Bit 1: Port analog switch control.

ASC2

Bit 2: Port analog switch control.

ASC3

Bit 3: Port analog switch control.

ASC4

Bit 4: Port analog switch control.

ASC5

Bit 5: Port analog switch control.

ASC6

Bit 6: Port analog switch control.

ASC7

Bit 7: Port analog switch control.

ASC8

Bit 8: Port analog switch control.

ASC9

Bit 9: Port analog switch control.

ASC10

Bit 10: Port analog switch control.

ASC11

Bit 11: Port analog switch control.

ASC12

Bit 12: Port analog switch control.

ASC13

Bit 13: Port analog switch control.

ASC14

Bit 14: Port analog switch control.

ASC15

Bit 15: Port analog switch control.

GPIOI

0x48002000: General-purpose I/Os

177/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw 		MODER[14]
rw 		MODER[13]
rw 		MODER[12]
rw 		MODER[11]
rw 		MODER[10]
rw 		MODER[9]
rw 		MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw 		MODER[6]
rw 		MODER[5]
rw 		MODER[4]
rw 		MODER[3]
rw 		MODER[2]
rw 		MODER[1]
rw 		MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT[15]
rw 		OT[14]
rw 		OT[13]
rw 		OT[12]
rw 		OT[11]
rw 		OT[10]
rw 		OT[9]
rw 		OT[8]
rw 		OT[7]
rw 		OT[6]
rw 		OT[5]
rw 		OT[4]
rw 		OT[3]
rw 		OT[2]
rw 		OT[1]
rw 		OT[0]
rw
Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR[15]
rw 		OSPEEDR[14]
rw 		OSPEEDR[13]
rw 		OSPEEDR[12]
rw 		OSPEEDR[11]
rw 		OSPEEDR[10]
rw 		OSPEEDR[9]
rw 		OSPEEDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR[7]
rw 		OSPEEDR[6]
rw 		OSPEEDR[5]
rw 		OSPEEDR[4]
rw 		OSPEEDR[3]
rw 		OSPEEDR[2]
rw 		OSPEEDR[1]
rw 		OSPEEDR[0]
rw
Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw 		PUPDR[14]
rw 		PUPDR[13]
rw 		PUPDR[12]
rw 		PUPDR[11]
rw 		PUPDR[10]
rw 		PUPDR[9]
rw 		PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw 		PUPDR[6]
rw 		PUPDR[5]
rw 		PUPDR[4]
rw 		PUPDR[3]
rw 		PUPDR[2]
rw 		PUPDR[1]
rw 		PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR[15]
r 		IDR[14]
r 		IDR[13]
r 		IDR[12]
r 		IDR[11]
r 		IDR[10]
r 		IDR[9]
r 		IDR[8]
r 		IDR[7]
r 		IDR[6]
r 		IDR[5]
r 		IDR[4]
r 		IDR[3]
r 		IDR[2]
r 		IDR[1]
r 		IDR[0]
r
Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR[15]
rw 		ODR[14]
rw 		ODR[13]
rw 		ODR[12]
rw 		ODR[11]
rw 		ODR[10]
rw 		ODR[9]
rw 		ODR[8]
rw 		ODR[7]
rw 		ODR[6]
rw 		ODR[5]
rw 		ODR[4]
rw 		ODR[3]
rw 		ODR[2]
rw 		ODR[1]
rw 		ODR[0]
rw
Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS[15]
w 		BS[14]
w 		BS[13]
w 		BS[12]
w 		BS[11]
w 		BS[10]
w 		BS[9]
w 		BS[8]
w 		BS[7]
w 		BS[6]
w 		BS[5]
w 		BS[4]
w 		BS[3]
w 		BS[2]
w 		BS[1]
w 		BS[0]
w
Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw 		LCK[14]
rw 		LCK[13]
rw 		LCK[12]
rw 		LCK[11]
rw 		LCK[10]
rw 		LCK[9]
rw 		LCK[8]
rw 		LCK[7]
rw 		LCK[6]
rw 		LCK[5]
rw 		LCK[4]
rw 		LCK[3]
rw 		LCK[2]
rw 		LCK[1]
rw 		LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[L7]
rw 		AFR[L6]
rw 		AFR[L5]
rw 		AFR[L4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[L3]
rw 		AFR[L2]
rw 		AFR[L1]
rw 		AFR[L0]
rw
Toggle fields

AFR[L0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[L7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[H15]
rw 		AFR[H14]
rw 		AFR[H13]
rw 		AFR[H12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[H11]
rw 		AFR[H10]
rw 		AFR[H9]
rw 		AFR[H8]
rw
Toggle fields

AFR[H8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[H15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR[15]
w 		BR[14]
w 		BR[13]
w 		BR[12]
w 		BR[11]
w 		BR[10]
w 		BR[9]
w 		BR[8]
w 		BR[7]
w 		BR[6]
w 		BR[5]
w 		BR[4]
w 		BR[3]
w 		BR[2]
w 		BR[1]
w 		BR[0]
w
Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

HASH

0x50060400: Hash processor

13/82 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HR[0]
0x20 IMR
0x24 SR
0xf8 CSR[0]
0xfc CSR[1]
0x100 CSR[2]
0x104 CSR[3]
0x108 CSR[4]
0x10c CSR[5]
0x110 CSR[6]
0x114 CSR[7]
0x118 CSR[8]
0x11c CSR[9]
0x120 CSR[10]
0x124 CSR[11]
0x128 CSR[12]
0x12c CSR[13]
0x130 CSR[14]
0x134 CSR[15]
0x138 CSR[16]
0x13c CSR[17]
0x140 CSR[18]
0x144 CSR[19]
0x148 CSR[20]
0x14c CSR[21]
0x150 CSR[22]
0x154 CSR[23]
0x158 CSR[24]
0x15c CSR[25]
0x160 CSR[26]
0x164 CSR[27]
0x168 CSR[28]
0x16c CSR[29]
0x170 CSR[30]
0x174 CSR[31]
0x178 CSR[32]
0x17c CSR[33]
0x180 CSR[34]
0x184 CSR[35]
0x188 CSR[36]
0x18c CSR[37]
0x190 CSR[38]
0x194 CSR[39]
0x198 CSR[40]
0x19c CSR[41]
0x1a0 CSR[42]
0x1a4 CSR[43]
0x1a8 CSR[44]
0x1ac CSR[45]
0x1b0 CSR[46]
0x1b4 CSR[47]
0x1b8 CSR[48]
0x1bc CSR[49]
0x1c0 CSR[50]
0x1c4 CSR[51]
0x1c8 CSR[52]
0x1cc CSR[53]
0x310 HASH_HR[0]
0x314 HASH_HR[1]
0x318 HASH_HR[2]
0x31c HASH_HR[3]
0x320 HASH_HR[4]
0x324 HASH_HR[5]
0x328 HASH_HR[6]
0x32c HASH_HR[7]
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw 		LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAT
rw 		DINNE
r 		NBW
r 		ALGO0
rw 		MODE
rw 		DATATYPE
rw 		DMAE
rw 		INIT
w
Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

ALGO0

Bit 7: Algorithm selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO1

Bit 18: ALGO.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
w 		NBLW
rw
Toggle fields

NBLW

Bits 0-4: Number of valid bits in the last word of the message.

DCAL

Bit 8: Digest calculation.

HR[0]

digest registers

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

IMR

interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw 		DINIE
rw
Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		DMAS
r 		DCIS
rw 		DINIS
rw
Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

CSR[0]

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[1]

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[2]

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[3]

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[4]

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[5]

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[6]

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[7]

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[8]

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[9]

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[10]

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[11]

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[12]

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[13]

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[14]

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[15]

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[16]

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[17]

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[18]

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[19]

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[20]

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[21]

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[22]

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[23]

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[24]

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[25]

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[26]

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[27]

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[28]

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[29]

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[30]

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[31]

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[32]

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[33]

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[34]

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[35]

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[36]

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[37]

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[38]

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[39]

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[40]

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[41]

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[42]

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[43]

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[44]

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[45]

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[46]

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[47]

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[48]

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[49]

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[50]

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[51]

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[52]

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

CSR[53]

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle fields

CSR

Bits 0-31: CSR0.

HASH_HR[0]

HASH digest register 0

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[1]

HASH digest register 1

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[2]

HASH digest register 2

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[3]

HASH digest register 3

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[4]

HASH digest register 4

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[5]

HASH digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[6]

HASH digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

HASH_HR[7]

HASH digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle fields

H

Bits 0-31: H0.

I2C1

0x40005400: Inter-integrated circuit

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2C2

0x40005800: Inter-integrated circuit

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2C3

0x40005c00: Inter-integrated circuit

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

I2C4

0x40008400: Inter-integrated circuit

76/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0x0-0x3ff

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0x0-0xff

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

Allowed values: 0x0-0x3ff

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

Allowed values: 0x0-0x7f

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0x0-0xff

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0x0-0xff

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0x0-0xf

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0x0-0xf

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0x0-0xf

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0x0-0xfff

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0x0-0xfff

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0x0-0x7f

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0x0-0xff

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0x0-0xff

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0x0-0xff

IWDG

0x40003000: Independent watchdog

7/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 KR
0x4 PR
0x8 RLR
0xc SR
0x10 WINR
Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0x0-0xfff

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

Allowed values: 0x0-0xfff

LPTIM1

0x40007c00: Low power timer

8/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

LPTIM2

0x40009400: Low power timer

8/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

LPUART1

0x40008000: Universal synchronous asynchronous receiver transmitter

72/73 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		STOP
rw 		CLKEN
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		HDSEL
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-19: BRR.

Allowed values: 0x0-0xfffff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFRQ
w 		MMRQ
w 		SBKRQ
w
Toggle fields

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r 		CTSIF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: clock prescaler.

LTCD

0x40016800: Liquid crystal display controller

13/93 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x8 SSCR
0xc BPCR
0x10 AWCR
0x14 TWCR
0x18 GCR
0x24 SRCR
0x2c BCCR
0x34 IER
0x38 ISR
0x3c ICR
0x40 LIPCR
0x44 CPSR
0x48 CDSR
0x84 L1CR
0x88 L1WHPCR
0x8c L1WVPCR
0x90 L1CKCR
0x94 L1PFCR
0x98 L1CACR
0x9c L1DCCR
0xa0 L1BFCR
0xac L1CFBAR
0xb0 L1CFBLR
0xb4 L1CFBLNR
0xc4 L1CLUTWR
0x104 L2CR
0x108 L2WHPCR
0x10c L2WVPCR
0x110 L2CKCR
0x114 L2PFCR
0x118 L2CACR
0x11c L2DCCR
0x124 L2BFCR
0x12c L2CFBAR
0x130 L2CFBLR
0x134 L2CFBLNR
0x144 L2CLUTWR
Toggle registers

SSCR

LTDC Synchronization Size Configuration Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSH
rw
Toggle fields

VSH

Bits 0-10: Vertical Synchronization Height (in units of horizontal scan line).

HSW

Bits 16-27: Horizontal Synchronization Width (in units of pixel clock period).

BPCR

LTDC Back Porch Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AVBP
rw
Toggle fields

AVBP

Bits 0-10: Accumulated Vertical back porch (in units of horizontal scan line).

AHBP

Bits 16-27: Accumulated Horizontal back porch (in units of pixel clock period).

AWCR

LTDC Active Width Configuration Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AAW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AAH
rw
Toggle fields

AAH

Bits 0-10: Accumulated Active Height (in units of horizontal scan line).

AAW

Bits 16-27: Accumulated Active Width (in units of pixel clock period).

TWCR

LTDC Total Width Configuration Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOTALW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOTALH
rw
Toggle fields

TOTALH

Bits 0-10: Total Height (in units of horizontal scan line).

TOTALW

Bits 16-27: Total Width (in units of pixel clock period).

GCR

LTDC Global Control Register

Offset: 0x18, size: 32, reset: 0x00002220, access: Unspecified

3/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSPOL
rw 		VSPOL
rw 		DEPOL
rw 		PCPOL
rw 		DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRW
r 		DGW
r 		DBW
r 		LTDCEN
rw
Toggle fields

LTDCEN

Bit 0: LCD-TFT controller enable bit.

DBW

Bits 4-6: Dither Blue Width.

DGW

Bits 8-10: Dither Green Width.

DRW

Bits 12-14: Dither Red Width.

DEN

Bit 16: Dither Enable.

PCPOL

Bit 28: Pixel Clock Polarity.

DEPOL

Bit 29: Not Data Enable Polarity.

VSPOL

Bit 30: Vertical Synchronization Polarity.

HSPOL

Bit 31: Horizontal Synchronization Polarity.

SRCR

LTDC Shadow Reload Configuration Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBR
rw 		IMR
rw
Toggle fields

IMR

Bit 0: Immediate Reload.

VBR

Bit 1: Vertical Blanking Reload.

BCCR

LTDC Background Color Configuration Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCGREEN
rw 		BCBLUE
rw
Toggle fields

BCBLUE

Bits 0-7: Background Color Blue value.

BCGREEN

Bits 8-15: Background Color Green value.

BCRED

Bits 16-23: Background Color Red value.

IER

LTDC Interrupt Enable Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIE
rw 		TERRIE
rw 		FUIE
rw 		LIE
rw
Toggle fields

LIE

Bit 0: Line Interrupt Enable.

FUIE

Bit 1: FIFO Underrun Interrupt Enable.

TERRIE

Bit 2: Transfer Error Interrupt Enable.

RRIE

Bit 3: Register Reload interrupt enable.

ISR

LTDC Interrupt Status Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIF
r 		TERRIF
r 		FUIF
r 		LIF
r
Toggle fields

LIF

Bit 0: Line Interrupt flag.

FUIF

Bit 1: FIFO Underrun Interrupt flag.

TERRIF

Bit 2: Transfer Error interrupt flag.

RRIF

Bit 3: Register Reload Interrupt Flag.

ICR

LTDC Interrupt Clear Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRRIF
w 		CTERRIF
w 		CFUIF
w 		CLIF
w
Toggle fields

CLIF

Bit 0: Clears the Line Interrupt Flag.

CFUIF

Bit 1: Clears the FIFO Underrun Interrupt flag.

CTERRIF

Bit 2: Clears the Transfer Error Interrupt Flag.

CRRIF

Bit 3: Clears Register Reload Interrupt Flag.

LIPCR

LTDC Line Interrupt Position Configuration Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LIPOS
rw
Toggle fields

LIPOS

Bits 0-10: Line Interrupt Position.

CPSR

LTDC Current Position Status Register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CXPOS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYPOS
r
Toggle fields

CYPOS

Bits 0-15: Current Y Position.

CXPOS

Bits 16-31: Current X Position.

CDSR

LTDC Current Display Status Register

Offset: 0x48, size: 32, reset: 0x0000000F, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSYNCS
r 		VSYNCS
r 		HDES
r 		VDES
r
Toggle fields

VDES

Bit 0: Vertical Data Enable display Status.

HDES

Bit 1: Horizontal Data Enable display Status.

VSYNCS

Bit 2: Vertical Synchronization display Status.

HSYNCS

Bit 3: Horizontal Synchronization display Status.

L1CR

LTDC Layer Control Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLUTEN
rw 		COLKEN
rw 		LEN
rw
Toggle fields

LEN

Bit 0: Layer Enable.

COLKEN

Bit 1: Color Keying Enable.

CLUTEN

Bit 4: Color Look-Up Table Enable.

L1WHPCR

LTDC Layer Window Horizontal Position Configuration Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WHSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSTPOS
rw
Toggle fields

WHSTPOS

Bits 0-11: Window Horizontal Start Position.

WHSPPOS

Bits 16-27: Window Horizontal Stop Position.

L1WVPCR

LTDC Layer Window Vertical Position Configuration Register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVSTPOS
rw
Toggle fields

WVSTPOS

Bits 0-10: Window Vertical Start Position.

WVSPPOS

Bits 16-26: Window Vertical Stop Position.

L1CKCR

LTDC Layer Color Keying Configuration Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKGREEN
rw 		CKBLUE
rw
Toggle fields

CKBLUE

Bits 0-7: Color Key Blue value.

CKGREEN

Bits 8-15: Color Key Green value.

CKRED

Bits 16-23: Color Key Red value.

L1PFCR

LTDC Layer Pixel Format Configuration Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF
rw
Toggle fields

PF

Bits 0-2: Pixel Format.

L1CACR

LTDC Layer Constant Alpha Configuration Register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONSTA
rw
Toggle fields

CONSTA

Bits 0-7: Constant Alpha.

L1DCCR

LTDC Layer Default Color Configuration Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCALPHA
rw 		DCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCGREEN
rw 		DCBLUE
rw
Toggle fields

DCBLUE

Bits 0-7: Default Color Blue.

DCGREEN

Bits 8-15: Default Color Green.

DCRED

Bits 16-23: Default Color Red.

DCALPHA

Bits 24-31: Default Color Alpha.

L1BFCR

LTDC Layer Blending Factors Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BF1
rw 		BF2
rw
Toggle fields

BF2

Bits 0-2: Blending Factor 2.

BF1

Bits 8-10: Blending Factor 1.

L1CFBAR

LTDC Layer Color Frame Buffer Address Register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBADD
rw
Toggle fields

CFBADD

Bits 0-31: Color Frame Buffer Start Address.

L1CFBLR

LTDC Layer Color Frame Buffer Length Register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLL
rw
Toggle fields

CFBLL

Bits 0-12: Color Frame Buffer Line Length.

CFBP

Bits 16-28: Color Frame Buffer Pitch in bytes.

L1CFBLNR

LTDC Layer ColorFrame Buffer Line Number Register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLNBR
rw
Toggle fields

CFBLNBR

Bits 0-10: Frame Buffer Line Number.

L1CLUTWR

LTDC Layerx CLUT Write Register

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLUTADD
w 		RED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
w 		BLUE
w
Toggle fields

BLUE

Bits 0-7: Blue value.

GREEN

Bits 8-15: Green value.

RED

Bits 16-23: Red value.

CLUTADD

Bits 24-31: CLUT Address.

L2CR

LTDC Layer Control Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLUTEN
rw 		COLKEN
rw 		LEN
rw
Toggle fields

LEN

Bit 0: Layer Enable.

COLKEN

Bit 1: Color Keying Enable.

CLUTEN

Bit 4: Color Look-Up Table Enable.

L2WHPCR

LTDC Layerx Window Horizontal Position Configuration Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WHSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSTPOS
rw
Toggle fields

WHSTPOS

Bits 0-11: Window Horizontal Start Position.

WHSPPOS

Bits 16-27: Window Horizontal Stop Position.

L2WVPCR

LTDC Layer Window Vertical Position Configuration Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVSTPOS
rw
Toggle fields

WVSTPOS

Bits 0-10: Window Vertical Start Position.

WVSPPOS

Bits 16-26: Window Vertical Stop Position.

L2CKCR

LTDC Layer Color Keying Configuration Register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKGREEN
rw 		CKBLUE
rw
Toggle fields

CKBLUE

Bits 0-7: Color Key Blue value.

CKGREEN

Bits 8-15: Color Key Green value.

CKRED

Bits 16-23: Color Key Red value.

L2PFCR

LTDC Layer Pixel Format Configuration Register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF
rw
Toggle fields

PF

Bits 0-2: Pixel Format.

L2CACR

LTDC Layer Constant Alpha Configuration Register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONSTA
rw
Toggle fields

CONSTA

Bits 0-7: Constant Alpha.

L2DCCR

LTDC Layer Default Color Configuration Register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCALPHA
rw 		DCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCGREEN
rw 		DCBLUE
rw
Toggle fields

DCBLUE

Bits 0-7: Default Color Blue.

DCGREEN

Bits 8-15: Default Color Green.

DCRED

Bits 16-23: Default Color Red.

DCALPHA

Bits 24-31: Default Color Alpha.

L2BFCR

LTDC Layer Blending Factors Configuration Register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BF1
rw 		BF2
rw
Toggle fields

BF2

Bits 0-2: Blending Factor 2.

BF1

Bits 8-10: Blending Factor 1.

L2CFBAR

LTDC Layer Color Frame Buffer Address Register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBADD
rw
Toggle fields

CFBADD

Bits 0-31: Color Frame Buffer Start Address.

L2CFBLR

LTDC Layer Color Frame Buffer Length Register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLL
rw
Toggle fields

CFBLL

Bits 0-12: Color Frame Buffer Line Length.

CFBP

Bits 16-28: Color Frame Buffer Pitch in bytes.

L2CFBLNR

LTDC Layer ColorFrame Buffer Line Number Register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLNBR
rw
Toggle fields

CFBLNBR

Bits 0-10: Frame Buffer Line Number.

L2CLUTWR

LTDC Layerx CLUT Write Register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLUTADD
w 		RED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
w 		BLUE
w
Toggle fields

BLUE

Bits 0-7: Blue value.

GREEN

Bits 8-15: Green value.

RED

Bits 16-23: Red value.

CLUTADD

Bits 24-31: CLUT Address.

MPU

0xe000ed90: Memory protection unit

3/19 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TYPER
0x4 CTRL
0x8 RNR
0xc RBAR
0x10 RASR
Toggle registers

TYPER

MPU type register

Offset: 0x0, size: 32, reset: 0x00000800, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREGION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DREGION
r 		SEPARATE
r
Toggle fields

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

CTRL

MPU control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIVDEFENA
rw 		HFNMIENA
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

RNR

MPU region number register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGION
rw
Toggle fields

REGION

Bits 0-7: MPU region.

RBAR

MPU region base address register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw 		VALID
rw 		REGION
rw
Toggle fields

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

RASR

MPU region attribute and size register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XN
rw 		AP
rw 		TEX
rw 		S
rw 		C
rw 		B
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD
rw 		SIZE
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xe000e100: Nested Vectored Interrupt Controller

3/99 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISER0
0x4 ISER1
0x8 ISER2
0x80 ICER0
0x84 ICER1
0x88 ICER2
0x100 ISPR0
0x104 ISPR1
0x108 ISPR2
0x180 ICPR0
0x184 ICPR1
0x188 ICPR2
0x200 IABR0
0x204 IABR1
0x208 IABR2
0x300 IPR0
0x304 IPR1
0x308 IPR2
0x30c IPR3
0x310 IPR4
0x314 IPR5
0x318 IPR6
0x31c IPR7
0x320 IPR8
0x324 IPR9
0x328 IPR10
0x32c IPR11
0x330 IPR12
0x334 IPR13
0x338 IPR14
0x33c IPR15
0x340 IPR16
0x344 IPR17
0x348 IPR18
0x34c IPR19
0x350 IPR20
Toggle registers

ISER0

Interrupt Set-Enable Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set-Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear-Enable Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR2

Interrupt Active Bit Register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR18

Interrupt Priority Register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR19

Interrupt Priority Register

Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR20

Interrupt Priority Register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xe000ef00: Nested vectored interrupt controller

0/1 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 STIR
Toggle registers

STIR

Software trigger interrupt register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
rw
Toggle fields

INTID

Bits 0-8: Software generated interrupt ID.

OCTOSPI1

0xa0001000: OctoSPI

9/88 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x8 DCR1
0xc DCR2
0x10 DCR3
0x20 SR
0x24 FCR
0x40 DLR
0x48 AR
0x50 DR
0x80 PSMKR
0x88 PSMAR
0x90 PIR
0x100 CCR
0x108 TCR
0x110 IR
0x120 ABR
0x130 LPTR
0x180 WCCR
0x188 WTCR
0x190 WIR
0x1a0 WABR
0x200 HLCR
0x3f0 HWCFGR
0x3f4 VER
0x3f8 ID
0x3fc MID
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMODE
rw 		PMM
rw 		APMS
rw 		TOIE
rw 		SMIE
rw 		FTIE
rw 		TCIE
rw 		TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw 		FSEL
rw 		DQM
rw 		TCEN
rw 		DMAEN
rw 		ABORT
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTYP
rw 		DEVSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw 		FRCK
rw 		CKMODE
rw
Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

CSHT

Bits 8-10: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-25: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRAPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSBOUND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CSBOUND

Bits 16-20: CS boundary.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
rw 		BUSY
rw 		TOF
rw 		SMF
rw 		FTF
rw 		TCF
rw 		TEF
rw
Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-13: FIFO level.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w 		CSMF
w 		CTCF
w 		CTEF
w
Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: Data length.

AR

address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: ADDRESS.

DR

data register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: Status match.

PIR

polling interval register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: Polling interval.

CCR

communication configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw 		DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

TCR

timing configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw 		DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

IR

instruction register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

ABR

alternate bytes register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

LPTR

low-power timeout register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

WCCR

write communication configuration register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw 		DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

WTCR

write timing configuration register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

WIR

write instruction register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WABR

write alternate bytes register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

HLCR

HyperBusTM latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACC
rw 		WZL
rw 		LM
rw
Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

HWCFGR

HW configuration register

Offset: 0x3f0, size: 32, reset: 0x11300080, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MST
r 		MMW
r 		IDL
r 		PRES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRES
r 		FIFO
r 		AXI
r
Toggle fields

AXI

Bits 0-3: AXI interface.

FIFO

Bits 4-11: FIFO depth.

PRES

Bits 12-19: Prescaler.

IDL

Bits 20-23: ID Length.

MMW

Bits 24-27: Memory map write.

MST

Bits 28-31: Master.

VER

version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VER
r
Toggle fields

VER

Bits 0-7: Version.

ID

identification

Offset: 0x3f8, size: 32, reset: 0x00140041, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: Identification.

MID

magic ID

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MID
r
Toggle fields

MID

Bits 0-31: Magic ID.

OCTOSPI2

0xa0001400: OctoSPI

9/88 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x8 DCR1
0xc DCR2
0x10 DCR3
0x20 SR
0x24 FCR
0x40 DLR
0x48 AR
0x50 DR
0x80 PSMKR
0x88 PSMAR
0x90 PIR
0x100 CCR
0x108 TCR
0x110 IR
0x120 ABR
0x130 LPTR
0x180 WCCR
0x188 WTCR
0x190 WIR
0x1a0 WABR
0x200 HLCR
0x3f0 HWCFGR
0x3f4 VER
0x3f8 ID
0x3fc MID
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMODE
rw 		PMM
rw 		APMS
rw 		TOIE
rw 		SMIE
rw 		FTIE
rw 		TCIE
rw 		TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw 		FSEL
rw 		DQM
rw 		TCEN
rw 		DMAEN
rw 		ABORT
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTYP
rw 		DEVSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw 		FRCK
rw 		CKMODE
rw
Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

CSHT

Bits 8-10: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-25: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRAPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSBOUND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CSBOUND

Bits 16-20: CS boundary.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
rw 		BUSY
rw 		TOF
rw 		SMF
rw 		FTF
rw 		TCF
rw 		TEF
rw
Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-13: FIFO level.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w 		CSMF
w 		CTCF
w 		CTEF
w
Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: Data length.

AR

address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: ADDRESS.

DR

data register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: Status match.

PIR

polling interval register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: Polling interval.

CCR

communication configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw 		DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

TCR

timing configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw 		DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

IR

instruction register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

ABR

alternate bytes register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

LPTR

low-power timeout register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

WCCR

write communication configuration register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw 		DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

WTCR

write timing configuration register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

WIR

write instruction register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WABR

write alternate bytes register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

HLCR

HyperBusTM latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACC
rw 		WZL
rw 		LM
rw
Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

HWCFGR

HW configuration register

Offset: 0x3f0, size: 32, reset: 0x11300080, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MST
r 		MMW
r 		IDL
r 		PRES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRES
r 		FIFO
r 		AXI
r
Toggle fields

AXI

Bits 0-3: AXI interface.

FIFO

Bits 4-11: FIFO depth.

PRES

Bits 12-19: Prescaler.

IDL

Bits 20-23: ID Length.

MMW

Bits 24-27: Memory map write.

MST

Bits 28-31: Master.

VER

version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VER
r
Toggle fields

VER

Bits 0-7: Version.

ID

identification

Offset: 0x3f8, size: 32, reset: 0x00140041, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: Identification.

MID

magic ID

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MID
r
Toggle fields

MID

Bits 0-31: Magic ID.

OCTOSPIM

0x50061c00: OctoSPI IO Manager

0/20 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4 P1CR
0x8 P2CR
Toggle registers

P1CR

OctoSPI IO Manager Port 1 Configuration Register

Offset: 0x4, size: 32, reset: 0x03010111, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHSRC
rw 		IOHEN
rw 		IOLSRC
rw 		IOLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCSSRC
rw 		NCSEN
rw 		DQSSRC
rw 		DQSEN
rw 		CLKSRC
rw 		CLKEN
rw
Toggle fields

CLKEN

Bit 0: CLK/CLK Enable for Port.

CLKSRC

Bit 1: CLK/CLK Source for Port.

DQSEN

Bit 4: DQS Enable for Port.

DQSSRC

Bit 5: DQS Source for Port.

NCSEN

Bit 8: CS Enable for Port.

NCSSRC

Bit 9: CS Source for Port.

IOLEN

Bit 16: Enable for Port.

IOLSRC

Bits 17-18: Source for Port.

IOHEN

Bit 24: Enable for Port n.

IOHSRC

Bits 25-26: Source for Port.

P2CR

OctoSPI IO Manager Port 2 Configuration Register

Offset: 0x8, size: 32, reset: 0x07050333, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHSRC
rw 		IOHEN
rw 		IOLSRC
rw 		IOLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCSSRC
rw 		NCSEN
rw 		DQSSRC
rw 		DQSEN
rw 		CLKSRC
rw 		CLKEN
rw
Toggle fields

CLKEN

Bit 0: CLK/CLK Enable for Port.

CLKSRC

Bit 1: CLK/CLK Source for Port.

DQSEN

Bit 4: DQS Enable for Port.

DQSSRC

Bit 5: DQS Source for Port.

NCSEN

Bit 8: CS Enable for Port.

NCSSRC

Bit 9: CS Source for Port.

IOLEN

Bit 16: Enable for Port.

IOLSRC

Bits 17-18: Source for Port.

IOHEN

Bit 24: Enable for Port n.

IOHSRC

Bits 25-26: Source for Port.

OPAMP

0x40007800: Operational amplifiers

0/29 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OPAMP1_CSR
0x4 OPAMP1_OTR
0x8 OPAMP1_LPOTR
0x10 OPAMP2_CSR
0x14 OPAMP2_OTR
0x18 OPAMP2_LPOTR
Toggle registers

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_RANGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw 		USERTRIM
rw 		CALSEL
rw 		CALON
rw 		VP_SEL
rw 		VM_SEL
rw 		PGA_GAIN
rw 		OPAMODE
rw 		OPALPM
rw 		OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: Inverting input selection.

VP_SEL

Bit 10: Non inverted input selection.

CALON

Bit 12: Calibration mode enabled.

CALSEL

Bit 13: Calibration selection.

USERTRIM

Bit 14: allows to switch from AOP offset trimmed values to AOP offset.

CALOUT

Bit 15: Operational amplifier calibration output.

OPA_RANGE

Bit 31: Operational amplifier power supply range for stability.

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw 		TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_LPOTR

OPAMP1 offset trimming register in low-power mode

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw 		TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_CSR

OPAMP2 control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw 		USERTRIM
rw 		CALSEL
rw 		CALON
rw 		VP_SEL
rw 		VM_SEL
rw 		PGA_GAIN
rw 		OPAMODE
rw 		OPALPM
rw 		OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: Inverting input selection.

VP_SEL

Bit 10: Non inverted input selection.

CALON

Bit 12: Calibration mode enabled.

CALSEL

Bit 13: Calibration selection.

USERTRIM

Bit 14: allows to switch from AOP offset trimmed values to AOP offset.

CALOUT

Bit 15: Operational amplifier calibration output.

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw 		TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_LPOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw 		TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OTG_FS_DEVICE

0x50000800: USB on the go full speed

49/292 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DCFG
0x4 DCTL
0x8 DSTS
0x10 DIEPMSK
0x14 DOEPMSK
0x18 DAINT
0x1c DAINTMSK
0x28 DVBUSDIS
0x2c DVBUSPULSE
0x34 DIEPEMPMSK
0x100 CTL [0]
0x108 INT [0]
0x110 TSIZ [0]
0x118 TXFSTS [0]
0x120 CTL [1]
0x128 INT [1]
0x130 TSIZ [1]
0x138 TXFSTS [1]
0x140 CTL [2]
0x148 INT [2]
0x150 TSIZ [2]
0x158 TXFSTS [2]
0x160 CTL [3]
0x168 INT [3]
0x170 TSIZ [3]
0x178 TXFSTS [3]
0x180 CTL [4]
0x188 INT [4]
0x190 TSIZ [4]
0x198 TXFSTS [4]
0x1a0 CTL [5]
0x1a8 INT [5]
0x1b0 TSIZ [5]
0x1b8 TXFSTS [5]
0x300 CTL [0]
0x308 INT [0]
0x310 TSIZ [0]
0x320 CTL [1]
0x328 INT [1]
0x330 TSIZ [1]
0x340 CTL [2]
0x348 INT [2]
0x350 TSIZ [2]
0x360 CTL [3]
0x368 INT [3]
0x370 TSIZ [3]
0x380 CTL [4]
0x388 INT [4]
0x390 TSIZ [4]
0x3a0 CTL [5]
0x3a8 INT [5]
0x3b0 TSIZ [5]
Toggle registers

DCFG

OTG_FS device configuration register (OTG_FS_DCFG)

Offset: 0x0, size: 32, reset: 0x02200000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFIVL
rw 		DAD
rw 		NZLSOHSK
rw 		DSPD
rw
Toggle fields

DSPD

Bits 0-1: Device speed.

NZLSOHSK

Bit 2: Non-zero-length status OUT handshake.

DAD

Bits 4-10: Device address.

PFIVL

Bits 11-12: Periodic frame interval.

DCTL

OTG_FS device control register (OTG_FS_DCTL)

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POPRGDNE
rw 		CGONAK
rw 		SGONAK
rw 		CGINAK
rw 		SGINAK
rw 		TCTL
rw 		GONSTS
r 		GINSTS
r 		SDIS
rw 		RWUSIG
rw
Toggle fields

RWUSIG

Bit 0: Remote wakeup signaling.

SDIS

Bit 1: Soft disconnect.

GINSTS

Bit 2: Global IN NAK status.

GONSTS

Bit 3: Global OUT NAK status.

TCTL

Bits 4-6: Test control.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POPRGDNE

Bit 11: Power-on programming done.

DSTS

OTG_FS device status register (OTG_FS_DSTS)

Offset: 0x8, size: 32, reset: 0x00000010, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNSOF
r 		EERR
r 		ENUMSPD
r 		SUSPSTS
r
Toggle fields

SUSPSTS

Bit 0: Suspend status.

ENUMSPD

Bits 1-2: Enumerated speed.

EERR

Bit 3: Erratic error.

FNSOF

Bits 8-21: Frame number of the received SOF.

DIEPMSK

OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPNEM
rw 		INEPNMM
rw 		ITTXFEMSK
rw 		TOM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (Non-isochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

DOEPMSK

OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTEPDM
rw 		STUPM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

DAINT

OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPINT
r
Toggle fields

IEPINT

Bits 0-15: IN endpoint interrupt bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

DAINTMSK

OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPM
rw
Toggle fields

IEPM

Bits 0-15: IN EP interrupt mask bits.

OEPM

Bits 16-31: OUT EP interrupt mask bits.

DVBUSDIS

OTG_FS device VBUS discharge time register

Offset: 0x28, size: 32, reset: 0x000017D7, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSDT
rw
Toggle fields

VBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPULSE

OTG_FS device VBUS pulsing time register

Offset: 0x2c, size: 32, reset: 0x000005B8, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSP
rw
Toggle fields

DVBUSP

Bits 0-11: Device VBUS pulsing time.

DIEPEMPMSK

OTG_FS device IN endpoint FIFO empty interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXFEM
rw
Toggle fields

INEPTXFEM

Bits 0-15: IN EP Tx FIFO empty interrupt mask bits.

CTL [0]

OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)

Offset: 0x100, size: 32, reset: 0x00000000, access: Unspecified

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
r 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
r 		NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-1: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

INT [0]

device endpoint-x interrupt register

Offset: 0x108, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [0]

device endpoint-0 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bits 19-20: Packet count.

TXFSTS [0]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [1]

OTG device endpoint-1 control register

Offset: 0x120, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM_SD1PID
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [1]

device endpoint-1 interrupt register

Offset: 0x128, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [1]

device endpoint-1 transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

TXFSTS [1]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [2]

OTG device endpoint-1 control register

Offset: 0x140, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM_SD1PID
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [2]

device endpoint-1 interrupt register

Offset: 0x148, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [2]

device endpoint-1 transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

TXFSTS [2]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [3]

OTG device endpoint-1 control register

Offset: 0x160, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM_SD1PID
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [3]

device endpoint-1 interrupt register

Offset: 0x168, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [3]

device endpoint-1 transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

TXFSTS [3]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [4]

OTG device endpoint-1 control register

Offset: 0x180, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM_SD1PID
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [4]

device endpoint-1 interrupt register

Offset: 0x188, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [4]

device endpoint-1 transfer size register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

TXFSTS [4]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [5]

OTG device endpoint-1 control register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM_SD1PID
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [5]

device endpoint-1 interrupt register

Offset: 0x1a8, size: 32, reset: 0x00000080, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		INEPNE
rw 		ITTXFE
rw 		TOC
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TSIZ [5]

device endpoint-1 transfer size register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

TXFSTS [5]

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

CTL [0]

device endpoint-0 control register

Offset: 0x300, size: 32, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
r 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
r 		NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r 		MPSIZ
r
Toggle fields

MPSIZ

Bits 0-1: MPSIZ.

USBAEP

Bit 15: USBAEP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [0]

device endpoint-0 interrupt register

Offset: 0x308, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [0]

device OUT endpoint-0 transfer size register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STUPCNT
rw 		PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bit 19: Packet count.

STUPCNT

Bits 29-30: SETUP packet count.

CTL [1]

device endpoint-1 control register

Offset: 0x320, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [1]

device endpoint-1 interrupt register

Offset: 0x328, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [1]

device OUT endpoint-1 transfer size register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

CTL [2]

device endpoint-1 control register

Offset: 0x340, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [2]

device endpoint-1 interrupt register

Offset: 0x348, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [2]

device OUT endpoint-1 transfer size register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

CTL [3]

device endpoint-1 control register

Offset: 0x360, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [3]

device endpoint-1 interrupt register

Offset: 0x368, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [3]

device OUT endpoint-1 transfer size register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

CTL [4]

device endpoint-1 control register

Offset: 0x380, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [4]

device endpoint-1 interrupt register

Offset: 0x388, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [4]

device OUT endpoint-1 transfer size register

Offset: 0x390, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

CTL [5]

device endpoint-1 control register

Offset: 0x3a0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

INT [5]

device endpoint-1 interrupt register

Offset: 0x3a8, size: 32, reset: 0x00000080, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw 		OTEPDIS
rw 		STUP
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

TSIZ [5]

device OUT endpoint-1 transfer size register

Offset: 0x3b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_FS_GLOBAL

0x50000000: USB on the go full speed

39/127 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GOTGCTL
0x4 GOTGINT
0x8 GAHBCFG
0xc GUSBCFG
0x10 GRSTCTL
0x14 GINTSTS
0x18 GINTMSK
0x1c GRXSTSR_Device
0x1c GRXSTSR_Host
0x20 GRXSTSP_Device
0x20 GRXSTSP_Host
0x24 GRXFSIZ
0x28 DIEPTXF0
0x28 HNPTXFSIZ
0x2c GNPTXSTS
0x38 GCCFG
0x3c CID
0x100 HPTXFSIZ
0x104 DIEPTXF[1]
0x108 DIEPTXF[2]
0x10c DIEPTXF[3]
0x110 DIEPTXF[4]
0x114 DIEPTXF[5]
Toggle registers

GOTGCTL

OTG_FS control and status register (OTG_FS_GOTGCTL)

Offset: 0x0, size: 32, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSVLD
r 		ASVLD
r 		DBCT
r 		CIDSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw 		HSHNPEN
rw 		HNPRQ
rw 		HNGSCS
r 		SRQ
rw 		SRQSCS
r
Toggle fields

SRQSCS

Bit 0: Session request success.

SRQ

Bit 1: Session request.

HNGSCS

Bit 8: Host negotiation success.

HNPRQ

Bit 9: HNP request.

HSHNPEN

Bit 10: Host set HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

CIDSTS

Bit 16: Connector ID status.

DBCT

Bit 17: Long/short debounce time.

ASVLD

Bit 18: A-session valid.

BSVLD

Bit 19: B-session valid.

GOTGINT

OTG_FS interrupt register (OTG_FS_GOTGINT)

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBCDNE
rw 		ADTOCHG
rw 		HNGDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNSSCHG
rw 		SRSSCHG
rw 		SEDET
rw
Toggle fields

SEDET

Bit 2: Session end detected.

SRSSCHG

Bit 8: Session request success status change.

HNSSCHG

Bit 9: Host negotiation success status change.

HNGDET

Bit 17: Host negotiation detected.

ADTOCHG

Bit 18: A-device timeout change.

DBCDNE

Bit 19: Debounce done.

GAHBCFG

OTG_FS AHB configuration register (OTG_FS_GAHBCFG)

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFELVL
rw 		TXFELVL
rw 		GINT
rw
Toggle fields

GINT

Bit 0: Global interrupt mask.

TXFELVL

Bit 7: TxFIFO empty level.

PTXFELVL

Bit 8: Periodic TxFIFO empty level.

GUSBCFG

OTG_FS USB configuration register (OTG_FS_GUSBCFG)

Offset: 0xc, size: 32, reset: 0x00000A00, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTXPKT
rw 		FDMOD
rw 		FHMOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRDT
rw 		HNPCAP
rw 		SRPCAP
rw 		PHYSEL
w 		TOCAL
rw
Toggle fields

TOCAL

Bits 0-2: FS timeout calibration.

PHYSEL

Bit 6: Full Speed serial transceiver select.

SRPCAP

Bit 8: SRP-capable.

HNPCAP

Bit 9: HNP-capable.

TRDT

Bits 10-13: USB turnaround time.

FHMOD

Bit 29: Force host mode.

FDMOD

Bit 30: Force device mode.

CTXPKT

Bit 31: Corrupt Tx packet.

GRSTCTL

OTG_FS reset register (OTG_FS_GRSTCTL)

Offset: 0x10, size: 32, reset: 0x20000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBIDL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw 		TXFFLSH
rw 		RXFFLSH
rw 		FCRST
rw 		HSRST
rw 		CSRST
rw
Toggle fields

CSRST

Bit 0: Core soft reset.

HSRST

Bit 1: HCLK soft reset.

FCRST

Bit 2: Host frame counter reset.

RXFFLSH

Bit 4: RxFIFO flush.

TXFFLSH

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

AHBIDL

Bit 31: AHB master idle.

GINTSTS

OTG_FS core interrupt register (OTG_FS_GINTSTS)

Offset: 0x14, size: 32, reset: 0x04000020, access: Unspecified

11/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPINT
rw 		SRQINT
rw 		DISCINT
rw 		CIDSCHG
rw 		PTXFE
r 		HCINT
r 		HPRTINT
r 		IPXFR_INCOMPISOOUT
rw 		IISOIXFR
rw 		OEPINT
r 		IEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPF
rw 		ISOODRP
rw 		ENUMDNE
rw 		USBRST
rw 		USBSUSP
rw 		ESUSP
rw 		GOUTNAKEFF
r 		GINAKEFF
r 		NPTXFE
r 		RXFLVL
r 		SOF
rw 		OTGINT
r 		MMIS
rw 		CMOD
r
Toggle fields

CMOD

Bit 0: Current mode of operation.

MMIS

Bit 1: Mode mismatch interrupt.

OTGINT

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFLVL

Bit 4: RxFIFO non-empty.

NPTXFE

Bit 5: Non-periodic TxFIFO empty.

GINAKEFF

Bit 6: Global IN non-periodic NAK effective.

GOUTNAKEFF

Bit 7: Global OUT NAK effective.

ESUSP

Bit 10: Early suspend.

USBSUSP

Bit 11: USB suspend.

USBRST

Bit 12: USB reset.

ENUMDNE

Bit 13: Enumeration done.

ISOODRP

Bit 14: Isochronous OUT packet dropped interrupt.

EOPF

Bit 15: End of periodic frame interrupt.

IEPINT

Bit 18: IN endpoint interrupt.

OEPINT

Bit 19: OUT endpoint interrupt.

IISOIXFR

Bit 20: Incomplete isochronous IN transfer.

IPXFR_INCOMPISOOUT

Bit 21: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode).

HPRTINT

Bit 24: Host port interrupt.

HCINT

Bit 25: Host channels interrupt.

PTXFE

Bit 26: Periodic TxFIFO empty.

CIDSCHG

Bit 28: Connector ID status change.

DISCINT

Bit 29: Disconnect detected interrupt.

SRQINT

Bit 30: Session request/new session detected interrupt.

WKUPINT

Bit 31: Resume/remote wakeup detected interrupt.

GINTMSK

OTG_FS interrupt mask register (OTG_FS_GINTMSK)

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIM
rw 		SRQIM
rw 		DISCINT
rw 		CIDSCHGM
rw 		PTXFEM
rw 		HCIM
rw 		PRTIM
rw 		IPXFRM_IISOOXFRM
rw 		IISOIXFRM
rw 		OEPINT
rw 		IEPINT
rw 		EPMISM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFM
rw 		ISOODRPM
rw 		ENUMDNEM
rw 		USBRST
rw 		USBSUSPM
rw 		ESUSPM
rw 		GONAKEFFM
rw 		GINAKEFFM
rw 		NPTXFEM
rw 		RXFLVLM
rw 		SOFM
rw 		OTGINT
rw 		MMISM
rw
Toggle fields

MMISM

Bit 1: Mode mismatch interrupt mask.

OTGINT

Bit 2: OTG interrupt mask.

SOFM

Bit 3: Start of frame mask.

RXFLVLM

Bit 4: Receive FIFO non-empty mask.

NPTXFEM

Bit 5: Non-periodic TxFIFO empty mask.

GINAKEFFM

Bit 6: Global non-periodic IN NAK effective mask.

GONAKEFFM

Bit 7: Global OUT NAK effective mask.

ESUSPM

Bit 10: Early suspend mask.

USBSUSPM

Bit 11: USB suspend mask.

USBRST

Bit 12: USB reset mask.

ENUMDNEM

Bit 13: Enumeration done mask.

ISOODRPM

Bit 14: Isochronous OUT packet dropped interrupt mask.

EOPFM

Bit 15: End of periodic frame interrupt mask.

EPMISM

Bit 17: Endpoint mismatch interrupt mask.

IEPINT

Bit 18: IN endpoints interrupt mask.

OEPINT

Bit 19: OUT endpoints interrupt mask.

IISOIXFRM

Bit 20: Incomplete isochronous IN transfer mask.

IPXFRM_IISOOXFRM

Bit 21: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode).

PRTIM

Bit 24: Host port interrupt mask.

HCIM

Bit 25: Host channels interrupt mask.

PTXFEM

Bit 26: Periodic TxFIFO empty mask.

CIDSCHGM

Bit 28: Connector ID status change mask.

DISCINT

Bit 29: Disconnect detected interrupt mask.

SRQIM

Bit 30: Session request/new session detected interrupt mask.

WUIM

Bit 31: Resume/remote wakeup detected interrupt mask.

GRXSTSR_Device

OTG_FS Receive status debug read(Device mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r 		PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		EPNUM
r
Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

GRXSTSR_Host

OTG status debug read (host mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		CHNUM
r
Toggle fields

CHNUM

Bits 0-3: Channel number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

GRXSTSP_Device

OTG status read and pop (device mode)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r 		PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		EPNUM
r
Toggle fields

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

GRXSTSP_Host

OTG status read and pop (host mode)

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		CHNUM
r
Toggle fields

CHNUM

Bits 0-3: Channel number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

GRXFSIZ

OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle fields

RXFD

Bits 0-15: RxFIFO depth.

DIEPTXF0

OTG_FS non-periodic transmit FIFO size register (Device mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX0FD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX0FSA
rw
Toggle fields

TX0FSA

Bits 0-15: Endpoint 0 transmit RAM start address.

TX0FD

Bits 16-31: Endpoint 0 TxFIFO depth.

HNPTXFSIZ

OTG_FS non-periodic transmit FIFO size register (Host mode)

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSA
rw
Toggle fields

NPTXFSA

Bits 0-15: Non-periodic transmit RAM start address.

NPTXFD

Bits 16-31: Non-periodic TxFIFO depth.

GNPTXSTS

OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)

Offset: 0x2c, size: 32, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXQTOP
r 		NPTQXSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSAV
r
Toggle fields

NPTXFSAV

Bits 0-15: Non-periodic TxFIFO space available.

NPTQXSAV

Bits 16-23: Non-periodic transmit request queue space available.

NPTXQTOP

Bits 24-30: Top of the non-periodic transmit request queue.

GCCFG

OTG_FS general core configuration register (OTG_FS_GCCFG)

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOFOUTEN
rw 		VBUSBSEN
rw 		VBUSASEN
rw 		PWRDWN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PWRDWN

Bit 16: Power down.

VBUSASEN

Bit 18: Enable the VBUS sensing device.

VBUSBSEN

Bit 19: Enable the VBUS sensing device.

SOFOUTEN

Bit 20: SOF output enable.

CID

core ID register

Offset: 0x3c, size: 32, reset: 0x00001000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCT_ID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRODUCT_ID
rw
Toggle fields

PRODUCT_ID

Bits 0-31: Product ID field.

HPTXFSIZ

OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)

Offset: 0x100, size: 32, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXFSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXSA
rw
Toggle fields

PTXSA

Bits 0-15: Host periodic TxFIFO start address.

PTXFSIZ

Bits 16-31: Host periodic TxFIFO depth.

DIEPTXF[1]

OTF_FS device IN endpoint transmit FIFO size register

Offset: 0x104, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[2]

OTF_FS device IN endpoint transmit FIFO size register

Offset: 0x108, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[3]

OTF_FS device IN endpoint transmit FIFO size register

Offset: 0x10c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[4]

OTF_FS device IN endpoint transmit FIFO size register

Offset: 0x110, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEPTXF[5]

OTF_FS device IN endpoint transmit FIFO size register

Offset: 0x114, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_FS_HOST

0x50000400: USB on the go full speed

9/407 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 HCFG
0x4 HFIR
0x8 HFNUM
0x10 HPTXSTS
0x14 HAINT
0x18 HAINTMSK
0x40 HPRT
0x100 CHAR [0]
0x108 INT [0]
0x10c INTMSK [0]
0x110 TSIZ [0]
0x120 CHAR [1]
0x128 INT [1]
0x12c INTMSK [1]
0x130 TSIZ [1]
0x140 CHAR [2]
0x148 INT [2]
0x14c INTMSK [2]
0x150 TSIZ [2]
0x160 CHAR [3]
0x168 INT [3]
0x16c INTMSK [3]
0x170 TSIZ [3]
0x180 CHAR [4]
0x188 INT [4]
0x18c INTMSK [4]
0x190 TSIZ [4]
0x1a0 CHAR [5]
0x1a8 INT [5]
0x1ac INTMSK [5]
0x1b0 TSIZ [5]
0x1c0 CHAR [6]
0x1c8 INT [6]
0x1cc INTMSK [6]
0x1d0 TSIZ [6]
0x1e0 CHAR [7]
0x1e8 INT [7]
0x1ec INTMSK [7]
0x1f0 TSIZ [7]
0x200 CHAR [8]
0x208 INT [8]
0x20c INTMSK [8]
0x210 TSIZ [8]
0x220 CHAR [9]
0x228 INT [9]
0x22c INTMSK [9]
0x230 TSIZ [9]
0x240 CHAR [10]
0x248 INT [10]
0x24c INTMSK [10]
0x250 TSIZ [10]
0x260 CHAR [11]
0x268 INT [11]
0x26c INTMSK [11]
0x270 TSIZ [11]
Toggle registers

HCFG

OTG_FS host configuration register (OTG_FS_HCFG)

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSLSS
rw 		FSLSPCS
rw
Toggle fields

FSLSPCS

Bits 0-1: FS/LS PHY clock select.

FSLSS

Bit 2: FS- and LS-only support.

HFIR

OTG_FS Host frame interval register

Offset: 0x4, size: 32, reset: 0x0000EA60, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
rw
Toggle fields

FRIVL

Bits 0-15: Frame interval.

HFNUM

OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)

Offset: 0x8, size: 32, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTREM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle fields

FRNUM

Bits 0-15: Frame number.

FTREM

Bits 16-31: Frame time remaining.

HPTXSTS

OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)

Offset: 0x10, size: 32, reset: 0x00080100, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXQTOP
r 		PTXQSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFSAVL
rw
Toggle fields

PTXFSAVL

Bits 0-15: Periodic transmit data FIFO space available.

PTXQSAV

Bits 16-23: Periodic transmit request queue space available.

PTXQTOP

Bits 24-31: Top of the periodic transmit request queue.

HAINT

OTG_FS Host all channels interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINT
r
Toggle fields

HAINT

Bits 0-15: Channel interrupts.

HAINTMSK

OTG_FS host all channels interrupt mask register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINTM
rw
Toggle fields

HAINTM

Bits 0-15: Channel interrupt mask.

HPRT

OTG_FS host port control and status register (OTG_FS_HPRT)

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

4/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSPD
r 		PTCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTCTL
rw 		PPWR
rw 		PLSTS
r 		PRST
rw 		PSUSP
rw 		PRES
rw 		POCCHNG
rw 		POCA
r 		PENCHNG
rw 		PENA
rw 		PCDET
rw 		PCSTS
r
Toggle fields

PCSTS

Bit 0: Port connect status.

PCDET

Bit 1: Port connect detected.

PENA

Bit 2: Port enable.

PENCHNG

Bit 3: Port enable/disable change.

POCA

Bit 4: Port overcurrent active.

POCCHNG

Bit 5: Port overcurrent change.

PRES

Bit 6: Port resume.

PSUSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLSTS

Bits 10-11: Port line status.

PPWR

Bit 12: Port power.

PTCTL

Bits 13-16: Port test control.

PSPD

Bits 17-18: Port speed.

CHAR [0]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [0]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [0]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [0]

OTG_FS host channel-0 transfer size register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [1]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [1]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [1]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [1]

OTG_FS host channel-0 transfer size register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [2]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [2]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [2]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [2]

OTG_FS host channel-0 transfer size register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [3]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [3]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [3]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [3]

OTG_FS host channel-0 transfer size register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [4]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [4]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [4]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [4]

OTG_FS host channel-0 transfer size register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [5]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [5]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [5]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [5]

OTG_FS host channel-0 transfer size register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [6]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [6]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [6]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [6]

OTG_FS host channel-0 transfer size register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [7]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [7]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [7]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [7]

OTG_FS host channel-0 transfer size register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [8]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [8]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [8]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [8]

OTG_FS host channel-0 transfer size register

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [9]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [9]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x228, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [9]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [9]

OTG_FS host channel-0 transfer size register

Offset: 0x230, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [10]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [10]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [10]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [10]

OTG_FS host channel-0 transfer size register

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

CHAR [11]

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		ODDFRM
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

INT [11]

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

INTMSK [11]

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

TSIZ [11]

OTG_FS host channel-0 transfer size register

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_FS_PWRCLK

0x50000e00: USB on the go full speed

0/3 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PCGCCTL
Toggle registers

PCGCCTL

OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSUSP
rw 		GATEHCLK
rw 		STPPCLK
rw
Toggle fields

STPPCLK

Bit 0: Stop PHY clock.

GATEHCLK

Bit 1: Gate HCLK.

PHYSUSP

Bit 4: PHY Suspended.

PWR

0x40007000: Power control

15/276 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc CR4
0x10 SR1
0x14 SR2
0x18 SCR
0x20 PUCRA
0x24 PDCRA
0x28 PUCRB
0x2c PDCRB
0x30 PUCRC
0x34 PDCRC
0x38 PUCRD
0x3c PDCRD
0x40 PUCRE
0x44 PDCRE
0x48 PUCRF
0x4c PDCRF
0x50 PUCRG
0x54 PDCRG
0x58 PUCRH
0x5c PDCRH
Toggle registers

CR1

Power control register 1

Offset: 0x0, size: 32, reset: 0x00000200, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR
rw 		VOS
rw 		DBP
rw 		LPMS
rw
Toggle fields

LPMS

Bits 0-2: Low-power mode selection.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USV
rw 		IOSV
rw 		PVME4
rw 		PVME3
rw 		PVME2
rw 		PVME1
rw 		PLS
rw 		PVDE
rw
Toggle fields

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection.

PVME1

Bit 4: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V.

PVME2

Bit 5: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V.

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

PVME4

Bit 7: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V.

IOSV

Bit 9: VDDIO2 Independent I/Os supply valid.

USV

Bit 10: VDDUSB USB supply valid.

CR3

Power control register 3

Offset: 0x8, size: 32, reset: 0x00008000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWF
rw 		APC
rw 		RRS
rw 		EWUP5
rw 		EWUP4
rw 		EWUP3
rw 		EWUP2
rw 		EWUP1
rw
Toggle fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable Wakeup pin WKUP5.

RRS

Bit 8: SRAM2 retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration.

EWF

Bit 15: Enable internal wakeup line.

CR4

Power control register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBRS
rw 		VBE
rw 		WP5
rw 		WP4
rw 		WP3
rw 		WP2
rw 		WP1
rw
Toggle fields

WP1

Bit 0: Wakeup pin WKUP1 polarity.

WP2

Bit 1: Wakeup pin WKUP2 polarity.

WP3

Bit 2: Wakeup pin WKUP3 polarity.

WP4

Bit 3: Wakeup pin WKUP4 polarity.

WP5

Bit 4: Wakeup pin WKUP5 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

SR1

Power status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUFI
r 		CSBF
r 		CWUF5
r 		CWUF4
r 		CWUF3
r 		CWUF2
r 		CWUF1
r
Toggle fields

CWUF1

Bit 0: Wakeup flag 1.

CWUF2

Bit 1: Wakeup flag 2.

CWUF3

Bit 2: Wakeup flag 3.

CWUF4

Bit 3: Wakeup flag 4.

CWUF5

Bit 4: Wakeup flag 5.

CSBF

Bit 8: Standby flag.

WUFI

Bit 15: Wakeup flag internal.

SR2

Power status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO4
r 		PVMO3
r 		PVMO2
r 		PVMO1
r 		PVDO
r 		VOSF
r 		REGLPF
r 		REGLPS
r
Toggle fields

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO1

Bit 12: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V.

PVMO2

Bit 13: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

PVMO4

Bit 15: Peripheral voltage monitoring output: VDDA vs. 2.2 V.

SCR

Power status clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBF
w 		WUF5
w 		WUF4
w 		WUF3
w 		WUF2
w 		WUF1
w
Toggle fields

WUF1

Bit 0: Clear wakeup flag 1.

WUF2

Bit 1: Clear wakeup flag 2.

WUF3

Bit 2: Clear wakeup flag 3.

WUF4

Bit 3: Clear wakeup flag 4.

WUF5

Bit 4: Clear wakeup flag 5.

SBF

Bit 8: Clear standby flag.

PUCRA

Power Port A pull-up control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU14

Bit 14: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD13

Bit 13: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PD15

Bit 15: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD4

Bit 4: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU7

Bit 7: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PU10

Bit 10: Port D pull-up bit y (y=0..15).

PU11

Bit 11: Port D pull-up bit y (y=0..15).

PU12

Bit 12: Port D pull-up bit y (y=0..15).

PU13

Bit 13: Port D pull-up bit y (y=0..15).

PU14

Bit 14: Port D pull-up bit y (y=0..15).

PU15

Bit 15: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD7

Bit 7: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PD10

Bit 10: Port D pull-down bit y (y=0..15).

PD11

Bit 11: Port D pull-down bit y (y=0..15).

PD12

Bit 12: Port D pull-down bit y (y=0..15).

PD13

Bit 13: Port D pull-down bit y (y=0..15).

PD14

Bit 14: Port D pull-down bit y (y=0..15).

PD15

Bit 15: Port D pull-down bit y (y=0..15).

PUCRE

Power Port E pull-up control register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port E pull-up bit y (y=0..15).

PU1

Bit 1: Port E pull-up bit y (y=0..15).

PU2

Bit 2: Port E pull-up bit y (y=0..15).

PU3

Bit 3: Port E pull-up bit y (y=0..15).

PU4

Bit 4: Port E pull-up bit y (y=0..15).

PU5

Bit 5: Port E pull-up bit y (y=0..15).

PU6

Bit 6: Port E pull-up bit y (y=0..15).

PU7

Bit 7: Port E pull-up bit y (y=0..15).

PU8

Bit 8: Port E pull-up bit y (y=0..15).

PU9

Bit 9: Port E pull-up bit y (y=0..15).

PU10

Bit 10: Port E pull-up bit y (y=0..15).

PU11

Bit 11: Port E pull-up bit y (y=0..15).

PU12

Bit 12: Port E pull-up bit y (y=0..15).

PU13

Bit 13: Port E pull-up bit y (y=0..15).

PU14

Bit 14: Port E pull-up bit y (y=0..15).

PU15

Bit 15: Port E pull-up bit y (y=0..15).

PDCRE

Power Port E pull-down control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port E pull-down bit y (y=0..15).

PD1

Bit 1: Port E pull-down bit y (y=0..15).

PD2

Bit 2: Port E pull-down bit y (y=0..15).

PD3

Bit 3: Port E pull-down bit y (y=0..15).

PD4

Bit 4: Port E pull-down bit y (y=0..15).

PD5

Bit 5: Port E pull-down bit y (y=0..15).

PD6

Bit 6: Port E pull-down bit y (y=0..15).

PD7

Bit 7: Port E pull-down bit y (y=0..15).

PD8

Bit 8: Port E pull-down bit y (y=0..15).

PD9

Bit 9: Port E pull-down bit y (y=0..15).

PD10

Bit 10: Port E pull-down bit y (y=0..15).

PD11

Bit 11: Port E pull-down bit y (y=0..15).

PD12

Bit 12: Port E pull-down bit y (y=0..15).

PD13

Bit 13: Port E pull-down bit y (y=0..15).

PD14

Bit 14: Port E pull-down bit y (y=0..15).

PD15

Bit 15: Port E pull-down bit y (y=0..15).

PUCRF

Power Port F pull-up control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port F pull-up bit y (y=0..15).

PU1

Bit 1: Port F pull-up bit y (y=0..15).

PU2

Bit 2: Port F pull-up bit y (y=0..15).

PU3

Bit 3: Port F pull-up bit y (y=0..15).

PU4

Bit 4: Port F pull-up bit y (y=0..15).

PU5

Bit 5: Port F pull-up bit y (y=0..15).

PU6

Bit 6: Port F pull-up bit y (y=0..15).

PU7

Bit 7: Port F pull-up bit y (y=0..15).

PU8

Bit 8: Port F pull-up bit y (y=0..15).

PU9

Bit 9: Port F pull-up bit y (y=0..15).

PU10

Bit 10: Port F pull-up bit y (y=0..15).

PU11

Bit 11: Port F pull-up bit y (y=0..15).

PU12

Bit 12: Port F pull-up bit y (y=0..15).

PU13

Bit 13: Port F pull-up bit y (y=0..15).

PU14

Bit 14: Port F pull-up bit y (y=0..15).

PU15

Bit 15: Port F pull-up bit y (y=0..15).

PDCRF

Power Port F pull-down control register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port F pull-down bit y (y=0..15).

PD1

Bit 1: Port F pull-down bit y (y=0..15).

PD2

Bit 2: Port F pull-down bit y (y=0..15).

PD3

Bit 3: Port F pull-down bit y (y=0..15).

PD4

Bit 4: Port F pull-down bit y (y=0..15).

PD5

Bit 5: Port F pull-down bit y (y=0..15).

PD6

Bit 6: Port F pull-down bit y (y=0..15).

PD7

Bit 7: Port F pull-down bit y (y=0..15).

PD8

Bit 8: Port F pull-down bit y (y=0..15).

PD9

Bit 9: Port F pull-down bit y (y=0..15).

PD10

Bit 10: Port F pull-down bit y (y=0..15).

PD11

Bit 11: Port F pull-down bit y (y=0..15).

PD12

Bit 12: Port F pull-down bit y (y=0..15).

PD13

Bit 13: Port F pull-down bit y (y=0..15).

PD14

Bit 14: Port F pull-down bit y (y=0..15).

PD15

Bit 15: Port F pull-down bit y (y=0..15).

PUCRG

Power Port G pull-up control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRG

Power Port G pull-down control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port H pull-up bit y (y=0..1).

PU1

Bit 1: Port H pull-up bit y (y=0..1).

PDCRH

Power Port H pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port H pull-down bit y (y=0..1).

PD1

Bit 1: Port H pull-down bit y (y=0..1).

RCC

0x40021000: Reset and clock control

56/341 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ICSCR
0x8 CFGR
0xc PLLCFGR
0x10 PLLSAI1CFGR
0x14 PLLSAI2CFGR
0x18 CIER
0x1c CIFR
0x20 CICR
0x28 AHB1RSTR
0x2c AHB2RSTR
0x30 AHB3RSTR
0x38 APB1RSTR1
0x3c APB1RSTR2
0x40 APB2RSTR
0x48 AHB1ENR
0x4c AHB2ENR
0x50 AHB3ENR
0x58 APB1ENR1
0x5c APB1ENR2
0x60 APB2ENR
0x68 AHB1SMENR
0x6c AHB2SMENR
0x70 AHB3SMENR
0x78 APB1SMENR1
0x7c APB1SMENR2
0x80 APB2SMENR
0x88 CCIPR
0x90 BDCR
0x94 CSR
0x98 CRRCR
0x9c CCIPR2
Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000063, access: Unspecified

7/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI2RDY
r 		PLLSAI2ON
rw 		PLLSAI1RDY
r 		PLLSAI1ON
rw 		PLLRDY
r 		PLLON
rw 		CSSON
w 		HSEBYP
rw 		HSERDY
r 		HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIASFS
rw 		HSIRDY
r 		HSIKERON
rw 		HSION
rw 		MSIRANGE
rw 		MSIRGSEL
w 		MSIPLLEN
rw 		MSIRDY
r 		MSION
rw
Toggle fields

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag.

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRGSEL

Bit 3: MSI clock range selection.

MSIRANGE

Bits 4-7: MSI clock ranges.

Allowed values:
0: Range100K: range 0 around 100 kHz
1: Range200K: range 1 around 200 kHz
2: Range400K: range 2 around 400 kHz
3: Range800K: range 3 around 800 kHz
4: Range1M: range 4 around 1 MHz
5: Range2M: range 5 around 2 MHz
6: Range4M: range 6 around 4 MHz
7: Range8M: range 7 around 8 MHz
8: Range16M: range 8 around 16 MHz
9: Range24M: range 9 around 24 MHz
10: Range32M: range 10 around 32 MHz
11: Range48M: range 11 around 48 MHz

HSION

Bit 8: HSI clock enable.

HSIKERON

Bit 9: HSI always enable for peripheral kernels.

HSIRDY

Bit 10: HSI clock ready flag.

HSIASFS

Bit 11: HSI automatic start from Stop.

HSEON

Bit 16: HSE clock enable.

HSERDY

Bit 17: HSE clock ready flag.

HSEBYP

Bit 18: HSE crystal oscillator bypass.

CSSON

Bit 19: Clock security system enable.

PLLON

Bit 24: Main PLL enable.

PLLRDY

Bit 25: Main PLL clock ready flag.

PLLSAI1ON

Bit 26: SAI1 PLL enable.

PLLSAI1RDY

Bit 27: SAI1 PLL clock ready flag.

PLLSAI2ON

Bit 28: SAI2 PLL enable.

PLLSAI2RDY

Bit 29: SAI2 PLL clock ready flag.

ICSCR

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x10000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw 		HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM
rw 		MSICAL
r
Toggle fields

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI clock calibration.

HSITRIM

Bits 24-30: HSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
r 		MCOSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK
rw 		PPRE2
rw 		PPRE1
rw 		HPRE
rw 		SWS
r 		SW
rw
Toggle fields

SW

Bits 0-1: System clock switch.

SWS

Bits 2-3: System clock switch status.

HPRE

Bits 4-7: AHB prescaler.

PPRE1

Bits 8-10: PB low-speed prescaler (APB1).

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

MCOSEL

Bits 24-26: Microcontroller clock output.

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

PLLCFGR

PLL configuration register

Offset: 0xc, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPDIV
rw 		PLLR
rw 		PLLREN
rw 		PLLQ
rw 		PLLQEN
rw 		PLLP
rw 		PLLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw 		PLLM
rw 		PLLSRC
rw
Toggle fields

PLLSRC

Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.

PLLM

Bits 4-7: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.

PLLN

Bits 8-14: Main PLL multiplication factor for VCO.

PLLPEN

Bit 16: Main PLL PLLSAI3CLK output enable.

PLLP

Bit 17: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).

PLLQEN

Bit 20: Main PLL PLLUSB1CLK output enable.

PLLQ

Bits 21-22: Main PLL division factor for PLLUSB1CLK(48 MHz clock).

PLLREN

Bit 24: Main PLL PLLCLK output enable.

PLLR

Bits 25-26: Main PLL division factor for PLLCLK (system clock).

PLLPDIV

Bits 27-31: Main PLL division factor for PLLSAI2CLK.

PLLSAI1CFGR

PLLSAI1 configuration register

Offset: 0x10, size: 32, reset: 0x00001000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI1PDIV
rw 		PLLSAI1R
rw 		PLLSAI1REN
rw 		PLLSAI1Q
rw 		PLLSAI1QEN
rw 		PLLSAI1P
rw 		PLLSAI1PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI1N
rw 		PLLSAI1M
rw
Toggle fields

PLLSAI1M

Bits 4-7: Division factor for PLLSAI1 input clock.

PLLSAI1N

Bits 8-14: SAI1PLL multiplication factor for VCO.

PLLSAI1PEN

Bit 16: SAI1PLL PLLSAI1CLK output enable.

PLLSAI1P

Bit 17: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).

PLLSAI1QEN

Bit 20: SAI1PLL PLLUSB2CLK output enable.

PLLSAI1Q

Bits 21-22: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock).

PLLSAI1REN

Bit 24: PLLSAI1 PLLADC1CLK output enable.

PLLSAI1R

Bits 25-26: PLLSAI1 division factor for PLLADC1CLK (ADC clock).

PLLSAI1PDIV

Bits 27-31: PLLSAI1 division factor for PLLSAI1CLK.

PLLSAI2CFGR

PLLSAI2 configuration register

Offset: 0x14, size: 32, reset: 0x00001000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI2PDIV
rw 		PLLSAI2R
rw 		PLLSAI2REN
rw 		PLLSAI2Q
rw 		PLLSAI2QEN
rw 		PLLSAI2P
rw 		PLLSAI2PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI2N
rw 		PLLSAI2M
rw
Toggle fields

PLLSAI2M

Bits 4-7: Division factor for PLLSAI2 input clock.

PLLSAI2N

Bits 8-14: SAI2PLL multiplication factor for VCO.

PLLSAI2PEN

Bit 16: SAI2PLL PLLSAI2CLK output enable.

PLLSAI2P

Bit 17: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock).

PLLSAI2QEN

Bit 20: PLLSAI2 division factor for PLLDISCLK.

PLLSAI2Q

Bits 21-22: SAI2PLL PLLSAI2CLK output enable.

PLLSAI2REN

Bit 24: PLLSAI2 PLLADC2CLK output enable.

PLLSAI2R

Bits 25-26: PLLSAI2 division factor for PLLADC2CLK (ADC clock).

PLLSAI2PDIV

Bits 27-31: PLLSAI2 division factor for PLLSAI2CLK.

CIER

Clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYIE
rw 		LSECSSIE
rw 		PLLSAI2RDYIE
rw 		PLLSAI1RDYIE
rw 		PLLRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		MSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw
Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLRDYIE

Bit 5: PLL ready interrupt enable.

PLLSAI1RDYIE

Bit 6: PLLSAI1 ready interrupt enable.

PLLSAI2RDYIE

Bit 7: PLLSAI2 ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

HSI48RDYIE

Bit 10: HSI48 ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYF
r 		LSECSSF
r 		CSSF
r 		PLLSAI2RDYF
r 		PLLSAI1RDYF
r 		PLLRDYF
r 		HSERDYF
r 		HSIRDYF
r 		MSIRDYF
r 		LSERDYF
r 		LSIRDYF
r
Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

PLLSAI1RDYF

Bit 6: PLLSAI1 ready interrupt flag.

PLLSAI2RDYF

Bit 7: PLLSAI2 ready interrupt flag.

CSSF

Bit 8: Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

HSI48RDYF

Bit 10: HSI48 ready interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYC
w 		LSECSSC
w 		CSSC
w 		PLLSAI2RDYC
w 		PLLSAI1RDYC
w 		PLLRDYC
w 		HSERDYC
w 		HSIRDYC
w 		MSIRDYC
w 		LSERDYC
w 		LSIRDYC
w
Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

PLLSAI1RDYC

Bit 6: PLLSAI1 ready interrupt clear.

PLLSAI2RDYC

Bit 7: PLLSAI2 ready interrupt clear.

CSSC

Bit 8: Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

HSI48RDYC

Bit 10: HSI48 oscillator ready interrupt clear.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GFXMMURST
rw 		DMA2DRST
rw 		TSCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw 		FLASHRST
rw 		DMAMUX1RST
rw 		DMA2RST
rw 		DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1 reset.

DMA2RST

Bit 1: DMA2 reset.

DMAMUX1RST

Bit 2: DMAMUXRST.

FLASHRST

Bit 8: Flash memory interface reset.

CRCRST

Bit 12: CRC reset.

TSCRST

Bit 16: Touch Sensing Controller reset.

DMA2DRST

Bit 17: DMA2D reset.

GFXMMURST

Bit 18: GFXMMU reset.

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1RST
rw 		OSPIMRST
rw 		RNGRST
rw 		HASHRST
rw 		AESRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCMIRST
rw 		ADCRST
rw 		OTGFSRST
rw 		GPIOIRST
rw 		GPIOHRST
rw 		GPIOGRST
rw 		GPIOFRST
rw 		GPIOERST
rw 		GPIODRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: IO port A reset.

GPIOBRST

Bit 1: IO port B reset.

GPIOCRST

Bit 2: IO port C reset.

GPIODRST

Bit 3: IO port D reset.

GPIOERST

Bit 4: IO port E reset.

GPIOFRST

Bit 5: IO port F reset.

GPIOGRST

Bit 6: IO port G reset.

GPIOHRST

Bit 7: IO port H reset.

GPIOIRST

Bit 8: IO port I reset.

OTGFSRST

Bit 12: USB OTG FS reset.

ADCRST

Bit 13: ADC reset.

DCMIRST

Bit 14: Digital Camera Interface reset.

AESRST

Bit 16: AES hardware accelerator reset.

HASHRST

Bit 17: Hash reset.

RNGRST

Bit 18: Random number generator reset.

OSPIMRST

Bit 20: OCTOSPI IO manager reset.

SDMMC1RST

Bit 22: SDMMC1 reset.

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI2RST
rw 		FMCRST
rw
Toggle fields

FMCRST

Bit 0: Flexible memory controller reset.

OSPI2RST

Bit 9: OctOSPI2 memory interface reset.

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1RST
rw 		OPAMPRST
rw 		DAC1RST
rw 		PWRRST
rw 		CAN1RST
rw 		CRSRST
rw 		I2C3RST
rw 		I2C2RST
rw 		I2C1RST
rw 		UART5RST
rw 		UART4RST
rw 		USART3RST
rw 		USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw 		SPI2RST
rw 		TIM7RST
rw 		TIM6RST
rw 		TIM5RST
rw 		TIM4RST
rw 		TIM3RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2 timer reset.

TIM3RST

Bit 1: TIM3 timer reset.

TIM4RST

Bit 2: TIM3 timer reset.

TIM5RST

Bit 3: TIM5 timer reset.

TIM6RST

Bit 4: TIM6 timer reset.

TIM7RST

Bit 5: TIM7 timer reset.

SPI2RST

Bit 14: SPI2 reset.

SPI3RST

Bit 15: SPI3 reset.

USART2RST

Bit 17: USART2 reset.

USART3RST

Bit 18: USART3 reset.

UART4RST

Bit 19: UART4 reset.

UART5RST

Bit 20: UART5 reset.

I2C1RST

Bit 21: I2C1 reset.

I2C2RST

Bit 22: I2C2 reset.

I2C3RST

Bit 23: I2C3 reset.

CRSRST

Bit 24: CRS reset.

CAN1RST

Bit 25: CAN1 reset.

PWRRST

Bit 28: Power interface reset.

DAC1RST

Bit 29: DAC1 interface reset.

OPAMPRST

Bit 30: OPAMP interface reset.

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM2RST
rw 		I2C4RST
rw 		LPUART1RST
rw
Toggle fields

LPUART1RST

Bit 0: Low-power UART 1 reset.

I2C4RST

Bit 1: I2C4 reset.

LPTIM2RST

Bit 5: Low-power timer 2 reset.

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSIRST
rw 		LTDCRST
rw 		DFSDM1RST
rw 		SAI2RST
rw 		SAI1RST
rw 		TIM17RST
rw 		TIM16RST
rw 		TIM15RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		TIM8RST
rw 		SPI1RST
rw 		TIM1RST
rw 		SYSCFGRST
rw
Toggle fields

SYSCFGRST

Bit 0: System configuration (SYSCFG) reset.

TIM1RST

Bit 11: TIM1 timer reset.

SPI1RST

Bit 12: SPI1 reset.

TIM8RST

Bit 13: TIM8 timer reset.

USART1RST

Bit 14: USART1 reset.

TIM15RST

Bit 16: TIM15 timer reset.

TIM16RST

Bit 17: TIM16 timer reset.

TIM17RST

Bit 18: TIM17 timer reset.

SAI1RST

Bit 21: Serial audio interface 1 (SAI1) reset.

SAI2RST

Bit 22: Serial audio interface 2 (SAI2) reset.

DFSDM1RST

Bit 24: Digital filters for sigma-delata modulators (DFSDM) reset.

LTDCRST

Bit 26: LCD-TFT reset.

DSIRST

Bit 27: DSI reset.

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, size: 32, reset: 0x00000100, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GFXMMUEN
rw 		DMA2DEN
rw 		TSCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		FLASHEN
rw 		DMAMUX1EN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1 clock enable.

DMA2EN

Bit 1: DMA2 clock enable.

DMAMUX1EN

Bit 2: DMAMUX clock enable.

FLASHEN

Bit 8: Flash memory interface clock enable.

CRCEN

Bit 12: CRC clock enable.

TSCEN

Bit 16: Touch Sensing Controller clock enable.

DMA2DEN

Bit 17: DMA2D clock enable.

GFXMMUEN

Bit 18: Graphic MMU clock enable.

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1EN
rw 		OSPIMEN
rw 		RNGEN
rw 		HASHEN
rw 		AESEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCMIEN
rw 		ADCEN
rw 		OTGFSEN
rw 		GPIOIEN
rw 		GPIOHEN
rw 		GPIOGEN
rw 		GPIOFEN
rw 		GPIOEEN
rw 		GPIODEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: IO port A clock enable.

GPIOBEN

Bit 1: IO port B clock enable.

GPIOCEN

Bit 2: IO port C clock enable.

GPIODEN

Bit 3: IO port D clock enable.

GPIOEEN

Bit 4: IO port E clock enable.

GPIOFEN

Bit 5: IO port F clock enable.

GPIOGEN

Bit 6: IO port G clock enable.

GPIOHEN

Bit 7: IO port H clock enable.

GPIOIEN

Bit 8: IO port I clock enable.

OTGFSEN

Bit 12: OTG full speed clock enable.

ADCEN

Bit 13: ADC clock enable.

Allowed values:
0: Disabled: ADC clock disabled
1: Enabled: ADC clock enabled

DCMIEN

Bit 14: DCMI clock enable.

AESEN

Bit 16: AES accelerator clock enable.

HASHEN

Bit 17: HASH clock enable.

RNGEN

Bit 18: Random Number Generator clock enable.

OSPIMEN

Bit 20: OctoSPI IO manager clock enable.

SDMMC1EN

Bit 22: SDMMC1 clock enable.

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI2EN
rw 		FMCEN
rw
Toggle fields

FMCEN

Bit 0: Flexible memory controller clock enable.

OSPI2EN

Bit 9: OSPI2EN memory interface clock enable.

APB1ENR1

APB1ENR1

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

4/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw 		OPAMPEN
rw 		DAC1EN
rw 		PWREN
rw 		CAN1EN
rw 		CRSEN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		UART5EN
rw 		UART4EN
rw 		USART3EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3EN
rw 		SPI2EN
rw 		WWDGEN
rw 		RTCAPBEN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2 timer clock enable.

TIM3EN

Bit 1: TIM3 timer clock enable.

TIM4EN

Bit 2: TIM4 timer clock enable.

TIM5EN

Bit 3: TIM5 timer clock enable.

TIM6EN

Bit 4: TIM6 timer clock enable.

TIM7EN

Bit 5: TIM7 timer clock enable.

RTCAPBEN

Bit 10: RTC APB clock enable.

WWDGEN

Bit 11: Window watchdog clock enable.

SPI2EN

Bit 14: SPI2 clock enable.

SPI3EN

Bit 15: SPI peripheral 3 clock enable.

USART2EN

Bit 17: USART2 clock enable.

USART3EN

Bit 18: USART3 clock enable.

UART4EN

Bit 19: UART4 clock enable.

UART5EN

Bit 20: UART5 clock enable.

I2C1EN

Bit 21: I2C1 clock enable.

Allowed values:
0: Disabled: I2C1 clock disabled
1: Enabled: I2C1 clock enabled

I2C2EN

Bit 22: I2C2 clock enable.

Allowed values:
0: Disabled: I2C2 clock disabled
1: Enabled: I2C2 clock enabled

I2C3EN

Bit 23: I2C3 clock enable.

Allowed values:
0: Disabled: I2C3 clock disabled
1: Enabled: I2C3 clock enabled

CRSEN

Bit 24: Clock Recovery System clock enable.

CAN1EN

Bit 25: CAN1 clock enable.

PWREN

Bit 28: Power interface clock enable.

DAC1EN

Bit 29: DAC1 interface clock enable.

OPAMPEN

Bit 30: OPAMP interface clock enable.

LPTIM1EN

Bit 31: Low power timer 1 clock enable.

Allowed values:
0: Disabled: LPTIM1 clock disabled
1: Enabled: LPTIM1 clock enabled

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM2EN
rw 		I2C4EN
rw 		LPUART1EN
rw
Toggle fields

LPUART1EN

Bit 0: Low power UART 1 clock enable.

Allowed values:
0: Disabled: LPUART1 clock disabled
1: Enabled: LPUART1 clock enabled

I2C4EN

Bit 1: I2C4 clock enable.

LPTIM2EN

Bit 5: LPTIM2EN.

Allowed values:
0: Disabled: LPTIM2 clock disabled
1: Enabled: LPTIM2 clock enabled

APB2ENR

APB2ENR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

1/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSIEN
rw 		LTDCEN
rw 		DFSDM1EN
rw 		SAI2EN
rw 		SAI1EN
rw 		TIM17EN
rw 		TIM16EN
rw 		TIM15EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw 		TIM8EN
rw 		SPI1EN
rw 		TIM1EN
rw 		FWEN
rw 		SYSCFGEN
rw
Toggle fields

SYSCFGEN

Bit 0: SYSCFG clock enable.

FWEN

Bit 7: Firewall clock enable.

TIM1EN

Bit 11: TIM1 timer clock enable.

SPI1EN

Bit 12: SPI1 clock enable.

TIM8EN

Bit 13: TIM8 timer clock enable.

USART1EN

Bit 14: USART1clock enable.

Allowed values:
0: Disabled: USART1 clock disabled
1: Enabled: USART1 clock enabled

TIM15EN

Bit 16: TIM15 timer clock enable.

TIM16EN

Bit 17: TIM16 timer clock enable.

TIM17EN

Bit 18: TIM17 timer clock enable.

SAI1EN

Bit 21: SAI1 clock enable.

SAI2EN

Bit 22: SAI2 clock enable.

DFSDM1EN

Bit 24: DFSDM timer clock enable.

LTDCEN

Bit 26: LCD-TFT clock enable.

DSIEN

Bit 27: DSI clock enable.

AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x68, size: 32, reset: 0x00011303, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GFXMMUSMEN
rw 		DMA2DSMEN
rw 		TSCSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw 		SRAM1SMEN
rw 		FLASHSMEN
rw 		DMAMUX1SMEN
rw 		DMA2SMEN
rw 		DMA1SMEN
rw
Toggle fields

DMA1SMEN

Bit 0: DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: DMA2 clocks enable during Sleep and Stop modes.

DMAMUX1SMEN

Bit 2: DMAMUX clock enable during Sleep and Stop modes.

FLASHSMEN

Bit 8: Flash memory interface clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: SRAM1 interface clocks enable during Sleep and Stop modes.

CRCSMEN

Bit 12: CRCSMEN.

TSCSMEN

Bit 16: Touch Sensing Controller clocks enable during Sleep and Stop modes.

DMA2DSMEN

Bit 17: DMA2D clock enable during Sleep and Stop modes.

GFXMMUSMEN

Bit 18: GFXMMU clock enable during Sleep and Stop modes.

AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x6c, size: 32, reset: 0x000532FF, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SMEN
rw 		OSPIMSMEN
rw 		RNGSMEN
rw 		HASHSMEN
rw 		AESSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCMISMEN
rw 		ADCFSSMEN
rw 		OTGFSSMEN
rw 		SRAM3SMEN
rw 		SRAM2SMEN
rw 		GPIOISMEN
rw 		GPIOHSMEN
rw 		GPIOGSMEN
rw 		GPIOFSMEN
rw 		GPIOESMEN
rw 		GPIODSMEN
rw 		GPIOCSMEN
rw 		GPIOBSMEN
rw 		GPIOASMEN
rw
Toggle fields

GPIOASMEN

Bit 0: IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: IO port E clocks enable during Sleep and Stop modes.

GPIOFSMEN

Bit 5: IO port F clocks enable during Sleep and Stop modes.

GPIOGSMEN

Bit 6: IO port G clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: IO port H clocks enable during Sleep and Stop modes.

GPIOISMEN

Bit 8: IO port I clocks enable during Sleep and Stop modes.

SRAM2SMEN

Bit 9: SRAM2 interface clocks enable during Sleep and Stop modes.

SRAM3SMEN

Bit 10: SRAM2 interface clocks enable during Sleep and Stop modes.

OTGFSSMEN

Bit 12: OTG full speed clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: ADC clocks enable during Sleep and Stop modes.

DCMISMEN

Bit 14: DCMI clock enable during Sleep and Stop modes.

AESSMEN

Bit 16: AES accelerator clocks enable during Sleep and Stop modes.

HASHSMEN

Bit 17: HASH clock enable during Sleep and Stop modes.

RNGSMEN

Bit 18: Random Number Generator clocks enable during Sleep and Stop modes.

OSPIMSMEN

Bit 20: OctoSPI IO manager clocks enable during Sleep and Stop modes.

SDMMC1SMEN

Bit 22: SDMMC1 clocks enable during Sleep and Stop modes.

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, size: 32, reset: 0x00000101, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTOSPI2
rw 		FMCSMEN
rw
Toggle fields

FMCSMEN

Bit 0: Flexible memory controller clocks enable during Sleep and Stop modes.

OCTOSPI2

Bit 9: OctoSPI2 memory interface clocks enable during Sleep and Stop modes.

APB1SMENR1

APB1SMENR1

Offset: 0x78, size: 32, reset: 0xF2FECA3F, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SMEN
rw 		OPAMPSMEN
rw 		DAC1SMEN
rw 		PWRSMEN
rw 		CAN1SMEN
rw 		CRSSMEN
rw 		I2C3SMEN
rw 		I2C2SMEN
rw 		I2C1SMEN
rw 		UART5SMEN
rw 		UART4SMEN
rw 		USART3SMEN
rw 		USART2SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP3SMEN
rw 		SPI2SMEN
rw 		WWDGSMEN
rw 		RTCAPBSMEN
rw 		TIM7SMEN
rw 		TIM6SMEN
rw 		TIM5SMEN
rw 		TIM4SMEN
rw 		TIM3SMEN
rw 		TIM2SMEN
rw
Toggle fields

TIM2SMEN

Bit 0: TIM2 timer clocks enable during Sleep and Stop modes.

TIM3SMEN

Bit 1: TIM3 timer clocks enable during Sleep and Stop modes.

TIM4SMEN

Bit 2: TIM4 timer clocks enable during Sleep and Stop modes.

TIM5SMEN

Bit 3: TIM5 timer clocks enable during Sleep and Stop modes.

TIM6SMEN

Bit 4: TIM6 timer clocks enable during Sleep and Stop modes.

TIM7SMEN

Bit 5: TIM7 timer clocks enable during Sleep and Stop modes.

RTCAPBSMEN

Bit 10: RTC APB clock enable during Sleep and Stop modes.

WWDGSMEN

Bit 11: Window watchdog clocks enable during Sleep and Stop modes.

SPI2SMEN

Bit 14: SPI2 clocks enable during Sleep and Stop modes.

SP3SMEN

Bit 15: SPI3 clocks enable during Sleep and Stop modes.

USART2SMEN

Bit 17: USART2 clocks enable during Sleep and Stop modes.

USART3SMEN

Bit 18: USART3 clocks enable during Sleep and Stop modes.

UART4SMEN

Bit 19: UART4 clocks enable during Sleep and Stop modes.

UART5SMEN

Bit 20: UART5 clocks enable during Sleep and Stop modes.

I2C1SMEN

Bit 21: I2C1 clocks enable during Sleep and Stop modes.

I2C2SMEN

Bit 22: I2C2 clocks enable during Sleep and Stop modes.

I2C3SMEN

Bit 23: I2C3 clocks enable during Sleep and Stop modes.

CRSSMEN

Bit 24: CRS clock enable during Sleep and Stop modes.

CAN1SMEN

Bit 25: CAN1 clocks enable during Sleep and Stop modes.

PWRSMEN

Bit 28: Power interface clocks enable during Sleep and Stop modes.

DAC1SMEN

Bit 29: DAC1 interface clocks enable during Sleep and Stop modes.

OPAMPSMEN

Bit 30: OPAMP interface clocks enable during Sleep and Stop modes.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during Sleep and Stop modes.

APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x7c, size: 32, reset: 0x00000025, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM2SMEN
rw 		I2C4SMEN
rw 		LPUART1SMEN
rw
Toggle fields

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during Sleep and Stop modes.

I2C4SMEN

Bit 1: I2C4 clocks enable during Sleep and Stop modes.

LPTIM2SMEN

Bit 5: LPTIM2SMEN.

APB2SMENR

APB2SMENR

Offset: 0x80, size: 32, reset: 0x01677C01, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSISMEN
rw 		LTDCSMEN
rw 		DFSDM1SMEN
rw 		SAI2SMEN
rw 		SAI1SMEN
rw 		TIM17SMEN
rw 		TIM16SMEN
rw 		TIM15SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw 		TIM8SMEN
rw 		SPI1SMEN
rw 		TIM1SMEN
rw 		SYSCFGSMEN
rw
Toggle fields

SYSCFGSMEN

Bit 0: SYSCFG clocks enable during Sleep and Stop modes.

TIM1SMEN

Bit 11: TIM1 timer clocks enable during Sleep and Stop modes.

SPI1SMEN

Bit 12: SPI1 clocks enable during Sleep and Stop modes.

TIM8SMEN

Bit 13: TIM8 timer clocks enable during Sleep and Stop modes.

USART1SMEN

Bit 14: USART1clocks enable during Sleep and Stop modes.

TIM15SMEN

Bit 16: TIM15 timer clocks enable during Sleep and Stop modes.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during Sleep and Stop modes.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during Sleep and Stop modes.

SAI1SMEN

Bit 21: SAI1 clocks enable during Sleep and Stop modes.

SAI2SMEN

Bit 22: SAI2 clocks enable during Sleep and Stop modes.

DFSDM1SMEN

Bit 24: DFSDM timer clocks enable during Sleep and Stop modes.

LTDCSMEN

Bit 26: LCD-TFT timer clocks enable during Sleep and Stop modes.

DSISMEN

Bit 27: DSI clocks enable during Sleep and Stop modes.

CCIPR

CCIPR

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

11/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCSEL
rw 		CLK48SEL
rw 		SAI2SEL
rw 		SAI1SEL
rw 		LPTIM2SEL
rw 		LPTIM1SEL
rw 		I2C3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw 		I2C1SEL
rw 		LPUART1SEL
rw 		UART5SEL
rw 		UART4SEL
rw 		USART3SEL
rw 		USART2SEL
rw 		USART1SEL
rw
Toggle fields

USART1SEL

Bits 0-1: USART1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

USART2SEL

Bits 2-3: USART2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

USART3SEL

Bits 4-5: USART3 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

UART4SEL

Bits 6-7: UART4 clock source selection.

UART5SEL

Bits 8-9: UART5 clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

I2C1SEL

Bits 12-13: I2C1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

I2C2SEL

Bits 14-15: I2C2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

I2C3SEL

Bits 16-17: I2C3 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: SYSCLK: SYSCLK clock selected
2: HSI16: HSI16 clock selected

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

Allowed values:
0: PCLK: PCLK clock selected
1: LSI: LSI clock selected
2: HSI16: HSI16 clock selected
3: LSE: LSE clock selected

SAI1SEL

Bits 22-23: SAI1 clock source selection.

SAI2SEL

Bits 24-25: SAI2 clock source selection.

CLK48SEL

Bits 26-27: 48 MHz clock source selection.

Allowed values:
0: HSI48: HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)
1: PLLSAI1: PLLSAI1 clock selected
2: PLL: PLL clock selected
3: MSI: MSI clock selected

ADCSEL

Bits 28-29: ADCs clock source selection.

Allowed values:
0: NoClock: No clock selected
1: PLLSAI1: PLLSAI1 clock selected
2: PLLSAI2: PLLSAI2 clock selected (only for STM32L47x/L48x/L49x/L4Ax devices)
3: SYSCLK: SYSCLK clock selected

BDCR

BDCR

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

4/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOSEL
rw 		LSCOEN
rw 		BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		RTCSEL
rw 		LSECSSD
r 		LSECSSON
rw 		LSEDRV
rw 		LSEBYP
rw 		LSERDY
r 		LSEON
rw
Toggle fields

LSEON

Bit 0: LSE oscillator enable.

LSERDY

Bit 1: LSE oscillator ready.

LSEBYP

Bit 2: LSE oscillator bypass.

LSEDRV

Bits 3-4: SE oscillator drive capability.

LSECSSON

Bit 5: LSECSSON.

LSECSSD

Bit 6: LSECSSD.

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock selected
2: LSI: LSI oscillator clock selected
3: HSE: HSE oscillator clock divided by 32 selected

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

LSCOEN

Bit 24: Low speed clock output enable.

LSCOSEL

Bit 25: Low speed clock output selection.

CSR

CSR

Offset: 0x94, size: 32, reset: 0x0C000600, access: Unspecified

9/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRSTF
r 		WWDGRSTF
r 		IWDGRSTF
r 		SFTRSTF
r 		BORRSTF
r 		PINRSTF
r 		OBLRSTF
r 		FWRSTF
r 		RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSISRANGE
rw 		LSIRDY
r 		LSION
rw
Toggle fields

LSION

Bit 0: LSI oscillator enable.

LSIRDY

Bit 1: LSI oscillator ready.

MSISRANGE

Bits 8-11: SI range after Standby mode.

RMVF

Bit 23: Remove reset flag.

FWRSTF

Bit 24: Firewall reset flag.

OBLRSTF

Bit 25: Option byte loader reset flag.

PINRSTF

Bit 26: Pin reset flag.

BORRSTF

Bit 27: BOR flag.

SFTRSTF

Bit 28: Software reset flag.

IWDGRSTF

Bit 29: Independent window watchdog reset flag.

WWDGRSTF

Bit 30: Window watchdog reset flag.

LPWRSTF

Bit 31: Low-power reset flag.

CRRCR

Clock recovery RC register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48CAL
r 		HSI48RDY
r 		HSI48ON
rw
Toggle fields

HSI48ON

Bit 0: HSI48 clock enable.

HSI48RDY

Bit 1: HSI48 clock ready flag.

HSI48CAL

Bits 7-15: HSI48 clock calibration.

CCIPR2

Peripherals independent clock configuration register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPISEL
rw 		PLLSAI2DIVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMCSEL
rw 		DSISEL
rw 		SAI2SEL
rw 		SAI1SEL
rw 		ADFSDMSEL
rw 		DFSDMSEL
rw 		I2C4SEL
rw
Toggle fields

I2C4SEL

Bits 0-1: I2C4 clock source selection.

DFSDMSEL

Bit 2: Digital filter for sigma delta modulator kernel clock source selection.

ADFSDMSEL

Bits 3-4: Digital filter for sigma delta modulator audio clock source selection.

SAI1SEL

Bits 5-7: SAI1 clock source selection.

SAI2SEL

Bits 8-10: SAI2 clock source selection.

DSISEL

Bit 12: clock selection.

SDMMCSEL

Bit 14: SDMMC clock selection.

PLLSAI2DIVR

Bits 16-17: division factor for LTDC clock.

OSPISEL

Bits 20-21: Octospi clock source selection.

RNG

0x50060800: Random number generator

4/8 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IE
rw 		RNGEN
rw
Toggle fields

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw 		CEIS
rw 		SECS
r 		CECS
r 		DRDY
r
Toggle fields

DRDY

Bit 0: Data ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: Random data.

RTC

0x40002800: Real-time clock

8/165 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 CR
0xc ISR
0x10 PRER
0x14 WUTR
0x1c ALRM[A]R
0x20 ALRM[B]R
0x24 WPR
0x28 SSR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x3c CALR
0x40 TAMPCR
0x44 ALRM[A]SSR
0x48 ALRM[B]SSR
0x4c OR
0x50 BKP[0]R
0x54 BKP[1]R
0x58 BKP[2]R
0x5c BKP[3]R
0x60 BKP[4]R
0x64 BKP[5]R
0x68 BKP[6]R
0x6c BKP[7]R
0x70 BKP[8]R
0x74 BKP[9]R
0x78 BKP[10]R
0x7c BKP[11]R
0x80 BKP[12]R
0x84 BKP[13]R
0x88 BKP[14]R
0x8c BKP[15]R
0x90 BKP[16]R
0x94 BKP[17]R
0x98 BKP[18]R
0x9c BKP[19]R
0xa0 BKP[20]R
0xa4 BKP[21]R
0xa8 BKP[22]R
0xac BKP[23]R
0xb0 BKP[24]R
0xb4 BKP[25]R
0xb8 BKP[26]R
0xbc BKP[27]R
0xc0 BKP[28]R
0xc4 BKP[29]R
0xc8 BKP[30]R
0xcc BKP[31]R
Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITSE
rw 		COE
rw 		OSEL
rw 		POL
rw 		COSEL
rw 		BKP
rw 		SUB1H
rw 		ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALRBIE
rw 		ALRAIE
rw 		TSE
rw 		WUTE
rw 		ALRBE
rw 		ALRAE
rw 		FMT
rw 		BYPSHAD
rw 		REFCKON
rw 		TSEDGE
rw 		WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: Wakeup clock selection.

TSEDGE

Bit 3: Time-stamp event active edge.

REFCKON

Bit 4: Reference clock detection enable (50 or 60 Hz).

BYPSHAD

Bit 5: Bypass the shadow registers.

FMT

Bit 6: Hour format.

ALRAE

Bit 8: Alarm A enable.

ALRBE

Bit 9: Alarm B enable.

WUTE

Bit 10: Wakeup timer enable.

TSE

Bit 11: Time stamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

ALRBIE

Bit 13: Alarm B interrupt enable.

WUTIE

Bit 14: Wakeup timer interrupt enable.

TSIE

Bit 15: Time-stamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change).

SUB1H

Bit 17: Subtract 1 hour (winter time change).

BKP

Bit 18: Backup.

COSEL

Bit 19: Calibration output selection.

POL

Bit 20: Output polarity.

OSEL

Bits 21-22: Output selection.

COE

Bit 23: Calibration output enable.

ITSE

Bit 24: timestamp on internal event enable.

ISR

initialization and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

6/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3F
rw 		TAMP2F
rw 		TAMP1F
rw 		TSOVF
rw 		TSF
rw 		WUTF
rw 		ALRBF
rw 		ALRAF
rw 		INIT
rw 		INITF
r 		RSF
rw 		INITS
r 		SHPF
rw 		WUTWF
r 		ALRBWF
r 		ALRAWF
r
Toggle fields

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

ALRAF

Bit 8: Alarm A flag.

ALRBF

Bit 9: Alarm B flag.

WUTF

Bit 10: Wakeup timer flag.

TSF

Bit 11: Time-stamp flag.

TSOVF

Bit 12: Time-stamp overflow flag.

TAMP1F

Bit 13: Tamper detection flag.

TAMP2F

Bit 14: RTC_TAMP2 detection flag.

TAMP3F

Bit 15: RTC_TAMP3 detection flag.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

ALRM[A]R

Alarm A register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

ALRM[B]R

Alarm B register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

SSR

sub second register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value.

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: Sub second value.

CALR

calibration register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

TAMPCR

tamper configuration register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP3MF
rw 		TAMP3NOERASE
rw 		TAMP3IE
rw 		TAMP2MF
rw 		TAMP2NOERASE
rw 		TAMP2IE
rw 		TAMP1MF
rw 		TAMP1NOERASE
rw 		TAMP1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw 		TAMPTS
rw 		TAMP3TRG
rw 		TAMP3E
rw 		TAMP2TRG
rw 		TAMP2E
rw 		TAMPIE
rw 		TAMP1TRG
rw 		TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1TRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP2E

Bit 3: Tamper 2 detection enable.

TAMP2TRG

Bit 4: Active level for tamper 2.

TAMP3E

Bit 5: Tamper 3 detection enable.

TAMP3TRG

Bit 6: Active level for tamper 3.

TAMPTS

Bit 7: Activate timestamp on tamper detection event.

TAMPFREQ

Bits 8-10: Tamper sampling frequency.

TAMPFLT

Bits 11-12: Tamper filter count.

TAMPPRCH

Bits 13-14: Tamper precharge duration.

TAMPPUDIS

Bit 15: TAMPER pull-up disable.

TAMP1IE

Bit 16: Tamper 1 interrupt enable.

TAMP1NOERASE

Bit 17: Tamper 1 no erase.

TAMP1MF

Bit 18: Tamper 1 mask flag.

TAMP2IE

Bit 19: Tamper 2 interrupt enable.

TAMP2NOERASE

Bit 20: Tamper 2 no erase.

TAMP2MF

Bit 21: Tamper 2 mask flag.

TAMP3IE

Bit 22: Tamper 3 interrupt enable.

TAMP3NOERASE

Bit 23: Tamper 3 no erase.

TAMP3MF

Bit 24: Tamper 3 mask flag.

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

OR

option register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC_OUT_RMP
rw 		RTC_ALARM_TYPE
rw
Toggle fields

RTC_ALARM_TYPE

Bit 0: RTC_ALARM on PC13 output type.

RTC_OUT_RMP

Bit 1: RTC_OUT remap.

BKP[0]R

backup register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[1]R

backup register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[2]R

backup register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[3]R

backup register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[4]R

backup register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[5]R

backup register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[6]R

backup register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[7]R

backup register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[8]R

backup register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[9]R

backup register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[10]R

backup register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[11]R

backup register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[12]R

backup register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[13]R

backup register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[14]R

backup register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[15]R

backup register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[16]R

backup register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[17]R

backup register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[18]R

backup register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[19]R

backup register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[20]R

backup register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[21]R

backup register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[22]R

backup register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[23]R

backup register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[24]R

backup register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[25]R

backup register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[26]R

backup register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[27]R

backup register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[28]R

backup register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[29]R

backup register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[30]R

backup register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[31]R

backup register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

SAI1

0x40015400: Serial audio interface

84/102 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
Toggle registers

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

SAI2

0x40015800: Serial audio interface

84/102 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
Toggle registers

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

SCB

0xe000ed00: System control block

5/74 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CPUID
0x4 ICSR
0x8 VTOR
0xc AIRCR
0x10 SCR
0x14 CCR
0x18 SHPR1
0x1c SHPR2
0x20 SHPR3
0x24 SHCSR
0x28 CFSR_UFSR_BFSR_MMFSR
0x2c HFSR
0x34 MMFAR
0x38 BFAR
0x3c AFSR
Toggle registers

CPUID

CPUID base register

Offset: 0x0, size: 32, reset: 0x410FC241, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Implementer
r 		Variant
r 		Constant
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PartNo
r 		Revision
r
Toggle fields

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIPENDSET
rw 		PENDSVSET
rw 		PENDSVCLR
rw 		PENDSTSET
rw 		PENDSTCLR
rw 		ISRPENDING
rw 		VECTPENDING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTPENDING
rw 		RETTOBASE
rw 		VECTACTIVE
rw
Toggle fields

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBLOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBLOFF
rw
Toggle fields

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEYSTAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIANESS
rw 		PRIGROUP
rw 		SYSRESETREQ
rw 		VECTCLRACTIVE
rw 		VECTRESET
rw
Toggle fields

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEVEONPEND
rw 		SLEEPDEEP
rw 		SLEEPONEXIT
rw
Toggle fields

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKALIGN
rw 		BFHFNMIGN
rw 		DIV_0_TRP
rw 		UNALIGN__TRP
rw 		USERSETMPEND
rw 		NONBASETHRDENA
rw
Toggle fields

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_5
rw 		PRI_4
rw
Toggle fields

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_15
rw 		PRI_14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCSR

System handler control and state register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USGFAULTENA
rw 		BUSFAULTENA
rw 		MEMFAULTENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVCALLPENDED
rw 		BUSFAULTPENDED
rw 		MEMFAULTPENDED
rw 		USGFAULTPENDED
rw 		SYSTICKACT
rw 		PENDSVACT
rw 		MONITORACT
rw 		SVCALLACT
rw 		USGFAULTACT
rw 		BUSFAULTACT
rw 		MEMFAULTACT
rw
Toggle fields

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVBYZERO
rw 		UNALIGNED
rw 		NOCP
rw 		INVPC
rw 		INVSTATE
rw 		UNDEFINSTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFARVALID
rw 		LSPERR
rw 		STKERR
rw 		UNSTKERR
rw 		IMPRECISERR
rw 		PRECISERR
rw 		IBUSERR
rw 		MMARVALID
rw 		MLSPERR
rw 		MSTKERR
rw 		MUNSTKERR
rw 		IACCVIOL
rw
Toggle fields

IACCVIOL

Bit 1: Instruction access violation flag.

MUNSTKERR

Bit 3: Memory manager fault on unstacking for a return from exception.

MSTKERR

Bit 4: Memory manager fault on stacking for exception entry..

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: Memory Management Fault Address Register (MMAR) valid flag.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUG_VT
rw 		FORCED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTTBL
rw
Toggle fields

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMFAR
rw
Toggle fields

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFAR
rw
Toggle fields

BFAR

Bits 0-31: Bus fault address.

AFSR

Auxiliary fault status register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMPDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMPDEF
rw
Toggle fields

IMPDEF

Bits 0-31: Implementation defined.

SCB_ACTRL

0xe000e008: System control block ACTLR

0/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACTRL
Toggle registers

ACTRL

Auxiliary control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISOOFP
rw 		DISFPCA
rw 		DISFOLD
rw 		DISDEFWBUF
rw 		DISMCYCINT
rw
Toggle fields

DISMCYCINT

Bit 0: DISMCYCINT.

DISDEFWBUF

Bit 1: DISDEFWBUF.

DISFOLD

Bit 2: DISFOLD.

DISFPCA

Bit 8: DISFPCA.

DISOOFP

Bit 9: DISOOFP.

SDMMC1

0x50062400: Secure digital input/output interface

31/98 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARG
0xc CMD
0x10 RESPCMD
0x14 RESP1
0x18 RESP2
0x1c RESP3
0x20 RESP4
0x24 DTIMER
0x28 DLEN
0x2c DCTRL
0x30 DCOUNT
0x34 STA
0x38 ICR
0x3c MASK
0x48 FIFOCNT
0x80 FIFO
Toggle registers

POWER

power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: PWRCTRL.

CLKCR

SDI clock control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWFC_EN
rw 		NEGEDGE
rw 		WIDBUS
rw 		BYPASS
rw 		PWRSAV
rw 		CLKEN
rw 		CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-7: Clock divide factor.

CLKEN

Bit 8: Clock enable bit.

PWRSAV

Bit 9: Power saving configuration bit.

BYPASS

Bit 10: Clock divider bypass enable bit.

WIDBUS

Bits 11-12: Wide bus mode enable bit.

NEGEDGE

Bit 13: SDIO_CK dephasing selection bit.

HWFC_EN

Bit 14: HW Flow Control enable.

ARG

argument register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument.

CMD

command register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CE_ATACMD
rw 		nIEN
rw 		ENCMDcompl
rw 		SDIOSuspend
rw 		CPSMEN
rw 		WAITPEND
rw 		WAITINT
rw 		WAITRESP
rw 		CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: Command index.

WAITRESP

Bits 6-7: Wait for response bits.

WAITINT

Bit 8: CPSM waits for interrupt request.

WAITPEND

Bit 9: CPSM Waits for ends of data transfer (CmdPend internal signal).

CPSMEN

Bit 10: Command path state machine (CPSM) Enable bit.

SDIOSuspend

Bit 11: SD I/O suspend command.

ENCMDcompl

Bit 12: Enable CMD completion.

nIEN

Bit 13: not Interrupt Enable.

CE_ATACMD

Bit 14: CE-ATA command.

RESPCMD

command response register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1

response 1..4 register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: see Table 132.

RESP2

response 1..4 register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: see Table 132.

RESP3

response 1..4 register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: see Table 132.

RESP4

response 1..4 register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: see Table 132.

DTIMER

data timer register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: Data timeout period.

DLEN

data length register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: Data length value.

DCTRL

data control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw 		RWMOD
rw 		RWSTOP
rw 		RWSTART
rw 		DBLOCKSIZE
rw 		DMAEN
rw 		DTMODE
rw 		DTDIR
rw 		DTEN
rw
Toggle fields

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: Data transfer direction selection.

DTMODE

Bit 2: Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

DMAEN

Bit 3: DMA enable bit.

DBLOCKSIZE

Bits 4-7: Data block size.

RWSTART

Bit 8: Read wait start.

RWSTOP

Bit 9: Read wait stop.

RWMOD

Bit 10: Read wait mode.

SDIOEN

Bit 11: SD I/O enable functions.

DCOUNT

data counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: Data count value.

STA

status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAEND
r 		SDIOIT
r 		RXDAVL
r 		TXDAVL
r 		RXFIFOE
r 		TXFIFOE
r 		RXFIFOF
r 		TXFIFOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHF
r 		TXFIFOHE
r 		RXACT
r 		TXACT
r 		CMDACT
r 		DBCKEND
r 		STBITERR
r 		DATAEND
r 		CMDSENT
r 		CMDREND
r 		RXOVERR
r 		TXUNDERR
r 		DTIMEOUT
r 		CTIMEOUT
r 		DCRCFAIL
r 		CCRCFAIL
r
Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed).

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed).

CTIMEOUT

Bit 2: Command response timeout.

DTIMEOUT

Bit 3: Data timeout.

TXUNDERR

Bit 4: Transmit FIFO underrun error.

RXOVERR

Bit 5: Received FIFO overrun error.

CMDREND

Bit 6: Command response received (CRC check passed).

CMDSENT

Bit 7: Command sent (no response required).

DATAEND

Bit 8: Data end (data counter, SDIDCOUNT, is zero).

STBITERR

Bit 9: Start bit not detected on all data signals in wide bus mode.

DBCKEND

Bit 10: Data block sent/received (CRC check passed).

CMDACT

Bit 11: Command transfer in progress.

TXACT

Bit 12: Data transmit in progress.

RXACT

Bit 13: Data receive in progress.

TXFIFOHE

Bit 14: Transmit FIFO half empty: at least 8 words can be written into the FIFO.

RXFIFOHF

Bit 15: Receive FIFO half full: there are at least 8 words in the FIFO.

TXFIFOF

Bit 16: Transmit FIFO full.

RXFIFOF

Bit 17: Receive FIFO full.

TXFIFOE

Bit 18: Transmit FIFO empty.

RXFIFOE

Bit 19: Receive FIFO empty.

TXDAVL

Bit 20: Data available in transmit FIFO.

RXDAVL

Bit 21: Data available in receive FIFO.

SDIOIT

Bit 22: SDIO interrupt received.

CEATAEND

Bit 23: CE-ATA command completion signal received for CMD61.

ICR

interrupt clear register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDC
rw 		SDIOITC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBCKENDC
rw 		STBITERRC
rw 		DATAENDC
rw 		CMDSENTC
rw 		CMDRENDC
rw 		RXOVERRC
rw 		TXUNDERRC
rw 		DTIMEOUTC
rw 		CTIMEOUTC
rw 		DCRCFAILC
rw 		CCRCFAILC
rw
Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit.

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit.

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit.

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit.

TXUNDERRC

Bit 4: TXUNDERR flag clear bit.

RXOVERRC

Bit 5: RXOVERR flag clear bit.

CMDRENDC

Bit 6: CMDREND flag clear bit.

CMDSENTC

Bit 7: CMDSENT flag clear bit.

DATAENDC

Bit 8: DATAEND flag clear bit.

STBITERRC

Bit 9: STBITERR flag clear bit.

DBCKENDC

Bit 10: DBCKEND flag clear bit.

SDIOITC

Bit 22: SDIOIT flag clear bit.

CEATAENDC

Bit 23: CEATAEND flag clear bit.

MASK

mask register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDIE
rw 		SDIOITIE
rw 		RXDAVLIE
rw 		TXDAVLIE
rw 		RXFIFOEIE
rw 		TXFIFOEIE
rw 		RXFIFOFIE
rw 		TXFIFOFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHFIE
rw 		TXFIFOHEIE
rw 		RXACTIE
rw 		TXACTIE
rw 		CMDACTIE
rw 		DBCKENDIE
rw 		STBITERRIE
rw 		DATAENDIE
rw 		CMDSENTIE
rw 		CMDRENDIE
rw 		RXOVERRIE
rw 		TXUNDERRIE
rw 		DTIMEOUTIE
rw 		CTIMEOUTIE
rw 		DCRCFAILIE
rw 		CCRCFAILIE
rw
Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable.

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable.

CTIMEOUTIE

Bit 2: Command timeout interrupt enable.

DTIMEOUTIE

Bit 3: Data timeout interrupt enable.

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable.

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable.

CMDRENDIE

Bit 6: Command response received interrupt enable.

CMDSENTIE

Bit 7: Command sent interrupt enable.

DATAENDIE

Bit 8: Data end interrupt enable.

STBITERRIE

Bit 9: Start bit error interrupt enable.

DBCKENDIE

Bit 10: Data block end interrupt enable.

CMDACTIE

Bit 11: Command acting interrupt enable.

TXACTIE

Bit 12: Data transmit acting interrupt enable.

RXACTIE

Bit 13: Data receive acting interrupt enable.

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable.

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable.

TXFIFOFIE

Bit 16: Tx FIFO full interrupt enable.

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable.

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable.

RXFIFOEIE

Bit 19: Rx FIFO empty interrupt enable.

TXDAVLIE

Bit 20: Data available in Tx FIFO interrupt enable.

RXDAVLIE

Bit 21: Data available in Rx FIFO interrupt enable.

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable.

CEATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCOUNT
r
Toggle fields

FIFOCOUNT

Bits 0-23: Remaining number of words to be written to or read from the FIFO.

FIFO

data FIFO register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOData
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOData
rw
Toggle fields

FIFOData

Bits 0-31: Receive and transmit FIFO data.

SPI1

0x40013000: Serial peripheral interface/Inter-IC sound

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SPI2

0x40003800: Serial peripheral interface/Inter-IC sound

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SPI3

0x40003c00: Serial peripheral interface/Inter-IC sound

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		DFF
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

STK

0xe000e010: SysTick timer

0/9 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTRL
0x4 LOAD
0x8 VAL
0xc CALIB
Toggle registers

CTRL

SysTick control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNTFLAG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSOURCE
rw 		TICKINT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD

SysTick reload value register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOAD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT
rw
Toggle fields

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOREF
rw 		SKEW
rw 		TENMS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TENMS
rw
Toggle fields

TENMS

Bits 0-23: Calibration value.

SKEW

Bit 30: SKEW flag: Indicates whether the TENMS value is exact.

NOREF

Bit 31: NOREF flag. Reads as zero.

SWPMI1

0x40008800: Single Wire Protocol Master Interface

13/38 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 BRR
0xc ISR
0x10 ICR
0x14 IER
0x18 RFL
0x1c TDR
0x20 RDR
Toggle registers

CR

SWPMI Configuration/Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEACT
rw 		SWPME
rw 		LPBK
rw 		TXMODE
rw 		RXMODE
rw 		TXDMA
rw 		RXDMA
rw
Toggle fields

RXDMA

Bit 0: Reception DMA enable.

TXDMA

Bit 1: Transmission DMA enable.

RXMODE

Bit 2: Reception buffering mode.

TXMODE

Bit 3: Transmission buffering mode.

LPBK

Bit 4: Loopback mode enable.

SWPME

Bit 5: Single wire protocol master interface enable.

DEACT

Bit 10: Single wire protocol master interface deactivate.

BRR

SWPMI Bitrate register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR
rw
Toggle fields

BR

Bits 0-5: Bitrate prescaler.

ISR

SWPMI Interrupt and Status register

Offset: 0xc, size: 32, reset: 0x000002C2, access: read-only

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEACTF
r 		SUSP
r 		SRF
r 		TCF
r 		TXE
r 		RXNE
r 		TXUNRF
r 		RXOVRF
r 		RXBERF
r 		TXBEF
r 		RXBFF
r
Toggle fields

RXBFF

Bit 0: Receive buffer full flag.

TXBEF

Bit 1: Transmit buffer empty flag.

RXBERF

Bit 2: Receive CRC error flag.

RXOVRF

Bit 3: Receive overrun error flag.

TXUNRF

Bit 4: Transmit underrun error flag.

RXNE

Bit 5: Receive data register not empty.

TXE

Bit 6: Transmit data register empty.

TCF

Bit 7: Transfer complete flag.

SRF

Bit 8: Slave resume flag.

SUSP

Bit 9: SUSPEND flag.

DEACTF

Bit 10: DEACTIVATED flag.

ICR

SWPMI Interrupt Flag Clear register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSRF
w 		CTCF
w 		CTXUNRF
w 		CRXOVRF
w 		CRXBERF
w 		CTXBEF
w 		CRXBFF
w
Toggle fields

CRXBFF

Bit 0: Clear receive buffer full flag.

CTXBEF

Bit 1: Clear transmit buffer empty flag.

CRXBERF

Bit 2: Clear receive CRC error flag.

CRXOVRF

Bit 3: Clear receive overrun error flag.

CTXUNRF

Bit 4: Clear transmit underrun error flag.

CTCF

Bit 7: Clear transfer complete flag.

CSRF

Bit 8: Clear slave resume flag.

IER

SWPMI Interrupt Enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRIE
rw 		TCIE
rw 		TIE
rw 		RIE
rw 		TXUNRIE
rw 		RXOVRIE
rw 		RXBERIE
rw 		TXBEIE
rw 		RXBFIE
rw
Toggle fields

RXBFIE

Bit 0: Receive buffer full interrupt enable.

TXBEIE

Bit 1: Transmit buffer empty interrupt enable.

RXBERIE

Bit 2: Receive CRC error interrupt enable.

RXOVRIE

Bit 3: Receive overrun error interrupt enable.

TXUNRIE

Bit 4: Transmit underrun error interrupt enable.

RIE

Bit 5: Receive interrupt enable.

TIE

Bit 6: Transmit interrupt enable.

TCIE

Bit 7: Transmit complete interrupt enable.

SRIE

Bit 8: Slave resume interrupt enable.

RFL

SWPMI Receive Frame Length register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFL
r
Toggle fields

RFL

Bits 0-4: Receive frame length.

TDR

SWPMI Transmit data register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TD
w
Toggle fields

TD

Bits 0-31: Transmit data.

RDR

SWPMI Receive data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD
r
Toggle fields

RD

Bits 0-31: received data.

SYSCFG

0x40010000: System configuration controller

1/69 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MEMRMP
0x4 CFGR1
0x8 EXTICR1
0xc EXTICR2
0x10 EXTICR3
0x14 EXTICR4
0x18 SCSR
0x1c CFGR2
0x20 SWPR
0x24 SKR
Toggle registers

MEMRMP

memory remap register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB_MODE
rw 		QFS
rw 		MEM_MODE
rw
Toggle fields

MEM_MODE

Bits 0-2: Memory mapping selection.

QFS

Bit 3: QUADSPI memory mapping swap.

FB_MODE

Bit 8: Flash Bank mode selection.

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x7C000001, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPU_IE
rw 		I2C3_FMP
rw 		I2C2_FMP
rw 		I2C1_FMP
rw 		I2C_PB9_FMP
rw 		I2C_PB8_FMP
rw 		I2C_PB7_FMP
rw 		I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOSTEN
rw 		FWDIS
rw
Toggle fields

FWDIS

Bit 0: Firewall disable.

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C2_FMP

Bit 21: I2C2 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

FPU_IE

Bits 26-31: Floating Point Unit interrupts enable bits.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw 		EXTI2
rw 		EXTI1
rw 		EXTI0
rw
Toggle fields

EXTI0

Bits 0-2: EXTI 0 configuration bits.

EXTI1

Bits 4-6: EXTI 1 configuration bits.

EXTI2

Bits 8-10: EXTI 2 configuration bits.

EXTI3

Bits 12-14: EXTI 3 configuration bits.

EXTICR2

external interrupt configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw 		EXTI6
rw 		EXTI5
rw 		EXTI4
rw
Toggle fields

EXTI4

Bits 0-2: EXTI 4 configuration bits.

EXTI5

Bits 4-6: EXTI 5 configuration bits.

EXTI6

Bits 8-10: EXTI 6 configuration bits.

EXTI7

Bits 12-14: EXTI 7 configuration bits.

EXTICR3

external interrupt configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw 		EXTI10
rw 		EXTI9
rw 		EXTI8
rw
Toggle fields

EXTI8

Bits 0-2: EXTI 8 configuration bits.

EXTI9

Bits 4-6: EXTI 9 configuration bits.

EXTI10

Bits 8-10: EXTI 10 configuration bits.

EXTI11

Bits 12-14: EXTI 11 configuration bits.

EXTICR4

external interrupt configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw 		EXTI14
rw 		EXTI13
rw 		EXTI12
rw
Toggle fields

EXTI12

Bits 0-2: EXTI12 configuration bits.

EXTI13

Bits 4-6: EXTI13 configuration bits.

EXTI14

Bits 8-10: EXTI14 configuration bits.

EXTI15

Bits 12-14: EXTI15 configuration bits.

SCSR

SCSR

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2BSY
r 		SRAM2ER
rw
Toggle fields

SRAM2ER

Bit 0: SRAM2 Erase.

SRAM2BSY

Bit 1: SRAM2 busy by erase operation.

CFGR2

CFGR2

Offset: 0x1c, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPF
rw 		ECCL
w 		PVDL
w 		SPL
w 		CLL
w
Toggle fields

CLL

Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SWPR

SWPR

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31WP
w 		P30WP
w 		P29WP
w 		P28WP
w 		P27WP
w 		P26WP
w 		P25WP
w 		P24WP
w 		P23WP
w 		P22WP
w 		P21WP
w 		P20WP
w 		P19WP
w 		P18WP
w 		P17WP
w 		P16WP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15WP
w 		P14WP
w 		P13WP
w 		P12WP
w 		P11WP
w 		P10WP
w 		P9WP
w 		P8WP
w 		P7WP
w 		P6WP
w 		P5WP
w 		P4WP
w 		P3WP
w 		P2WP
w 		P1WP
w 		P0WP
w
Toggle fields

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: SRAM2 page 31 write protection.

SKR

SKR

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: SRAM2 write protection key for software erase.

TIM1

0x40012c00: Advanced-timers

100/164 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw 		OIS[3]N
rw 		OIS[3]
rw 		OIS[2]N
rw 		OIS[2]
rw 		OIS[1]N
rw 		OIS[1]
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]NE
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]NE
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw 		ETR_ADC3_RMP
rw 		ETR_ADC1_RMP
rw
Toggle fields

ETR_ADC1_RMP

Bits 0-1: External trigger remap on ADC1 analog watchdog.

ETR_ADC3_RMP

Bits 2-3: External trigger remap on ADC3 analog watchdog.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw 		OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw 		OC[6]M
rw 		OC[6]PE
rw 		OC[6]FE
rw 		OC[5]CE
rw 		OC[5]M
rw 		OC[5]PE
rw 		OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

OC[5]PE

Bit 3: Output compare 5 preload enable.

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

OC[6]FE

Bit 10: Output compare 6 fast enable.

OC[6]PE

Bit 11: Output compare 6 preload enable.

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDFBK0E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK0E

Bit 8: BRK DFSDM_BREAK0 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2DFBK0E
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TIM15

0x40014000: General purpose timers

13/62 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

TIM16

0x40014400: General purpose timers

21/70 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Default: Capture/compare are updated only by setting the COMG bit
1: WithRisingEdge: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS1

Bit 8: Output Idle state 1.

Allowed values:
0: Reset: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: Set: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1.

Allowed values:
0: Reset: OC1N=0 after a dead-time when MOE=0
1: Set: OC1N=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

5/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CC1 interrupt disabled
1: Enabled: CC1 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CC1 DMA request disabled
1: Enabled: CC1 DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDFBK1E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK1E

Bit 8: BRK DFSDM_BREAK1 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM17

0x40014800: General purpose timers

21/70 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Default: Capture/compare are updated only by setting the COMG bit
1: WithRisingEdge: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS1

Bit 8: Output Idle state 1.

Allowed values:
0: Reset: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: Set: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1.

Allowed values:
0: Reset: OC1N=0 after a dead-time when MOE=0
1: Set: OC1N=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

5/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CC1 interrupt disabled
1: Enabled: CC1 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CC1 DMA request disabled
1: Enabled: CC1 DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDFBK1E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK1E

Bit 8: BRK DFSDM_BREAK1 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM2

0x40000000: General-purpose-timers

81/107 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw 		ETR_RMP
rw
Toggle fields

ETR_RMP

Bits 0-2: Timer2 ETR remap.

TI4_RMP

Bits 3-4: Internal trigger.

TIM3

0x40000400: General-purpose-timers

81/107 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw 		ETR_RMP
rw
Toggle fields

ETR_RMP

Bits 0-2: Timer2 ETR remap.

TI4_RMP

Bits 3-4: Internal trigger.

TIM4

0x40000800: General-purpose-timers

81/107 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw 		ETR_RMP
rw
Toggle fields

ETR_RMP

Bits 0-2: Timer2 ETR remap.

TI4_RMP

Bits 3-4: Internal trigger.

TIM5

0x40000c00: General-purpose-timers

81/107 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		TIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		TIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw 		CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw 		ETR_RMP
rw
Toggle fields

ETR_RMP

Bits 0-2: Timer2 ETR remap.

TI4_RMP

Bits 3-4: Internal trigger.

TIM6

0x40001000: Basic-timers

13/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Low counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0x0-0xffff

TIM7

0x40001400: Basic-timers

13/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Low counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0x0-0xffff

TIM8

0x40013400: Advanced-timers

100/164 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw 		OIS[3]N
rw 		OIS[3]
rw 		OIS[2]N
rw 		OIS[2]
rw 		OIS[1]N
rw 		OIS[1]
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC[4]DE
rw 		CC[3]DE
rw 		CC[2]DE
rw 		CC[1]DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC[4]IE
rw 		CC[3]IE
rw 		CC[2]IE
rw 		CC[1]IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
rw 		CC[3]OF
rw 		CC[2]OF
rw 		CC[1]OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC[4]IF
rw 		CC[3]IF
rw 		CC[2]IF
rw 		CC[1]IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC[4]G
w 		CC[3]G
w 		CC[2]G
w 		CC[1]G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw 		IC[2]PSC
rw 		CC[2]S
rw 		IC[1]F
rw 		IC[1]PSC
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw 		OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw 		OC[2]M
rw 		OC[2]PE
rw 		OC[2]FE
rw 		CC[2]S
rw 		OC[1]CE
rw 		OC[1]M
rw 		OC[1]PE
rw 		OC[1]FE
rw 		CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CC1 channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
1: Enabled: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw 		IC[4]PSC
rw 		CC[4]S
rw 		IC[3]F
rw 		IC[3]PSC
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0x0-0x3

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values: 0x0-0xf

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0x0-0x3

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values: 0x0-0xf

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw 		OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw 		OC[4]M
rw 		OC[4]PE
rw 		OC[4]FE
rw 		CC[4]S
rw 		OC[3]CE
rw 		OC[3]M
rw 		OC[3]PE
rw 		OC[3]FE
rw 		CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CC3 channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately
1: Enabled: Preload register on CCR3 enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]P
rw 		CC[4]E
rw 		CC[3]NP
rw 		CC[3]NE
rw 		CC[3]P
rw 		CC[3]E
rw 		CC[2]NP
rw 		CC[2]NE
rw 		CC[2]P
rw 		CC[2]E
rw 		CC[1]NP
rw 		CC[1]NE
rw 		CC[1]P
rw 		CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x disabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw 		ETR_ADC3_RMP
rw 		ETR_ADC2_RMP
rw
Toggle fields

ETR_ADC2_RMP

Bits 0-1: External trigger remap on ADC2 analog watchdog.

ETR_ADC3_RMP

Bits 2-3: External trigger remap on ADC3 analog watchdog.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw 		OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw 		OC[6]M
rw 		OC[6]PE
rw 		OC[6]FE
rw 		OC[5]CE
rw 		OC[5]M
rw 		OC[5]PE
rw 		OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

OC[5]PE

Bit 3: Output compare 5 preload enable.

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

OC[6]FE

Bit 10: Output compare 6 fast enable.

OC[6]PE

Bit 11: Output compare 6 preload enable.

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDFBK2E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK2E

Bit 8: BRK DFSDM_BREAK2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2DFBK3E
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK3E

Bit 8: BRK2 DFSDM_BREAK3 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TSC

0x40024000: Touch sensing controller

16/170 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 IER
0x8 ICR
0xc ISR
0x10 IOHCR
0x18 IOASCR
0x20 IOSCR
0x28 IOCCR
0x30 IOGCSR
0x34 IOG[1]CR
0x38 IOG[2]CR
0x3c IOG[3]CR
0x40 IOG[4]CR
0x44 IOG[5]CR
0x48 IOG[6]CR
0x4c IOG[7]CR
0x50 IOG[8]CR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTPH
rw 		CTPL
rw 		SSD
rw 		SSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSPSC
rw 		PGPSC
rw 		MCV
rw 		IODEF
rw 		SYNCPOL
rw 		AM
rw 		START
rw 		TSCE
rw
Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIE
rw 		EOAIE
rw
Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIC
rw 		EOAIC
rw
Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEF
rw 		EOAF
rw
Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

8/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8S
r 		G7S
r 		G6S
r 		G5S
r 		G4S
r 		G3S
r 		G2S
r 		G1S
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G8E
rw 		G7E
rw 		G6E
rw 		G5E
rw 		G4E
rw 		G3E
rw 		G2E
rw 		G1E
rw
Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

G8S

Bit 23: Analog I/O group x status.

IOG[1]CR

I/O group x counter register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[2]CR

I/O group x counter register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[3]CR

I/O group x counter register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[4]CR

I/O group x counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[5]CR

I/O group x counter register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[6]CR

I/O group x counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[7]CR

I/O group x counter register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG[8]CR

I/O group x counter register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

UART4

0x40004c00: Universal synchronous asynchronous receiver transmitter

104/104 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

UART5

0x40005000: Universal synchronous asynchronous receiver transmitter

104/104 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

104/104 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

104/104 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

104/104 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

VREFBUF

0x40010030: Voltage reference buffer

1/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
Toggle registers

CSR

VREF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r 		VRS
rw 		HIZ
rw 		ENVR
rw
Toggle fields

ENVR

Bit 0: Voltage reference buffer enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle fields

TRIM

Bits 0-5: Trimming code.

WWDG

0x40002c00: System window watchdog

6/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFR
0x8 SR
Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

Allowed values: 0x0-0x7f

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw 		WDGTB
rw 		W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

Allowed values: 0x0-0x7f

WDGTB

Bits 7-8: Timer base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWI

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
0: Finished: The EWI Interrupt Service Routine has been serviced
1: Pending: The EWI Interrupt Service Routine has been triggered