Overall: 5343/25897 fields covered

ADC1

0x42028000: Analog-to-Digital Converter

7/130 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		DEEPPWD
rw 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw 		AWDCH1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		DMACFG
rw 		DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 3-4: RES.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWDCH1CH

Bits 26-30: AWDCH1CH.

JQDIS

Bit 31: JQDIS.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		JOVSE
rw 		ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

JOVSE

Bit 1: DMACFG.

OVSR

Bits 2-4: RES.

OVSS

Bits 5-8: ALIGN.

TOVS

Bit 9: EXTSEL.

ROVSM

Bit 10: EXTEN.

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

HT2

Bits 16-23: HT2.

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

HT3

Bits 16-23: HT3.

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: L.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: regularDATA.

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-5: JEXTSEL.

JEXTEN

Bits 6-7: JEXTEN.

JSQ1

Bits 8-12: JSQ1.

JSQ2

Bits 14-18: JSQ2.

JSQ3

Bits 20-24: JSQ3.

JSQ4

Bits 26-30: JSQ4.

OFR1

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw 		OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-11: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

OFFSET1_EN

Bit 31: OFFSET1_EN.

OFR2

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw 		OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-11: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

OFFSET2_EN

Bit 31: OFFSET2_EN.

OFR3

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw 		OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-11: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

OFFSET3_EN

Bit 31: OFFSET3_EN.

OFR4

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw 		OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-11: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

OFFSET4_EN

Bit 31: OFFSET4_EN.

JDR1

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle fields

AWD2CH

Bits 0-18: AWD2CH.

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle fields

AWD3CH

Bits 0-18: AWD3CH.

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_16_18
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_1_15
rw 		DIFSEL_0
r
Toggle fields

DIFSEL_0

Bit 0: Differential mode for channel 0.

DIFSEL_1_15

Bits 1-15: Differential mode for channels 15 to 1.

DIFSEL_16_18

Bits 16-18: Differential mode for channels 18 to 16.

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

CALFACT_D

Bits 16-22: CALFACT_D.

ADC2

0x42028100: Analog-to-Digital Converter

7/130 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		DEEPPWD
rw 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw 		AWDCH1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		DMACFG
rw 		DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 3-4: RES.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWDCH1CH

Bits 26-30: AWDCH1CH.

JQDIS

Bit 31: JQDIS.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		JOVSE
rw 		ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

JOVSE

Bit 1: DMACFG.

OVSR

Bits 2-4: RES.

OVSS

Bits 5-8: ALIGN.

TOVS

Bit 9: EXTSEL.

ROVSM

Bit 10: EXTEN.

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

HT2

Bits 16-23: HT2.

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

HT3

Bits 16-23: HT3.

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: L.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: regularDATA.

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-5: JEXTSEL.

JEXTEN

Bits 6-7: JEXTEN.

JSQ1

Bits 8-12: JSQ1.

JSQ2

Bits 14-18: JSQ2.

JSQ3

Bits 20-24: JSQ3.

JSQ4

Bits 26-30: JSQ4.

OFR1

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw 		OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-11: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

OFFSET1_EN

Bit 31: OFFSET1_EN.

OFR2

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw 		OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-11: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

OFFSET2_EN

Bit 31: OFFSET2_EN.

OFR3

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw 		OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-11: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

OFFSET3_EN

Bit 31: OFFSET3_EN.

OFR4

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw 		OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-11: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

OFFSET4_EN

Bit 31: OFFSET4_EN.

JDR1

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle fields

AWD2CH

Bits 0-18: AWD2CH.

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle fields

AWD3CH

Bits 0-18: AWD3CH.

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_16_18
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_1_15
rw 		DIFSEL_0
r
Toggle fields

DIFSEL_0

Bit 0: Differential mode for channel 0.

DIFSEL_1_15

Bits 1-15: Differential mode for channels 15 to 1.

DIFSEL_16_18

Bits 16-18: Differential mode for channels 18 to 16.

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

CALFACT_D

Bits 16-22: CALFACT_D.

ADC_Common

0x42028300: Analog-to-Digital Converter

24/33 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x8 CCR
0xc CDR
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQOVF_SLV
r 		AWD3_SLV
r 		AWD2_SLV
r 		AWD1_SLV
r 		JEOS_SLV
r 		JEOC_SLV
r 		OVR_SLV
r 		EOS_SLV
r 		EOC_SLV
r 		EOSMP_SLV
r 		ADRDY_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF_MST
r 		AWD3_MST
r 		AWD2_MST
r 		AWD1_MST
r 		JEOS_MST
r 		JEOC_MST
r 		OVR_MST
r 		EOS_MST
r 		EOC_MST
r 		EOSMP_MST
r 		ADDRDY_MST
r
Toggle fields

ADDRDY_MST

Bit 0: ADDRDY_MST.

EOSMP_MST

Bit 1: EOSMP_MST.

EOC_MST

Bit 2: EOC_MST.

EOS_MST

Bit 3: EOS_MST.

OVR_MST

Bit 4: OVR_MST.

JEOC_MST

Bit 5: JEOC_MST.

JEOS_MST

Bit 6: JEOS_MST.

AWD1_MST

Bit 7: AWD1_MST.

AWD2_MST

Bit 8: AWD2_MST.

AWD3_MST

Bit 9: AWD3_MST.

JQOVF_MST

Bit 10: JQOVF_MST.

ADRDY_SLV

Bit 16: ADRDY_SLV.

EOSMP_SLV

Bit 17: EOSMP_SLV.

EOC_SLV

Bit 18: EOC_SLV.

EOS_SLV

Bit 19: EOS_SLV.

OVR_SLV

Bit 20: OVR_SLV.

JEOC_SLV

Bit 21: JEOC_SLV.

JEOS_SLV

Bit 22: JEOS_SLV.

AWD1_SLV

Bit 23: AWD1_SLV.

AWD2_SLV

Bit 24: AWD2_SLV.

AWD3_SLV

Bit 25: AWD3_SLV.

JQOVF_SLV

Bit 26: JQOVF_SLV.

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH18SEL
rw 		CH17SEL
rw 		VREFEN
rw 		PRESC
rw 		CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMA
rw 		DMACFG
rw 		DELAY
rw 		DUAL
rw
Toggle fields

DUAL

Bits 0-4: DUAL.

DELAY

Bits 8-10: DELAY.

DMACFG

Bit 13: DMACFG.

MDMA

Bits 14-15: MDMA.

CKMODE

Bits 16-17: ADC clock mode.

PRESC

Bits 18-21: ADC prescaler.

VREFEN

Bit 22: VREFINT enable.

CH17SEL

Bit 23: CH17SEL.

CH18SEL

Bit 24: CH18SEL.

CDR

Common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle fields

RDATA_MST

Bits 0-15: RDATA_MST.

RDATA_SLV

Bits 16-31: RDATA_SLV.

COMP

0x40010200: Comparator

2/23 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 COMP1_CSR
0x4 COMP2_CSR
Toggle registers

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP1_LOCK
w 		COMP1_VALUE
r 		COMP1_SCALEN
rw 		COMP1_BRGEN
rw 		COMP1_BLANKING
rw 		COMP1_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP1_POLARITY
rw 		COMP1_INPSEL
rw 		COMP1_INMSEL
rw 		COMP1_PWRMODE
rw 		COMP1_EN
rw
Toggle fields

COMP1_EN

Bit 0: Comparator 1 enable bit.

COMP1_PWRMODE

Bits 2-3: Power Mode of the comparator 1.

COMP1_INMSEL

Bits 4-6: Comparator 1 Input Minus connection configuration bit.

COMP1_INPSEL

Bit 7: Comparator1 input plus selection bit.

COMP1_POLARITY

Bit 15: Comparator 1 polarity selection bit.

COMP1_HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

COMP1_BLANKING

Bits 18-20: Comparator 1 blanking source selection bits.

COMP1_BRGEN

Bit 22: Scaler bridge enable.

COMP1_SCALEN

Bit 23: Voltage scaler enable bit.

COMP1_VALUE

Bit 30: Comparator 1 output status bit.

COMP1_LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP2_LOCK
w 		COMP2_VALUE
r 		COMP2_SCALEN
rw 		COMP2_BRGEN
rw 		COMP2_BLANKING
rw 		COMP2_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP2_POLARITY
rw 		COMP2_WINMODE
rw 		COMP2_INPSEL
rw 		COMP2_INMSEL
rw 		COMP2_PWRMODE
rw 		COMP2_EN
rw
Toggle fields

COMP2_EN

Bit 0: Comparator 2 enable bit.

COMP2_PWRMODE

Bits 2-3: Power Mode of the comparator 2.

COMP2_INMSEL

Bits 4-6: Comparator 2 Input Minus connection configuration bit.

COMP2_INPSEL

Bit 7: Comparator 2 Input Plus connection configuration bit.

COMP2_WINMODE

Bit 9: Windows mode selection bit.

COMP2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COMP2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

COMP2_BRGEN

Bit 22: Scaler bridge enable.

COMP2_SCALEN

Bit 23: Voltage scaler enable bit.

COMP2_VALUE

Bit 30: Comparator 2 output status bit.

COMP2_LOCK

Bit 31: COMP2_CSR register lock bit.

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-7: General-purpose 8-bit data register bits.

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
w
Toggle fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle fields

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Polynomialcoefficients
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Polynomialcoefficients
rw
Toggle fields

Polynomialcoefficients

Bits 0-31: Programmable polynomial.

CRS

0x40006000: Clock recovery system

9/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 ISR
0xc ICR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00004000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw 		SWSYNC
rw 		AUTOTRIMEN
rw 		CEN
rw 		ESYNCIE
rw 		ERRIE
rw 		SYNCWARNIE
rw 		SYNCOKIE
rw
Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-14: HSI48 oscillator smooth trimming.

CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL
rw 		SYNCSRC
rw 		SYNCDIV
rw 		FELIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEDIR
r 		TRIMOVF
r 		SYNCMISS
r 		SYNCERR
r 		ESYNCF
r 		ERRF
r 		SYNCWARNF
r 		SYNCOKF
r
Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ESYNCC
rw 		ERRC
rw 		SYNCWARNC
rw 		SYNCOKC
rw
Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

DAC

0x40007400: DAC

6/55 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRGR
0x8 DHR12R1
0xc DHR12L1
0x10 DHR8R1
0x14 DHR12R2
0x18 DHR12L2
0x1c DHR8R2
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR1
0x30 DOR2
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR1
0x44 SHSR2
0x48 SHHR
0x4c SHRR
Toggle registers

CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN2
rw 		DMAUDRIE2
rw 		DMAEN2
rw 		MAMP2
rw 		WAVE2
rw 		TSEL23
rw 		TSEL22
rw 		TSEL21
rw 		TSEL20
rw 		TEN2
rw 		EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HFSEL
rw 		CEN1
rw 		DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL13
rw 		TSEL12
rw 		TSEL11
rw 		TSEL10
rw 		TEN1
rw 		EN1
rw
Toggle fields

EN1

Bit 0: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1..

TEN1

Bit 1: DAC channel1 trigger enable.

TSEL10

Bit 2: TSEL10.

TSEL11

Bit 3: TSEL11.

TSEL12

Bit 4: TSEL12.

TSEL13

Bit 5: TSEL13.

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

DMAEN1

Bit 12: DAC channel1 DMA enable This bit is set and cleared by software..

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software..

CEN1

Bit 14: DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

HFSEL

Bit 15: HFSEL.

EN2

Bit 16: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2..

TEN2

Bit 17: DAC channel2 trigger enable.

TSEL20

Bit 18: TSEL20.

TSEL21

Bit 19: TSEL21.

TSEL22

Bit 20: TSEL22.

TSEL23

Bit 21: TSEL23.

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

DMAEN2

Bit 28: DAC channel2 DMA enable This bit is set and cleared by software..

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software..

CEN2

Bit 30: DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w 		SWTRIG1
w
Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register..

SWTRIG2

Bit 1: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register..

DHR12R1

DAC channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DHR12L1

DAC channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DHR8R1

DAC channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DHR12R2

DAC channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DHR12L2

DAC channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2..

DHR8R2

DAC channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw 		DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DOR1

DAC channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

DOR2

DAC channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2..

SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST2
r 		CAL_FLAG2
r 		DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST1
r 		CAL_FLAG1
r 		DMAUDR1
rw
Toggle fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

CAL_FLAG1

Bit 14: DAC Channel 1 calibration offset status This bit is set and cleared by hardware.

BWST1

Bit 15: DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization)..

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

CAL_FLAG2

Bit 30: DAC Channel 2 calibration offset status This bit is set and cleared by hardware.

BWST2

Bit 31: DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization)..

CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM1
rw
Toggle fields

OTRIM1

Bits 0-4: DAC Channel 1 offset trimming value.

OTRIM2

Bits 16-20: DAC Channel 2 offset trimming value.

MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE1
rw
Toggle fields

MODE1

Bits 0-2: DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample & hold mode.

MODE2

Bits 16-18: DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample & hold mode.

SHSR1

DAC Sample and Hold sample time register 1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE1
rw
Toggle fields

TSAMPLE1

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

SHSR2

DAC Sample and Hold sample time register 2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE2
rw
Toggle fields

TSAMPLE2

Bits 0-9: DAC Channel 2 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored..

SHHR

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD1
rw
Toggle fields

THOLD1

Bits 0-9: DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI.

THOLD2

Bits 16-25: DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI.

SHRR

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH1
rw
Toggle fields

TREFRESH1

Bits 0-7: DAC Channel 1 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI.

TREFRESH2

Bits 16-23: DAC Channel 2 refresh Time (only valid in sample & hold mode) Refresh time= (TREFRESH[7:0]) x T LSI.

DBGMCU

0xe0044000: MCU debug component

2/28 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IDCODE
0x4 CR
0x8 APB1LFZR
0xc APB1HFZR
0x10 APB2FZR
Toggle registers

IDCODE

DBGMCU_IDCODE

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle fields

DEV_ID

Bits 0-11: Device identifier.

REV_ID

Bits 16-31: Revision identifie.

CR

Debug MCU configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw 		TRACE_EN
rw 		TRACE_IOEN
rw 		DBG_STANDBY
rw 		DBG_STOP
rw
Toggle fields

DBG_STOP

Bit 1: Debug Stop mode.

DBG_STANDBY

Bit 2: Debug Standby mode.

TRACE_IOEN

Bit 4: Trace pin assignment control.

TRACE_EN

Bit 5: trace port and clock enable.

TRACE_MODE

Bits 6-7: Trace pin assignment control.

APB1LFZR

Debug MCU APB1 freeze register1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIM1_STOP
rw 		DBG_I2C3_STOP
rw 		DBG_I2C2_STOP
rw 		DBG_I2C1_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw 		DBG_WWDG_STOP
rw 		DBG_RTC_STOP
rw 		DBG_TIM7_STOP
rw 		DBG_TIM6_STOP
rw 		DBG_TIM5_STOP
rw 		DBG_TIM4_STOP
rw 		DBG_TIM3_STOP
rw 		DBG_TIM2_STOP
rw
Toggle fields

DBG_TIM2_STOP

Bit 0: TIM2 counter stopped when core is halted.

DBG_TIM3_STOP

Bit 1: TIM3 stop in debug.

DBG_TIM4_STOP

Bit 2: TIM4 stop in debug.

DBG_TIM5_STOP

Bit 3: TIM5 stop in debug.

DBG_TIM6_STOP

Bit 4: TIM6 counter stopped when core is halted.

DBG_TIM7_STOP

Bit 5: TIM7 counter stopped when core is halted.

DBG_RTC_STOP

Bit 10: RTC counter stopped when core is halted.

DBG_WWDG_STOP

Bit 11: Window watchdog counter stopped when core is halted.

DBG_IWDG_STOP

Bit 12: Independent watchdog counter stopped when core is halted.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout counter stopped when core is halted.

DBG_I2C2_STOP

Bit 22: I2C2 SMBUS timeout counter stopped when core is halted.

DBG_I2C3_STOP

Bit 23: I2C3 SMBUS timeout counter stopped when core is halted.

DBG_LPTIM1_STOP

Bit 31: LPTIM1 counter stopped when core is halted.

APB1HFZR

Debug MCU APB1 freeze register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_LPTIM3_STOP
rw 		DBG_LPTIM2_STOP
rw 		DBG_I2C4_STOP
rw
Toggle fields

DBG_I2C4_STOP

Bit 1: I2C4 stop in debug.

DBG_LPTIM2_STOP

Bit 5: LPTIM2 counter stopped when core is halted.

DBG_LPTIM3_STOP

Bit 6: LPTIM3 stop in debug.

APB2FZR

Debug MCU APB2 freeze register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM17_STOP
rw 		DBG_TIM16_STOP
rw 		DBG_TIM15_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM8_STOP
rw 		DBG_TIM1_STOP
rw
Toggle fields

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM8_STOP

Bit 13: TIM8 stop in debug.

DBG_TIM15_STOP

Bit 16: TIM15 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DBG_TIM17_STOP

Bit 18: DBG_TIM17_STOP.

DCB

0xe000ee08: Debug Control Block

0/1 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DSCSR
Toggle registers

DSCSR

Debug Security Control and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CDS

Bit 16: Current domain Secure.

DFSDM1

0x40016000: Digital filter for sigma delta modulators

84/400 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CH0CFGR1
0x4 CH0CFGR2
0x8 CH0AWSCDR
0xc CH0WDATR
0x10 CH0DATINR
0x14 CH0DLYR
0x20 CH1CFGR1
0x24 CH1CFGR2
0x28 CH1AWSCDR
0x2c CH1WDATR
0x30 CH1DATINR
0x34 CH1DLYR
0x40 CH2CFGR1
0x44 CH2CFGR2
0x48 CH2AWSCDR
0x4c CH2WDATR
0x50 CH2DATINR
0x54 CH2DLYR
0x60 CH3CFGR1
0x64 CH3CFGR2
0x68 CH3AWSCDR
0x6c CH3WDATR
0x70 CH3DATINR
0x74 CH3DLYR
0x80 CH4CFGR1
0x84 CH4CFGR2
0x88 CH4AWSCDR
0x8c CH4WDATR
0x90 CH4DATINR
0x94 CH4DLYR
0xa0 CH5CFGR1
0xa4 CH5CFGR2
0xa8 CH5AWSCDR
0xac CH5WDATR
0xb0 CH5DATINR
0xb4 CH5DLYR
0xc0 CH6CFGR1
0xc4 CH6CFGR2
0xc8 CH6AWSCDR
0xcc CH6WDATR
0xd0 CH6DATINR
0xd4 CH6DLYR
0xe0 CH7CFGR1
0xe4 CH7CFGR2
0xe8 CH7AWSCDR
0xec CH7WDATR
0xf0 CH7DATINR
0xf4 CH7DLYR
0x100 FLT0CR1
0x104 FLT0CR2
0x108 FLT0ISR
0x10c FLT0ICR
0x110 FLT0JCHGR
0x114 FLT0FCR
0x118 FLT0JDATAR
0x11c FLT0RDATAR
0x120 FLT0AWHTR
0x124 FLT0AWLTR
0x128 FLT0AWSR
0x12c FLT0AWCFR
0x130 FLT0EXMAX
0x134 FLT0EXMIN
0x138 FLT0CNVTIMR
0x180 FLT1CR1
0x184 FLT1CR2
0x188 FLT1ISR
0x18c FLT1ICR
0x190 FLT1JCHGR
0x194 FLT1FCR
0x198 FLT1JDATAR
0x19c FLT1RDATAR
0x1a4 FLT1AWLTR
0x1a8 FLT1AWSR
0x1ac FLT1AWCFR
0x1ac FLT1AWHTR
0x1b0 FLT1EXMAX
0x1b4 FLT1EXMIN
0x1b8 FLT1CNVTIMR
0x200 FLT2CR1
0x204 FLT2CR2
0x208 FLT2ISR
0x20c FLT2ICR
0x210 FLT2JCHGR
0x214 FLT2FCR
0x218 FLT2JDATAR
0x21c FLT2RDATAR
0x220 FLT2AWHTR
0x224 FLT2AWLTR
0x228 FLT2AWSR
0x22c FLT2AWCFR
0x230 FLT2EXMAX
0x234 FLT2EXMIN
0x238 FLT2CNVTIMR
0x280 FLT3CR1
0x284 FLT3CR2
0x288 FLT3ISR
0x28c FLT3ICR
0x290 FLT3JCHGR
0x294 FLT3FCR
0x298 FLT3JDATAR
0x29c FLT3RDATAR
0x2a0 FLT3AWHTR
0x2a4 FLT3AWLTR
0x2a8 FLT3AWSR
0x2ac FLT3AWCFR
0x2b0 FLT3EXMAX
0x2b4 FLT3EXMIN
0x2b8 FLT3CNVTIMR
Toggle registers

CH0CFGR1

channel configuration y register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH0CFGR2

channel configuration y register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH0AWSCDR

analog watchdog and short-circuit detector register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH0WDATR

channel watchdog filter data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH0DATINR

channel data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH0DLYR

DFSDM channel y delay register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function.

CH1CFGR1

CHCFG1R1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH1CFGR2

CHCFG1R2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH1AWSCDR

AWSCD1R

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH1WDATR

CHWDAT1R

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH1DATINR

CHDATIN1R

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH1DLYR

DFSDM channel y delay register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH2CFGR1

CHCFG2R1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH2CFGR2

CHCFG2R2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH2AWSCDR

AWSCD2R

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH2WDATR

CHWDAT2R

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH2DATINR

CHDATIN2R

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH2DLYR

DFSDM channel y delay register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH3CFGR1

CHCFG3R1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH3CFGR2

CHCFG3R2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH3AWSCDR

AWSCD3R

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH3WDATR

CHWDAT3R

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH3DATINR

CHDATIN3R

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH3DLYR

DFSDM channel y delay register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH4CFGR1

CHCFG4R1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH4CFGR2

CHCFG4R2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH4AWSCDR

AWSCD4R

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH4WDATR

CHWDAT4R

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH4DATINR

CHDATIN4R

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH4DLYR

DFSDM channel y delay register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH5CFGR1

CHCFG5R1

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH5CFGR2

CHCFG5R2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH5AWSCDR

AWSCD5R

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH5WDATR

CHWDAT5R

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH5DATINR

CHDATIN5R

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH5DLYR

DFSDM channel y delay register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: read-only.

CH6CFGR1

CHCFG6R1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH6CFGR2

CH6CFGR2

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH6AWSCDR

AWSCD6R

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH6WDATR

CHWDAT6R

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH6DATINR

CHDATIN6R

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH6DLYR

DFSDM channel y delay register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH7CFGR1

CHCFG7R1

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH7CFGR2

CHCFG7R2

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH7AWSCDR

AWSCD7R

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH7WDATR

CHWDAT7R

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH7DATINR

CHDATIN7R

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH7DLYR

DFSDM channel y delay register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

FLT0CR1

control register 1

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT0CR2

control register 2

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT0ISR

interrupt and status register

Offset: 0x108, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT0ICR

interrupt flag clear register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT0JCHGR

injected channel group selection register

Offset: 0x110, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT0FCR

filter control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT0JDATAR

data register for injected group

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT0RDATAR

data register for the regular channel

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT0AWHTR

analog watchdog high threshold register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT0AWLTR

analog watchdog low threshold register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT0AWSR

analog watchdog status register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT0AWCFR

analog watchdog clear flag register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT0EXMAX

Extremes detector maximum register

Offset: 0x130, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT0EXMIN

Extremes detector minimum register

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT0CNVTIMR

conversion timer register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT1CR1

control register 1

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT1CR2

control register 2

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT1ISR

interrupt and status register

Offset: 0x188, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT1ICR

interrupt flag clear register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT1JCHGR

injected channel group selection register

Offset: 0x190, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT1FCR

filter control register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT1JDATAR

data register for injected group

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT1RDATAR

data register for the regular channel

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT1AWLTR

analog watchdog low threshold register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT1AWSR

analog watchdog status register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT1AWCFR

analog watchdog clear flag register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT1AWHTR

analog watchdog high threshold register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT1EXMAX

Extremes detector maximum register

Offset: 0x1b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT1EXMIN

Extremes detector minimum register

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT1CNVTIMR

conversion timer register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT2CR1

control register 1

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT2CR2

control register 2

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT2ISR

interrupt and status register

Offset: 0x208, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT2ICR

interrupt flag clear register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT2JCHGR

injected channel group selection register

Offset: 0x210, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT2FCR

filter control register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT2JDATAR

data register for injected group

Offset: 0x218, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT2RDATAR

data register for the regular channel

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT2AWHTR

analog watchdog high threshold register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT2AWLTR

analog watchdog low threshold register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT2AWSR

analog watchdog status register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT2AWCFR

analog watchdog clear flag register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT2EXMAX

Extremes detector maximum register

Offset: 0x230, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT2EXMIN

Extremes detector minimum register

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT2CNVTIMR

conversion timer register

Offset: 0x238, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT3CR1

control register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT3CR2

control register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT3ISR

interrupt and status register

Offset: 0x288, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT3ICR

interrupt flag clear register

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT3JCHGR

injected channel group selection register

Offset: 0x290, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT3FCR

filter control register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT3JDATAR

data register for injected group

Offset: 0x298, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT3RDATAR

data register for the regular channel

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT3AWHTR

analog watchdog high threshold register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT3AWLTR

analog watchdog low threshold register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT3AWSR

analog watchdog status register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT3AWCFR

analog watchdog clear flag register

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT3EXMAX

Extremes detector maximum register

Offset: 0x2b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT3EXMIN

Extremes detector minimum register

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT3CNVTIMR

conversion timer register

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

DMA1

0x40020000: Direct memory access controller

32/241 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 M0AR [1]
0x18 M1AR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 M0AR [2]
0x2c M1AR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c M0AR [3]
0x40 M1AR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 M0AR [4]
0x54 M1AR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 M0AR [5]
0x68 M1AR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 M0AR [6]
0x7c M1AR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c M0AR [7]
0x90 M1AR [7]
0x94 CR [8]
0x98 NDTR [8]
0x9c PAR [8]
0xa0 M0AR [8]
0xa4 M1AR [8]
0xa8 CSELR
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF8
r 		HTIF8
r 		TCIF8
r 		GIF8
r 		TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle fields

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

GIF8

Bit 28: global interrupt flag for channel 8.

TCIF8

Bit 29: transfer complete (TC) flag for channel 8.

HTIF8

Bit 30: half transfer (HT) flag for channel 8.

TEIF8

Bit 31: transfer error (TE) flag for channel 8.

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF8
w 		CHTIF8
w 		CTCIF8
w 		CGIF8
w 		CTEIF7
w 		CHTIF7
w 		CTCIF7
w 		CGIF7
w 		CTEIF6
w 		CHTIF6
w 		CTCIF6
w 		CGIF6
w 		CTEIF5
w 		CHTIF5
w 		CTCIF5
w 		CGIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4
w 		CHTIF4
w 		CTCIF4
w 		CGIF4
w 		CTEIF3
w 		CHTIF3
w 		CTCIF3
w 		CGIF3
w 		CTEIF2
w 		CHTIF2
w 		CTCIF2
w 		CGIF2
w 		CTEIF1
w 		CHTIF1
w 		CTCIF1
w 		CGIF1
w
Toggle fields

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CGIF8

Bit 28: global interrupt flag clear for channel 8.

CTCIF8

Bit 29: transfer complete flag clear for channel 8.

CHTIF8

Bit 30: half transfer flag clear for channel 8.

CTEIF8

Bit 31: transfer error flag clear for channel 8.

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [1]

channel x memory address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [2]

channel x memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [3]

channel x memory address register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [4]

channel x memory address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [5]

channel x memory address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [6]

channel x memory address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [7]

channel x memory address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [8]

channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [8]

channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [8]

channel x peripheral address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [8]

channel x memory address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [8]

channel x memory address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CSELR

channel selection register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

DMA2

0x40020400: Direct memory access controller

32/241 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 M0AR [1]
0x18 M1AR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 M0AR [2]
0x2c M1AR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c M0AR [3]
0x40 M1AR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 M0AR [4]
0x54 M1AR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 M0AR [5]
0x68 M1AR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 M0AR [6]
0x7c M1AR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c M0AR [7]
0x90 M1AR [7]
0x94 CR [8]
0x98 NDTR [8]
0x9c PAR [8]
0xa0 M0AR [8]
0xa4 M1AR [8]
0xa8 CSELR
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF8
r 		HTIF8
r 		TCIF8
r 		GIF8
r 		TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle fields

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

GIF8

Bit 28: global interrupt flag for channel 8.

TCIF8

Bit 29: transfer complete (TC) flag for channel 8.

HTIF8

Bit 30: half transfer (HT) flag for channel 8.

TEIF8

Bit 31: transfer error (TE) flag for channel 8.

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF8
w 		CHTIF8
w 		CTCIF8
w 		CGIF8
w 		CTEIF7
w 		CHTIF7
w 		CTCIF7
w 		CGIF7
w 		CTEIF6
w 		CHTIF6
w 		CTCIF6
w 		CGIF6
w 		CTEIF5
w 		CHTIF5
w 		CTCIF5
w 		CGIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4
w 		CHTIF4
w 		CTCIF4
w 		CGIF4
w 		CTEIF3
w 		CHTIF3
w 		CTCIF3
w 		CGIF3
w 		CTEIF2
w 		CHTIF2
w 		CTCIF2
w 		CGIF2
w 		CTEIF1
w 		CHTIF1
w 		CTCIF1
w 		CGIF1
w
Toggle fields

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CGIF8

Bit 28: global interrupt flag clear for channel 8.

CTCIF8

Bit 29: transfer complete flag clear for channel 8.

CHTIF8

Bit 30: half transfer flag clear for channel 8.

CTEIF8

Bit 31: transfer error flag clear for channel 8.

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [1]

channel x memory address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [2]

channel x memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [3]

channel x memory address register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [4]

channel x memory address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [5]

channel x memory address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [6]

channel x memory address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [7]

channel x memory address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [8]

channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [8]

channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [8]

channel x peripheral address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [8]

channel x memory address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [8]

channel x memory address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CSELR

channel selection register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

DMAMUX1

0x40020800: Direct memory access Multiplexer

4/172 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR[0]
0x4 CCR[1]
0x8 CCR[2]
0xc CCR[3]
0x10 CCR[4]
0x14 CCR[5]
0x18 CCR[6]
0x1c CCR[7]
0x20 CCR[8]
0x24 CCR[9]
0x28 CCR[10]
0x2c CCR[11]
0x30 CCR[12]
0x34 CCR[13]
0x38 CCR[14]
0x3c CCR[15]
0x80 CSR
0x84 CCFR
0x100 RGCR[0]
0x104 RGCR[1]
0x108 RGCR[2]
0x10c RGCR[3]
0x140 RGSR
0x144 RGCFR
Toggle registers

CCR[0]

DMA Multiplexer Channel 0 Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[1]

DMA Multiplexer Channel 1 Control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[2]

DMA Multiplexer Channel 2 Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[3]

DMA Multiplexer Channel 3 Control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[4]

DMA Multiplexer Channel 4 Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[5]

DMA Multiplexer Channel 5 Control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[6]

DMA Multiplexer Channel 6 Control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[7]

DMA Multiplexer Channel 7 Control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[8]

DMA Multiplexer Channel 8 Control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[9]

DMA Multiplexer Channel 9 Control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[10]

DMA Multiplexer Channel 10 Control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[11]

DMA Multiplexer Channel 11 Control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[12]

DMA Multiplexer Channel 12 Control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[13]

DMA Multiplexer Channel 13 Control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[14]

DMA Multiplexer Channel 14 Control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[15]

DMA Multiplexer Channel 15 Control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CSR

DMA Multiplexer Channel Status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF15
rw 		SOF14
rw 		SOF13
rw 		SOF12
rw 		SOF11
rw 		SOF10
rw 		SOF9
rw 		SOF8
rw 		SOF7
rw 		SOF6
rw 		SOF5
rw 		SOF4
rw 		SOF3
rw 		SOF2
rw 		SOF1
rw 		SOF0
rw
Toggle fields

SOF0

Bit 0: Synchronization Overrun Flag 0.

SOF1

Bit 1: Synchronization Overrun Flag 1.

SOF2

Bit 2: Synchronization Overrun Flag 2.

SOF3

Bit 3: Synchronization Overrun Flag 3.

SOF4

Bit 4: Synchronization Overrun Flag 4.

SOF5

Bit 5: Synchronization Overrun Flag 5.

SOF6

Bit 6: Synchronization Overrun Flag 6.

SOF7

Bit 7: Synchronization Overrun Flag 7.

SOF8

Bit 8: Synchronization Overrun Flag 8.

SOF9

Bit 9: Synchronization Overrun Flag 9.

SOF10

Bit 10: Synchronization Overrun Flag 10.

SOF11

Bit 11: Synchronization Overrun Flag 11.

SOF12

Bit 12: Synchronization Overrun Flag 12.

SOF13

Bit 13: Synchronization Overrun Flag 13.

SOF14

Bit 14: Synchronization Overrun Flag 13.

SOF15

Bit 15: Synchronization Overrun Flag 13.

CCFR

DMA Channel Clear Flag Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF15
rw 		CSOF14
rw 		CSOF13
rw 		CSOF12
rw 		CSOF11
rw 		CSOF10
rw 		CSOF9
rw 		CSOF8
rw 		CSOF7
rw 		CSOF6
rw 		CSOF5
rw 		CSOF4
rw 		CSOF3
rw 		CSOF2
rw 		CSOF1
rw 		CSOF0
rw
Toggle fields

CSOF0

Bit 0: Synchronization Clear Overrun Flag 0.

CSOF1

Bit 1: Synchronization Clear Overrun Flag 1.

CSOF2

Bit 2: Synchronization Clear Overrun Flag 2.

CSOF3

Bit 3: Synchronization Clear Overrun Flag 3.

CSOF4

Bit 4: Synchronization Clear Overrun Flag 4.

CSOF5

Bit 5: Synchronization Clear Overrun Flag 5.

CSOF6

Bit 6: Synchronization Clear Overrun Flag 6.

CSOF7

Bit 7: Synchronization Clear Overrun Flag 7.

CSOF8

Bit 8: Synchronization Clear Overrun Flag 8.

CSOF9

Bit 9: Synchronization Clear Overrun Flag 9.

CSOF10

Bit 10: Synchronization Clear Overrun Flag 10.

CSOF11

Bit 11: Synchronization Clear Overrun Flag 11.

CSOF12

Bit 12: Synchronization Clear Overrun Flag 12.

CSOF13

Bit 13: Synchronization Clear Overrun Flag 13.

CSOF14

Bit 14: Synchronization Clear Overrun Flag 13.

CSOF15

Bit 15: Synchronization Clear Overrun Flag 13.

RGCR[0]

DMA Request Generator 0 Control Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[1]

DMA Request Generator 1 Control Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[2]

DMA Request Generator 2 Control Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[3]

DMA Request Generator 3 Control Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGSR

DMA Request Generator Status Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF3
r 		OF2
r 		OF1
r 		OF0
r
Toggle fields

OF0

Bit 0: Generator Overrun Flag 0.

OF1

Bit 1: Generator Overrun Flag 1.

OF2

Bit 2: Generator Overrun Flag 2.

OF3

Bit 3: Generator Overrun Flag 3.

RGCFR

DMA Request Generator Clear Flag Register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF3
rw 		CSOF2
rw 		CSOF1
rw 		CSOF0
rw
Toggle fields

CSOF0

Bit 0: Generator Clear Overrun Flag 0.

CSOF1

Bit 1: Generator Clear Overrun Flag 1.

CSOF2

Bit 2: Generator Clear Overrun Flag 2.

CSOF3

Bit 3: Generator Clear Overrun Flag 3.

EXTI

0x4002f400: External interrupt/event controller

0/302 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 RTSR1
0x4 FTSR1
0x8 SWIER1
0xc RPR1
0x10 FPR1
0x14 SECCFGR1
0x18 PRIVCFGR1
0x20 RTSR2
0x24 FTSR2
0x28 SWIER2
0x2c RPR2
0x30 FPR2
0x34 PRIVCFGR2
0x38 SECCFGR2
0x60 EXTICR1
0x64 EXTICR2
0x68 EXTICR3
0x6c EXTICR4
0x70 LOCKRG
0x80 IMR1
0x84 EMR1
0x90 IMR2
0x94 EMR2
Toggle registers

RTSR1

EXTI rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT22
rw 		RT21
rw 		RT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT15
rw 		RT14
rw 		RT13
rw 		RT12
rw 		RT11
rw 		RT10
rw 		RT9
rw 		RT8
rw 		RT7
rw 		RT6
rw 		RT5
rw 		RT4
rw 		RT3
rw 		RT2
rw 		RT1
rw 		RT0
rw
Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of configurable event input x.

RT1

Bit 1: Rising trigger event configuration bit of configurable event input x.

RT2

Bit 2: Rising trigger event configuration bit of configurable event input x.

RT3

Bit 3: Rising trigger event configuration bit of configurable event input x.

RT4

Bit 4: Rising trigger event configuration bit of configurable event input x.

RT5

Bit 5: Rising trigger event configuration bit of configurable event input x.

RT6

Bit 6: Rising trigger event configuration bit of configurable event input x.

RT7

Bit 7: Rising trigger event configuration bit of configurable event input x.

RT8

Bit 8: Rising trigger event configuration bit of configurable event input x.

RT9

Bit 9: Rising trigger event configuration bit of configurable event input x.

RT10

Bit 10: Rising trigger event configuration bit of configurable event input x.

RT11

Bit 11: Rising trigger event configuration bit of configurable event input x.

RT12

Bit 12: Rising trigger event configuration bit of configurable event input x.

RT13

Bit 13: Rising trigger event configuration bit of configurable event input x.

RT14

Bit 14: Rising trigger event configuration bit of configurable event input x.

RT15

Bit 15: Rising trigger event configuration bit of configurable event input x.

RT16

Bit 16: Rising trigger event configuration bit of configurable event input x.

RT21

Bit 21: Rising trigger event configuration bit of configurable event input x.

RT22

Bit 22: Rising trigger event configuration bit of configurable event input x.

FTSR1

EXTI falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FT22
rw 		FT21
rw 		FT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT15
rw 		FT14
rw 		FT13
rw 		FT12
rw 		FT11
rw 		FT10
rw 		FT9
rw 		FT8
rw 		FT7
rw 		FT6
rw 		FT5
rw 		FT4
rw 		FT3
rw 		FT2
rw 		FT1
rw 		FT0
rw
Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of configurable event input x.

FT1

Bit 1: Falling trigger event configuration bit of configurable event input x.

FT2

Bit 2: Falling trigger event configuration bit of configurable event input x.

FT3

Bit 3: Falling trigger event configuration bit of configurable event input x.

FT4

Bit 4: Falling trigger event configuration bit of configurable event input x.

FT5

Bit 5: Falling trigger event configuration bit of configurable event input x.

FT6

Bit 6: Falling trigger event configuration bit of configurable event input x.

FT7

Bit 7: Falling trigger event configuration bit of configurable event input x.

FT8

Bit 8: Falling trigger event configuration bit of configurable event input x.

FT9

Bit 9: Falling trigger event configuration bit of configurable event input x.

FT10

Bit 10: Falling trigger event configuration bit of configurable event input x.

FT11

Bit 11: Falling trigger event configuration bit of configurable event input x.

FT12

Bit 12: Falling trigger event configuration bit of configurable event input x.

FT13

Bit 13: Falling trigger event configuration bit of configurable event input x.

FT14

Bit 14: Falling trigger event configuration bit of configurable event input x.

FT15

Bit 15: Falling trigger event configuration bit of configurable event input x.

FT16

Bit 16: Falling trigger event configuration bit of configurable event input x.

FT21

Bit 21: Falling trigger event configuration bit of configurable event input x.

FT22

Bit 22: Falling trigger event configuration bit of configurable event input x.

SWIER1

EXTI software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI22
rw 		SWI21
rw 		SWI16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI15
rw 		SWI14
rw 		SWI13
rw 		SWI12
rw 		SWI11
rw 		SWI10
rw 		SWI9
rw 		SWI8
rw 		SWI7
rw 		SWI6
rw 		SWI5
rw 		SWI4
rw 		SWI3
rw 		SWI2
rw 		SWI1
rw 		SWI0
rw
Toggle fields

SWI0

Bit 0: Software interrupt on event x.

SWI1

Bit 1: Software interrupt on event x.

SWI2

Bit 2: Software interrupt on event x.

SWI3

Bit 3: Software interrupt on event x.

SWI4

Bit 4: Software interrupt on event x.

SWI5

Bit 5: Software interrupt on event x.

SWI6

Bit 6: Software interrupt on event x.

SWI7

Bit 7: Software interrupt on event x.

SWI8

Bit 8: Software interrupt on event x.

SWI9

Bit 9: Software interrupt on event x.

SWI10

Bit 10: Software interrupt on event x.

SWI11

Bit 11: Software interrupt on event x.

SWI12

Bit 12: Software interrupt on event x.

SWI13

Bit 13: Software interrupt on event x.

SWI14

Bit 14: Software interrupt on event x.

SWI15

Bit 15: Software interrupt on event x.

SWI16

Bit 16: Software interrupt on event x.

SWI21

Bit 21: Software interrupt on event x.

SWI22

Bit 22: Software interrupt on event x.

RPR1

EXTI rising edge pending register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPIF22
rw 		RPIF21
rw 		RPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF15
rw 		RPIF14
rw 		RPIF13
rw 		RPIF12
rw 		RPIF11
rw 		RPIF10
rw 		RPIF9
rw 		RPIF8
rw 		RPIF7
rw 		RPIF6
rw 		RPIF5
rw 		RPIF4
rw 		RPIF3
rw 		RPIF2
rw 		RPIF1
rw 		RPIF0
rw
Toggle fields

RPIF0

Bit 0: configurable event inputs x rising edge pending bit.

RPIF1

Bit 1: configurable event inputs x rising edge pending bit.

RPIF2

Bit 2: configurable event inputs x rising edge pending bit.

RPIF3

Bit 3: configurable event inputs x rising edge pending bit.

RPIF4

Bit 4: configurable event inputs x rising edge pending bit.

RPIF5

Bit 5: configurable event inputs x rising edge pending bit.

RPIF6

Bit 6: configurable event inputs x rising edge pending bit.

RPIF7

Bit 7: configurable event inputs x rising edge pending bit.

RPIF8

Bit 8: configurable event inputs x rising edge pending bit.

RPIF9

Bit 9: configurable event inputs x rising edge pending bit.

RPIF10

Bit 10: configurable event inputs x rising edge pending bit.

RPIF11

Bit 11: configurable event inputs x rising edge pending bit.

RPIF12

Bit 12: configurable event inputs x rising edge pending bit.

RPIF13

Bit 13: configurable event inputs x rising edge pending bit.

RPIF14

Bit 14: configurable event inputs x rising edge pending bit.

RPIF15

Bit 15: configurable event inputs x rising edge pending bit.

RPIF16

Bit 16: configurable event inputs x rising edge pending bit.

RPIF21

Bit 21: configurable event inputs x rising edge pending bit.

RPIF22

Bit 22: configurable event inputs x rising edge pending bit.

FPR1

EXTI falling edge pending register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPIF22
rw 		FPIF21
rw 		FPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF15
rw 		FPIF14
rw 		FPIF13
rw 		FPIF12
rw 		FPIF11
rw 		FPIF10
rw 		FPIF9
rw 		FPIF8
rw 		FPIF7
rw 		FPIF6
rw 		FPIF5
rw 		FPIF4
rw 		FPIF3
rw 		FPIF2
rw 		FPIF1
rw 		FPIF0
rw
Toggle fields

FPIF0

Bit 0: configurable event inputs x falling edge pending bit..

FPIF1

Bit 1: configurable event inputs x falling edge pending bit..

FPIF2

Bit 2: configurable event inputs x falling edge pending bit..

FPIF3

Bit 3: configurable event inputs x falling edge pending bit..

FPIF4

Bit 4: configurable event inputs x falling edge pending bit..

FPIF5

Bit 5: configurable event inputs x falling edge pending bit..

FPIF6

Bit 6: configurable event inputs x falling edge pending bit..

FPIF7

Bit 7: configurable event inputs x falling edge pending bit..

FPIF8

Bit 8: configurable event inputs x falling edge pending bit..

FPIF9

Bit 9: configurable event inputs x falling edge pending bit..

FPIF10

Bit 10: configurable event inputs x falling edge pending bit..

FPIF11

Bit 11: configurable event inputs x falling edge pending bit..

FPIF12

Bit 12: configurable event inputs x falling edge pending bit..

FPIF13

Bit 13: configurable event inputs x falling edge pending bit..

FPIF14

Bit 14: configurable event inputs x falling edge pending bit..

FPIF15

Bit 15: configurable event inputs x falling edge pending bit..

FPIF16

Bit 16: configurable event inputs x falling edge pending bit..

FPIF21

Bit 21: configurable event inputs x falling edge pending bit..

FPIF22

Bit 22: configurable event inputs x falling edge pending bit..

SECCFGR1

EXTI security configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEC31
rw 		SEC30
rw 		SEC29
rw 		SEC28
rw 		SEC27
rw 		SEC26
rw 		SEC25
rw 		SEC24
rw 		SEC23
rw 		SEC22
rw 		SEC21
rw 		SEC20
rw 		SEC19
rw 		SEC18
rw 		SEC17
rw 		SEC16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
rw 		SEC14
rw 		SEC13
rw 		SEC12
rw 		SEC11
rw 		SEC10
rw 		SEC9
rw 		SEC8
rw 		SEC7
rw 		SEC6
rw 		SEC5
rw 		SEC4
rw 		SEC3
rw 		SEC2
rw 		SEC1
rw 		SEC0
rw
Toggle fields

SEC0

Bit 0: Security enable on event input x.

SEC1

Bit 1: Security enable on event input x.

SEC2

Bit 2: Security enable on event input x.

SEC3

Bit 3: Security enable on event input x.

SEC4

Bit 4: Security enable on event input x.

SEC5

Bit 5: Security enable on event input x.

SEC6

Bit 6: Security enable on event input x.

SEC7

Bit 7: Security enable on event input x.

SEC8

Bit 8: Security enable on event input x.

SEC9

Bit 9: Security enable on event input x.

SEC10

Bit 10: Security enable on event input x.

SEC11

Bit 11: Security enable on event input x.

SEC12

Bit 12: Security enable on event input x.

SEC13

Bit 13: Security enable on event input x.

SEC14

Bit 14: Security enable on event input x.

SEC15

Bit 15: Security enable on event input x.

SEC16

Bit 16: Security enable on event input x.

SEC17

Bit 17: Security enable on event input x.

SEC18

Bit 18: Security enable on event input x.

SEC19

Bit 19: Security enable on event input x.

SEC20

Bit 20: Security enable on event input x.

SEC21

Bit 21: Security enable on event input x.

SEC22

Bit 22: Security enable on event input x.

SEC23

Bit 23: Security enable on event input x.

SEC24

Bit 24: Security enable on event input x.

SEC25

Bit 25: Security enable on event input x.

SEC26

Bit 26: Security enable on event input x.

SEC27

Bit 27: Security enable on event input x.

SEC28

Bit 28: Security enable on event input x.

SEC29

Bit 29: Security enable on event input x.

SEC30

Bit 30: Security enable on event input x.

SEC31

Bit 31: Security enable on event input x.

PRIVCFGR1

EXTI privilege configuration register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV31
rw 		PRIV30
rw 		PRIV29
rw 		PRIV28
rw 		PRIV27
rw 		PRIV26
rw 		PRIV25
rw 		PRIV24
rw 		PRIV23
rw 		PRIV22
rw 		PRIV21
rw 		PRIV20
rw 		PRIV19
rw 		PRIV18
rw 		PRIV17
rw 		PRIV16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV15
rw 		PRIV14
rw 		PRIV13
rw 		PRIV12
rw 		PRIV11
rw 		PRIV10
rw 		PRIV9
rw 		PRIV8
rw 		PRIV7
rw 		PRIV6
rw 		PRIV5
rw 		PRIV4
rw 		PRIV3
rw 		PRIV2
rw 		PRIV1
rw 		PRIV0
rw
Toggle fields

PRIV0

Bit 0: Security enable on event input x.

PRIV1

Bit 1: Security enable on event input x.

PRIV2

Bit 2: Security enable on event input x.

PRIV3

Bit 3: Security enable on event input x.

PRIV4

Bit 4: Security enable on event input x.

PRIV5

Bit 5: Security enable on event input x.

PRIV6

Bit 6: Security enable on event input x.

PRIV7

Bit 7: Security enable on event input x.

PRIV8

Bit 8: Security enable on event input x.

PRIV9

Bit 9: Security enable on event input x.

PRIV10

Bit 10: Security enable on event input x.

PRIV11

Bit 11: Security enable on event input x.

PRIV12

Bit 12: Security enable on event input x.

PRIV13

Bit 13: Security enable on event input x.

PRIV14

Bit 14: Security enable on event input x.

PRIV15

Bit 15: Security enable on event input x.

PRIV16

Bit 16: Security enable on event input x.

PRIV17

Bit 17: Security enable on event input x.

PRIV18

Bit 18: Security enable on event input x.

PRIV19

Bit 19: Security enable on event input x.

PRIV20

Bit 20: Security enable on event input x.

PRIV21

Bit 21: Security enable on event input x.

PRIV22

Bit 22: Security enable on event input x.

PRIV23

Bit 23: Security enable on event input x.

PRIV24

Bit 24: Security enable on event input x.

PRIV25

Bit 25: Security enable on event input x.

PRIV26

Bit 26: Security enable on event input x.

PRIV27

Bit 27: Security enable on event input x.

PRIV28

Bit 28: Security enable on event input x.

PRIV29

Bit 29: Security enable on event input x.

PRIV30

Bit 30: Security enable on event input x.

PRIV31

Bit 31: Security enable on event input x.

RTSR2

EXTI rising trigger selection register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT38
rw 		RT37
rw 		RT36
rw 		RT35
rw
Toggle fields

RT35

Bit 3: Rising trigger event configuration bit of configurable event input x.

RT36

Bit 4: Rising trigger event configuration bit of configurable event input x.

RT37

Bit 5: Rising trigger event configuration bit of configurable event input x.

RT38

Bit 6: Rising trigger event configuration bit of configurable event input x.

FTSR2

EXTI falling trigger selection register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT38
rw 		FT37
rw 		FT36
rw 		FT35
rw
Toggle fields

FT35

Bit 3: FT35.

FT36

Bit 4: FT36.

FT37

Bit 5: FT37.

FT38

Bit 6: FT38.

SWIER2

EXTI software interrupt event register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI38
rw 		SWI37
rw 		SWI36
rw 		SWI35
rw
Toggle fields

SWI35

Bit 3: SWI35.

SWI36

Bit 4: SWI36.

SWI37

Bit 5: SWI37.

SWI38

Bit 6: SWI38.

RPR2

EXTI rising edge pending register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF38
rw 		RPIF37
rw 		RPIF36
rw 		RPIF35
rw
Toggle fields

RPIF35

Bit 3: RPIF35.

RPIF36

Bit 4: RPIF36.

RPIF37

Bit 5: RPIF37.

RPIF38

Bit 6: RPIF38.

FPR2

EXTI falling edge pending register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF38
rw 		FPIF37
rw 		FPIF36
rw 		FPIF35
rw
Toggle fields

FPIF35

Bit 3: FPIF35.

FPIF36

Bit 4: FPIF36.

FPIF37

Bit 5: FPIF37.

FPIF38

Bit 6: FPIF38.

PRIVCFGR2

EXTI security enable register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV42
rw 		PRIV41
rw 		PRIV40
rw 		PRIV39
rw 		PRIV38
rw 		PRIV37
rw 		PRIV36
rw 		PRIV35
rw 		PRIV34
rw 		PRIV33
rw 		PRIV32
rw
Toggle fields

PRIV32

Bit 0: PRIV32.

PRIV33

Bit 1: PRIV33.

PRIV34

Bit 2: PRIV34.

PRIV35

Bit 3: PRIV35.

PRIV36

Bit 4: PRIV36.

PRIV37

Bit 5: PRIV37.

PRIV38

Bit 6: PRIV38.

PRIV39

Bit 7: PRIV39.

PRIV40

Bit 8: PRIV40.

PRIV41

Bit 9: PRIV41.

PRIV42

Bit 10: PRIV42.

SECCFGR2

EXTI security enable register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC42
rw 		SEC41
rw 		SEC40
rw 		SEC39
rw 		SEC38
rw 		SEC37
rw 		SEC36
rw 		SEC35
rw 		SEC34
rw 		SEC33
rw 		SEC32
rw
Toggle fields

SEC32

Bit 0: SEC32.

SEC33

Bit 1: SEC33.

SEC34

Bit 2: SEC34.

SEC35

Bit 3: SEC35.

SEC36

Bit 4: SEC36.

SEC37

Bit 5: SEC37.

SEC38

Bit 6: SEC38.

SEC39

Bit 7: SEC39.

SEC40

Bit 8: SEC40.

SEC41

Bit 9: SEC41.

SEC42

Bit 10: SEC42.

EXTICR1

EXTI external interrupt selection register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI24_31
rw 		EXTI16_23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI8_15
rw 		EXTI0_7
rw
Toggle fields

EXTI0_7

Bits 0-7: EXTIm GPIO port selection.

EXTI8_15

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI16_23

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI24_31

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR2

EXTI external interrupt selection register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI24_31
rw 		EXTI16_23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI8_15
rw 		EXTI0_7
rw
Toggle fields

EXTI0_7

Bits 0-7: EXTIm GPIO port selection.

EXTI8_15

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI16_23

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI24_31

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR3

EXTI external interrupt selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI24_31
rw 		EXTI16_23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI8_15
rw 		EXTI0_7
rw
Toggle fields

EXTI0_7

Bits 0-7: EXTIm GPIO port selection.

EXTI8_15

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI16_23

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI24_31

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR4

EXTI external interrupt selection register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI24_31
rw 		EXTI16_23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI8_15
rw 		EXTI0_7
rw
Toggle fields

EXTI0_7

Bits 0-7: EXTIm GPIO port selection.

EXTI8_15

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI16_23

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI24_31

Bits 24-31: EXTIm+3 GPIO port selection.

LOCKRG

EXTI lock register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
rw
Toggle fields

LOCK

Bit 0: LOCK.

IMR1

EXTI CPU wakeup with interrupt mask register

Offset: 0x80, size: 32, reset: 0xFF9E0000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31
rw 		IM30
rw 		IM29
rw 		IM28
rw 		IM27
rw 		IM26
rw 		IM25
rw 		IM24
rw 		IM23
rw 		IM22
rw 		IM21
rw 		IM20
rw 		IM19
rw 		IM18
rw 		IM17
rw 		IM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15
rw 		IM14
rw 		IM13
rw 		IM12
rw 		IM11
rw 		IM10
rw 		IM9
rw 		IM8
rw 		IM7
rw 		IM6
rw 		IM5
rw 		IM4
rw 		IM3
rw 		IM2
rw 		IM1
rw 		IM0
rw
Toggle fields

IM0

Bit 0: CPU wakeup with interrupt mask on event input.

IM1

Bit 1: CPU wakeup with interrupt mask on event input.

IM2

Bit 2: CPU wakeup with interrupt mask on event input.

IM3

Bit 3: CPU wakeup with interrupt mask on event input.

IM4

Bit 4: CPU wakeup with interrupt mask on event input.

IM5

Bit 5: CPU wakeup with interrupt mask on event input.

IM6

Bit 6: CPU wakeup with interrupt mask on event input.

IM7

Bit 7: CPU wakeup with interrupt mask on event input.

IM8

Bit 8: CPU wakeup with interrupt mask on event input.

IM9

Bit 9: CPU wakeup with interrupt mask on event input.

IM10

Bit 10: CPU wakeup with interrupt mask on event input.

IM11

Bit 11: CPU wakeup with interrupt mask on event input.

IM12

Bit 12: CPU wakeup with interrupt mask on event input.

IM13

Bit 13: CPU wakeup with interrupt mask on event input.

IM14

Bit 14: CPU wakeup with interrupt mask on event input.

IM15

Bit 15: CPU wakeup with interrupt mask on event input.

IM16

Bit 16: CPU wakeup with interrupt mask on event input.

IM17

Bit 17: CPU wakeup with interrupt mask on event input.

IM18

Bit 18: CPU wakeup with interrupt mask on event input.

IM19

Bit 19: CPU wakeup with interrupt mask on event input.

IM20

Bit 20: CPU wakeup with interrupt mask on event input.

IM21

Bit 21: CPU wakeup with interrupt mask on event input.

IM22

Bit 22: CPU wakeup with interrupt mask on event input.

IM23

Bit 23: CPU wakeup with interrupt mask on event input.

IM24

Bit 24: CPU wakeup with interrupt mask on event input.

IM25

Bit 25: CPU wakeup with interrupt mask on event input.

IM26

Bit 26: CPU wakeup with interrupt mask on event input.

IM27

Bit 27: CPU wakeup with interrupt mask on event input.

IM28

Bit 28: CPU wakeup with interrupt mask on event input.

IM29

Bit 29: CPU wakeup with interrupt mask on event input.

IM30

Bit 30: CPU wakeup with interrupt mask on event input.

IM31

Bit 31: CPU wakeup with interrupt mask on event input.

EMR1

EXTI CPU wakeup with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM31
rw 		EM30
rw 		EM29
rw 		EM28
rw 		EM27
rw 		EM26
rw 		EM25
rw 		EM24
rw 		EM23
rw 		EM22
rw 		EM21
rw 		EM20
rw 		EM19
rw 		EM18
rw 		EM17
rw 		EM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw 		EM14
rw 		EM13
rw 		EM12
rw 		EM11
rw 		EM10
rw 		EM9
rw 		EM8
rw 		EM7
rw 		EM6
rw 		EM5
rw 		EM4
rw 		EM3
rw 		EM2
rw 		EM1
rw 		EM0
rw
Toggle fields

EM0

Bit 0: CPU wakeup with interrupt mask on event input.

EM1

Bit 1: CPU wakeup with interrupt mask on event input.

EM2

Bit 2: CPU wakeup with interrupt mask on event input.

EM3

Bit 3: CPU wakeup with interrupt mask on event input.

EM4

Bit 4: CPU wakeup with interrupt mask on event input.

EM5

Bit 5: CPU wakeup with interrupt mask on event input.

EM6

Bit 6: CPU wakeup with interrupt mask on event input.

EM7

Bit 7: CPU wakeup with interrupt mask on event input.

EM8

Bit 8: CPU wakeup with interrupt mask on event input.

EM9

Bit 9: CPU wakeup with interrupt mask on event input.

EM10

Bit 10: CPU wakeup with interrupt mask on event input.

EM11

Bit 11: CPU wakeup with interrupt mask on event input.

EM12

Bit 12: CPU wakeup with interrupt mask on event input.

EM13

Bit 13: CPU wakeup with interrupt mask on event input.

EM14

Bit 14: CPU wakeup with interrupt mask on event input.

EM15

Bit 15: CPU wakeup with interrupt mask on event input.

EM16

Bit 16: CPU wakeup with interrupt mask on event input.

EM17

Bit 17: CPU wakeup with interrupt mask on event input.

EM18

Bit 18: CPU wakeup with interrupt mask on event input.

EM19

Bit 19: CPU wakeup with interrupt mask on event input.

EM20

Bit 20: CPU wakeup with interrupt mask on event input.

EM21

Bit 21: CPU wakeup with interrupt mask on event input.

EM22

Bit 22: CPU wakeup with interrupt mask on event input.

EM23

Bit 23: CPU wakeup with interrupt mask on event input.

EM24

Bit 24: CPU wakeup with interrupt mask on event input.

EM25

Bit 25: CPU wakeup with interrupt mask on event input.

EM26

Bit 26: CPU wakeup with interrupt mask on event input.

EM27

Bit 27: CPU wakeup with interrupt mask on event input.

EM28

Bit 28: CPU wakeup with interrupt mask on event input.

EM29

Bit 29: CPU wakeup with interrupt mask on event input.

EM30

Bit 30: CPU wakeup with interrupt mask on event input.

EM31

Bit 31: CPU wakeup with interrupt mask on event input.

IMR2

EXTI CPUm wakeup with interrupt mask register

Offset: 0x90, size: 32, reset: 0x00000787, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM42
rw 		IM41
rw 		IM40
rw 		IM38
rw 		IM37
rw 		IM36
rw 		IM35
rw 		IM34
rw 		IM33
rw 		IM32
rw
Toggle fields

IM32

Bit 0: CPU wakeup with interrupt mask on event input.

IM33

Bit 1: CPU wakeup with interrupt mask on event input.

IM34

Bit 2: CPU wakeup with interrupt mask on event input.

IM35

Bit 3: CPU wakeup with interrupt mask on event input.

IM36

Bit 4: CPU wakeup with interrupt mask on event input.

IM37

Bit 5: CPU wakeup with interrupt mask on event input.

IM38

Bit 6: CPU wakeup with interrupt mask on event input.

IM40

Bit 8: CPU wakeup with interrupt mask on event input.

IM41

Bit 9: CPU wakeup with interrupt mask on event input.

IM42

Bit 10: CPU wakeup with interrupt mask on event input.

EMR2

EXTI CPU wakeup with event mask register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM42
rw 		EM41
rw 		EM40
rw 		EM38
rw 		EM37
rw 		EM36
rw 		EM35
rw 		EM34
rw 		EM33
rw 		EM32
rw
Toggle fields

EM32

Bit 0: CPU wakeup with interrupt mask on event input.

EM33

Bit 1: CPU wakeup with interrupt mask on event input.

EM34

Bit 2: CPU wakeup with interrupt mask on event input.

EM35

Bit 3: CPU wakeup with interrupt mask on event input.

EM36

Bit 4: CPU wakeup with interrupt mask on event input.

EM37

Bit 5: CPU wakeup with interrupt mask on event input.

EM38

Bit 6: CPU wakeup with interrupt mask on event input.

EM40

Bit 8: CPU wakeup with interrupt mask on event input.

EM41

Bit 9: CPU wakeup with interrupt mask on event input.

EM42

Bit 10: CPU wakeup with interrupt mask on event input.

FDCAN1

0x4000a400: FDCAN1

36/159 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FDCAN_CREL
0x4 FDCAN_ENDN
0xc FDCAN_DBTP
0x10 FDCAN_TEST
0x14 FDCAN_RWD
0x18 FDCAN_CCCR
0x1c FDCAN_NBTP
0x20 FDCAN_TSCC
0x24 FDCAN_TSCV
0x28 FDCAN_TOCC
0x2c FDCAN_TOCV
0x40 FDCAN_ECR
0x44 FDCAN_PSR
0x48 FDCAN_TDCR
0x50 FDCAN_IR
0x54 FDCAN_IE
0x58 FDCAN_ILS
0x5c FDCAN_ILE
0x80 FDCAN_RXGFC
0x84 FDCAN_XIDAM
0x88 FDCAN_HPMS
0x90 FDCAN_RXF0S
0x94 FDCAN_RXF0A
0x98 FDCAN_RXF1S
0x9c FDCAN_RXF1A
0xc0 FDCAN_TXBC
0xc4 FDCAN_TXFQS
0xc8 FDCAN_TXBRP
0xcc FDCAN_TXBAR
0xd0 FDCAN_TXBCR
0xd4 FDCAN_TXBTO
0xd8 FDCAN_TXBCF
0xdc FDCAN_TXBTIE
0xe0 FDCAN_TXBCIE
0xe4 FDCAN_TXEFS
0xe8 FDCAN_TXEFA
0x100 FDCAN_CKDIV
Toggle registers

FDCAN_CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r 		STEP
r 		SUBSTEP
r 		YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r 		DAY
r
Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

FDCAN_ENDN

FDCAN Core Release Register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
r
Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

FDCAN_DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDC
rw 		DBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEG1
rw 		DTSEG2
rw 		DSJW
rw
Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

FDCAN_TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000010, access: Unspecified

1/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r 		TX
rw 		LBCK
rw
Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

FDCAN_RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDV
r 		WDC
rw
Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

FDCAN_CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NISO
rw 		TXP
rw 		EFBI
rw 		PXHD
rw 		BSE
rw 		FDOE
rw 		TEST
rw 		DAR
rw 		MON
rw 		CSR
rw 		CSA
rw 		ASM
rw 		CCE
rw 		INIT
rw
Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

FDCAN_NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x06000A03, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSJW
rw 		NBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTSEG1
rw 		TSEG2
rw
Toggle fields

TSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: NSJW: Nominal (Re)Synchronization Jump Width.

FDCAN_TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

FDCAN_TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSC
rw
Toggle fields

TSC

Bits 0-15: Timestamp Counter.

FDCAN_TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOS
rw 		ETOC
rw
Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

FDCAN_TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOC
rw
Toggle fields

TOC

Bits 0-15: Timeout Counter.

FDCAN_ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP
rw 		REC
r 		TEC
r
Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

FDCAN_PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PXE
rw 		REDL
rw 		RBRS
rw 		RESI
rw 		DLEC
rw 		BO
r 		EW
r 		EP
r 		ACT
r 		LEC
rw
Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

FDCAN_TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCO
rw 		TDCF
rw
Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

FDCAN_IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARA
rw 		PED
rw 		PEA
rw 		WDI
rw 		BO
rw 		EW
rw 		EP
rw 		ELO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOO
rw 		MRAF
rw 		TSW
rw 		TEFL
rw 		TEFF
rw 		TEFN
rw 		TFE
rw 		TCF
rw 		TC
rw 		HPM
rw 		RF1L
rw 		RF1F
rw 		RF1N
rw 		RF0L
rw 		RF0F
rw 		RF0N
rw
Toggle fields

RF0N

Bit 0: RF0N.

RF0F

Bit 1: RF0F.

RF0L

Bit 2: RF0L.

RF1N

Bit 3: RF1N.

RF1F

Bit 4: RF1F.

RF1L

Bit 5: RF1L.

HPM

Bit 6: HPM.

TC

Bit 7: TC.

TCF

Bit 8: TCF.

TFE

Bit 9: TFE.

TEFN

Bit 10: TEFN.

TEFF

Bit 11: TEFF.

TEFL

Bit 12: TEFL.

TSW

Bit 13: TSW.

MRAF

Bit 14: MRAF.

TOO

Bit 15: TOO.

ELO

Bit 16: ELO.

EP

Bit 17: EP.

EW

Bit 18: EW.

BO

Bit 19: BO.

WDI

Bit 20: WDI.

PEA

Bit 21: PEA.

PED

Bit 22: PED.

ARA

Bit 23: ARA.

FDCAN_IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAE
rw 		PEDE
rw 		PEAE
rw 		WDIE
rw 		BOE
rw 		EWE
rw 		EPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELOE
rw 		TOOE
rw 		MRAFE
rw 		TEFLE
rw 		TEFFE
rw 		TEFNE
rw 		TEFE
rw 		TCFE
rw 		TCE
rw 		HPME
rw 		RF1LE
rw 		RF1FE
rw 		RF1NE
rw 		RF0LE
rw 		RF0FE
rw 		RF0NE
rw
Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0FE

Bit 1: Rx FIFO 0 Full Enable.

RF0LE

Bit 2: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 3: Rx FIFO 1 New Message Enable.

RF1FE

Bit 4: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 5: Rx FIFO 1 Message Lost Enable.

HPME

Bit 6: High Priority Message Enable.

TCE

Bit 7: Transmission Completed Enable.

TCFE

Bit 8: Transmission Cancellation Finished Enable.

TEFE

Bit 9: Tx FIFO Empty Enable.

TEFNE

Bit 10: Tx Event FIFO New Entry Enable.

TEFFE

Bit 11: Tx Event FIFO Full Enable.

TEFLE

Bit 12: Tx Event FIFO Element Lost Enable.

MRAFE

Bit 13: Message RAM Access Failure Enable.

TOOE

Bit 14: Timeout Occurred Enable.

ELOE

Bit 15: Error Logging Overflow Enable.

EPE

Bit 16: Error Passive Enable.

EWE

Bit 17: Warning Status Enable.

BOE

Bit 18: Bus_Off Status Enable.

WDIE

Bit 19: Watchdog Interrupt Enable.

PEAE

Bit 20: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 21: Protocol Error in Data Phase Enable.

ARAE

Bit 22: Access to Reserved Address Enable.

FDCAN_ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERR
rw 		BERR
rw 		MISC
rw 		TFERR
rw 		SMSG
rw 		RxFIFO1
rw 		RxFIFO0
rw
Toggle fields

RxFIFO0

Bit 0: RxFIFO0.

RxFIFO1

Bit 1: RxFIFO1.

SMSG

Bit 2: SMSG.

TFERR

Bit 3: TFERR.

MISC

Bit 4: MISC.

BERR

Bit 5: BERR.

PERR

Bit 6: PERR.

FDCAN_ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EINT1
rw 		EINT0
rw
Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

FDCAN_RXGFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE
rw 		LSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0OM
rw 		F1OM
rw 		ANFS
rw 		ANFE
rw 		RRFS
rw 		RRFE
rw
Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

F1OM

Bit 8: F1OM.

F0OM

Bit 9: F0OM.

LSS

Bits 16-20: LSS.

LSE

Bits 24-27: LSE.

FDCAN_XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x84, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIDM
rw
Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

FDCAN_HPMS

FDCAN High Priority Message Status Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLST
r 		FIDX
r 		MSI
r 		BIDX
r
Toggle fields

BIDX

Bits 0-2: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-12: Filter Index.

FLST

Bit 15: Filter List.

FDCAN_RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF0L
rw 		F0F
rw 		F0PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0GI
rw 		F0FL
rw
Toggle fields

F0FL

Bits 0-3: Rx FIFO 0 Fill Level.

F0GI

Bits 8-9: Rx FIFO 0 Get Index.

F0PI

Bits 16-17: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

FDCAN_RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0AI
rw
Toggle fields

F0AI

Bits 0-2: Rx FIFO 0 Acknowledge Index.

FDCAN_RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF1L
r 		F1F
r 		F1PI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1GI
r 		F1FL
rw
Toggle fields

F1FL

Bits 0-3: Rx FIFO 1 Fill Level.

F1GI

Bits 8-9: Rx FIFO 1 Get Index.

F1PI

Bits 16-17: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

FDCAN_RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1AI
rw
Toggle fields

F1AI

Bits 0-2: Rx FIFO 1 Acknowledge Index.

FDCAN_TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

TFQM

Bit 24: Tx FIFO/Queue Mode.

FDCAN_TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000003, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQF
r 		TFQPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFGI
r 		TFFL
r
Toggle fields

TFFL

Bits 0-2: Tx FIFO Free Level.

TFGI

Bits 8-9: TFGI.

TFQPI

Bits 16-17: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

FDCAN_TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRP
r
Toggle fields

TRP

Bits 0-2: Transmission Request Pending.

FDCAN_TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
rw
Toggle fields

AR

Bits 0-2: Add Request.

FDCAN_TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
rw
Toggle fields

CR

Bits 0-2: Cancellation Request.

FDCAN_TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
r
Toggle fields

TO

Bits 0-2: Transmission Occurred..

FDCAN_TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
r
Toggle fields

CF

Bits 0-2: Cancellation Finished.

FDCAN_TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
Toggle fields

TIE

Bits 0-2: Transmission Interrupt Enable.

FDCAN_TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
rw
Toggle fields

CF

Bits 0-2: Cancellation Finished Interrupt Enable.

FDCAN_TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEFL
r 		EFF
r 		EFPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFGI
r 		EFFL
r
Toggle fields

EFFL

Bits 0-2: Event FIFO Fill Level.

EFGI

Bits 8-9: Event FIFO Get Index..

EFPI

Bits 16-17: Event FIFO Put Index.

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

FDCAN_TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFAI
rw
Toggle fields

EFAI

Bits 0-1: Event FIFO Acknowledge Index.

FDCAN_CKDIV

FDCAN TT Trigger Memory Configuration Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDIV
rw
Toggle fields

PDIV

Bits 0-3: PDIV.

FLASH

0x40022000: Flash

5/114 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 PDKEYR
0x8 NSKEYR
0xc SECKEYR
0x10 OPTKEYR
0x14 LVEKEYR
0x20 NSSR
0x24 SECSR
0x28 NSCR
0x2c SECCR
0x30 ECCR
0x40 OPTR
0x44 NSBOOTADD0R
0x48 NSBOOTADD1R
0x4c SECBOOTADD0R
0x50 SECWM1R1
0x54 SECWM1R2
0x58 WRP1AR
0x5c WRP1BR
0x60 SECWM2R1
0x64 SECWM2R2
0x68 WRP2AR
0x6c WRP2BR
0x80 SECBB1R[1]
0x84 SECBB1R[2]
0x88 SECBB1R[3]
0x8c SECBB1R[4]
0xa0 SECBB2R[1]
0xa4 SECBB2R[2]
0xa8 SECBB2R[3]
0xac SECBB2R[4]
0xc0 SECHDPCR
0xc4 PRIVCFGR
Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEN
rw 		SLEEP_PD
rw 		RUN_PD
rw 		LATENCY
rw
Toggle fields

LATENCY

Bits 0-3: Latency.

RUN_PD

Bit 13: Flash Power-down mode during Low-power run mode.

SLEEP_PD

Bit 14: Flash Power-down mode during Low-power sleep mode.

LVEN

Bit 15: LVEN.

PDKEYR

Power down key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR
w
Toggle fields

PDKEYR

Bits 0-31: RUN_PD in FLASH_ACR key.

NSKEYR

Flash non-secure key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSKEYR
w
Toggle fields

NSKEYR

Bits 0-31: NSKEYR.

SECKEYR

Flash secure key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECKEYR
w
Toggle fields

SECKEYR

Bits 0-31: SECKEYR.

OPTKEYR

Flash option key register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle fields

OPTKEYR

Bits 0-31: OPTKEYR.

LVEKEYR

Flash low voltage key register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVEKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEKEYR
w
Toggle fields

LVEKEYR

Bits 0-31: LVEKEYR.

NSSR

Flash status register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR
rw 		OPTWERR
rw 		NSPGSERR
rw 		NSSIZERR
rw 		NSPGAERR
rw 		NSWRPERR
rw 		NSPROGERR
rw 		NSOPERR
rw 		NSEOP
rw
Toggle fields

NSEOP

Bit 0: NSEOP.

NSOPERR

Bit 1: NSOPERR.

NSPROGERR

Bit 3: NSPROGERR.

NSWRPERR

Bit 4: NSWRPERR.

NSPGAERR

Bit 5: NSPGAERR.

NSSIZERR

Bit 6: NSSIZERR.

NSPGSERR

Bit 7: NSPGSERR.

OPTWERR

Bit 13: OPTWERR.

OPTVERR

Bit 15: OPTVERR.

NSBSY

Bit 16: NSBusy.

SECSR

Flash status register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECRDERR
rw 		SECPGSERR
rw 		SECSIZERR
rw 		SECPGAERR
rw 		SECWRPERR
rw 		SECPROGERR
rw 		SECOPERR
rw 		SECEOP
rw
Toggle fields

SECEOP

Bit 0: SECEOP.

SECOPERR

Bit 1: SECOPERR.

SECPROGERR

Bit 3: SECPROGERR.

SECWRPERR

Bit 4: SECWRPERR.

SECPGAERR

Bit 5: SECPGAERR.

SECSIZERR

Bit 6: SECSIZERR.

SECPGSERR

Bit 7: SECPGSERR.

SECRDERR

Bit 14: Secure read protection error.

SECBSY

Bit 16: SECBusy.

NSCR

Flash non-secure control register

Offset: 0x28, size: 32, reset: 0xC0000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSLOCK
rw 		OPTLOCK
rw 		OBL_LAUNCH
rw 		NSERRIE
rw 		NSEOPIE
rw 		OPTSTRT
rw 		NSSTRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSMER2
rw 		NSBKER
rw 		NSPNB
rw 		NSMER1
rw 		NSPER
rw 		NSPG
rw
Toggle fields

NSPG

Bit 0: NSPG.

NSPER

Bit 1: NSPER.

NSMER1

Bit 2: NSMER1.

NSPNB

Bits 3-9: NSPNB.

NSBKER

Bit 11: NSBKER.

NSMER2

Bit 15: NSMER2.

NSSTRT

Bit 16: Options modification start.

OPTSTRT

Bit 17: Options modification start.

NSEOPIE

Bit 24: NSEOPIE.

NSERRIE

Bit 25: NSERRIE.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

NSLOCK

Bit 31: NSLOCK.

SECCR

Flash secure control register

Offset: 0x2c, size: 32, reset: 0x80000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECLOCK
rw 		SECINV
rw 		SECRDERRIE
rw 		SECERRIE
rw 		SECEOPIE
rw 		SECSTRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECMER2
rw 		SECBKER
rw 		SECPNB
rw 		SECMER1
rw 		SECPER
rw 		SECPG
rw
Toggle fields

SECPG

Bit 0: SECPG.

SECPER

Bit 1: SECPER.

SECMER1

Bit 2: SECMER1.

SECPNB

Bits 3-9: SECPNB.

SECBKER

Bit 11: SECBKER.

SECMER2

Bit 15: SECMER2.

SECSTRT

Bit 16: SECSTRT.

SECEOPIE

Bit 24: SECEOPIE.

SECERRIE

Bit 25: SECERRIE.

SECRDERRIE

Bit 26: SECRDERRIE.

SECINV

Bit 29: SECINV.

SECLOCK

Bit 31: SECLOCK.

ECCR

Flash ECC register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD
rw 		ECCC
rw 		ECCD2
rw 		ECCC2
rw 		ECCIE
rw 		SYSF_ECC
r 		BK_ECC
r 		ADDR_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC
r
Toggle fields

ADDR_ECC

Bits 0-18: ECC fail address.

BK_ECC

Bit 21: BK_ECC.

SYSF_ECC

Bit 22: SYSF_ECC.

ECCIE

Bit 24: ECC correction interrupt enable.

ECCC2

Bit 28: ECCC2.

ECCD2

Bit 29: ECCD2.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZEN
rw 		PA15_PUPEN
rw 		nBOOT0
rw 		nSWBOOT0
rw 		SRAM2_RST
rw 		SRAM2_PE
rw 		DBANK
rw 		DB256K
rw 		SWAP_BANK
rw 		WWDG_SW
rw 		IWDG_STDBY
rw 		IWDG_STOP
rw 		IWDG_SW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_SHDW
rw 		nRST_STDBY
rw 		nRST_STOP
rw 		BOR_LEV
rw 		RDP
rw
Toggle fields

RDP

Bits 0-7: Read protection level.

BOR_LEV

Bits 8-10: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

nRST_SHDW

Bit 14: nRST_SHDW.

IWDG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

SWAP_BANK

Bit 20: SWAP_BANK.

DB256K

Bit 21: DB256K.

DBANK

Bit 22: DBANK.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: nSWBOOT0.

nBOOT0

Bit 27: nBOOT0.

PA15_PUPEN

Bit 28: PA15_PUPEN.

TZEN

Bit 31: TZEN.

NSBOOTADD0R

Flash non-secure boot address 0 register

Offset: 0x44, size: 32, reset: 0x0000000F, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD0
w
Toggle fields

NSBOOTADD0

Bits 7-31: NSBOOTADD0.

NSBOOTADD1R

Flash non-secure boot address 1 register

Offset: 0x48, size: 32, reset: 0x0000000F, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD1
w
Toggle fields

NSBOOTADD1

Bits 7-31: NSBOOTADD1.

SECBOOTADD0R

FFlash secure boot address 0 register

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBOOTADD0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBOOTADD0
w 		BOOT_LOCK
rw
Toggle fields

BOOT_LOCK

Bit 0: BOOT_LOCK.

SECBOOTADD0

Bits 7-31: SECBOOTADD0.

SECWM1R1

Flash bank 1 secure watermak1 register

Offset: 0x50, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECWM1_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECWM1_PSTRT
rw
Toggle fields

SECWM1_PSTRT

Bits 0-6: SECWM1_PSTRT.

SECWM1_PEND

Bits 16-22: SECWM1_PEND.

SECWM1R2

Flash secure watermak1 register 2

Offset: 0x54, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP1EN
rw 		HDP1_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1EN
rw 		PCROP1_PSTRT
rw
Toggle fields

PCROP1_PSTRT

Bits 0-6: PCROP1_PSTRT.

PCROP1EN

Bit 15: PCROP1EN.

HDP1_PEND

Bits 16-22: HDP1_PEND.

HDP1EN

Bit 31: HDP1EN.

WRP1AR

Flash Bank 1 WRP area A address register

Offset: 0x58, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1A_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1A_PSTRT
rw
Toggle fields

WRP1A_PSTRT

Bits 0-6: WRP1A_PSTRT.

WRP1A_PEND

Bits 16-22: WRP1A_PEND.

WRP1BR

Flash Bank 1 WRP area B address register

Offset: 0x5c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1B_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1B_PSTRT
rw
Toggle fields

WRP1B_PSTRT

Bits 0-6: WRP1B_PSTRT.

WRP1B_PEND

Bits 16-22: WRP1B_PEND.

SECWM2R1

Flash secure watermak2 register

Offset: 0x60, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECWM2_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECWM2_PSTRT
rw
Toggle fields

SECWM2_PSTRT

Bits 0-6: SECWM2_PSTRT.

SECWM2_PEND

Bits 16-22: SECWM2_PEND.

SECWM2R2

Flash secure watermak2 register2

Offset: 0x64, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP2EN
rw 		HDP2_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2EN
rw 		PCROP2_PSTRT
rw
Toggle fields

PCROP2_PSTRT

Bits 0-6: PCROP2_PSTRT.

PCROP2EN

Bit 15: PCROP2EN.

HDP2_PEND

Bits 16-22: HDP2_PEND.

HDP2EN

Bit 31: HDP2EN.

WRP2AR

Flash WPR2 area A address register

Offset: 0x68, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2A_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2A_PSTRT
rw
Toggle fields

WRP2A_PSTRT

Bits 0-6: WRP2A_PSTRT.

WRP2A_PEND

Bits 16-22: WRP2A_PEND.

WRP2BR

Flash WPR2 area B address register

Offset: 0x6c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2B_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2B_PSTRT
rw
Toggle fields

WRP2B_PSTRT

Bits 0-6: WRP2B_PSTRT.

WRP2B_PEND

Bits 16-22: WRP2B_PEND.

SECBB1R[1]

FLASH secure block based bank 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[2]

FLASH secure block based bank 1

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[3]

FLASH secure block based bank 1

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[4]

FLASH secure block based bank 1

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB2R[1]

FLASH secure block based bank 2

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[2]

FLASH secure block based bank 2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[3]

FLASH secure block based bank 2

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[4]

FLASH secure block based bank 2

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECHDPCR

FLASH secure HDP control register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDP2_ACCDIS
rw 		HDP1_ACCDIS
rw
Toggle fields

HDP1_ACCDIS

Bit 0: HDP1_ACCDIS.

HDP2_ACCDIS

Bit 1: HDP2_ACCDIS.

PRIVCFGR

Power privilege configuration register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
Toggle fields

PRIV

Bit 0: PRIV.

FMC

0x44020000: FMC

2/149 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BCR1
0x4 BTR1
0x8 BCR2
0xc BTR2
0x10 BCR3
0x14 BTR3
0x18 BCR4
0x1c BTR4
0x20 PCSCNTR
0x80 PCR
0x84 SR
0x88 PMEM
0x8c PATT
0x94 ECCR
0x104 BWTR1
0x10c BWTR2
0x114 BWTR3
0x11c BWTR4
Toggle registers

BCR1

FMC_BCR1

Offset: 0x0, size: 32, reset: 0x000030DB, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw 		WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

NBLSET

Bits 22-23: NBLSET.

BTR1

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0x4, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

DATAHLD

Bits 30-31: DATAHLD.

BCR2

FMC_BCR2

Offset: 0x8, size: 32, reset: 0x000030D2, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw 		WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

NBLSET

Bits 22-23: NBLSET.

BTR2

FMC_BTR2

Offset: 0xc, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

DATAHLD

Bits 30-31: DATAHLD.

BCR3

>FMC_BCR3

Offset: 0x10, size: 32, reset: 0x000030D2, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw 		WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

NBLSET

Bits 22-23: NBLSET.

BTR3

FMC_BTR3

Offset: 0x14, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

DATAHLD

Bits 30-31: DATAHLD.

BCR4

>FMC_BCR4

Offset: 0x18, size: 32, reset: 0x000030D2, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw 		WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

NBLSET

Bits 22-23: NBLSET.

BTR4

FMC_BTR4

Offset: 0x1c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

DATAHLD

Bits 30-31: DATAHLD.

PCSCNTR

PCSCNTR

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTB4EN
rw 		CNTB3EN
rw 		CNTB2EN
rw 		CNTB1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCOUNT
rw
Toggle fields

CSCOUNT

Bits 0-15: Chip select counter.

CNTB1EN

Bit 16: Counter Bank 1 enable.

CNTB2EN

Bit 17: Counter Bank 2 enable.

CNTB3EN

Bit 18: Counter Bank 3 enable.

CNTB4EN

Bit 19: Counter Bank 4 enable.

PCR

NAND Flash control registers

Offset: 0x80, size: 32, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw 		TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw 		TCLR
rw 		ECCEN
rw 		PWID
rw 		PTYP
rw 		PBKEN
rw 		PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:.

PBKEN

Bit 2: NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus.

PTYP

Bit 3: Memory type.

PWID

Bits 4-5: Data bus width. These bits define the external memory device width..

ECCEN

Bit 6: ECC computation logic enable bit.

TCLR

Bits 9-12: CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

TAR

Bits 13-16: ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

ECCPS

Bits 17-19: ECC page size. These bits define the page size for the extended ECC:.

SR

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Offset: 0x84, size: 32, reset: 0x00000040, access: Unspecified

1/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r 		IFEN
rw 		ILEN
rw 		IREN
rw 		IFS
rw 		ILS
rw 		IRS
rw
Toggle fields

IRS

Bit 0: Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

ILS

Bit 1: Interrupt high-level status The flag is set by hardware and reset by software..

IFS

Bit 2: Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

IREN

Bit 3: Interrupt rising edge detection enable bit.

ILEN

Bit 4: Interrupt high-level detection enable bit.

IFEN

Bit 5: Interrupt falling edge detection enable bit.

FEMPT

Bit 6: FIFO empty. Read-only bit that provides the status of the FIFO.

PMEM

The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.

Offset: 0x88, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw 		MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw 		MEMSET
rw
Toggle fields

MEMSET

Bits 0-7: Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:.

MEMWAIT

Bits 8-15: Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

MEMHOLD

Bits 16-23: Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:.

MEMHIZ

Bits 24-31: Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:.

PATT

The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

Offset: 0x8c, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle fields

ATTSET

Bits 0-7: Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

ATTWAIT

Bits 8-15: Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

ATTHOLD

Bits 16-23: Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

ATTHIZ

Bits 24-31: Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:.

ECCR

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle fields

ECC

Bits 0-31: ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields..

BWTR1

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

BWTR2

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

BWTR3

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x114, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

BWTR4

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x11c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

GPIOA

0x42020000: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

GPIOB

0x42020400: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

GPIOC

0x42020800: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

GPIOD

0x42020c00: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

GPIOE

0x42021000: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

GPIOF

0x42021400: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

GPIOG

0x42021800: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

GPIOH

0x42021c00: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x0000000F, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

GTZC_MPCBB1

0x40032c00: GTZC_MPCBB1

0/2115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 LCKVTR1
0x14 LCKVTR2
0x100 VCTR0
0x104 VCTR1
0x108 VCTR2
0x10c VCTR3
0x110 VCTR4
0x114 VCTR5
0x118 VCTR6
0x11c VCTR7
0x120 VCTR8
0x124 VCTR9
0x128 VCTR10
0x12c VCTR11
0x130 VCTR12
0x134 VCTR13
0x138 VCTR14
0x13c VCTR15
0x140 VCTR16
0x144 VCTR17
0x148 VCTR18
0x14c VCTR19
0x150 VCTR20
0x154 VCTR21
0x158 VCTR22
0x15c VCTR23
0x160 VCTR24
0x164 VCTR25
0x168 VCTR26
0x16c VCTR27
0x170 VCTR28
0x174 VCTR29
0x178 VCTR30
0x17c VCTR31
0x180 VCTR32
0x184 VCTR33
0x188 VCTR34
0x18c VCTR35
0x190 VCTR36
0x194 VCTR37
0x198 VCTR38
0x19c VCTR39
0x1a0 VCTR40
0x1a4 VCTR41
0x1a8 VCTR42
0x1ac VCTR43
0x1b0 VCTR44
0x1b4 VCTR45
0x1b8 VCTR46
0x1bc VCTR47
0x1c0 VCTR48
0x1c4 VCTR49
0x1c8 VCTR50
0x1cc VCTR51
0x1d0 VCTR52
0x1d4 VCTR53
0x1d8 VCTR54
0x1dc VCTR55
0x1e0 VCTR56
0x1e4 VCTR57
0x1e8 VCTR58
0x1ec VCTR59
0x1f0 VCTR60
0x1f4 VCTR61
0x1f8 VCTR62
0x1fc VCTR63
Toggle registers

CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRWILADIS
rw 		INVSECSTATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

INVSECSTATE

Bit 30: INVSECSTATE.

SRWILADIS

Bit 31: SRWILADIS.

LCKVTR1

MPCBB control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKSB31
rw 		LCKSB30
rw 		LCKSB29
rw 		LCKSB28
rw 		LCKSB27
rw 		LCKSB26
rw 		LCKSB25
rw 		LCKSB24
rw 		LCKSB23
rw 		LCKSB22
rw 		LCKSB21
rw 		LCKSB20
rw 		LCKSB19
rw 		LCKSB18
rw 		LCKSB17
rw 		LCKSB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB15
rw 		LCKSB14
rw 		LCKSB13
rw 		LCKSB12
rw 		LCKSB11
rw 		LCKSB10
rw 		LCKSB9
rw 		LCKSB8
rw 		LCKSB7
rw 		LCKSB6
rw 		LCKSB5
rw 		LCKSB4
rw 		LCKSB3
rw 		LCKSB2
rw 		LCKSB1
rw 		LCKSB0
rw
Toggle fields

LCKSB0

Bit 0: LCKSB0.

LCKSB1

Bit 1: LCKSB1.

LCKSB2

Bit 2: LCKSB2.

LCKSB3

Bit 3: LCKSB3.

LCKSB4

Bit 4: LCKSB4.

LCKSB5

Bit 5: LCKSB5.

LCKSB6

Bit 6: LCKSB6.

LCKSB7

Bit 7: LCKSB7.

LCKSB8

Bit 8: LCKSB8.

LCKSB9

Bit 9: LCKSB9.

LCKSB10

Bit 10: LCKSB10.

LCKSB11

Bit 11: LCKSB11.

LCKSB12

Bit 12: LCKSB12.

LCKSB13

Bit 13: LCKSB13.

LCKSB14

Bit 14: LCKSB14.

LCKSB15

Bit 15: LCKSB15.

LCKSB16

Bit 16: LCKSB16.

LCKSB17

Bit 17: LCKSB17.

LCKSB18

Bit 18: LCKSB18.

LCKSB19

Bit 19: LCKSB19.

LCKSB20

Bit 20: LCKSB20.

LCKSB21

Bit 21: LCKSB21.

LCKSB22

Bit 22: LCKSB22.

LCKSB23

Bit 23: LCKSB23.

LCKSB24

Bit 24: LCKSB24.

LCKSB25

Bit 25: LCKSB25.

LCKSB26

Bit 26: LCKSB26.

LCKSB27

Bit 27: LCKSB27.

LCKSB28

Bit 28: LCKSB28.

LCKSB29

Bit 29: LCKSB29.

LCKSB30

Bit 30: LCKSB30.

LCKSB31

Bit 31: LCKSB31.

LCKVTR2

MPCBB control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKSB63
rw 		LCKSB62
rw 		LCKSB61
rw 		LCKSB60
rw 		LCKSB59
rw 		LCKSB58
rw 		LCKSB57
rw 		LCKSB56
rw 		LCKSB55
rw 		LCKSB54
rw 		LCKSB53
rw 		LCKSB52
rw 		LCKSB51
rw 		LCKSB50
rw 		LCKSB49
rw 		LCKSB48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB47
rw 		LCKSB46
rw 		LCKSB45
rw 		LCKSB44
rw 		LCKSB43
rw 		LCKSB42
rw 		LCKSB41
rw 		LCKSB40
rw 		LCKSB39
rw 		LCKSB38
rw 		LCKSB37
rw 		LCKSB36
rw 		LCKSB35
rw 		LCKSB34
rw 		LCKSB33
rw 		LCKSB32
rw
Toggle fields

LCKSB32

Bit 0: LCKSB32.

LCKSB33

Bit 1: LCKSB33.

LCKSB34

Bit 2: LCKSB34.

LCKSB35

Bit 3: LCKSB35.

LCKSB36

Bit 4: LCKSB36.

LCKSB37

Bit 5: LCKSB37.

LCKSB38

Bit 6: LCKSB38.

LCKSB39

Bit 7: LCKSB39.

LCKSB40

Bit 8: LCKSB40.

LCKSB41

Bit 9: LCKSB41.

LCKSB42

Bit 10: LCKSB42.

LCKSB43

Bit 11: LCKSB43.

LCKSB44

Bit 12: LCKSB44.

LCKSB45

Bit 13: LCKSB45.

LCKSB46

Bit 14: LCKSB46.

LCKSB47

Bit 15: LCKSB47.

LCKSB48

Bit 16: LCKSB48.

LCKSB49

Bit 17: LCKSB49.

LCKSB50

Bit 18: LCKSB50.

LCKSB51

Bit 19: LCKSB51.

LCKSB52

Bit 20: LCKSB52.

LCKSB53

Bit 21: LCKSB53.

LCKSB54

Bit 22: LCKSB54.

LCKSB55

Bit 23: LCKSB55.

LCKSB56

Bit 24: LCKSB56.

LCKSB57

Bit 25: LCKSB57.

LCKSB58

Bit 26: LCKSB58.

LCKSB59

Bit 27: LCKSB59.

LCKSB60

Bit 28: LCKSB60.

LCKSB61

Bit 29: LCKSB61.

LCKSB62

Bit 30: LCKSB62.

LCKSB63

Bit 31: LCKSB63.

VCTR0

MPCBBx vector register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw 		B30
rw 		B29
rw 		B28
rw 		B27
rw 		B26
rw 		B25
rw 		B24
rw 		B23
rw 		B22
rw 		B21
rw 		B20
rw 		B19
rw 		B18
rw 		B17
rw 		B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw 		B14
rw 		B13
rw 		B12
rw 		B11
rw 		B10
rw 		B9
rw 		B8
rw 		B7
rw 		B6
rw 		B5
rw 		B4
rw 		B3
rw 		B2
rw 		B1
rw 		B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR1

MPCBBx vector register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B63
rw 		B62
rw 		B61
rw 		B60
rw 		B59
rw 		B58
rw 		B57
rw 		B56
rw 		B55
rw 		B54
rw 		B53
rw 		B52
rw 		B51
rw 		B50
rw 		B49
rw 		B48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B47
rw 		B46
rw 		B45
rw 		B44
rw 		B43
rw 		B42
rw 		B41
rw 		B40
rw 		B39
rw 		B38
rw 		B37
rw 		B36
rw 		B35
rw 		B34
rw 		B33
rw 		B32
rw
Toggle fields

B32

Bit 0: B32.

B33

Bit 1: B33.

B34

Bit 2: B34.

B35

Bit 3: B35.

B36

Bit 4: B36.

B37

Bit 5: B37.

B38

Bit 6: B38.

B39

Bit 7: B39.

B40

Bit 8: B40.

B41

Bit 9: B41.

B42

Bit 10: B42.

B43

Bit 11: B43.

B44

Bit 12: B44.

B45

Bit 13: B45.

B46

Bit 14: B46.

B47

Bit 15: B47.

B48

Bit 16: B48.

B49

Bit 17: B49.

B50

Bit 18: B50.

B51

Bit 19: B51.

B52

Bit 20: B52.

B53

Bit 21: B53.

B54

Bit 22: B54.

B55

Bit 23: B55.

B56

Bit 24: B56.

B57

Bit 25: B57.

B58

Bit 26: B58.

B59

Bit 27: B59.

B60

Bit 28: B60.

B61

Bit 29: B61.

B62

Bit 30: B62.

B63

Bit 31: B63.

VCTR2

MPCBBx vector register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B95
rw 		B94
rw 		B93
rw 		B92
rw 		B91
rw 		B90
rw 		B89
rw 		B88
rw 		B87
rw 		B86
rw 		B85
rw 		B84
rw 		B83
rw 		B82
rw 		B81
rw 		B80
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B79
rw 		B78
rw 		B77
rw 		B76
rw 		B75
rw 		B74
rw 		B73
rw 		B72
rw 		B71
rw 		B70
rw 		B69
rw 		B68
rw 		B67
rw 		B66
rw 		B65
rw 		B64
rw
Toggle fields

B64

Bit 0: B64.

B65

Bit 1: B65.

B66

Bit 2: B66.

B67

Bit 3: B67.

B68

Bit 4: B68.

B69

Bit 5: B69.

B70

Bit 6: B70.

B71

Bit 7: B71.

B72

Bit 8: B72.

B73

Bit 9: B73.

B74

Bit 10: B74.

B75

Bit 11: B75.

B76

Bit 12: B76.

B77

Bit 13: B77.

B78

Bit 14: B78.

B79

Bit 15: B79.

B80

Bit 16: B80.

B81

Bit 17: B81.

B82

Bit 18: B82.

B83

Bit 19: B83.

B84

Bit 20: B84.

B85

Bit 21: B85.

B86

Bit 22: B86.

B87

Bit 23: B87.

B88

Bit 24: B88.

B89

Bit 25: B89.

B90

Bit 26: B90.

B91

Bit 27: B91.

B92

Bit 28: B92.

B93

Bit 29: B93.

B94

Bit 30: B94.

B95

Bit 31: B95.

VCTR3

MPCBBx vector register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B127
rw 		B126
rw 		B125
rw 		B124
rw 		B123
rw 		B122
rw 		B121
rw 		B120
rw 		B119
rw 		B118
rw 		B117
rw 		B116
rw 		B115
rw 		B114
rw 		B113
rw 		B112
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B111
rw 		B110
rw 		B109
rw 		B108
rw 		B107
rw 		B106
rw 		B105
rw 		B104
rw 		B103
rw 		B102
rw 		B101
rw 		B100
rw 		B99
rw 		B98
rw 		B97
rw 		B96
rw
Toggle fields

B96

Bit 0: B96.

B97

Bit 1: B97.

B98

Bit 2: B98.

B99

Bit 3: B99.

B100

Bit 4: B100.

B101

Bit 5: B101.

B102

Bit 6: B102.

B103

Bit 7: B103.

B104

Bit 8: B104.

B105

Bit 9: B105.

B106

Bit 10: B106.

B107

Bit 11: B107.

B108

Bit 12: B108.

B109

Bit 13: B109.

B110

Bit 14: B110.

B111

Bit 15: B111.

B112

Bit 16: B112.

B113

Bit 17: B113.

B114

Bit 18: B114.

B115

Bit 19: B115.

B116

Bit 20: B116.

B117

Bit 21: B117.

B118

Bit 22: B118.

B119

Bit 23: B119.

B120

Bit 24: B120.

B121

Bit 25: B121.

B122

Bit 26: B122.

B123

Bit 27: B123.

B124

Bit 28: B124.

B125

Bit 29: B125.

B126

Bit 30: B126.

B127

Bit 31: B127.

VCTR4

MPCBBx vector register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B159
rw 		B158
rw 		B157
rw 		B156
rw 		B155
rw 		B154
rw 		B153
rw 		B152
rw 		B151
rw 		B150
rw 		B149
rw 		B148
rw 		B147
rw 		B146
rw 		B145
rw 		B144
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B143
rw 		B142
rw 		B141
rw 		B140
rw 		B139
rw 		B138
rw 		B137
rw 		B136
rw 		B135
rw 		B134
rw 		B133
rw 		B132
rw 		B131
rw 		B130
rw 		B129
rw 		B128
rw
Toggle fields

B128

Bit 0: B128.

B129

Bit 1: B129.

B130

Bit 2: B130.

B131

Bit 3: B131.

B132

Bit 4: B132.

B133

Bit 5: B133.

B134

Bit 6: B134.

B135

Bit 7: B135.

B136

Bit 8: B136.

B137

Bit 9: B137.

B138

Bit 10: B138.

B139

Bit 11: B139.

B140

Bit 12: B140.

B141

Bit 13: B141.

B142

Bit 14: B142.

B143

Bit 15: B143.

B144

Bit 16: B144.

B145

Bit 17: B145.

B146

Bit 18: B146.

B147

Bit 19: B147.

B148

Bit 20: B148.

B149

Bit 21: B149.

B150

Bit 22: B150.

B151

Bit 23: B151.

B152

Bit 24: B152.

B153

Bit 25: B153.

B154

Bit 26: B154.

B155

Bit 27: B155.

B156

Bit 28: B156.

B157

Bit 29: B157.

B158

Bit 30: B158.

B159

Bit 31: B159.

VCTR5

MPCBBx vector register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B191
rw 		B190
rw 		B189
rw 		B188
rw 		B187
rw 		B186
rw 		B185
rw 		B184
rw 		B183
rw 		B182
rw 		B181
rw 		B180
rw 		B179
rw 		B178
rw 		B177
rw 		B176
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B175
rw 		B174
rw 		B173
rw 		B172
rw 		B171
rw 		B170
rw 		B169
rw 		B168
rw 		B167
rw 		B166
rw 		B165
rw 		B164
rw 		B163
rw 		B162
rw 		B161
rw 		B160
rw
Toggle fields

B160

Bit 0: B160.

B161

Bit 1: B161.

B162

Bit 2: B162.

B163

Bit 3: B163.

B164

Bit 4: B164.

B165

Bit 5: B165.

B166

Bit 6: B166.

B167

Bit 7: B167.

B168

Bit 8: B168.

B169

Bit 9: B169.

B170

Bit 10: B170.

B171

Bit 11: B171.

B172

Bit 12: B172.

B173

Bit 13: B173.

B174

Bit 14: B174.

B175

Bit 15: B175.

B176

Bit 16: B176.

B177

Bit 17: B177.

B178

Bit 18: B178.

B179

Bit 19: B179.

B180

Bit 20: B180.

B181

Bit 21: B181.

B182

Bit 22: B182.

B183

Bit 23: B183.

B184

Bit 24: B184.

B185

Bit 25: B185.

B186

Bit 26: B186.

B187

Bit 27: B187.

B188

Bit 28: B188.

B189

Bit 29: B189.

B190

Bit 30: B190.

B191

Bit 31: B191.

VCTR6

MPCBBx vector register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B223
rw 		B222
rw 		B221
rw 		B220
rw 		B219
rw 		B218
rw 		B217
rw 		B216
rw 		B215
rw 		B214
rw 		B213
rw 		B212
rw 		B211
rw 		B210
rw 		B209
rw 		B208
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B207
rw 		B206
rw 		B205
rw 		B204
rw 		B203
rw 		B202
rw 		B201
rw 		B200
rw 		B199
rw 		B198
rw 		B197
rw 		B196
rw 		B195
rw 		B194
rw 		B193
rw 		B192
rw
Toggle fields

B192

Bit 0: B192.

B193

Bit 1: B193.

B194

Bit 2: B194.

B195

Bit 3: B195.

B196

Bit 4: B196.

B197

Bit 5: B197.

B198

Bit 6: B198.

B199

Bit 7: B199.

B200

Bit 8: B200.

B201

Bit 9: B201.

B202

Bit 10: B202.

B203

Bit 11: B203.

B204

Bit 12: B204.

B205

Bit 13: B205.

B206

Bit 14: B206.

B207

Bit 15: B207.

B208

Bit 16: B208.

B209

Bit 17: B209.

B210

Bit 18: B210.

B211

Bit 19: B211.

B212

Bit 20: B212.

B213

Bit 21: B213.

B214

Bit 22: B214.

B215

Bit 23: B215.

B216

Bit 24: B216.

B217

Bit 25: B217.

B218

Bit 26: B218.

B219

Bit 27: B219.

B220

Bit 28: B220.

B221

Bit 29: B221.

B222

Bit 30: B222.

B223

Bit 31: B223.

VCTR7

MPCBBx vector register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B255
rw 		B254
rw 		B253
rw 		B252
rw 		B251
rw 		B250
rw 		B249
rw 		B248
rw 		B247
rw 		B246
rw 		B245
rw 		B244
rw 		B243
rw 		B242
rw 		B241
rw 		B240
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B239
rw 		B238
rw 		B237
rw 		B236
rw 		B235
rw 		B234
rw 		B233
rw 		B232
rw 		B231
rw 		B230
rw 		B229
rw 		B228
rw 		B227
rw 		B226
rw 		B225
rw 		B224
rw
Toggle fields

B224

Bit 0: B224.

B225

Bit 1: B225.

B226

Bit 2: B226.

B227

Bit 3: B227.

B228

Bit 4: B228.

B229

Bit 5: B229.

B230

Bit 6: B230.

B231

Bit 7: B231.

B232

Bit 8: B232.

B233

Bit 9: B233.

B234

Bit 10: B234.

B235

Bit 11: B235.

B236

Bit 12: B236.

B237

Bit 13: B237.

B238

Bit 14: B238.

B239

Bit 15: B239.

B240

Bit 16: B240.

B241

Bit 17: B241.

B242

Bit 18: B242.

B243

Bit 19: B243.

B244

Bit 20: B244.

B245

Bit 21: B245.

B246

Bit 22: B246.

B247

Bit 23: B247.

B248

Bit 24: B248.

B249

Bit 25: B249.

B250

Bit 26: B250.

B251

Bit 27: B251.

B252

Bit 28: B252.

B253

Bit 29: B253.

B254

Bit 30: B254.

B255

Bit 31: B255.

VCTR8

MPCBBx vector register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B287
rw 		B286
rw 		B285
rw 		B284
rw 		B283
rw 		B282
rw 		B281
rw 		B280
rw 		B279
rw 		B278
rw 		B277
rw 		B276
rw 		B275
rw 		B274
rw 		B273
rw 		B272
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B271
rw 		B270
rw 		B269
rw 		B268
rw 		B267
rw 		B266
rw 		B265
rw 		B264
rw 		B263
rw 		B262
rw 		B261
rw 		B260
rw 		B259
rw 		B258
rw 		B257
rw 		B256
rw
Toggle fields

B256

Bit 0: B256.

B257

Bit 1: B257.

B258

Bit 2: B258.

B259

Bit 3: B259.

B260

Bit 4: B260.

B261

Bit 5: B261.

B262

Bit 6: B262.

B263

Bit 7: B263.

B264

Bit 8: B264.

B265

Bit 9: B265.

B266

Bit 10: B266.

B267

Bit 11: B267.

B268

Bit 12: B268.

B269

Bit 13: B269.

B270

Bit 14: B270.

B271

Bit 15: B271.

B272

Bit 16: B272.

B273

Bit 17: B273.

B274

Bit 18: B274.

B275

Bit 19: B275.

B276

Bit 20: B276.

B277

Bit 21: B277.

B278

Bit 22: B278.

B279

Bit 23: B279.

B280

Bit 24: B280.

B281

Bit 25: B281.

B282

Bit 26: B282.

B283

Bit 27: B283.

B284

Bit 28: B284.

B285

Bit 29: B285.

B286

Bit 30: B286.

B287

Bit 31: B287.

VCTR9

MPCBBx vector register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B319
rw 		B318
rw 		B317
rw 		B316
rw 		B315
rw 		B314
rw 		B313
rw 		B312
rw 		B311
rw 		B310
rw 		B309
rw 		B308
rw 		B307
rw 		B306
rw 		B305
rw 		B304
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B303
rw 		B302
rw 		B301
rw 		B300
rw 		B299
rw 		B298
rw 		B297
rw 		B296
rw 		B295
rw 		B294
rw 		B293
rw 		B292
rw 		B291
rw 		B290
rw 		B289
rw 		B288
rw
Toggle fields

B288

Bit 0: B288.

B289

Bit 1: B289.

B290

Bit 2: B290.

B291

Bit 3: B291.

B292

Bit 4: B292.

B293

Bit 5: B293.

B294

Bit 6: B294.

B295

Bit 7: B295.

B296

Bit 8: B296.

B297

Bit 9: B297.

B298

Bit 10: B298.

B299

Bit 11: B299.

B300

Bit 12: B300.

B301

Bit 13: B301.

B302

Bit 14: B302.

B303

Bit 15: B303.

B304

Bit 16: B304.

B305

Bit 17: B305.

B306

Bit 18: B306.

B307

Bit 19: B307.

B308

Bit 20: B308.

B309

Bit 21: B309.

B310

Bit 22: B310.

B311

Bit 23: B311.

B312

Bit 24: B312.

B313

Bit 25: B313.

B314

Bit 26: B314.

B315

Bit 27: B315.

B316

Bit 28: B316.

B317

Bit 29: B317.

B318

Bit 30: B318.

B319

Bit 31: B319.

VCTR10

MPCBBx vector register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B351
rw 		B350
rw 		B349
rw 		B348
rw 		B347
rw 		B346
rw 		B345
rw 		B344
rw 		B343
rw 		B342
rw 		B341
rw 		B340
rw 		B339
rw 		B338
rw 		B337
rw 		B336
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B335
rw 		B334
rw 		B333
rw 		B332
rw 		B331
rw 		B330
rw 		B329
rw 		B328
rw 		B327
rw 		B326
rw 		B325
rw 		B324
rw 		B323
rw 		B322
rw 		B321
rw 		B320
rw
Toggle fields

B320

Bit 0: B320.

B321

Bit 1: B321.

B322

Bit 2: B322.

B323

Bit 3: B323.

B324

Bit 4: B324.

B325

Bit 5: B325.

B326

Bit 6: B326.

B327

Bit 7: B327.

B328

Bit 8: B328.

B329

Bit 9: B329.

B330

Bit 10: B330.

B331

Bit 11: B331.

B332

Bit 12: B332.

B333

Bit 13: B333.

B334

Bit 14: B334.

B335

Bit 15: B335.

B336

Bit 16: B336.

B337

Bit 17: B337.

B338

Bit 18: B338.

B339

Bit 19: B339.

B340

Bit 20: B340.

B341

Bit 21: B341.

B342

Bit 22: B342.

B343

Bit 23: B343.

B344

Bit 24: B344.

B345

Bit 25: B345.

B346

Bit 26: B346.

B347

Bit 27: B347.

B348

Bit 28: B348.

B349

Bit 29: B349.

B350

Bit 30: B350.

B351

Bit 31: B351.

VCTR11

MPCBBx vector register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B383
rw 		B382
rw 		B381
rw 		B380
rw 		B379
rw 		B378
rw 		B377
rw 		B376
rw 		B375
rw 		B374
rw 		B373
rw 		B372
rw 		B371
rw 		B370
rw 		B369
rw 		B368
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B367
rw 		B366
rw 		B365
rw 		B364
rw 		B363
rw 		B362
rw 		B361
rw 		B360
rw 		B359
rw 		B358
rw 		B357
rw 		B356
rw 		B355
rw 		B354
rw 		B353
rw 		B352
rw
Toggle fields

B352

Bit 0: B352.

B353

Bit 1: B353.

B354

Bit 2: B354.

B355

Bit 3: B355.

B356

Bit 4: B356.

B357

Bit 5: B357.

B358

Bit 6: B358.

B359

Bit 7: B359.

B360

Bit 8: B360.

B361

Bit 9: B361.

B362

Bit 10: B362.

B363

Bit 11: B363.

B364

Bit 12: B364.

B365

Bit 13: B365.

B366

Bit 14: B366.

B367

Bit 15: B367.

B368

Bit 16: B368.

B369

Bit 17: B369.

B370

Bit 18: B370.

B371

Bit 19: B371.

B372

Bit 20: B372.

B373

Bit 21: B373.

B374

Bit 22: B374.

B375

Bit 23: B375.

B376

Bit 24: B376.

B377

Bit 25: B377.

B378

Bit 26: B378.

B379

Bit 27: B379.

B380

Bit 28: B380.

B381

Bit 29: B381.

B382

Bit 30: B382.

B383

Bit 31: B383.

VCTR12

MPCBBx vector register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B415
rw 		B414
rw 		B413
rw 		B412
rw 		B411
rw 		B410
rw 		B409
rw 		B408
rw 		B407
rw 		B406
rw 		B405
rw 		B404
rw 		B403
rw 		B402
rw 		B401
rw 		B400
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B399
rw 		B398
rw 		B397
rw 		B396
rw 		B395
rw 		B394
rw 		B393
rw 		B392
rw 		B391
rw 		B390
rw 		B389
rw 		B388
rw 		B387
rw 		B386
rw 		B385
rw 		B384
rw
Toggle fields

B384

Bit 0: B384.

B385

Bit 1: B385.

B386

Bit 2: B386.

B387

Bit 3: B387.

B388

Bit 4: B388.

B389

Bit 5: B389.

B390

Bit 6: B390.

B391

Bit 7: B391.

B392

Bit 8: B392.

B393

Bit 9: B393.

B394

Bit 10: B394.

B395

Bit 11: B395.

B396

Bit 12: B396.

B397

Bit 13: B397.

B398

Bit 14: B398.

B399

Bit 15: B399.

B400

Bit 16: B400.

B401

Bit 17: B401.

B402

Bit 18: B402.

B403

Bit 19: B403.

B404

Bit 20: B404.

B405

Bit 21: B405.

B406

Bit 22: B406.

B407

Bit 23: B407.

B408

Bit 24: B408.

B409

Bit 25: B409.

B410

Bit 26: B410.

B411

Bit 27: B411.

B412

Bit 28: B412.

B413

Bit 29: B413.

B414

Bit 30: B414.

B415

Bit 31: B415.

VCTR13

MPCBBx vector register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B447
rw 		B446
rw 		B445
rw 		B444
rw 		B443
rw 		B442
rw 		B441
rw 		B440
rw 		B439
rw 		B438
rw 		B437
rw 		B436
rw 		B435
rw 		B434
rw 		B433
rw 		B432
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B431
rw 		B430
rw 		B429
rw 		B428
rw 		B427
rw 		B426
rw 		B425
rw 		B424
rw 		B423
rw 		B422
rw 		B421
rw 		B420
rw 		B419
rw 		B418
rw 		B417
rw 		B416
rw
Toggle fields

B416

Bit 0: B416.

B417

Bit 1: B417.

B418

Bit 2: B418.

B419

Bit 3: B419.

B420

Bit 4: B420.

B421

Bit 5: B421.

B422

Bit 6: B422.

B423

Bit 7: B423.

B424

Bit 8: B424.

B425

Bit 9: B425.

B426

Bit 10: B426.

B427

Bit 11: B427.

B428

Bit 12: B428.

B429

Bit 13: B429.

B430

Bit 14: B430.

B431

Bit 15: B431.

B432

Bit 16: B432.

B433

Bit 17: B433.

B434

Bit 18: B434.

B435

Bit 19: B435.

B436

Bit 20: B436.

B437

Bit 21: B437.

B438

Bit 22: B438.

B439

Bit 23: B439.

B440

Bit 24: B440.

B441

Bit 25: B441.

B442

Bit 26: B442.

B443

Bit 27: B443.

B444

Bit 28: B444.

B445

Bit 29: B445.

B446

Bit 30: B446.

B447

Bit 31: B447.

VCTR14

MPCBBx vector register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B479
rw 		B478
rw 		B477
rw 		B476
rw 		B475
rw 		B474
rw 		B473
rw 		B472
rw 		B471
rw 		B470
rw 		B469
rw 		B468
rw 		B467
rw 		B466
rw 		B465
rw 		B464
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B463
rw 		B462
rw 		B461
rw 		B460
rw 		B459
rw 		B458
rw 		B457
rw 		B456
rw 		B455
rw 		B454
rw 		B453
rw 		B452
rw 		B451
rw 		B450
rw 		B449
rw 		B448
rw
Toggle fields

B448

Bit 0: B448.

B449

Bit 1: B449.

B450

Bit 2: B450.

B451

Bit 3: B451.

B452

Bit 4: B452.

B453

Bit 5: B453.

B454

Bit 6: B454.

B455

Bit 7: B455.

B456

Bit 8: B456.

B457

Bit 9: B457.

B458

Bit 10: B458.

B459

Bit 11: B459.

B460

Bit 12: B460.

B461

Bit 13: B461.

B462

Bit 14: B462.

B463

Bit 15: B463.

B464

Bit 16: B464.

B465

Bit 17: B465.

B466

Bit 18: B466.

B467

Bit 19: B467.

B468

Bit 20: B468.

B469

Bit 21: B469.

B470

Bit 22: B470.

B471

Bit 23: B471.

B472

Bit 24: B472.

B473

Bit 25: B473.

B474

Bit 26: B474.

B475

Bit 27: B475.

B476

Bit 28: B476.

B477

Bit 29: B477.

B478

Bit 30: B478.

B479

Bit 31: B479.

VCTR15

MPCBBx vector register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B511
rw 		B510
rw 		B509
rw 		B508
rw 		B507
rw 		B506
rw 		B505
rw 		B504
rw 		B503
rw 		B502
rw 		B501
rw 		B500
rw 		B499
rw 		B498
rw 		B497
rw 		B496
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B495
rw 		B494
rw 		B493
rw 		B492
rw 		B491
rw 		B490
rw 		B489
rw 		B488
rw 		B487
rw 		B486
rw 		B485
rw 		B484
rw 		B483
rw 		B482
rw 		B481
rw 		B480
rw
Toggle fields

B480

Bit 0: B480.

B481

Bit 1: B481.

B482

Bit 2: B482.

B483

Bit 3: B483.

B484

Bit 4: B484.

B485

Bit 5: B485.

B486

Bit 6: B486.

B487

Bit 7: B487.

B488

Bit 8: B488.

B489

Bit 9: B489.

B490

Bit 10: B490.

B491

Bit 11: B491.

B492

Bit 12: B492.

B493

Bit 13: B493.

B494

Bit 14: B494.

B495

Bit 15: B495.

B496

Bit 16: B496.

B497

Bit 17: B497.

B498

Bit 18: B498.

B499

Bit 19: B499.

B500

Bit 20: B500.

B501

Bit 21: B501.

B502

Bit 22: B502.

B503

Bit 23: B503.

B504

Bit 24: B504.

B505

Bit 25: B505.

B506

Bit 26: B506.

B507

Bit 27: B507.

B508

Bit 28: B508.

B509

Bit 29: B509.

B510

Bit 30: B510.

B511

Bit 31: B511.

VCTR16

MPCBBx vector register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B543
rw 		B542
rw 		B541
rw 		B540
rw 		B539
rw 		B538
rw 		B537
rw 		B536
rw 		B535
rw 		B534
rw 		B533
rw 		B532
rw 		B531
rw 		B530
rw 		B529
rw 		B528
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B527
rw 		B526
rw 		B525
rw 		B524
rw 		B523
rw 		B522
rw 		B521
rw 		B520
rw 		B519
rw 		B518
rw 		B517
rw 		B516
rw 		B515
rw 		B514
rw 		B513
rw 		B512
rw
Toggle fields

B512

Bit 0: B512.

B513

Bit 1: B513.

B514

Bit 2: B514.

B515

Bit 3: B515.

B516

Bit 4: B516.

B517

Bit 5: B517.

B518

Bit 6: B518.

B519

Bit 7: B519.

B520

Bit 8: B520.

B521

Bit 9: B521.

B522

Bit 10: B522.

B523

Bit 11: B523.

B524

Bit 12: B524.

B525

Bit 13: B525.

B526

Bit 14: B526.

B527

Bit 15: B527.

B528

Bit 16: B528.

B529

Bit 17: B529.

B530

Bit 18: B530.

B531

Bit 19: B531.

B532

Bit 20: B532.

B533

Bit 21: B533.

B534

Bit 22: B534.

B535

Bit 23: B535.

B536

Bit 24: B536.

B537

Bit 25: B537.

B538

Bit 26: B538.

B539

Bit 27: B539.

B540

Bit 28: B540.

B541

Bit 29: B541.

B542

Bit 30: B542.

B543

Bit 31: B543.

VCTR17

MPCBBx vector register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B575
rw 		B574
rw 		B573
rw 		B572
rw 		B571
rw 		B570
rw 		B569
rw 		B568
rw 		B567
rw 		B566
rw 		B565
rw 		B564
rw 		B563
rw 		B562
rw 		B561
rw 		B560
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B559
rw 		B558
rw 		B557
rw 		B556
rw 		B555
rw 		B554
rw 		B553
rw 		B552
rw 		B551
rw 		B550
rw 		B549
rw 		B548
rw 		B547
rw 		B546
rw 		B545
rw 		B544
rw
Toggle fields

B544

Bit 0: B544.

B545

Bit 1: B545.

B546

Bit 2: B546.

B547

Bit 3: B547.

B548

Bit 4: B548.

B549

Bit 5: B549.

B550

Bit 6: B550.

B551

Bit 7: B551.

B552

Bit 8: B552.

B553

Bit 9: B553.

B554

Bit 10: B554.

B555

Bit 11: B555.

B556

Bit 12: B556.

B557

Bit 13: B557.

B558

Bit 14: B558.

B559

Bit 15: B559.

B560

Bit 16: B560.

B561

Bit 17: B561.

B562

Bit 18: B562.

B563

Bit 19: B563.

B564

Bit 20: B564.

B565

Bit 21: B565.

B566

Bit 22: B566.

B567

Bit 23: B567.

B568

Bit 24: B568.

B569

Bit 25: B569.

B570

Bit 26: B570.

B571

Bit 27: B571.

B572

Bit 28: B572.

B573

Bit 29: B573.

B574

Bit 30: B574.

B575

Bit 31: B575.

VCTR18

MPCBBx vector register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B607
rw 		B606
rw 		B605
rw 		B604
rw 		B603
rw 		B602
rw 		B601
rw 		B600
rw 		B599
rw 		B598
rw 		B597
rw 		B596
rw 		B595
rw 		B594
rw 		B593
rw 		B592
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B591
rw 		B590
rw 		B589
rw 		B588
rw 		B587
rw 		B586
rw 		B585
rw 		B584
rw 		B583
rw 		B582
rw 		B581
rw 		B580
rw 		B579
rw 		B578
rw 		B577
rw 		B576
rw
Toggle fields

B576

Bit 0: B576.

B577

Bit 1: B577.

B578

Bit 2: B578.

B579

Bit 3: B579.

B580

Bit 4: B580.

B581

Bit 5: B581.

B582

Bit 6: B582.

B583

Bit 7: B583.

B584

Bit 8: B584.

B585

Bit 9: B585.

B586

Bit 10: B586.

B587

Bit 11: B587.

B588

Bit 12: B588.

B589

Bit 13: B589.

B590

Bit 14: B590.

B591

Bit 15: B591.

B592

Bit 16: B592.

B593

Bit 17: B593.

B594

Bit 18: B594.

B595

Bit 19: B595.

B596

Bit 20: B596.

B597

Bit 21: B597.

B598

Bit 22: B598.

B599

Bit 23: B599.

B600

Bit 24: B600.

B601

Bit 25: B601.

B602

Bit 26: B602.

B603

Bit 27: B603.

B604

Bit 28: B604.

B605

Bit 29: B605.

B606

Bit 30: B606.

B607

Bit 31: B607.

VCTR19

MPCBBx vector register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B639
rw 		B638
rw 		B637
rw 		B636
rw 		B635
rw 		B634
rw 		B633
rw 		B632
rw 		B631
rw 		B630
rw 		B629
rw 		B628
rw 		B627
rw 		B626
rw 		B625
rw 		B624
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B623
rw 		B622
rw 		B621
rw 		B620
rw 		B619
rw 		B618
rw 		B617
rw 		B616
rw 		B615
rw 		B614
rw 		B613
rw 		B612
rw 		B611
rw 		B610
rw 		B609
rw 		B608
rw
Toggle fields

B608

Bit 0: B608.

B609

Bit 1: B609.

B610

Bit 2: B610.

B611

Bit 3: B611.

B612

Bit 4: B612.

B613

Bit 5: B613.

B614

Bit 6: B614.

B615

Bit 7: B615.

B616

Bit 8: B616.

B617

Bit 9: B617.

B618

Bit 10: B618.

B619

Bit 11: B619.

B620

Bit 12: B620.

B621

Bit 13: B621.

B622

Bit 14: B622.

B623

Bit 15: B623.

B624

Bit 16: B624.

B625

Bit 17: B625.

B626

Bit 18: B626.

B627

Bit 19: B627.

B628

Bit 20: B628.

B629

Bit 21: B629.

B630

Bit 22: B630.

B631

Bit 23: B631.

B632

Bit 24: B632.

B633

Bit 25: B633.

B634

Bit 26: B634.

B635

Bit 27: B635.

B636

Bit 28: B636.

B637

Bit 29: B637.

B638

Bit 30: B638.

B639

Bit 31: B639.

VCTR20

MPCBBx vector register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B671
rw 		B670
rw 		B669
rw 		B668
rw 		B667
rw 		B666
rw 		B665
rw 		B664
rw 		B663
rw 		B662
rw 		B661
rw 		B660
rw 		B659
rw 		B658
rw 		B657
rw 		B656
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B655
rw 		B654
rw 		B653
rw 		B652
rw 		B651
rw 		B650
rw 		B649
rw 		B648
rw 		B647
rw 		B646
rw 		B645
rw 		B644
rw 		B643
rw 		B642
rw 		B641
rw 		B640
rw
Toggle fields

B640

Bit 0: B640.

B641

Bit 1: B641.

B642

Bit 2: B642.

B643

Bit 3: B643.

B644

Bit 4: B644.

B645

Bit 5: B645.

B646

Bit 6: B646.

B647

Bit 7: B647.

B648

Bit 8: B648.

B649

Bit 9: B649.

B650

Bit 10: B650.

B651

Bit 11: B651.

B652

Bit 12: B652.

B653

Bit 13: B653.

B654

Bit 14: B654.

B655

Bit 15: B655.

B656

Bit 16: B656.

B657

Bit 17: B657.

B658

Bit 18: B658.

B659

Bit 19: B659.

B660

Bit 20: B660.

B661

Bit 21: B661.

B662

Bit 22: B662.

B663

Bit 23: B663.

B664

Bit 24: B664.

B665

Bit 25: B665.

B666

Bit 26: B666.

B667

Bit 27: B667.

B668

Bit 28: B668.

B669

Bit 29: B669.

B670

Bit 30: B670.

B671

Bit 31: B671.

VCTR21

MPCBBx vector register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B703
rw 		B702
rw 		B701
rw 		B700
rw 		B699
rw 		B698
rw 		B697
rw 		B696
rw 		B695
rw 		B694
rw 		B693
rw 		B692
rw 		B691
rw 		B690
rw 		B689
rw 		B688
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B687
rw 		B686
rw 		B685
rw 		B684
rw 		B683
rw 		B682
rw 		B681
rw 		B680
rw 		B679
rw 		B678
rw 		B677
rw 		B676
rw 		B675
rw 		B674
rw 		B673
rw 		B672
rw
Toggle fields

B672

Bit 0: B672.

B673

Bit 1: B673.

B674

Bit 2: B674.

B675

Bit 3: B675.

B676

Bit 4: B676.

B677

Bit 5: B677.

B678

Bit 6: B678.

B679

Bit 7: B679.

B680

Bit 8: B680.

B681

Bit 9: B681.

B682

Bit 10: B682.

B683

Bit 11: B683.

B684

Bit 12: B684.

B685

Bit 13: B685.

B686

Bit 14: B686.

B687

Bit 15: B687.

B688

Bit 16: B688.

B689

Bit 17: B689.

B690

Bit 18: B690.

B691

Bit 19: B691.

B692

Bit 20: B692.

B693

Bit 21: B693.

B694

Bit 22: B694.

B695

Bit 23: B695.

B696

Bit 24: B696.

B697

Bit 25: B697.

B698

Bit 26: B698.

B699

Bit 27: B699.

B700

Bit 28: B700.

B701

Bit 29: B701.

B702

Bit 30: B702.

B703

Bit 31: B703.

VCTR22

MPCBBx vector register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B735
rw 		B734
rw 		B733
rw 		B732
rw 		B731
rw 		B730
rw 		B729
rw 		B728
rw 		B727
rw 		B726
rw 		B725
rw 		B724
rw 		B723
rw 		B722
rw 		B721
rw 		B720
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B719
rw 		B718
rw 		B717
rw 		B716
rw 		B715
rw 		B714
rw 		B713
rw 		B712
rw 		B711
rw 		B710
rw 		B709
rw 		B708
rw 		B707
rw 		B706
rw 		B705
rw 		B704
rw
Toggle fields

B704

Bit 0: B704.

B705

Bit 1: B705.

B706

Bit 2: B706.

B707

Bit 3: B707.

B708

Bit 4: B708.

B709

Bit 5: B709.

B710

Bit 6: B710.

B711

Bit 7: B711.

B712

Bit 8: B712.

B713

Bit 9: B713.

B714

Bit 10: B714.

B715

Bit 11: B715.

B716

Bit 12: B716.

B717

Bit 13: B717.

B718

Bit 14: B718.

B719

Bit 15: B719.

B720

Bit 16: B720.

B721

Bit 17: B721.

B722

Bit 18: B722.

B723

Bit 19: B723.

B724

Bit 20: B724.

B725

Bit 21: B725.

B726

Bit 22: B726.

B727

Bit 23: B727.

B728

Bit 24: B728.

B729

Bit 25: B729.

B730

Bit 26: B730.

B731

Bit 27: B731.

B732

Bit 28: B732.

B733

Bit 29: B733.

B734

Bit 30: B734.

B735

Bit 31: B735.

VCTR23

MPCBBx vector register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B767
rw 		B766
rw 		B765
rw 		B764
rw 		B763
rw 		B762
rw 		B761
rw 		B760
rw 		B759
rw 		B758
rw 		B757
rw 		B756
rw 		B755
rw 		B754
rw 		B753
rw 		B752
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B751
rw 		B750
rw 		B749
rw 		B748
rw 		B747
rw 		B746
rw 		B745
rw 		B744
rw 		B743
rw 		B742
rw 		B741
rw 		B740
rw 		B739
rw 		B738
rw 		B737
rw 		B736
rw
Toggle fields

B736

Bit 0: B736.

B737

Bit 1: B737.

B738

Bit 2: B738.

B739

Bit 3: B739.

B740

Bit 4: B740.

B741

Bit 5: B741.

B742

Bit 6: B742.

B743

Bit 7: B743.

B744

Bit 8: B744.

B745

Bit 9: B745.

B746

Bit 10: B746.

B747

Bit 11: B747.

B748

Bit 12: B748.

B749

Bit 13: B749.

B750

Bit 14: B750.

B751

Bit 15: B751.

B752

Bit 16: B752.

B753

Bit 17: B753.

B754

Bit 18: B754.

B755

Bit 19: B755.

B756

Bit 20: B756.

B757

Bit 21: B757.

B758

Bit 22: B758.

B759

Bit 23: B759.

B760

Bit 24: B760.

B761

Bit 25: B761.

B762

Bit 26: B762.

B763

Bit 27: B763.

B764

Bit 28: B764.

B765

Bit 29: B765.

B766

Bit 30: B766.

B767

Bit 31: B767.

VCTR24

MPCBBx vector register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B799
rw 		B798
rw 		B797
rw 		B796
rw 		B795
rw 		B794
rw 		B793
rw 		B792
rw 		B791
rw 		B790
rw 		B789
rw 		B788
rw 		B787
rw 		B786
rw 		B785
rw 		B784
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B783
rw 		B782
rw 		B781
rw 		B780
rw 		B779
rw 		B778
rw 		B777
rw 		B776
rw 		B775
rw 		B774
rw 		B773
rw 		B772
rw 		B771
rw 		B770
rw 		B769
rw 		B768
rw
Toggle fields

B768

Bit 0: B768.

B769

Bit 1: B769.

B770

Bit 2: B770.

B771

Bit 3: B771.

B772

Bit 4: B772.

B773

Bit 5: B773.

B774

Bit 6: B774.

B775

Bit 7: B775.

B776

Bit 8: B776.

B777

Bit 9: B777.

B778

Bit 10: B778.

B779

Bit 11: B779.

B780

Bit 12: B780.

B781

Bit 13: B781.

B782

Bit 14: B782.

B783

Bit 15: B783.

B784

Bit 16: B784.

B785

Bit 17: B785.

B786

Bit 18: B786.

B787

Bit 19: B787.

B788

Bit 20: B788.

B789

Bit 21: B789.

B790

Bit 22: B790.

B791

Bit 23: B791.

B792

Bit 24: B792.

B793

Bit 25: B793.

B794

Bit 26: B794.

B795

Bit 27: B795.

B796

Bit 28: B796.

B797

Bit 29: B797.

B798

Bit 30: B798.

B799

Bit 31: B799.

VCTR25

MPCBBx vector register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B831
rw 		B830
rw 		B829
rw 		B828
rw 		B827
rw 		B826
rw 		B825
rw 		B824
rw 		B823
rw 		B822
rw 		B821
rw 		B820
rw 		B819
rw 		B818
rw 		B817
rw 		B816
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B815
rw 		B814
rw 		B813
rw 		B812
rw 		B811
rw 		B810
rw 		B809
rw 		B808
rw 		B807
rw 		B806
rw 		B805
rw 		B804
rw 		B803
rw 		B802
rw 		B801
rw 		B800
rw
Toggle fields

B800

Bit 0: B800.

B801

Bit 1: B801.

B802

Bit 2: B802.

B803

Bit 3: B803.

B804

Bit 4: B804.

B805

Bit 5: B805.

B806

Bit 6: B806.

B807

Bit 7: B807.

B808

Bit 8: B808.

B809

Bit 9: B809.

B810

Bit 10: B810.

B811

Bit 11: B811.

B812

Bit 12: B812.

B813

Bit 13: B813.

B814

Bit 14: B814.

B815

Bit 15: B815.

B816

Bit 16: B816.

B817

Bit 17: B817.

B818

Bit 18: B818.

B819

Bit 19: B819.

B820

Bit 20: B820.

B821

Bit 21: B821.

B822

Bit 22: B822.

B823

Bit 23: B823.

B824

Bit 24: B824.

B825

Bit 25: B825.

B826

Bit 26: B826.

B827

Bit 27: B827.

B828

Bit 28: B828.

B829

Bit 29: B829.

B830

Bit 30: B830.

B831

Bit 31: B831.

VCTR26

MPCBBx vector register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B863
rw 		B862
rw 		B861
rw 		B860
rw 		B859
rw 		B858
rw 		B857
rw 		B856
rw 		B855
rw 		B854
rw 		B853
rw 		B852
rw 		B851
rw 		B850
rw 		B849
rw 		B848
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B847
rw 		B846
rw 		B845
rw 		B844
rw 		B843
rw 		B842
rw 		B841
rw 		B840
rw 		B839
rw 		B838
rw 		B837
rw 		B836
rw 		B835
rw 		B834
rw 		B833
rw 		B832
rw
Toggle fields

B832

Bit 0: B832.

B833

Bit 1: B833.

B834

Bit 2: B834.

B835

Bit 3: B835.

B836

Bit 4: B836.

B837

Bit 5: B837.

B838

Bit 6: B838.

B839

Bit 7: B839.

B840

Bit 8: B840.

B841

Bit 9: B841.

B842

Bit 10: B842.

B843

Bit 11: B843.

B844

Bit 12: B844.

B845

Bit 13: B845.

B846

Bit 14: B846.

B847

Bit 15: B847.

B848

Bit 16: B848.

B849

Bit 17: B849.

B850

Bit 18: B850.

B851

Bit 19: B851.

B852

Bit 20: B852.

B853

Bit 21: B853.

B854

Bit 22: B854.

B855

Bit 23: B855.

B856

Bit 24: B856.

B857

Bit 25: B857.

B858

Bit 26: B858.

B859

Bit 27: B859.

B860

Bit 28: B860.

B861

Bit 29: B861.

B862

Bit 30: B862.

B863

Bit 31: B863.

VCTR27

MPCBBx vector register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B895
rw 		B894
rw 		B893
rw 		B892
rw 		B891
rw 		B890
rw 		B889
rw 		B888
rw 		B887
rw 		B886
rw 		B885
rw 		B884
rw 		B883
rw 		B882
rw 		B881
rw 		B880
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B879
rw 		B878
rw 		B877
rw 		B876
rw 		B875
rw 		B874
rw 		B873
rw 		B872
rw 		B871
rw 		B870
rw 		B869
rw 		B868
rw 		B867
rw 		B866
rw 		B865
rw 		B864
rw
Toggle fields

B864

Bit 0: B864.

B865

Bit 1: B865.

B866

Bit 2: B866.

B867

Bit 3: B867.

B868

Bit 4: B868.

B869

Bit 5: B869.

B870

Bit 6: B870.

B871

Bit 7: B871.

B872

Bit 8: B872.

B873

Bit 9: B873.

B874

Bit 10: B874.

B875

Bit 11: B875.

B876

Bit 12: B876.

B877

Bit 13: B877.

B878

Bit 14: B878.

B879

Bit 15: B879.

B880

Bit 16: B880.

B881

Bit 17: B881.

B882

Bit 18: B882.

B883

Bit 19: B883.

B884

Bit 20: B884.

B885

Bit 21: B885.

B886

Bit 22: B886.

B887

Bit 23: B887.

B888

Bit 24: B888.

B889

Bit 25: B889.

B890

Bit 26: B890.

B891

Bit 27: B891.

B892

Bit 28: B892.

B893

Bit 29: B893.

B894

Bit 30: B894.

B895

Bit 31: B895.

VCTR28

MPCBBx vector register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B927
rw 		B926
rw 		B925
rw 		B924
rw 		B923
rw 		B922
rw 		B921
rw 		B920
rw 		B919
rw 		B918
rw 		B917
rw 		B916
rw 		B915
rw 		B914
rw 		B913
rw 		B912
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B911
rw 		B910
rw 		B909
rw 		B908
rw 		B907
rw 		B906
rw 		B905
rw 		B904
rw 		B903
rw 		B902
rw 		B901
rw 		B900
rw 		B899
rw 		B898
rw 		B897
rw 		B896
rw
Toggle fields

B896

Bit 0: B896.

B897

Bit 1: B897.

B898

Bit 2: B898.

B899

Bit 3: B899.

B900

Bit 4: B900.

B901

Bit 5: B901.

B902

Bit 6: B902.

B903

Bit 7: B903.

B904

Bit 8: B904.

B905

Bit 9: B905.

B906

Bit 10: B906.

B907

Bit 11: B907.

B908

Bit 12: B908.

B909

Bit 13: B909.

B910

Bit 14: B910.

B911

Bit 15: B911.

B912

Bit 16: B912.

B913

Bit 17: B913.

B914

Bit 18: B914.

B915

Bit 19: B915.

B916

Bit 20: B916.

B917

Bit 21: B917.

B918

Bit 22: B918.

B919

Bit 23: B919.

B920

Bit 24: B920.

B921

Bit 25: B921.

B922

Bit 26: B922.

B923

Bit 27: B923.

B924

Bit 28: B924.

B925

Bit 29: B925.

B926

Bit 30: B926.

B927

Bit 31: B927.

VCTR29

MPCBBx vector register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B959
rw 		B958
rw 		B957
rw 		B956
rw 		B955
rw 		B954
rw 		B953
rw 		B952
rw 		B951
rw 		B950
rw 		B949
rw 		B948
rw 		B947
rw 		B946
rw 		B945
rw 		B944
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B943
rw 		B942
rw 		B941
rw 		B940
rw 		B939
rw 		B938
rw 		B937
rw 		B936
rw 		B935
rw 		B934
rw 		B933
rw 		B932
rw 		B931
rw 		B930
rw 		B929
rw 		B928
rw
Toggle fields

B928

Bit 0: B928.

B929

Bit 1: B929.

B930

Bit 2: B930.

B931

Bit 3: B931.

B932

Bit 4: B932.

B933

Bit 5: B933.

B934

Bit 6: B934.

B935

Bit 7: B935.

B936

Bit 8: B936.

B937

Bit 9: B937.

B938

Bit 10: B938.

B939

Bit 11: B939.

B940

Bit 12: B940.

B941

Bit 13: B941.

B942

Bit 14: B942.

B943

Bit 15: B943.

B944

Bit 16: B944.

B945

Bit 17: B945.

B946

Bit 18: B946.

B947

Bit 19: B947.

B948

Bit 20: B948.

B949

Bit 21: B949.

B950

Bit 22: B950.

B951

Bit 23: B951.

B952

Bit 24: B952.

B953

Bit 25: B953.

B954

Bit 26: B954.

B955

Bit 27: B955.

B956

Bit 28: B956.

B957

Bit 29: B957.

B958

Bit 30: B958.

B959

Bit 31: B959.

VCTR30

MPCBBx vector register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B991
rw 		B990
rw 		B989
rw 		B988
rw 		B987
rw 		B986
rw 		B985
rw 		B984
rw 		B983
rw 		B982
rw 		B981
rw 		B980
rw 		B979
rw 		B978
rw 		B977
rw 		B976
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B975
rw 		B974
rw 		B973
rw 		B972
rw 		B971
rw 		B970
rw 		B969
rw 		B968
rw 		B967
rw 		B966
rw 		B965
rw 		B964
rw 		B963
rw 		B962
rw 		B961
rw 		B960
rw
Toggle fields

B960

Bit 0: B960.

B961

Bit 1: B961.

B962

Bit 2: B962.

B963

Bit 3: B963.

B964

Bit 4: B964.

B965

Bit 5: B965.

B966

Bit 6: B966.

B967

Bit 7: B967.

B968

Bit 8: B968.

B969

Bit 9: B969.

B970

Bit 10: B970.

B971

Bit 11: B971.

B972

Bit 12: B972.

B973

Bit 13: B973.

B974

Bit 14: B974.

B975

Bit 15: B975.

B976

Bit 16: B976.

B977

Bit 17: B977.

B978

Bit 18: B978.

B979

Bit 19: B979.

B980

Bit 20: B980.

B981

Bit 21: B981.

B982

Bit 22: B982.

B983

Bit 23: B983.

B984

Bit 24: B984.

B985

Bit 25: B985.

B986

Bit 26: B986.

B987

Bit 27: B987.

B988

Bit 28: B988.

B989

Bit 29: B989.

B990

Bit 30: B990.

B991

Bit 31: B991.

VCTR31

MPCBBx vector register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1023
rw 		B1022
rw 		B1021
rw 		B1020
rw 		B1019
rw 		B1018
rw 		B1017
rw 		B1016
rw 		B1015
rw 		B1014
rw 		B1013
rw 		B1012
rw 		B1011
rw 		B1010
rw 		B1009
rw 		B1008
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1007
rw 		B1006
rw 		B1005
rw 		B1004
rw 		B1003
rw 		B1002
rw 		B1001
rw 		B1000
rw 		B999
rw 		B998
rw 		B997
rw 		B996
rw 		B995
rw 		B994
rw 		B993
rw 		B992
rw
Toggle fields

B992

Bit 0: B992.

B993

Bit 1: B993.

B994

Bit 2: B994.

B995

Bit 3: B995.

B996

Bit 4: B996.

B997

Bit 5: B997.

B998

Bit 6: B998.

B999

Bit 7: B999.

B1000

Bit 8: B1000.

B1001

Bit 9: B1001.

B1002

Bit 10: B1002.

B1003

Bit 11: B1003.

B1004

Bit 12: B1004.

B1005

Bit 13: B1005.

B1006

Bit 14: B1006.

B1007

Bit 15: B1007.

B1008

Bit 16: B1008.

B1009

Bit 17: B1009.

B1010

Bit 18: B1010.

B1011

Bit 19: B1011.

B1012

Bit 20: B1012.

B1013

Bit 21: B1013.

B1014

Bit 22: B1014.

B1015

Bit 23: B1015.

B1016

Bit 24: B1016.

B1017

Bit 25: B1017.

B1018

Bit 26: B1018.

B1019

Bit 27: B1019.

B1020

Bit 28: B1020.

B1021

Bit 29: B1021.

B1022

Bit 30: B1022.

B1023

Bit 31: B1023.

VCTR32

MPCBBx vector register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1055
rw 		B1054
rw 		B1053
rw 		B1052
rw 		B1051
rw 		B1050
rw 		B1049
rw 		B1048
rw 		B1047
rw 		B1046
rw 		B1045
rw 		B1044
rw 		B1043
rw 		B1042
rw 		B1041
rw 		B1040
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1039
rw 		B1038
rw 		B1037
rw 		B1036
rw 		B1035
rw 		B1034
rw 		B1033
rw 		B1032
rw 		B1031
rw 		B1030
rw 		B1029
rw 		B1028
rw 		B1027
rw 		B1026
rw 		B1025
rw 		B1024
rw
Toggle fields

B1024

Bit 0: B1024.

B1025

Bit 1: B1025.

B1026

Bit 2: B1026.

B1027

Bit 3: B1027.

B1028

Bit 4: B1028.

B1029

Bit 5: B1029.

B1030

Bit 6: B1030.

B1031

Bit 7: B1031.

B1032

Bit 8: B1032.

B1033

Bit 9: B1033.

B1034

Bit 10: B1034.

B1035

Bit 11: B1035.

B1036

Bit 12: B1036.

B1037

Bit 13: B1037.

B1038

Bit 14: B1038.

B1039

Bit 15: B1039.

B1040

Bit 16: B1040.

B1041

Bit 17: B1041.

B1042

Bit 18: B1042.

B1043

Bit 19: B1043.

B1044

Bit 20: B1044.

B1045

Bit 21: B1045.

B1046

Bit 22: B1046.

B1047

Bit 23: B1047.

B1048

Bit 24: B1048.

B1049

Bit 25: B1049.

B1050

Bit 26: B1050.

B1051

Bit 27: B1051.

B1052

Bit 28: B1052.

B1053

Bit 29: B1053.

B1054

Bit 30: B1054.

B1055

Bit 31: B1055.

VCTR33

MPCBBx vector register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1087
rw 		B1086
rw 		B1085
rw 		B1084
rw 		B1083
rw 		B1082
rw 		B1081
rw 		B1080
rw 		B1079
rw 		B1078
rw 		B1077
rw 		B1076
rw 		B1075
rw 		B1074
rw 		B1073
rw 		B1072
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1071
rw 		B1070
rw 		B1069
rw 		B1068
rw 		B1067
rw 		B1066
rw 		B1065
rw 		B1064
rw 		B1063
rw 		B1062
rw 		B1061
rw 		B1060
rw 		B1059
rw 		B1058
rw 		B1057
rw 		B1056
rw
Toggle fields

B1056

Bit 0: B1056.

B1057

Bit 1: B1057.

B1058

Bit 2: B1058.

B1059

Bit 3: B1059.

B1060

Bit 4: B1060.

B1061

Bit 5: B1061.

B1062

Bit 6: B1062.

B1063

Bit 7: B1063.

B1064

Bit 8: B1064.

B1065

Bit 9: B1065.

B1066

Bit 10: B1066.

B1067

Bit 11: B1067.

B1068

Bit 12: B1068.

B1069

Bit 13: B1069.

B1070

Bit 14: B1070.

B1071

Bit 15: B1071.

B1072

Bit 16: B1072.

B1073

Bit 17: B1073.

B1074

Bit 18: B1074.

B1075

Bit 19: B1075.

B1076

Bit 20: B1076.

B1077

Bit 21: B1077.

B1078

Bit 22: B1078.

B1079

Bit 23: B1079.

B1080

Bit 24: B1080.

B1081

Bit 25: B1081.

B1082

Bit 26: B1082.

B1083

Bit 27: B1083.

B1084

Bit 28: B1084.

B1085

Bit 29: B1085.

B1086

Bit 30: B1086.

B1087

Bit 31: B1087.

VCTR34

MPCBBx vector register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1119
rw 		B1118
rw 		B1117
rw 		B1116
rw 		B1115
rw 		B1114
rw 		B1113
rw 		B1112
rw 		B1111
rw 		B1110
rw 		B1109
rw 		B1108
rw 		B1107
rw 		B1106
rw 		B1105
rw 		B1104
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1103
rw 		B1102
rw 		B1101
rw 		B1100
rw 		B1099
rw 		B1098
rw 		B1097
rw 		B1096
rw 		B1095
rw 		B1094
rw 		B1093
rw 		B1092
rw 		B1091
rw 		B1090
rw 		B1089
rw 		B1088
rw
Toggle fields

B1088

Bit 0: B1088.

B1089

Bit 1: B1089.

B1090

Bit 2: B1090.

B1091

Bit 3: B1091.

B1092

Bit 4: B1092.

B1093

Bit 5: B1093.

B1094

Bit 6: B1094.

B1095

Bit 7: B1095.

B1096

Bit 8: B1096.

B1097

Bit 9: B1097.

B1098

Bit 10: B1098.

B1099

Bit 11: B1099.

B1100

Bit 12: B1100.

B1101

Bit 13: B1101.

B1102

Bit 14: B1102.

B1103

Bit 15: B1103.

B1104

Bit 16: B1104.

B1105

Bit 17: B1105.

B1106

Bit 18: B1106.

B1107

Bit 19: B1107.

B1108

Bit 20: B1108.

B1109

Bit 21: B1109.

B1110

Bit 22: B1110.

B1111

Bit 23: B1111.

B1112

Bit 24: B1112.

B1113

Bit 25: B1113.

B1114

Bit 26: B1114.

B1115

Bit 27: B1115.

B1116

Bit 28: B1116.

B1117

Bit 29: B1117.

B1118

Bit 30: B1118.

B1119

Bit 31: B1119.

VCTR35

MPCBBx vector register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1151
rw 		B1150
rw 		B1149
rw 		B1148
rw 		B1147
rw 		B1146
rw 		B1145
rw 		B1144
rw 		B1143
rw 		B1142
rw 		B1141
rw 		B1140
rw 		B1139
rw 		B1138
rw 		B1137
rw 		B1136
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1135
rw 		B1134
rw 		B1133
rw 		B1132
rw 		B1131
rw 		B1130
rw 		B1129
rw 		B1128
rw 		B1127
rw 		B1126
rw 		B1125
rw 		B1124
rw 		B1123
rw 		B1122
rw 		B1121
rw 		B1120
rw
Toggle fields

B1120

Bit 0: B1120.

B1121

Bit 1: B1121.

B1122

Bit 2: B1122.

B1123

Bit 3: B1123.

B1124

Bit 4: B1124.

B1125

Bit 5: B1125.

B1126

Bit 6: B1126.

B1127

Bit 7: B1127.

B1128

Bit 8: B1128.

B1129

Bit 9: B1129.

B1130

Bit 10: B1130.

B1131

Bit 11: B1131.

B1132

Bit 12: B1132.

B1133

Bit 13: B1133.

B1134

Bit 14: B1134.

B1135

Bit 15: B1135.

B1136

Bit 16: B1136.

B1137

Bit 17: B1137.

B1138

Bit 18: B1138.

B1139

Bit 19: B1139.

B1140

Bit 20: B1140.

B1141

Bit 21: B1141.

B1142

Bit 22: B1142.

B1143

Bit 23: B1143.

B1144

Bit 24: B1144.

B1145

Bit 25: B1145.

B1146

Bit 26: B1146.

B1147

Bit 27: B1147.

B1148

Bit 28: B1148.

B1149

Bit 29: B1149.

B1150

Bit 30: B1150.

B1151

Bit 31: B1151.

VCTR36

MPCBBx vector register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1183
rw 		B1182
rw 		B1181
rw 		B1180
rw 		B1179
rw 		B1178
rw 		B1177
rw 		B1176
rw 		B1175
rw 		B1174
rw 		B1173
rw 		B1172
rw 		B1171
rw 		B1170
rw 		B1169
rw 		B1168
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1167
rw 		B1166
rw 		B1165
rw 		B1164
rw 		B1163
rw 		B1162
rw 		B1161
rw 		B1160
rw 		B1159
rw 		B1158
rw 		B1157
rw 		B1156
rw 		B1155
rw 		B1154
rw 		B1153
rw 		B1152
rw
Toggle fields

B1152

Bit 0: B1152.

B1153

Bit 1: B1153.

B1154

Bit 2: B1154.

B1155

Bit 3: B1155.

B1156

Bit 4: B1156.

B1157

Bit 5: B1157.

B1158

Bit 6: B1158.

B1159

Bit 7: B1159.

B1160

Bit 8: B1160.

B1161

Bit 9: B1161.

B1162

Bit 10: B1162.

B1163

Bit 11: B1163.

B1164

Bit 12: B1164.

B1165

Bit 13: B1165.

B1166

Bit 14: B1166.

B1167

Bit 15: B1167.

B1168

Bit 16: B1168.

B1169

Bit 17: B1169.

B1170

Bit 18: B1170.

B1171

Bit 19: B1171.

B1172

Bit 20: B1172.

B1173

Bit 21: B1173.

B1174

Bit 22: B1174.

B1175

Bit 23: B1175.

B1176

Bit 24: B1176.

B1177

Bit 25: B1177.

B1178

Bit 26: B1178.

B1179

Bit 27: B1179.

B1180

Bit 28: B1180.

B1181

Bit 29: B1181.

B1182

Bit 30: B1182.

B1183

Bit 31: B1183.

VCTR37

MPCBBx vector register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1215
rw 		B1214
rw 		B1213
rw 		B1212
rw 		B1211
rw 		B1210
rw 		B1209
rw 		B1208
rw 		B1207
rw 		B1206
rw 		B1205
rw 		B1204
rw 		B1203
rw 		B1202
rw 		B1201
rw 		B1200
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1199
rw 		B1198
rw 		B1197
rw 		B1196
rw 		B1195
rw 		B1194
rw 		B1193
rw 		B1192
rw 		B1191
rw 		B1190
rw 		B1189
rw 		B1188
rw 		B1187
rw 		B1186
rw 		B1185
rw 		B1184
rw
Toggle fields

B1184

Bit 0: B1184.

B1185

Bit 1: B1185.

B1186

Bit 2: B1186.

B1187

Bit 3: B1187.

B1188

Bit 4: B1188.

B1189

Bit 5: B1189.

B1190

Bit 6: B1190.

B1191

Bit 7: B1191.

B1192

Bit 8: B1192.

B1193

Bit 9: B1193.

B1194

Bit 10: B1194.

B1195

Bit 11: B1195.

B1196

Bit 12: B1196.

B1197

Bit 13: B1197.

B1198

Bit 14: B1198.

B1199

Bit 15: B1199.

B1200

Bit 16: B1200.

B1201

Bit 17: B1201.

B1202

Bit 18: B1202.

B1203

Bit 19: B1203.

B1204

Bit 20: B1204.

B1205

Bit 21: B1205.

B1206

Bit 22: B1206.

B1207

Bit 23: B1207.

B1208

Bit 24: B1208.

B1209

Bit 25: B1209.

B1210

Bit 26: B1210.

B1211

Bit 27: B1211.

B1212

Bit 28: B1212.

B1213

Bit 29: B1213.

B1214

Bit 30: B1214.

B1215

Bit 31: B1215.

VCTR38

MPCBBx vector register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1247
rw 		B1246
rw 		B1245
rw 		B1244
rw 		B1243
rw 		B1242
rw 		B1241
rw 		B1240
rw 		B1239
rw 		B1238
rw 		B1237
rw 		B1236
rw 		B1235
rw 		B1234
rw 		B1233
rw 		B1232
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1231
rw 		B1230
rw 		B1229
rw 		B1228
rw 		B1227
rw 		B1226
rw 		B1225
rw 		B1224
rw 		B1223
rw 		B1222
rw 		B1221
rw 		B1220
rw 		B1219
rw 		B1218
rw 		B1217
rw 		B1216
rw
Toggle fields

B1216

Bit 0: B1216.

B1217

Bit 1: B1217.

B1218

Bit 2: B1218.

B1219

Bit 3: B1219.

B1220

Bit 4: B1220.

B1221

Bit 5: B1221.

B1222

Bit 6: B1222.

B1223

Bit 7: B1223.

B1224

Bit 8: B1224.

B1225

Bit 9: B1225.

B1226

Bit 10: B1226.

B1227

Bit 11: B1227.

B1228

Bit 12: B1228.

B1229

Bit 13: B1229.

B1230

Bit 14: B1230.

B1231

Bit 15: B1231.

B1232

Bit 16: B1232.

B1233

Bit 17: B1233.

B1234

Bit 18: B1234.

B1235

Bit 19: B1235.

B1236

Bit 20: B1236.

B1237

Bit 21: B1237.

B1238

Bit 22: B1238.

B1239

Bit 23: B1239.

B1240

Bit 24: B1240.

B1241

Bit 25: B1241.

B1242

Bit 26: B1242.

B1243

Bit 27: B1243.

B1244

Bit 28: B1244.

B1245

Bit 29: B1245.

B1246

Bit 30: B1246.

B1247

Bit 31: B1247.

VCTR39

MPCBBx vector register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1279
rw 		B1278
rw 		B1277
rw 		B1276
rw 		B1275
rw 		B1274
rw 		B1273
rw 		B1272
rw 		B1271
rw 		B1270
rw 		B1269
rw 		B1268
rw 		B1267
rw 		B1266
rw 		B1265
rw 		B1264
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1263
rw 		B1262
rw 		B1261
rw 		B1260
rw 		B1259
rw 		B1258
rw 		B1257
rw 		B1256
rw 		B1255
rw 		B1254
rw 		B1253
rw 		B1252
rw 		B1251
rw 		B1250
rw 		B1249
rw 		B1248
rw
Toggle fields

B1248

Bit 0: B1248.

B1249

Bit 1: B1249.

B1250

Bit 2: B1250.

B1251

Bit 3: B1251.

B1252

Bit 4: B1252.

B1253

Bit 5: B1253.

B1254

Bit 6: B1254.

B1255

Bit 7: B1255.

B1256

Bit 8: B1256.

B1257

Bit 9: B1257.

B1258

Bit 10: B1258.

B1259

Bit 11: B1259.

B1260

Bit 12: B1260.

B1261

Bit 13: B1261.

B1262

Bit 14: B1262.

B1263

Bit 15: B1263.

B1264

Bit 16: B1264.

B1265

Bit 17: B1265.

B1266

Bit 18: B1266.

B1267

Bit 19: B1267.

B1268

Bit 20: B1268.

B1269

Bit 21: B1269.

B1270

Bit 22: B1270.

B1271

Bit 23: B1271.

B1272

Bit 24: B1272.

B1273

Bit 25: B1273.

B1274

Bit 26: B1274.

B1275

Bit 27: B1275.

B1276

Bit 28: B1276.

B1277

Bit 29: B1277.

B1278

Bit 30: B1278.

B1279

Bit 31: B1279.

VCTR40

MPCBBx vector register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1311
rw 		B1310
rw 		B1309
rw 		B1308
rw 		B1307
rw 		B1306
rw 		B1305
rw 		B1304
rw 		B1303
rw 		B1302
rw 		B1301
rw 		B1300
rw 		B1299
rw 		B1298
rw 		B1297
rw 		B1296
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1295
rw 		B1294
rw 		B1293
rw 		B1292
rw 		B1291
rw 		B1290
rw 		B1289
rw 		B1288
rw 		B1287
rw 		B1286
rw 		B1285
rw 		B1284
rw 		B1283
rw 		B1282
rw 		B1281
rw 		B1280
rw
Toggle fields

B1280

Bit 0: B1280.

B1281

Bit 1: B1281.

B1282

Bit 2: B1282.

B1283

Bit 3: B1283.

B1284

Bit 4: B1284.

B1285

Bit 5: B1285.

B1286

Bit 6: B1286.

B1287

Bit 7: B1287.

B1288

Bit 8: B1288.

B1289

Bit 9: B1289.

B1290

Bit 10: B1290.

B1291

Bit 11: B1291.

B1292

Bit 12: B1292.

B1293

Bit 13: B1293.

B1294

Bit 14: B1294.

B1295

Bit 15: B1295.

B1296

Bit 16: B1296.

B1297

Bit 17: B1297.

B1298

Bit 18: B1298.

B1299

Bit 19: B1299.

B1300

Bit 20: B1300.

B1301

Bit 21: B1301.

B1302

Bit 22: B1302.

B1303

Bit 23: B1303.

B1304

Bit 24: B1304.

B1305

Bit 25: B1305.

B1306

Bit 26: B1306.

B1307

Bit 27: B1307.

B1308

Bit 28: B1308.

B1309

Bit 29: B1309.

B1310

Bit 30: B1310.

B1311

Bit 31: B1311.

VCTR41

MPCBBx vector register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1343
rw 		B1342
rw 		B1341
rw 		B1340
rw 		B1339
rw 		B1338
rw 		B1337
rw 		B1336
rw 		B1335
rw 		B1334
rw 		B1333
rw 		B1332
rw 		B1331
rw 		B1330
rw 		B1329
rw 		B1328
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1327
rw 		B1326
rw 		B1325
rw 		B1324
rw 		B1323
rw 		B1322
rw 		B1321
rw 		B1320
rw 		B1319
rw 		B1318
rw 		B1317
rw 		B1316
rw 		B1315
rw 		B1314
rw 		B1313
rw 		B1312
rw
Toggle fields

B1312

Bit 0: B1312.

B1313

Bit 1: B1313.

B1314

Bit 2: B1314.

B1315

Bit 3: B1315.

B1316

Bit 4: B1316.

B1317

Bit 5: B1317.

B1318

Bit 6: B1318.

B1319

Bit 7: B1319.

B1320

Bit 8: B1320.

B1321

Bit 9: B1321.

B1322

Bit 10: B1322.

B1323

Bit 11: B1323.

B1324

Bit 12: B1324.

B1325

Bit 13: B1325.

B1326

Bit 14: B1326.

B1327

Bit 15: B1327.

B1328

Bit 16: B1328.

B1329

Bit 17: B1329.

B1330

Bit 18: B1330.

B1331

Bit 19: B1331.

B1332

Bit 20: B1332.

B1333

Bit 21: B1333.

B1334

Bit 22: B1334.

B1335

Bit 23: B1335.

B1336

Bit 24: B1336.

B1337

Bit 25: B1337.

B1338

Bit 26: B1338.

B1339

Bit 27: B1339.

B1340

Bit 28: B1340.

B1341

Bit 29: B1341.

B1342

Bit 30: B1342.

B1343

Bit 31: B1343.

VCTR42

MPCBBx vector register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1375
rw 		B1374
rw 		B1373
rw 		B1372
rw 		B1371
rw 		B1370
rw 		B1369
rw 		B1368
rw 		B1367
rw 		B1366
rw 		B1365
rw 		B1364
rw 		B1363
rw 		B1362
rw 		B1361
rw 		B1360
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1359
rw 		B1358
rw 		B1357
rw 		B1356
rw 		B1355
rw 		B1354
rw 		B1353
rw 		B1352
rw 		B1351
rw 		B1350
rw 		B1349
rw 		B1348
rw 		B1347
rw 		B1346
rw 		B1345
rw 		B1344
rw
Toggle fields

B1344

Bit 0: B1344.

B1345

Bit 1: B1345.

B1346

Bit 2: B1346.

B1347

Bit 3: B1347.

B1348

Bit 4: B1348.

B1349

Bit 5: B1349.

B1350

Bit 6: B1350.

B1351

Bit 7: B1351.

B1352

Bit 8: B1352.

B1353

Bit 9: B1353.

B1354

Bit 10: B1354.

B1355

Bit 11: B1355.

B1356

Bit 12: B1356.

B1357

Bit 13: B1357.

B1358

Bit 14: B1358.

B1359

Bit 15: B1359.

B1360

Bit 16: B1360.

B1361

Bit 17: B1361.

B1362

Bit 18: B1362.

B1363

Bit 19: B1363.

B1364

Bit 20: B1364.

B1365

Bit 21: B1365.

B1366

Bit 22: B1366.

B1367

Bit 23: B1367.

B1368

Bit 24: B1368.

B1369

Bit 25: B1369.

B1370

Bit 26: B1370.

B1371

Bit 27: B1371.

B1372

Bit 28: B1372.

B1373

Bit 29: B1373.

B1374

Bit 30: B1374.

B1375

Bit 31: B1375.

VCTR43

MPCBBx vector register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1407
rw 		B1406
rw 		B1405
rw 		B1404
rw 		B1403
rw 		B1402
rw 		B1401
rw 		B1400
rw 		B1399
rw 		B1398
rw 		B1397
rw 		B1396
rw 		B1395
rw 		B1394
rw 		B1393
rw 		B1392
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1391
rw 		B1390
rw 		B1389
rw 		B1388
rw 		B1387
rw 		B1386
rw 		B1385
rw 		B1384
rw 		B1383
rw 		B1382
rw 		B1381
rw 		B1380
rw 		B1379
rw 		B1378
rw 		B1377
rw 		B1376
rw
Toggle fields

B1376

Bit 0: B1376.

B1377

Bit 1: B1377.

B1378

Bit 2: B1378.

B1379

Bit 3: B1379.

B1380

Bit 4: B1380.

B1381

Bit 5: B1381.

B1382

Bit 6: B1382.

B1383

Bit 7: B1383.

B1384

Bit 8: B1384.

B1385

Bit 9: B1385.

B1386

Bit 10: B1386.

B1387

Bit 11: B1387.

B1388

Bit 12: B1388.

B1389

Bit 13: B1389.

B1390

Bit 14: B1390.

B1391

Bit 15: B1391.

B1392

Bit 16: B1392.

B1393

Bit 17: B1393.

B1394

Bit 18: B1394.

B1395

Bit 19: B1395.

B1396

Bit 20: B1396.

B1397

Bit 21: B1397.

B1398

Bit 22: B1398.

B1399

Bit 23: B1399.

B1400

Bit 24: B1400.

B1401

Bit 25: B1401.

B1402

Bit 26: B1402.

B1403

Bit 27: B1403.

B1404

Bit 28: B1404.

B1405

Bit 29: B1405.

B1406

Bit 30: B1406.

B1407

Bit 31: B1407.

VCTR44

MPCBBx vector register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1439
rw 		B1438
rw 		B1437
rw 		B1436
rw 		B1435
rw 		B1434
rw 		B1433
rw 		B1432
rw 		B1431
rw 		B1430
rw 		B1429
rw 		B1428
rw 		B1427
rw 		B1426
rw 		B1425
rw 		B1424
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1423
rw 		B1422
rw 		B1421
rw 		B1420
rw 		B1419
rw 		B1418
rw 		B1417
rw 		B1416
rw 		B1415
rw 		B1414
rw 		B1413
rw 		B1412
rw 		B1411
rw 		B1410
rw 		B1409
rw 		B1408
rw
Toggle fields

B1408

Bit 0: B1408.

B1409

Bit 1: B1409.

B1410

Bit 2: B1410.

B1411

Bit 3: B1411.

B1412

Bit 4: B1412.

B1413

Bit 5: B1413.

B1414

Bit 6: B1414.

B1415

Bit 7: B1415.

B1416

Bit 8: B1416.

B1417

Bit 9: B1417.

B1418

Bit 10: B1418.

B1419

Bit 11: B1419.

B1420

Bit 12: B1420.

B1421

Bit 13: B1421.

B1422

Bit 14: B1422.

B1423

Bit 15: B1423.

B1424

Bit 16: B1424.

B1425

Bit 17: B1425.

B1426

Bit 18: B1426.

B1427

Bit 19: B1427.

B1428

Bit 20: B1428.

B1429

Bit 21: B1429.

B1430

Bit 22: B1430.

B1431

Bit 23: B1431.

B1432

Bit 24: B1432.

B1433

Bit 25: B1433.

B1434

Bit 26: B1434.

B1435

Bit 27: B1435.

B1436

Bit 28: B1436.

B1437

Bit 29: B1437.

B1438

Bit 30: B1438.

B1439

Bit 31: B1439.

VCTR45

MPCBBx vector register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1471
rw 		B1470
rw 		B1469
rw 		B1468
rw 		B1467
rw 		B1466
rw 		B1465
rw 		B1464
rw 		B1463
rw 		B1462
rw 		B1461
rw 		B1460
rw 		B1459
rw 		B1458
rw 		B1457
rw 		B1456
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1455
rw 		B1454
rw 		B1453
rw 		B1452
rw 		B1451
rw 		B1450
rw 		B1449
rw 		B1448
rw 		B1447
rw 		B1446
rw 		B1445
rw 		B1444
rw 		B1443
rw 		B1442
rw 		B1441
rw 		B1440
rw
Toggle fields

B1440

Bit 0: B1440.

B1441

Bit 1: B1441.

B1442

Bit 2: B1442.

B1443

Bit 3: B1443.

B1444

Bit 4: B1444.

B1445

Bit 5: B1445.

B1446

Bit 6: B1446.

B1447

Bit 7: B1447.

B1448

Bit 8: B1448.

B1449

Bit 9: B1449.

B1450

Bit 10: B1450.

B1451

Bit 11: B1451.

B1452

Bit 12: B1452.

B1453

Bit 13: B1453.

B1454

Bit 14: B1454.

B1455

Bit 15: B1455.

B1456

Bit 16: B1456.

B1457

Bit 17: B1457.

B1458

Bit 18: B1458.

B1459

Bit 19: B1459.

B1460

Bit 20: B1460.

B1461

Bit 21: B1461.

B1462

Bit 22: B1462.

B1463

Bit 23: B1463.

B1464

Bit 24: B1464.

B1465

Bit 25: B1465.

B1466

Bit 26: B1466.

B1467

Bit 27: B1467.

B1468

Bit 28: B1468.

B1469

Bit 29: B1469.

B1470

Bit 30: B1470.

B1471

Bit 31: B1471.

VCTR46

MPCBBx vector register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1503
rw 		B1502
rw 		B1501
rw 		B1500
rw 		B1499
rw 		B1498
rw 		B1497
rw 		B1496
rw 		B1495
rw 		B1494
rw 		B1493
rw 		B1492
rw 		B1491
rw 		B1490
rw 		B1489
rw 		B1488
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1487
rw 		B1486
rw 		B1485
rw 		B1484
rw 		B1483
rw 		B1482
rw 		B1481
rw 		B1480
rw 		B1479
rw 		B1478
rw 		B1477
rw 		B1476
rw 		B1475
rw 		B1474
rw 		B1473
rw 		B1472
rw
Toggle fields

B1472

Bit 0: B1472.

B1473

Bit 1: B1473.

B1474

Bit 2: B1474.

B1475

Bit 3: B1475.

B1476

Bit 4: B1476.

B1477

Bit 5: B1477.

B1478

Bit 6: B1478.

B1479

Bit 7: B1479.

B1480

Bit 8: B1480.

B1481

Bit 9: B1481.

B1482

Bit 10: B1482.

B1483

Bit 11: B1483.

B1484

Bit 12: B1484.

B1485

Bit 13: B1485.

B1486

Bit 14: B1486.

B1487

Bit 15: B1487.

B1488

Bit 16: B1488.

B1489

Bit 17: B1489.

B1490

Bit 18: B1490.

B1491

Bit 19: B1491.

B1492

Bit 20: B1492.

B1493

Bit 21: B1493.

B1494

Bit 22: B1494.

B1495

Bit 23: B1495.

B1496

Bit 24: B1496.

B1497

Bit 25: B1497.

B1498

Bit 26: B1498.

B1499

Bit 27: B1499.

B1500

Bit 28: B1500.

B1501

Bit 29: B1501.

B1502

Bit 30: B1502.

B1503

Bit 31: B1503.

VCTR47

MPCBBx vector register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1535
rw 		B1534
rw 		B1533
rw 		B1532
rw 		B1531
rw 		B1530
rw 		B1529
rw 		B1528
rw 		B1527
rw 		B1526
rw 		B1525
rw 		B1524
rw 		B1523
rw 		B1522
rw 		B1521
rw 		B1520
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1519
rw 		B1518
rw 		B1517
rw 		B1516
rw 		B1515
rw 		B1514
rw 		B1513
rw 		B1512
rw 		B1511
rw 		B1510
rw 		B1509
rw 		B1508
rw 		B1507
rw 		B1506
rw 		B1505
rw 		B1504
rw
Toggle fields

B1504

Bit 0: B1504.

B1505

Bit 1: B1505.

B1506

Bit 2: B1506.

B1507

Bit 3: B1507.

B1508

Bit 4: B1508.

B1509

Bit 5: B1509.

B1510

Bit 6: B1510.

B1511

Bit 7: B1511.

B1512

Bit 8: B1512.

B1513

Bit 9: B1513.

B1514

Bit 10: B1514.

B1515

Bit 11: B1515.

B1516

Bit 12: B1516.

B1517

Bit 13: B1517.

B1518

Bit 14: B1518.

B1519

Bit 15: B1519.

B1520

Bit 16: B1520.

B1521

Bit 17: B1521.

B1522

Bit 18: B1522.

B1523

Bit 19: B1523.

B1524

Bit 20: B1524.

B1525

Bit 21: B1525.

B1526

Bit 22: B1526.

B1527

Bit 23: B1527.

B1528

Bit 24: B1528.

B1529

Bit 25: B1529.

B1530

Bit 26: B1530.

B1531

Bit 27: B1531.

B1532

Bit 28: B1532.

B1533

Bit 29: B1533.

B1534

Bit 30: B1534.

B1535

Bit 31: B1535.

VCTR48

MPCBBx vector register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1567
rw 		B1566
rw 		B1565
rw 		B1564
rw 		B1563
rw 		B1562
rw 		B1561
rw 		B1560
rw 		B1559
rw 		B1558
rw 		B1557
rw 		B1556
rw 		B1555
rw 		B1554
rw 		B1553
rw 		B1552
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1551
rw 		B1550
rw 		B1549
rw 		B1548
rw 		B1547
rw 		B1546
rw 		B1545
rw 		B1544
rw 		B1543
rw 		B1542
rw 		B1541
rw 		B1540
rw 		B1539
rw 		B1538
rw 		B1537
rw 		B1536
rw
Toggle fields

B1536

Bit 0: B1536.

B1537

Bit 1: B1537.

B1538

Bit 2: B1538.

B1539

Bit 3: B1539.

B1540

Bit 4: B1540.

B1541

Bit 5: B1541.

B1542

Bit 6: B1542.

B1543

Bit 7: B1543.

B1544

Bit 8: B1544.

B1545

Bit 9: B1545.

B1546

Bit 10: B1546.

B1547

Bit 11: B1547.

B1548

Bit 12: B1548.

B1549

Bit 13: B1549.

B1550

Bit 14: B1550.

B1551

Bit 15: B1551.

B1552

Bit 16: B1552.

B1553

Bit 17: B1553.

B1554

Bit 18: B1554.

B1555

Bit 19: B1555.

B1556

Bit 20: B1556.

B1557

Bit 21: B1557.

B1558

Bit 22: B1558.

B1559

Bit 23: B1559.

B1560

Bit 24: B1560.

B1561

Bit 25: B1561.

B1562

Bit 26: B1562.

B1563

Bit 27: B1563.

B1564

Bit 28: B1564.

B1565

Bit 29: B1565.

B1566

Bit 30: B1566.

B1567

Bit 31: B1567.

VCTR49

MPCBBx vector register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1599
rw 		B1598
rw 		B1597
rw 		B1596
rw 		B1595
rw 		B1594
rw 		B1593
rw 		B1592
rw 		B1591
rw 		B1590
rw 		B1589
rw 		B1588
rw 		B1587
rw 		B1586
rw 		B1585
rw 		B1584
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1583
rw 		B1582
rw 		B1581
rw 		B1580
rw 		B1579
rw 		B1578
rw 		B1577
rw 		B1576
rw 		B1575
rw 		B1574
rw 		B1573
rw 		B1572
rw 		B1571
rw 		B1570
rw 		B1569
rw 		B1568
rw
Toggle fields

B1568

Bit 0: B1568.

B1569

Bit 1: B1569.

B1570

Bit 2: B1570.

B1571

Bit 3: B1571.

B1572

Bit 4: B1572.

B1573

Bit 5: B1573.

B1574

Bit 6: B1574.

B1575

Bit 7: B1575.

B1576

Bit 8: B1576.

B1577

Bit 9: B1577.

B1578

Bit 10: B1578.

B1579

Bit 11: B1579.

B1580

Bit 12: B1580.

B1581

Bit 13: B1581.

B1582

Bit 14: B1582.

B1583

Bit 15: B1583.

B1584

Bit 16: B1584.

B1585

Bit 17: B1585.

B1586

Bit 18: B1586.

B1587

Bit 19: B1587.

B1588

Bit 20: B1588.

B1589

Bit 21: B1589.

B1590

Bit 22: B1590.

B1591

Bit 23: B1591.

B1592

Bit 24: B1592.

B1593

Bit 25: B1593.

B1594

Bit 26: B1594.

B1595

Bit 27: B1595.

B1596

Bit 28: B1596.

B1597

Bit 29: B1597.

B1598

Bit 30: B1598.

B1599

Bit 31: B1599.

VCTR50

MPCBBx vector register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1631
rw 		B1630
rw 		B1629
rw 		B1628
rw 		B1627
rw 		B1626
rw 		B1625
rw 		B1624
rw 		B1623
rw 		B1622
rw 		B1621
rw 		B1620
rw 		B1619
rw 		B1618
rw 		B1617
rw 		B1616
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1615
rw 		B1614
rw 		B1613
rw 		B1612
rw 		B1611
rw 		B1610
rw 		B1609
rw 		B1608
rw 		B1607
rw 		B1606
rw 		B1605
rw 		B1604
rw 		B1603
rw 		B1602
rw 		B1601
rw 		B1600
rw
Toggle fields

B1600

Bit 0: B1600.

B1601

Bit 1: B1601.

B1602

Bit 2: B1602.

B1603

Bit 3: B1603.

B1604

Bit 4: B1604.

B1605

Bit 5: B1605.

B1606

Bit 6: B1606.

B1607

Bit 7: B1607.

B1608

Bit 8: B1608.

B1609

Bit 9: B1609.

B1610

Bit 10: B1610.

B1611

Bit 11: B1611.

B1612

Bit 12: B1612.

B1613

Bit 13: B1613.

B1614

Bit 14: B1614.

B1615

Bit 15: B1615.

B1616

Bit 16: B1616.

B1617

Bit 17: B1617.

B1618

Bit 18: B1618.

B1619

Bit 19: B1619.

B1620

Bit 20: B1620.

B1621

Bit 21: B1621.

B1622

Bit 22: B1622.

B1623

Bit 23: B1623.

B1624

Bit 24: B1624.

B1625

Bit 25: B1625.

B1626

Bit 26: B1626.

B1627

Bit 27: B1627.

B1628

Bit 28: B1628.

B1629

Bit 29: B1629.

B1630

Bit 30: B1630.

B1631

Bit 31: B1631.

VCTR51

MPCBBx vector register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1663
rw 		B1662
rw 		B1661
rw 		B1660
rw 		B1659
rw 		B1658
rw 		B1657
rw 		B1656
rw 		B1655
rw 		B1654
rw 		B1653
rw 		B1652
rw 		B1651
rw 		B1650
rw 		B1649
rw 		B1648
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1647
rw 		B1646
rw 		B1645
rw 		B1644
rw 		B1643
rw 		B1642
rw 		B1641
rw 		B1640
rw 		B1639
rw 		B1638
rw 		B1637
rw 		B1636
rw 		B1635
rw 		B1634
rw 		B1633
rw 		B1632
rw
Toggle fields

B1632

Bit 0: B1632.

B1633

Bit 1: B1633.

B1634

Bit 2: B1634.

B1635

Bit 3: B1635.

B1636

Bit 4: B1636.

B1637

Bit 5: B1637.

B1638

Bit 6: B1638.

B1639

Bit 7: B1639.

B1640

Bit 8: B1640.

B1641

Bit 9: B1641.

B1642

Bit 10: B1642.

B1643

Bit 11: B1643.

B1644

Bit 12: B1644.

B1645

Bit 13: B1645.

B1646

Bit 14: B1646.

B1647

Bit 15: B1647.

B1648

Bit 16: B1648.

B1649

Bit 17: B1649.

B1650

Bit 18: B1650.

B1651

Bit 19: B1651.

B1652

Bit 20: B1652.

B1653

Bit 21: B1653.

B1654

Bit 22: B1654.

B1655

Bit 23: B1655.

B1656

Bit 24: B1656.

B1657

Bit 25: B1657.

B1658

Bit 26: B1658.

B1659

Bit 27: B1659.

B1660

Bit 28: B1660.

B1661

Bit 29: B1661.

B1662

Bit 30: B1662.

B1663

Bit 31: B1663.

VCTR52

MPCBBx vector register

Offset: 0x1d0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1695
rw 		B1694
rw 		B1693
rw 		B1692
rw 		B1691
rw 		B1690
rw 		B1689
rw 		B1688
rw 		B1687
rw 		B1686
rw 		B1685
rw 		B1684
rw 		B1683
rw 		B1682
rw 		B1681
rw 		B1680
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1679
rw 		B1678
rw 		B1677
rw 		B1676
rw 		B1675
rw 		B1674
rw 		B1673
rw 		B1672
rw 		B1671
rw 		B1670
rw 		B1669
rw 		B1668
rw 		B1667
rw 		B1666
rw 		B1665
rw 		B1664
rw
Toggle fields

B1664

Bit 0: B1664.

B1665

Bit 1: B1665.

B1666

Bit 2: B1666.

B1667

Bit 3: B1667.

B1668

Bit 4: B1668.

B1669

Bit 5: B1669.

B1670

Bit 6: B1670.

B1671

Bit 7: B1671.

B1672

Bit 8: B1672.

B1673

Bit 9: B1673.

B1674

Bit 10: B1674.

B1675

Bit 11: B1675.

B1676

Bit 12: B1676.

B1677

Bit 13: B1677.

B1678

Bit 14: B1678.

B1679

Bit 15: B1679.

B1680

Bit 16: B1680.

B1681

Bit 17: B1681.

B1682

Bit 18: B1682.

B1683

Bit 19: B1683.

B1684

Bit 20: B1684.

B1685

Bit 21: B1685.

B1686

Bit 22: B1686.

B1687

Bit 23: B1687.

B1688

Bit 24: B1688.

B1689

Bit 25: B1689.

B1690

Bit 26: B1690.

B1691

Bit 27: B1691.

B1692

Bit 28: B1692.

B1693

Bit 29: B1693.

B1694

Bit 30: B1694.

B1695

Bit 31: B1695.

VCTR53

MPCBBx vector register

Offset: 0x1d4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1727
rw 		B1726
rw 		B1725
rw 		B1724
rw 		B1723
rw 		B1722
rw 		B1721
rw 		B1720
rw 		B1719
rw 		B1718
rw 		B1717
rw 		B1716
rw 		B1715
rw 		B1714
rw 		B1713
rw 		B1712
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1711
rw 		B1710
rw 		B1709
rw 		B1708
rw 		B1707
rw 		B1706
rw 		B1705
rw 		B1704
rw 		B1703
rw 		B1702
rw 		B1701
rw 		B1700
rw 		B1699
rw 		B1698
rw 		B1697
rw 		B1696
rw
Toggle fields

B1696

Bit 0: B1696.

B1697

Bit 1: B1697.

B1698

Bit 2: B1698.

B1699

Bit 3: B1699.

B1700

Bit 4: B1700.

B1701

Bit 5: B1701.

B1702

Bit 6: B1702.

B1703

Bit 7: B1703.

B1704

Bit 8: B1704.

B1705

Bit 9: B1705.

B1706

Bit 10: B1706.

B1707

Bit 11: B1707.

B1708

Bit 12: B1708.

B1709

Bit 13: B1709.

B1710

Bit 14: B1710.

B1711

Bit 15: B1711.

B1712

Bit 16: B1712.

B1713

Bit 17: B1713.

B1714

Bit 18: B1714.

B1715

Bit 19: B1715.

B1716

Bit 20: B1716.

B1717

Bit 21: B1717.

B1718

Bit 22: B1718.

B1719

Bit 23: B1719.

B1720

Bit 24: B1720.

B1721

Bit 25: B1721.

B1722

Bit 26: B1722.

B1723

Bit 27: B1723.

B1724

Bit 28: B1724.

B1725

Bit 29: B1725.

B1726

Bit 30: B1726.

B1727

Bit 31: B1727.

VCTR54

MPCBBx vector register

Offset: 0x1d8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1759
rw 		B1758
rw 		B1757
rw 		B1756
rw 		B1755
rw 		B1754
rw 		B1753
rw 		B1752
rw 		B1751
rw 		B1750
rw 		B1749
rw 		B1748
rw 		B1747
rw 		B1746
rw 		B1745
rw 		B1744
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1743
rw 		B1742
rw 		B1741
rw 		B1740
rw 		B1739
rw 		B1738
rw 		B1737
rw 		B1736
rw 		B1735
rw 		B1734
rw 		B1733
rw 		B1732
rw 		B1731
rw 		B1730
rw 		B1729
rw 		B1728
rw
Toggle fields

B1728

Bit 0: B1728.

B1729

Bit 1: B1729.

B1730

Bit 2: B1730.

B1731

Bit 3: B1731.

B1732

Bit 4: B1732.

B1733

Bit 5: B1733.

B1734

Bit 6: B1734.

B1735

Bit 7: B1735.

B1736

Bit 8: B1736.

B1737

Bit 9: B1737.

B1738

Bit 10: B1738.

B1739

Bit 11: B1739.

B1740

Bit 12: B1740.

B1741

Bit 13: B1741.

B1742

Bit 14: B1742.

B1743

Bit 15: B1743.

B1744

Bit 16: B1744.

B1745

Bit 17: B1745.

B1746

Bit 18: B1746.

B1747

Bit 19: B1747.

B1748

Bit 20: B1748.

B1749

Bit 21: B1749.

B1750

Bit 22: B1750.

B1751

Bit 23: B1751.

B1752

Bit 24: B1752.

B1753

Bit 25: B1753.

B1754

Bit 26: B1754.

B1755

Bit 27: B1755.

B1756

Bit 28: B1756.

B1757

Bit 29: B1757.

B1758

Bit 30: B1758.

B1759

Bit 31: B1759.

VCTR55

MPCBBx vector register

Offset: 0x1dc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1791
rw 		B1790
rw 		B1789
rw 		B1788
rw 		B1787
rw 		B1786
rw 		B1785
rw 		B1784
rw 		B1783
rw 		B1782
rw 		B1781
rw 		B1780
rw 		B1779
rw 		B1778
rw 		B1777
rw 		B1776
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1775
rw 		B1774
rw 		B1773
rw 		B1772
rw 		B1771
rw 		B1770
rw 		B1769
rw 		B1768
rw 		B1767
rw 		B1766
rw 		B1765
rw 		B1764
rw 		B1763
rw 		B1762
rw 		B1761
rw 		B1760
rw
Toggle fields

B1760

Bit 0: B1760.

B1761

Bit 1: B1761.

B1762

Bit 2: B1762.

B1763

Bit 3: B1763.

B1764

Bit 4: B1764.

B1765

Bit 5: B1765.

B1766

Bit 6: B1766.

B1767

Bit 7: B1767.

B1768

Bit 8: B1768.

B1769

Bit 9: B1769.

B1770

Bit 10: B1770.

B1771

Bit 11: B1771.

B1772

Bit 12: B1772.

B1773

Bit 13: B1773.

B1774

Bit 14: B1774.

B1775

Bit 15: B1775.

B1776

Bit 16: B1776.

B1777

Bit 17: B1777.

B1778

Bit 18: B1778.

B1779

Bit 19: B1779.

B1780

Bit 20: B1780.

B1781

Bit 21: B1781.

B1782

Bit 22: B1782.

B1783

Bit 23: B1783.

B1784

Bit 24: B1784.

B1785

Bit 25: B1785.

B1786

Bit 26: B1786.

B1787

Bit 27: B1787.

B1788

Bit 28: B1788.

B1789

Bit 29: B1789.

B1790

Bit 30: B1790.

B1791

Bit 31: B1791.

VCTR56

MPCBBx vector register

Offset: 0x1e0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1823
rw 		B1822
rw 		B1821
rw 		B1820
rw 		B1819
rw 		B1818
rw 		B1817
rw 		B1816
rw 		B1815
rw 		B1814
rw 		B1813
rw 		B1812
rw 		B1811
rw 		B1810
rw 		B1809
rw 		B1808
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1807
rw 		B1806
rw 		B1805
rw 		B1804
rw 		B1803
rw 		B1802
rw 		B1801
rw 		B1800
rw 		B1799
rw 		B1798
rw 		B1797
rw 		B1796
rw 		B1795
rw 		B1794
rw 		B1793
rw 		B1792
rw
Toggle fields

B1792

Bit 0: B1792.

B1793

Bit 1: B1793.

B1794

Bit 2: B1794.

B1795

Bit 3: B1795.

B1796

Bit 4: B1796.

B1797

Bit 5: B1797.

B1798

Bit 6: B1798.

B1799

Bit 7: B1799.

B1800

Bit 8: B1800.

B1801

Bit 9: B1801.

B1802

Bit 10: B1802.

B1803

Bit 11: B1803.

B1804

Bit 12: B1804.

B1805

Bit 13: B1805.

B1806

Bit 14: B1806.

B1807

Bit 15: B1807.

B1808

Bit 16: B1808.

B1809

Bit 17: B1809.

B1810

Bit 18: B1810.

B1811

Bit 19: B1811.

B1812

Bit 20: B1812.

B1813

Bit 21: B1813.

B1814

Bit 22: B1814.

B1815

Bit 23: B1815.

B1816

Bit 24: B1816.

B1817

Bit 25: B1817.

B1818

Bit 26: B1818.

B1819

Bit 27: B1819.

B1820

Bit 28: B1820.

B1821

Bit 29: B1821.

B1822

Bit 30: B1822.

B1823

Bit 31: B1823.

VCTR57

MPCBBx vector register

Offset: 0x1e4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1855
rw 		B1854
rw 		B1853
rw 		B1852
rw 		B1851
rw 		B1850
rw 		B1849
rw 		B1848
rw 		B1847
rw 		B1846
rw 		B1845
rw 		B1844
rw 		B1843
rw 		B1842
rw 		B1841
rw 		B1840
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1839
rw 		B1838
rw 		B1837
rw 		B1836
rw 		B1835
rw 		B1834
rw 		B1833
rw 		B1832
rw 		B1831
rw 		B1830
rw 		B1829
rw 		B1828
rw 		B1827
rw 		B1826
rw 		B1825
rw 		B1824
rw
Toggle fields

B1824

Bit 0: B1824.

B1825

Bit 1: B1825.

B1826

Bit 2: B1826.

B1827

Bit 3: B1827.

B1828

Bit 4: B1828.

B1829

Bit 5: B1829.

B1830

Bit 6: B1830.

B1831

Bit 7: B1831.

B1832

Bit 8: B1832.

B1833

Bit 9: B1833.

B1834

Bit 10: B1834.

B1835

Bit 11: B1835.

B1836

Bit 12: B1836.

B1837

Bit 13: B1837.

B1838

Bit 14: B1838.

B1839

Bit 15: B1839.

B1840

Bit 16: B1840.

B1841

Bit 17: B1841.

B1842

Bit 18: B1842.

B1843

Bit 19: B1843.

B1844

Bit 20: B1844.

B1845

Bit 21: B1845.

B1846

Bit 22: B1846.

B1847

Bit 23: B1847.

B1848

Bit 24: B1848.

B1849

Bit 25: B1849.

B1850

Bit 26: B1850.

B1851

Bit 27: B1851.

B1852

Bit 28: B1852.

B1853

Bit 29: B1853.

B1854

Bit 30: B1854.

B1855

Bit 31: B1855.

VCTR58

MPCBBx vector register

Offset: 0x1e8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1887
rw 		B1886
rw 		B1885
rw 		B1884
rw 		B1883
rw 		B1882
rw 		B1881
rw 		B1880
rw 		B1879
rw 		B1878
rw 		B1877
rw 		B1876
rw 		B1875
rw 		B1874
rw 		B1873
rw 		B1872
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1871
rw 		B1870
rw 		B1869
rw 		B1868
rw 		B1867
rw 		B1866
rw 		B1865
rw 		B1864
rw 		B1863
rw 		B1862
rw 		B1861
rw 		B1860
rw 		B1859
rw 		B1858
rw 		B1857
rw 		B1856
rw
Toggle fields

B1856

Bit 0: B1856.

B1857

Bit 1: B1857.

B1858

Bit 2: B1858.

B1859

Bit 3: B1859.

B1860

Bit 4: B1860.

B1861

Bit 5: B1861.

B1862

Bit 6: B1862.

B1863

Bit 7: B1863.

B1864

Bit 8: B1864.

B1865

Bit 9: B1865.

B1866

Bit 10: B1866.

B1867

Bit 11: B1867.

B1868

Bit 12: B1868.

B1869

Bit 13: B1869.

B1870

Bit 14: B1870.

B1871

Bit 15: B1871.

B1872

Bit 16: B1872.

B1873

Bit 17: B1873.

B1874

Bit 18: B1874.

B1875

Bit 19: B1875.

B1876

Bit 20: B1876.

B1877

Bit 21: B1877.

B1878

Bit 22: B1878.

B1879

Bit 23: B1879.

B1880

Bit 24: B1880.

B1881

Bit 25: B1881.

B1882

Bit 26: B1882.

B1883

Bit 27: B1883.

B1884

Bit 28: B1884.

B1885

Bit 29: B1885.

B1886

Bit 30: B1886.

B1887

Bit 31: B1887.

VCTR59

MPCBBx vector register

Offset: 0x1ec, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1919
rw 		B1918
rw 		B1917
rw 		B1916
rw 		B1915
rw 		B1914
rw 		B1913
rw 		B1912
rw 		B1911
rw 		B1910
rw 		B1909
rw 		B1908
rw 		B1907
rw 		B1906
rw 		B1905
rw 		B1904
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1903
rw 		B1902
rw 		B1901
rw 		B1900
rw 		B1899
rw 		B1898
rw 		B1897
rw 		B1896
rw 		B1895
rw 		B1894
rw 		B1893
rw 		B1892
rw 		B1891
rw 		B1890
rw 		B1889
rw 		B1888
rw
Toggle fields

B1888

Bit 0: B1888.

B1889

Bit 1: B1889.

B1890

Bit 2: B1890.

B1891

Bit 3: B1891.

B1892

Bit 4: B1892.

B1893

Bit 5: B1893.

B1894

Bit 6: B1894.

B1895

Bit 7: B1895.

B1896

Bit 8: B1896.

B1897

Bit 9: B1897.

B1898

Bit 10: B1898.

B1899

Bit 11: B1899.

B1900

Bit 12: B1900.

B1901

Bit 13: B1901.

B1902

Bit 14: B1902.

B1903

Bit 15: B1903.

B1904

Bit 16: B1904.

B1905

Bit 17: B1905.

B1906

Bit 18: B1906.

B1907

Bit 19: B1907.

B1908

Bit 20: B1908.

B1909

Bit 21: B1909.

B1910

Bit 22: B1910.

B1911

Bit 23: B1911.

B1912

Bit 24: B1912.

B1913

Bit 25: B1913.

B1914

Bit 26: B1914.

B1915

Bit 27: B1915.

B1916

Bit 28: B1916.

B1917

Bit 29: B1917.

B1918

Bit 30: B1918.

B1919

Bit 31: B1919.

VCTR60

MPCBBx vector register

Offset: 0x1f0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1951
rw 		B1950
rw 		B1949
rw 		B1948
rw 		B1947
rw 		B1946
rw 		B1945
rw 		B1944
rw 		B1943
rw 		B1942
rw 		B1941
rw 		B1940
rw 		B1939
rw 		B1938
rw 		B1937
rw 		B1936
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1935
rw 		B1934
rw 		B1933
rw 		B1932
rw 		B1931
rw 		B1930
rw 		B1929
rw 		B1928
rw 		B1927
rw 		B1926
rw 		B1925
rw 		B1924
rw 		B1923
rw 		B1922
rw 		B1921
rw 		B1920
rw
Toggle fields

B1920

Bit 0: B1920.

B1921

Bit 1: B1921.

B1922

Bit 2: B1922.

B1923

Bit 3: B1923.

B1924

Bit 4: B1924.

B1925

Bit 5: B1925.

B1926

Bit 6: B1926.

B1927

Bit 7: B1927.

B1928

Bit 8: B1928.

B1929

Bit 9: B1929.

B1930

Bit 10: B1930.

B1931

Bit 11: B1931.

B1932

Bit 12: B1932.

B1933

Bit 13: B1933.

B1934

Bit 14: B1934.

B1935

Bit 15: B1935.

B1936

Bit 16: B1936.

B1937

Bit 17: B1937.

B1938

Bit 18: B1938.

B1939

Bit 19: B1939.

B1940

Bit 20: B1940.

B1941

Bit 21: B1941.

B1942

Bit 22: B1942.

B1943

Bit 23: B1943.

B1944

Bit 24: B1944.

B1945

Bit 25: B1945.

B1946

Bit 26: B1946.

B1947

Bit 27: B1947.

B1948

Bit 28: B1948.

B1949

Bit 29: B1949.

B1950

Bit 30: B1950.

B1951

Bit 31: B1951.

VCTR61

MPCBBx vector register

Offset: 0x1f4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1983
rw 		B1982
rw 		B1981
rw 		B1980
rw 		B1979
rw 		B1978
rw 		B1977
rw 		B1976
rw 		B1975
rw 		B1974
rw 		B1973
rw 		B1972
rw 		B1971
rw 		B1970
rw 		B1969
rw 		B1968
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1967
rw 		B1966
rw 		B1965
rw 		B1964
rw 		B1963
rw 		B1962
rw 		B1961
rw 		B1960
rw 		B1959
rw 		B1958
rw 		B1957
rw 		B1956
rw 		B1955
rw 		B1954
rw 		B1953
rw 		B1952
rw
Toggle fields

B1952

Bit 0: B1952.

B1953

Bit 1: B1953.

B1954

Bit 2: B1954.

B1955

Bit 3: B1955.

B1956

Bit 4: B1956.

B1957

Bit 5: B1957.

B1958

Bit 6: B1958.

B1959

Bit 7: B1959.

B1960

Bit 8: B1960.

B1961

Bit 9: B1961.

B1962

Bit 10: B1962.

B1963

Bit 11: B1963.

B1964

Bit 12: B1964.

B1965

Bit 13: B1965.

B1966

Bit 14: B1966.

B1967

Bit 15: B1967.

B1968

Bit 16: B1968.

B1969

Bit 17: B1969.

B1970

Bit 18: B1970.

B1971

Bit 19: B1971.

B1972

Bit 20: B1972.

B1973

Bit 21: B1973.

B1974

Bit 22: B1974.

B1975

Bit 23: B1975.

B1976

Bit 24: B1976.

B1977

Bit 25: B1977.

B1978

Bit 26: B1978.

B1979

Bit 27: B1979.

B1980

Bit 28: B1980.

B1981

Bit 29: B1981.

B1982

Bit 30: B1982.

B1983

Bit 31: B1983.

VCTR62

MPCBBx vector register

Offset: 0x1f8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B2015
rw 		B2014
rw 		B2013
rw 		B2012
rw 		B2011
rw 		B2010
rw 		B2009
rw 		B2008
rw 		B2007
rw 		B2006
rw 		B2005
rw 		B2004
rw 		B2003
rw 		B2002
rw 		B2001
rw 		B2000
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1999
rw 		B1998
rw 		B1997
rw 		B1996
rw 		B1995
rw 		B1994
rw 		B1993
rw 		B1992
rw 		B1991
rw 		B1990
rw 		B1989
rw 		B1988
rw 		B1987
rw 		B1986
rw 		B1985
rw 		B1984
rw
Toggle fields

B1984

Bit 0: B1984.

B1985

Bit 1: B1985.

B1986

Bit 2: B1986.

B1987

Bit 3: B1987.

B1988

Bit 4: B1988.

B1989

Bit 5: B1989.

B1990

Bit 6: B1990.

B1991

Bit 7: B1991.

B1992

Bit 8: B1992.

B1993

Bit 9: B1993.

B1994

Bit 10: B1994.

B1995

Bit 11: B1995.

B1996

Bit 12: B1996.

B1997

Bit 13: B1997.

B1998

Bit 14: B1998.

B1999

Bit 15: B1999.

B2000

Bit 16: B2000.

B2001

Bit 17: B2001.

B2002

Bit 18: B2002.

B2003

Bit 19: B2003.

B2004

Bit 20: B2004.

B2005

Bit 21: B2005.

B2006

Bit 22: B2006.

B2007

Bit 23: B2007.

B2008

Bit 24: B2008.

B2009

Bit 25: B2009.

B2010

Bit 26: B2010.

B2011

Bit 27: B2011.

B2012

Bit 28: B2012.

B2013

Bit 29: B2013.

B2014

Bit 30: B2014.

B2015

Bit 31: B2015.

VCTR63

MPCBBx vector register

Offset: 0x1fc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B2047
rw 		B2046
rw 		B2045
rw 		B2044
rw 		B2043
rw 		B2042
rw 		B2041
rw 		B2040
rw 		B2039
rw 		B2038
rw 		B2037
rw 		B2036
rw 		B2035
rw 		B2034
rw 		B2033
rw 		B2032
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2031
rw 		B2030
rw 		B2029
rw 		B2028
rw 		B2027
rw 		B2026
rw 		B2025
rw 		B2024
rw 		B2023
rw 		B2022
rw 		B2021
rw 		B2020
rw 		B2019
rw 		B2018
rw 		B2017
rw 		B2016
rw
Toggle fields

B2016

Bit 0: B2016.

B2017

Bit 1: B2017.

B2018

Bit 2: B2018.

B2019

Bit 3: B2019.

B2020

Bit 4: B2020.

B2021

Bit 5: B2021.

B2022

Bit 6: B2022.

B2023

Bit 7: B2023.

B2024

Bit 8: B2024.

B2025

Bit 9: B2025.

B2026

Bit 10: B2026.

B2027

Bit 11: B2027.

B2028

Bit 12: B2028.

B2029

Bit 13: B2029.

B2030

Bit 14: B2030.

B2031

Bit 15: B2031.

B2032

Bit 16: B2032.

B2033

Bit 17: B2033.

B2034

Bit 18: B2034.

B2035

Bit 19: B2035.

B2036

Bit 20: B2036.

B2037

Bit 21: B2037.

B2038

Bit 22: B2038.

B2039

Bit 23: B2039.

B2040

Bit 24: B2040.

B2041

Bit 25: B2041.

B2042

Bit 26: B2042.

B2043

Bit 27: B2043.

B2044

Bit 28: B2044.

B2045

Bit 29: B2045.

B2046

Bit 30: B2046.

B2047

Bit 31: B2047.

GTZC_MPCBB2

0x40033000: GTZC_MPCBB2

0/2115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 LCKVTR1
0x14 LCKVTR2
0x100 VCTR0
0x104 VCTR1
0x108 VCTR2
0x10c VCTR3
0x110 VCTR4
0x114 VCTR5
0x118 VCTR6
0x11c VCTR7
0x120 VCTR8
0x124 VCTR9
0x128 VCTR10
0x12c VCTR11
0x130 VCTR12
0x134 VCTR13
0x138 VCTR14
0x13c VCTR15
0x140 VCTR16
0x144 VCTR17
0x148 VCTR18
0x14c VCTR19
0x150 VCTR20
0x154 VCTR21
0x158 VCTR22
0x15c VCTR23
0x160 VCTR24
0x164 VCTR25
0x168 VCTR26
0x16c VCTR27
0x170 VCTR28
0x174 VCTR29
0x178 VCTR30
0x17c VCTR31
0x180 VCTR32
0x184 VCTR33
0x188 VCTR34
0x18c VCTR35
0x190 VCTR36
0x194 VCTR37
0x198 VCTR38
0x19c VCTR39
0x1a0 VCTR40
0x1a4 VCTR41
0x1a8 VCTR42
0x1ac VCTR43
0x1b0 VCTR44
0x1b4 VCTR45
0x1b8 VCTR46
0x1bc VCTR47
0x1c0 VCTR48
0x1c4 VCTR49
0x1c8 VCTR50
0x1cc VCTR51
0x1d0 VCTR52
0x1d4 VCTR53
0x1d8 VCTR54
0x1dc VCTR55
0x1e0 VCTR56
0x1e4 VCTR57
0x1e8 VCTR58
0x1ec VCTR59
0x1f0 VCTR60
0x1f4 VCTR61
0x1f8 VCTR62
0x1fc VCTR63
Toggle registers

CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRWILADIS
rw 		INVSECSTATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

INVSECSTATE

Bit 30: INVSECSTATE.

SRWILADIS

Bit 31: SRWILADIS.

LCKVTR1

MPCBB control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKSB31
rw 		LCKSB30
rw 		LCKSB29
rw 		LCKSB28
rw 		LCKSB27
rw 		LCKSB26
rw 		LCKSB25
rw 		LCKSB24
rw 		LCKSB23
rw 		LCKSB22
rw 		LCKSB21
rw 		LCKSB20
rw 		LCKSB19
rw 		LCKSB18
rw 		LCKSB17
rw 		LCKSB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB15
rw 		LCKSB14
rw 		LCKSB13
rw 		LCKSB12
rw 		LCKSB11
rw 		LCKSB10
rw 		LCKSB9
rw 		LCKSB8
rw 		LCKSB7
rw 		LCKSB6
rw 		LCKSB5
rw 		LCKSB4
rw 		LCKSB3
rw 		LCKSB2
rw 		LCKSB1
rw 		LCKSB0
rw
Toggle fields

LCKSB0

Bit 0: LCKSB0.

LCKSB1

Bit 1: LCKSB1.

LCKSB2

Bit 2: LCKSB2.

LCKSB3

Bit 3: LCKSB3.

LCKSB4

Bit 4: LCKSB4.

LCKSB5

Bit 5: LCKSB5.

LCKSB6

Bit 6: LCKSB6.

LCKSB7

Bit 7: LCKSB7.

LCKSB8

Bit 8: LCKSB8.

LCKSB9

Bit 9: LCKSB9.

LCKSB10

Bit 10: LCKSB10.

LCKSB11

Bit 11: LCKSB11.

LCKSB12

Bit 12: LCKSB12.

LCKSB13

Bit 13: LCKSB13.

LCKSB14

Bit 14: LCKSB14.

LCKSB15

Bit 15: LCKSB15.

LCKSB16

Bit 16: LCKSB16.

LCKSB17

Bit 17: LCKSB17.

LCKSB18

Bit 18: LCKSB18.

LCKSB19

Bit 19: LCKSB19.

LCKSB20

Bit 20: LCKSB20.

LCKSB21

Bit 21: LCKSB21.

LCKSB22

Bit 22: LCKSB22.

LCKSB23

Bit 23: LCKSB23.

LCKSB24

Bit 24: LCKSB24.

LCKSB25

Bit 25: LCKSB25.

LCKSB26

Bit 26: LCKSB26.

LCKSB27

Bit 27: LCKSB27.

LCKSB28

Bit 28: LCKSB28.

LCKSB29

Bit 29: LCKSB29.

LCKSB30

Bit 30: LCKSB30.

LCKSB31

Bit 31: LCKSB31.

LCKVTR2

MPCBB control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKSB63
rw 		LCKSB62
rw 		LCKSB61
rw 		LCKSB60
rw 		LCKSB59
rw 		LCKSB58
rw 		LCKSB57
rw 		LCKSB56
rw 		LCKSB55
rw 		LCKSB54
rw 		LCKSB53
rw 		LCKSB52
rw 		LCKSB51
rw 		LCKSB50
rw 		LCKSB49
rw 		LCKSB48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB47
rw 		LCKSB46
rw 		LCKSB45
rw 		LCKSB44
rw 		LCKSB43
rw 		LCKSB42
rw 		LCKSB41
rw 		LCKSB40
rw 		LCKSB39
rw 		LCKSB38
rw 		LCKSB37
rw 		LCKSB36
rw 		LCKSB35
rw 		LCKSB34
rw 		LCKSB33
rw 		LCKSB32
rw
Toggle fields

LCKSB32

Bit 0: LCKSB32.

LCKSB33

Bit 1: LCKSB33.

LCKSB34

Bit 2: LCKSB34.

LCKSB35

Bit 3: LCKSB35.

LCKSB36

Bit 4: LCKSB36.

LCKSB37

Bit 5: LCKSB37.

LCKSB38

Bit 6: LCKSB38.

LCKSB39

Bit 7: LCKSB39.

LCKSB40

Bit 8: LCKSB40.

LCKSB41

Bit 9: LCKSB41.

LCKSB42

Bit 10: LCKSB42.

LCKSB43

Bit 11: LCKSB43.

LCKSB44

Bit 12: LCKSB44.

LCKSB45

Bit 13: LCKSB45.

LCKSB46

Bit 14: LCKSB46.

LCKSB47

Bit 15: LCKSB47.

LCKSB48

Bit 16: LCKSB48.

LCKSB49

Bit 17: LCKSB49.

LCKSB50

Bit 18: LCKSB50.

LCKSB51

Bit 19: LCKSB51.

LCKSB52

Bit 20: LCKSB52.

LCKSB53

Bit 21: LCKSB53.

LCKSB54

Bit 22: LCKSB54.

LCKSB55

Bit 23: LCKSB55.

LCKSB56

Bit 24: LCKSB56.

LCKSB57

Bit 25: LCKSB57.

LCKSB58

Bit 26: LCKSB58.

LCKSB59

Bit 27: LCKSB59.

LCKSB60

Bit 28: LCKSB60.

LCKSB61

Bit 29: LCKSB61.

LCKSB62

Bit 30: LCKSB62.

LCKSB63

Bit 31: LCKSB63.

VCTR0

MPCBBx vector register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw 		B30
rw 		B29
rw 		B28
rw 		B27
rw 		B26
rw 		B25
rw 		B24
rw 		B23
rw 		B22
rw 		B21
rw 		B20
rw 		B19
rw 		B18
rw 		B17
rw 		B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw 		B14
rw 		B13
rw 		B12
rw 		B11
rw 		B10
rw 		B9
rw 		B8
rw 		B7
rw 		B6
rw 		B5
rw 		B4
rw 		B3
rw 		B2
rw 		B1
rw 		B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR1

MPCBBx vector register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B63
rw 		B62
rw 		B61
rw 		B60
rw 		B59
rw 		B58
rw 		B57
rw 		B56
rw 		B55
rw 		B54
rw 		B53
rw 		B52
rw 		B51
rw 		B50
rw 		B49
rw 		B48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B47
rw 		B46
rw 		B45
rw 		B44
rw 		B43
rw 		B42
rw 		B41
rw 		B40
rw 		B39
rw 		B38
rw 		B37
rw 		B36
rw 		B35
rw 		B34
rw 		B33
rw 		B32
rw
Toggle fields

B32

Bit 0: B32.

B33

Bit 1: B33.

B34

Bit 2: B34.

B35

Bit 3: B35.

B36

Bit 4: B36.

B37

Bit 5: B37.

B38

Bit 6: B38.

B39

Bit 7: B39.

B40

Bit 8: B40.

B41

Bit 9: B41.

B42

Bit 10: B42.

B43

Bit 11: B43.

B44

Bit 12: B44.

B45

Bit 13: B45.

B46

Bit 14: B46.

B47

Bit 15: B47.

B48

Bit 16: B48.

B49

Bit 17: B49.

B50

Bit 18: B50.

B51

Bit 19: B51.

B52

Bit 20: B52.

B53

Bit 21: B53.

B54

Bit 22: B54.

B55

Bit 23: B55.

B56

Bit 24: B56.

B57

Bit 25: B57.

B58

Bit 26: B58.

B59

Bit 27: B59.

B60

Bit 28: B60.

B61

Bit 29: B61.

B62

Bit 30: B62.

B63

Bit 31: B63.

VCTR2

MPCBBx vector register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B95
rw 		B94
rw 		B93
rw 		B92
rw 		B91
rw 		B90
rw 		B89
rw 		B88
rw 		B87
rw 		B86
rw 		B85
rw 		B84
rw 		B83
rw 		B82
rw 		B81
rw 		B80
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B79
rw 		B78
rw 		B77
rw 		B76
rw 		B75
rw 		B74
rw 		B73
rw 		B72
rw 		B71
rw 		B70
rw 		B69
rw 		B68
rw 		B67
rw 		B66
rw 		B65
rw 		B64
rw
Toggle fields

B64

Bit 0: B64.

B65

Bit 1: B65.

B66

Bit 2: B66.

B67

Bit 3: B67.

B68

Bit 4: B68.

B69

Bit 5: B69.

B70

Bit 6: B70.

B71

Bit 7: B71.

B72

Bit 8: B72.

B73

Bit 9: B73.

B74

Bit 10: B74.

B75

Bit 11: B75.

B76

Bit 12: B76.

B77

Bit 13: B77.

B78

Bit 14: B78.

B79

Bit 15: B79.

B80

Bit 16: B80.

B81

Bit 17: B81.

B82

Bit 18: B82.

B83

Bit 19: B83.

B84

Bit 20: B84.

B85

Bit 21: B85.

B86

Bit 22: B86.

B87

Bit 23: B87.

B88

Bit 24: B88.

B89

Bit 25: B89.

B90

Bit 26: B90.

B91

Bit 27: B91.

B92

Bit 28: B92.

B93

Bit 29: B93.

B94

Bit 30: B94.

B95

Bit 31: B95.

VCTR3

MPCBBx vector register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B127
rw 		B126
rw 		B125
rw 		B124
rw 		B123
rw 		B122
rw 		B121
rw 		B120
rw 		B119
rw 		B118
rw 		B117
rw 		B116
rw 		B115
rw 		B114
rw 		B113
rw 		B112
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B111
rw 		B110
rw 		B109
rw 		B108
rw 		B107
rw 		B106
rw 		B105
rw 		B104
rw 		B103
rw 		B102
rw 		B101
rw 		B100
rw 		B99
rw 		B98
rw 		B97
rw 		B96
rw
Toggle fields

B96

Bit 0: B96.

B97

Bit 1: B97.

B98

Bit 2: B98.

B99

Bit 3: B99.

B100

Bit 4: B100.

B101

Bit 5: B101.

B102

Bit 6: B102.

B103

Bit 7: B103.

B104

Bit 8: B104.

B105

Bit 9: B105.

B106

Bit 10: B106.

B107

Bit 11: B107.

B108

Bit 12: B108.

B109

Bit 13: B109.

B110

Bit 14: B110.

B111

Bit 15: B111.

B112

Bit 16: B112.

B113

Bit 17: B113.

B114

Bit 18: B114.

B115

Bit 19: B115.

B116

Bit 20: B116.

B117

Bit 21: B117.

B118

Bit 22: B118.

B119

Bit 23: B119.

B120

Bit 24: B120.

B121

Bit 25: B121.

B122

Bit 26: B122.

B123

Bit 27: B123.

B124

Bit 28: B124.

B125

Bit 29: B125.

B126

Bit 30: B126.

B127

Bit 31: B127.

VCTR4

MPCBBx vector register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B159
rw 		B158
rw 		B157
rw 		B156
rw 		B155
rw 		B154
rw 		B153
rw 		B152
rw 		B151
rw 		B150
rw 		B149
rw 		B148
rw 		B147
rw 		B146
rw 		B145
rw 		B144
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B143
rw 		B142
rw 		B141
rw 		B140
rw 		B139
rw 		B138
rw 		B137
rw 		B136
rw 		B135
rw 		B134
rw 		B133
rw 		B132
rw 		B131
rw 		B130
rw 		B129
rw 		B128
rw
Toggle fields

B128

Bit 0: B128.

B129

Bit 1: B129.

B130

Bit 2: B130.

B131

Bit 3: B131.

B132

Bit 4: B132.

B133

Bit 5: B133.

B134

Bit 6: B134.

B135

Bit 7: B135.

B136

Bit 8: B136.

B137

Bit 9: B137.

B138

Bit 10: B138.

B139

Bit 11: B139.

B140

Bit 12: B140.

B141

Bit 13: B141.

B142

Bit 14: B142.

B143

Bit 15: B143.

B144

Bit 16: B144.

B145

Bit 17: B145.

B146

Bit 18: B146.

B147

Bit 19: B147.

B148

Bit 20: B148.

B149

Bit 21: B149.

B150

Bit 22: B150.

B151

Bit 23: B151.

B152

Bit 24: B152.

B153

Bit 25: B153.

B154

Bit 26: B154.

B155

Bit 27: B155.

B156

Bit 28: B156.

B157

Bit 29: B157.

B158

Bit 30: B158.

B159

Bit 31: B159.

VCTR5

MPCBBx vector register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B191
rw 		B190
rw 		B189
rw 		B188
rw 		B187
rw 		B186
rw 		B185
rw 		B184
rw 		B183
rw 		B182
rw 		B181
rw 		B180
rw 		B179
rw 		B178
rw 		B177
rw 		B176
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B175
rw 		B174
rw 		B173
rw 		B172
rw 		B171
rw 		B170
rw 		B169
rw 		B168
rw 		B167
rw 		B166
rw 		B165
rw 		B164
rw 		B163
rw 		B162
rw 		B161
rw 		B160
rw
Toggle fields

B160

Bit 0: B160.

B161

Bit 1: B161.

B162

Bit 2: B162.

B163

Bit 3: B163.

B164

Bit 4: B164.

B165

Bit 5: B165.

B166

Bit 6: B166.

B167

Bit 7: B167.

B168

Bit 8: B168.

B169

Bit 9: B169.

B170

Bit 10: B170.

B171

Bit 11: B171.

B172

Bit 12: B172.

B173

Bit 13: B173.

B174

Bit 14: B174.

B175

Bit 15: B175.

B176

Bit 16: B176.

B177

Bit 17: B177.

B178

Bit 18: B178.

B179

Bit 19: B179.

B180

Bit 20: B180.

B181

Bit 21: B181.

B182

Bit 22: B182.

B183

Bit 23: B183.

B184

Bit 24: B184.

B185

Bit 25: B185.

B186

Bit 26: B186.

B187

Bit 27: B187.

B188

Bit 28: B188.

B189

Bit 29: B189.

B190

Bit 30: B190.

B191

Bit 31: B191.

VCTR6

MPCBBx vector register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B223
rw 		B222
rw 		B221
rw 		B220
rw 		B219
rw 		B218
rw 		B217
rw 		B216
rw 		B215
rw 		B214
rw 		B213
rw 		B212
rw 		B211
rw 		B210
rw 		B209
rw 		B208
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B207
rw 		B206
rw 		B205
rw 		B204
rw 		B203
rw 		B202
rw 		B201
rw 		B200
rw 		B199
rw 		B198
rw 		B197
rw 		B196
rw 		B195
rw 		B194
rw 		B193
rw 		B192
rw
Toggle fields

B192

Bit 0: B192.

B193

Bit 1: B193.

B194

Bit 2: B194.

B195

Bit 3: B195.

B196

Bit 4: B196.

B197

Bit 5: B197.

B198

Bit 6: B198.

B199

Bit 7: B199.

B200

Bit 8: B200.

B201

Bit 9: B201.

B202

Bit 10: B202.

B203

Bit 11: B203.

B204

Bit 12: B204.

B205

Bit 13: B205.

B206

Bit 14: B206.

B207

Bit 15: B207.

B208

Bit 16: B208.

B209

Bit 17: B209.

B210

Bit 18: B210.

B211

Bit 19: B211.

B212

Bit 20: B212.

B213

Bit 21: B213.

B214

Bit 22: B214.

B215

Bit 23: B215.

B216

Bit 24: B216.

B217

Bit 25: B217.

B218

Bit 26: B218.

B219

Bit 27: B219.

B220

Bit 28: B220.

B221

Bit 29: B221.

B222

Bit 30: B222.

B223

Bit 31: B223.

VCTR7

MPCBBx vector register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B255
rw 		B254
rw 		B253
rw 		B252
rw 		B251
rw 		B250
rw 		B249
rw 		B248
rw 		B247
rw 		B246
rw 		B245
rw 		B244
rw 		B243
rw 		B242
rw 		B241
rw 		B240
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B239
rw 		B238
rw 		B237
rw 		B236
rw 		B235
rw 		B234
rw 		B233
rw 		B232
rw 		B231
rw 		B230
rw 		B229
rw 		B228
rw 		B227
rw 		B226
rw 		B225
rw 		B224
rw
Toggle fields

B224

Bit 0: B224.

B225

Bit 1: B225.

B226

Bit 2: B226.

B227

Bit 3: B227.

B228

Bit 4: B228.

B229

Bit 5: B229.

B230

Bit 6: B230.

B231

Bit 7: B231.

B232

Bit 8: B232.

B233

Bit 9: B233.

B234

Bit 10: B234.

B235

Bit 11: B235.

B236

Bit 12: B236.

B237

Bit 13: B237.

B238

Bit 14: B238.

B239

Bit 15: B239.

B240

Bit 16: B240.

B241

Bit 17: B241.

B242

Bit 18: B242.

B243

Bit 19: B243.

B244

Bit 20: B244.

B245

Bit 21: B245.

B246

Bit 22: B246.

B247

Bit 23: B247.

B248

Bit 24: B248.

B249

Bit 25: B249.

B250

Bit 26: B250.

B251

Bit 27: B251.

B252

Bit 28: B252.

B253

Bit 29: B253.

B254

Bit 30: B254.

B255

Bit 31: B255.

VCTR8

MPCBBx vector register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B287
rw 		B286
rw 		B285
rw 		B284
rw 		B283
rw 		B282
rw 		B281
rw 		B280
rw 		B279
rw 		B278
rw 		B277
rw 		B276
rw 		B275
rw 		B274
rw 		B273
rw 		B272
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B271
rw 		B270
rw 		B269
rw 		B268
rw 		B267
rw 		B266
rw 		B265
rw 		B264
rw 		B263
rw 		B262
rw 		B261
rw 		B260
rw 		B259
rw 		B258
rw 		B257
rw 		B256
rw
Toggle fields

B256

Bit 0: B256.

B257

Bit 1: B257.

B258

Bit 2: B258.

B259

Bit 3: B259.

B260

Bit 4: B260.

B261

Bit 5: B261.

B262

Bit 6: B262.

B263

Bit 7: B263.

B264

Bit 8: B264.

B265

Bit 9: B265.

B266

Bit 10: B266.

B267

Bit 11: B267.

B268

Bit 12: B268.

B269

Bit 13: B269.

B270

Bit 14: B270.

B271

Bit 15: B271.

B272

Bit 16: B272.

B273

Bit 17: B273.

B274

Bit 18: B274.

B275

Bit 19: B275.

B276

Bit 20: B276.

B277

Bit 21: B277.

B278

Bit 22: B278.

B279

Bit 23: B279.

B280

Bit 24: B280.

B281

Bit 25: B281.

B282

Bit 26: B282.

B283

Bit 27: B283.

B284

Bit 28: B284.

B285

Bit 29: B285.

B286

Bit 30: B286.

B287

Bit 31: B287.

VCTR9

MPCBBx vector register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B319
rw 		B318
rw 		B317
rw 		B316
rw 		B315
rw 		B314
rw 		B313
rw 		B312
rw 		B311
rw 		B310
rw 		B309
rw 		B308
rw 		B307
rw 		B306
rw 		B305
rw 		B304
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B303
rw 		B302
rw 		B301
rw 		B300
rw 		B299
rw 		B298
rw 		B297
rw 		B296
rw 		B295
rw 		B294
rw 		B293
rw 		B292
rw 		B291
rw 		B290
rw 		B289
rw 		B288
rw
Toggle fields

B288

Bit 0: B288.

B289

Bit 1: B289.

B290

Bit 2: B290.

B291

Bit 3: B291.

B292

Bit 4: B292.

B293

Bit 5: B293.

B294

Bit 6: B294.

B295

Bit 7: B295.

B296

Bit 8: B296.

B297

Bit 9: B297.

B298

Bit 10: B298.

B299

Bit 11: B299.

B300

Bit 12: B300.

B301

Bit 13: B301.

B302

Bit 14: B302.

B303

Bit 15: B303.

B304

Bit 16: B304.

B305

Bit 17: B305.

B306

Bit 18: B306.

B307

Bit 19: B307.

B308

Bit 20: B308.

B309

Bit 21: B309.

B310

Bit 22: B310.

B311

Bit 23: B311.

B312

Bit 24: B312.

B313

Bit 25: B313.

B314

Bit 26: B314.

B315

Bit 27: B315.

B316

Bit 28: B316.

B317

Bit 29: B317.

B318

Bit 30: B318.

B319

Bit 31: B319.

VCTR10

MPCBBx vector register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B351
rw 		B350
rw 		B349
rw 		B348
rw 		B347
rw 		B346
rw 		B345
rw 		B344
rw 		B343
rw 		B342
rw 		B341
rw 		B340
rw 		B339
rw 		B338
rw 		B337
rw 		B336
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B335
rw 		B334
rw 		B333
rw 		B332
rw 		B331
rw 		B330
rw 		B329
rw 		B328
rw 		B327
rw 		B326
rw 		B325
rw 		B324
rw 		B323
rw 		B322
rw 		B321
rw 		B320
rw
Toggle fields

B320

Bit 0: B320.

B321

Bit 1: B321.

B322

Bit 2: B322.

B323

Bit 3: B323.

B324

Bit 4: B324.

B325

Bit 5: B325.

B326

Bit 6: B326.

B327

Bit 7: B327.

B328

Bit 8: B328.

B329

Bit 9: B329.

B330

Bit 10: B330.

B331

Bit 11: B331.

B332

Bit 12: B332.

B333

Bit 13: B333.

B334

Bit 14: B334.

B335

Bit 15: B335.

B336

Bit 16: B336.

B337

Bit 17: B337.

B338

Bit 18: B338.

B339

Bit 19: B339.

B340

Bit 20: B340.

B341

Bit 21: B341.

B342

Bit 22: B342.

B343

Bit 23: B343.

B344

Bit 24: B344.

B345

Bit 25: B345.

B346

Bit 26: B346.

B347

Bit 27: B347.

B348

Bit 28: B348.

B349

Bit 29: B349.

B350

Bit 30: B350.

B351

Bit 31: B351.

VCTR11

MPCBBx vector register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B383
rw 		B382
rw 		B381
rw 		B380
rw 		B379
rw 		B378
rw 		B377
rw 		B376
rw 		B375
rw 		B374
rw 		B373
rw 		B372
rw 		B371
rw 		B370
rw 		B369
rw 		B368
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B367
rw 		B366
rw 		B365
rw 		B364
rw 		B363
rw 		B362
rw 		B361
rw 		B360
rw 		B359
rw 		B358
rw 		B357
rw 		B356
rw 		B355
rw 		B354
rw 		B353
rw 		B352
rw
Toggle fields

B352

Bit 0: B352.

B353

Bit 1: B353.

B354

Bit 2: B354.

B355

Bit 3: B355.

B356

Bit 4: B356.

B357

Bit 5: B357.

B358

Bit 6: B358.

B359

Bit 7: B359.

B360

Bit 8: B360.

B361

Bit 9: B361.

B362

Bit 10: B362.

B363

Bit 11: B363.

B364

Bit 12: B364.

B365

Bit 13: B365.

B366

Bit 14: B366.

B367

Bit 15: B367.

B368

Bit 16: B368.

B369

Bit 17: B369.

B370

Bit 18: B370.

B371

Bit 19: B371.

B372

Bit 20: B372.

B373

Bit 21: B373.

B374

Bit 22: B374.

B375

Bit 23: B375.

B376

Bit 24: B376.

B377

Bit 25: B377.

B378

Bit 26: B378.

B379

Bit 27: B379.

B380

Bit 28: B380.

B381

Bit 29: B381.

B382

Bit 30: B382.

B383

Bit 31: B383.

VCTR12

MPCBBx vector register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B415
rw 		B414
rw 		B413
rw 		B412
rw 		B411
rw 		B410
rw 		B409
rw 		B408
rw 		B407
rw 		B406
rw 		B405
rw 		B404
rw 		B403
rw 		B402
rw 		B401
rw 		B400
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B399
rw 		B398
rw 		B397
rw 		B396
rw 		B395
rw 		B394
rw 		B393
rw 		B392
rw 		B391
rw 		B390
rw 		B389
rw 		B388
rw 		B387
rw 		B386
rw 		B385
rw 		B384
rw
Toggle fields

B384

Bit 0: B384.

B385

Bit 1: B385.

B386

Bit 2: B386.

B387

Bit 3: B387.

B388

Bit 4: B388.

B389

Bit 5: B389.

B390

Bit 6: B390.

B391

Bit 7: B391.

B392

Bit 8: B392.

B393

Bit 9: B393.

B394

Bit 10: B394.

B395

Bit 11: B395.

B396

Bit 12: B396.

B397

Bit 13: B397.

B398

Bit 14: B398.

B399

Bit 15: B399.

B400

Bit 16: B400.

B401

Bit 17: B401.

B402

Bit 18: B402.

B403

Bit 19: B403.

B404

Bit 20: B404.

B405

Bit 21: B405.

B406

Bit 22: B406.

B407

Bit 23: B407.

B408

Bit 24: B408.

B409

Bit 25: B409.

B410

Bit 26: B410.

B411

Bit 27: B411.

B412

Bit 28: B412.

B413

Bit 29: B413.

B414

Bit 30: B414.

B415

Bit 31: B415.

VCTR13

MPCBBx vector register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B447
rw 		B446
rw 		B445
rw 		B444
rw 		B443
rw 		B442
rw 		B441
rw 		B440
rw 		B439
rw 		B438
rw 		B437
rw 		B436
rw 		B435
rw 		B434
rw 		B433
rw 		B432
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B431
rw 		B430
rw 		B429
rw 		B428
rw 		B427
rw 		B426
rw 		B425
rw 		B424
rw 		B423
rw 		B422
rw 		B421
rw 		B420
rw 		B419
rw 		B418
rw 		B417
rw 		B416
rw
Toggle fields

B416

Bit 0: B416.

B417

Bit 1: B417.

B418

Bit 2: B418.

B419

Bit 3: B419.

B420

Bit 4: B420.

B421

Bit 5: B421.

B422

Bit 6: B422.

B423

Bit 7: B423.

B424

Bit 8: B424.

B425

Bit 9: B425.

B426

Bit 10: B426.

B427

Bit 11: B427.

B428

Bit 12: B428.

B429

Bit 13: B429.

B430

Bit 14: B430.

B431

Bit 15: B431.

B432

Bit 16: B432.

B433

Bit 17: B433.

B434

Bit 18: B434.

B435

Bit 19: B435.

B436

Bit 20: B436.

B437

Bit 21: B437.

B438

Bit 22: B438.

B439

Bit 23: B439.

B440

Bit 24: B440.

B441

Bit 25: B441.

B442

Bit 26: B442.

B443

Bit 27: B443.

B444

Bit 28: B444.

B445

Bit 29: B445.

B446

Bit 30: B446.

B447

Bit 31: B447.

VCTR14

MPCBBx vector register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B479
rw 		B478
rw 		B477
rw 		B476
rw 		B475
rw 		B474
rw 		B473
rw 		B472
rw 		B471
rw 		B470
rw 		B469
rw 		B468
rw 		B467
rw 		B466
rw 		B465
rw 		B464
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B463
rw 		B462
rw 		B461
rw 		B460
rw 		B459
rw 		B458
rw 		B457
rw 		B456
rw 		B455
rw 		B454
rw 		B453
rw 		B452
rw 		B451
rw 		B450
rw 		B449
rw 		B448
rw
Toggle fields

B448

Bit 0: B448.

B449

Bit 1: B449.

B450

Bit 2: B450.

B451

Bit 3: B451.

B452

Bit 4: B452.

B453

Bit 5: B453.

B454

Bit 6: B454.

B455

Bit 7: B455.

B456

Bit 8: B456.

B457

Bit 9: B457.

B458

Bit 10: B458.

B459

Bit 11: B459.

B460

Bit 12: B460.

B461

Bit 13: B461.

B462

Bit 14: B462.

B463

Bit 15: B463.

B464

Bit 16: B464.

B465

Bit 17: B465.

B466

Bit 18: B466.

B467

Bit 19: B467.

B468

Bit 20: B468.

B469

Bit 21: B469.

B470

Bit 22: B470.

B471

Bit 23: B471.

B472

Bit 24: B472.

B473

Bit 25: B473.

B474

Bit 26: B474.

B475

Bit 27: B475.

B476

Bit 28: B476.

B477

Bit 29: B477.

B478

Bit 30: B478.

B479

Bit 31: B479.

VCTR15

MPCBBx vector register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B511
rw 		B510
rw 		B509
rw 		B508
rw 		B507
rw 		B506
rw 		B505
rw 		B504
rw 		B503
rw 		B502
rw 		B501
rw 		B500
rw 		B499
rw 		B498
rw 		B497
rw 		B496
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B495
rw 		B494
rw 		B493
rw 		B492
rw 		B491
rw 		B490
rw 		B489
rw 		B488
rw 		B487
rw 		B486
rw 		B485
rw 		B484
rw 		B483
rw 		B482
rw 		B481
rw 		B480
rw
Toggle fields

B480

Bit 0: B480.

B481

Bit 1: B481.

B482

Bit 2: B482.

B483

Bit 3: B483.

B484

Bit 4: B484.

B485

Bit 5: B485.

B486

Bit 6: B486.

B487

Bit 7: B487.

B488

Bit 8: B488.

B489

Bit 9: B489.

B490

Bit 10: B490.

B491

Bit 11: B491.

B492

Bit 12: B492.

B493

Bit 13: B493.

B494

Bit 14: B494.

B495

Bit 15: B495.

B496

Bit 16: B496.

B497

Bit 17: B497.

B498

Bit 18: B498.

B499

Bit 19: B499.

B500

Bit 20: B500.

B501

Bit 21: B501.

B502

Bit 22: B502.

B503

Bit 23: B503.

B504

Bit 24: B504.

B505

Bit 25: B505.

B506

Bit 26: B506.

B507

Bit 27: B507.

B508

Bit 28: B508.

B509

Bit 29: B509.

B510

Bit 30: B510.

B511

Bit 31: B511.

VCTR16

MPCBBx vector register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B543
rw 		B542
rw 		B541
rw 		B540
rw 		B539
rw 		B538
rw 		B537
rw 		B536
rw 		B535
rw 		B534
rw 		B533
rw 		B532
rw 		B531
rw 		B530
rw 		B529
rw 		B528
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B527
rw 		B526
rw 		B525
rw 		B524
rw 		B523
rw 		B522
rw 		B521
rw 		B520
rw 		B519
rw 		B518
rw 		B517
rw 		B516
rw 		B515
rw 		B514
rw 		B513
rw 		B512
rw
Toggle fields

B512

Bit 0: B512.

B513

Bit 1: B513.

B514

Bit 2: B514.

B515

Bit 3: B515.

B516

Bit 4: B516.

B517

Bit 5: B517.

B518

Bit 6: B518.

B519

Bit 7: B519.

B520

Bit 8: B520.

B521

Bit 9: B521.

B522

Bit 10: B522.

B523

Bit 11: B523.

B524

Bit 12: B524.

B525

Bit 13: B525.

B526

Bit 14: B526.

B527

Bit 15: B527.

B528

Bit 16: B528.

B529

Bit 17: B529.

B530

Bit 18: B530.

B531

Bit 19: B531.

B532

Bit 20: B532.

B533

Bit 21: B533.

B534

Bit 22: B534.

B535

Bit 23: B535.

B536

Bit 24: B536.

B537

Bit 25: B537.

B538

Bit 26: B538.

B539

Bit 27: B539.

B540

Bit 28: B540.

B541

Bit 29: B541.

B542

Bit 30: B542.

B543

Bit 31: B543.

VCTR17

MPCBBx vector register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B575
rw 		B574
rw 		B573
rw 		B572
rw 		B571
rw 		B570
rw 		B569
rw 		B568
rw 		B567
rw 		B566
rw 		B565
rw 		B564
rw 		B563
rw 		B562
rw 		B561
rw 		B560
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B559
rw 		B558
rw 		B557
rw 		B556
rw 		B555
rw 		B554
rw 		B553
rw 		B552
rw 		B551
rw 		B550
rw 		B549
rw 		B548
rw 		B547
rw 		B546
rw 		B545
rw 		B544
rw
Toggle fields

B544

Bit 0: B544.

B545

Bit 1: B545.

B546

Bit 2: B546.

B547

Bit 3: B547.

B548

Bit 4: B548.

B549

Bit 5: B549.

B550

Bit 6: B550.

B551

Bit 7: B551.

B552

Bit 8: B552.

B553

Bit 9: B553.

B554

Bit 10: B554.

B555

Bit 11: B555.

B556

Bit 12: B556.

B557

Bit 13: B557.

B558

Bit 14: B558.

B559

Bit 15: B559.

B560

Bit 16: B560.

B561

Bit 17: B561.

B562

Bit 18: B562.

B563

Bit 19: B563.

B564

Bit 20: B564.

B565

Bit 21: B565.

B566

Bit 22: B566.

B567

Bit 23: B567.

B568

Bit 24: B568.

B569

Bit 25: B569.

B570

Bit 26: B570.

B571

Bit 27: B571.

B572

Bit 28: B572.

B573

Bit 29: B573.

B574

Bit 30: B574.

B575

Bit 31: B575.

VCTR18

MPCBBx vector register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B607
rw 		B606
rw 		B605
rw 		B604
rw 		B603
rw 		B602
rw 		B601
rw 		B600
rw 		B599
rw 		B598
rw 		B597
rw 		B596
rw 		B595
rw 		B594
rw 		B593
rw 		B592
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B591
rw 		B590
rw 		B589
rw 		B588
rw 		B587
rw 		B586
rw 		B585
rw 		B584
rw 		B583
rw 		B582
rw 		B581
rw 		B580
rw 		B579
rw 		B578
rw 		B577
rw 		B576
rw
Toggle fields

B576

Bit 0: B576.

B577

Bit 1: B577.

B578

Bit 2: B578.

B579

Bit 3: B579.

B580

Bit 4: B580.

B581

Bit 5: B581.

B582

Bit 6: B582.

B583

Bit 7: B583.

B584

Bit 8: B584.

B585

Bit 9: B585.

B586

Bit 10: B586.

B587

Bit 11: B587.

B588

Bit 12: B588.

B589

Bit 13: B589.

B590

Bit 14: B590.

B591

Bit 15: B591.

B592

Bit 16: B592.

B593

Bit 17: B593.

B594

Bit 18: B594.

B595

Bit 19: B595.

B596

Bit 20: B596.

B597

Bit 21: B597.

B598

Bit 22: B598.

B599

Bit 23: B599.

B600

Bit 24: B600.

B601

Bit 25: B601.

B602

Bit 26: B602.

B603

Bit 27: B603.

B604

Bit 28: B604.

B605

Bit 29: B605.

B606

Bit 30: B606.

B607

Bit 31: B607.

VCTR19

MPCBBx vector register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B639
rw 		B638
rw 		B637
rw 		B636
rw 		B635
rw 		B634
rw 		B633
rw 		B632
rw 		B631
rw 		B630
rw 		B629
rw 		B628
rw 		B627
rw 		B626
rw 		B625
rw 		B624
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B623
rw 		B622
rw 		B621
rw 		B620
rw 		B619
rw 		B618
rw 		B617
rw 		B616
rw 		B615
rw 		B614
rw 		B613
rw 		B612
rw 		B611
rw 		B610
rw 		B609
rw 		B608
rw
Toggle fields

B608

Bit 0: B608.

B609

Bit 1: B609.

B610

Bit 2: B610.

B611

Bit 3: B611.

B612

Bit 4: B612.

B613

Bit 5: B613.

B614

Bit 6: B614.

B615

Bit 7: B615.

B616

Bit 8: B616.

B617

Bit 9: B617.

B618

Bit 10: B618.

B619

Bit 11: B619.

B620

Bit 12: B620.

B621

Bit 13: B621.

B622

Bit 14: B622.

B623

Bit 15: B623.

B624

Bit 16: B624.

B625

Bit 17: B625.

B626

Bit 18: B626.

B627

Bit 19: B627.

B628

Bit 20: B628.

B629

Bit 21: B629.

B630

Bit 22: B630.

B631

Bit 23: B631.

B632

Bit 24: B632.

B633

Bit 25: B633.

B634

Bit 26: B634.

B635

Bit 27: B635.

B636

Bit 28: B636.

B637

Bit 29: B637.

B638

Bit 30: B638.

B639

Bit 31: B639.

VCTR20

MPCBBx vector register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B671
rw 		B670
rw 		B669
rw 		B668
rw 		B667
rw 		B666
rw 		B665
rw 		B664
rw 		B663
rw 		B662
rw 		B661
rw 		B660
rw 		B659
rw 		B658
rw 		B657
rw 		B656
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B655
rw 		B654
rw 		B653
rw 		B652
rw 		B651
rw 		B650
rw 		B649
rw 		B648
rw 		B647
rw 		B646
rw 		B645
rw 		B644
rw 		B643
rw 		B642
rw 		B641
rw 		B640
rw
Toggle fields

B640

Bit 0: B640.

B641

Bit 1: B641.

B642

Bit 2: B642.

B643

Bit 3: B643.

B644

Bit 4: B644.

B645

Bit 5: B645.

B646

Bit 6: B646.

B647

Bit 7: B647.

B648

Bit 8: B648.

B649

Bit 9: B649.

B650

Bit 10: B650.

B651

Bit 11: B651.

B652

Bit 12: B652.

B653

Bit 13: B653.

B654

Bit 14: B654.

B655

Bit 15: B655.

B656

Bit 16: B656.

B657

Bit 17: B657.

B658

Bit 18: B658.

B659

Bit 19: B659.

B660

Bit 20: B660.

B661

Bit 21: B661.

B662

Bit 22: B662.

B663

Bit 23: B663.

B664

Bit 24: B664.

B665

Bit 25: B665.

B666

Bit 26: B666.

B667

Bit 27: B667.

B668

Bit 28: B668.

B669

Bit 29: B669.

B670

Bit 30: B670.

B671

Bit 31: B671.

VCTR21

MPCBBx vector register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B703
rw 		B702
rw 		B701
rw 		B700
rw 		B699
rw 		B698
rw 		B697
rw 		B696
rw 		B695
rw 		B694
rw 		B693
rw 		B692
rw 		B691
rw 		B690
rw 		B689
rw 		B688
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B687
rw 		B686
rw 		B685
rw 		B684
rw 		B683
rw 		B682
rw 		B681
rw 		B680
rw 		B679
rw 		B678
rw 		B677
rw 		B676
rw 		B675
rw 		B674
rw 		B673
rw 		B672
rw
Toggle fields

B672

Bit 0: B672.

B673

Bit 1: B673.

B674

Bit 2: B674.

B675

Bit 3: B675.

B676

Bit 4: B676.

B677

Bit 5: B677.

B678

Bit 6: B678.

B679

Bit 7: B679.

B680

Bit 8: B680.

B681

Bit 9: B681.

B682

Bit 10: B682.

B683

Bit 11: B683.

B684

Bit 12: B684.

B685

Bit 13: B685.

B686

Bit 14: B686.

B687

Bit 15: B687.

B688

Bit 16: B688.

B689

Bit 17: B689.

B690

Bit 18: B690.

B691

Bit 19: B691.

B692

Bit 20: B692.

B693

Bit 21: B693.

B694

Bit 22: B694.

B695

Bit 23: B695.

B696

Bit 24: B696.

B697

Bit 25: B697.

B698

Bit 26: B698.

B699

Bit 27: B699.

B700

Bit 28: B700.

B701

Bit 29: B701.

B702

Bit 30: B702.

B703

Bit 31: B703.

VCTR22

MPCBBx vector register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B735
rw 		B734
rw 		B733
rw 		B732
rw 		B731
rw 		B730
rw 		B729
rw 		B728
rw 		B727
rw 		B726
rw 		B725
rw 		B724
rw 		B723
rw 		B722
rw 		B721
rw 		B720
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B719
rw 		B718
rw 		B717
rw 		B716
rw 		B715
rw 		B714
rw 		B713
rw 		B712
rw 		B711
rw 		B710
rw 		B709
rw 		B708
rw 		B707
rw 		B706
rw 		B705
rw 		B704
rw
Toggle fields

B704

Bit 0: B704.

B705

Bit 1: B705.

B706

Bit 2: B706.

B707

Bit 3: B707.

B708

Bit 4: B708.

B709

Bit 5: B709.

B710

Bit 6: B710.

B711

Bit 7: B711.

B712

Bit 8: B712.

B713

Bit 9: B713.

B714

Bit 10: B714.

B715

Bit 11: B715.

B716

Bit 12: B716.

B717

Bit 13: B717.

B718

Bit 14: B718.

B719

Bit 15: B719.

B720

Bit 16: B720.

B721

Bit 17: B721.

B722

Bit 18: B722.

B723

Bit 19: B723.

B724

Bit 20: B724.

B725

Bit 21: B725.

B726

Bit 22: B726.

B727

Bit 23: B727.

B728

Bit 24: B728.

B729

Bit 25: B729.

B730

Bit 26: B730.

B731

Bit 27: B731.

B732

Bit 28: B732.

B733

Bit 29: B733.

B734

Bit 30: B734.

B735

Bit 31: B735.

VCTR23

MPCBBx vector register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B767
rw 		B766
rw 		B765
rw 		B764
rw 		B763
rw 		B762
rw 		B761
rw 		B760
rw 		B759
rw 		B758
rw 		B757
rw 		B756
rw 		B755
rw 		B754
rw 		B753
rw 		B752
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B751
rw 		B750
rw 		B749
rw 		B748
rw 		B747
rw 		B746
rw 		B745
rw 		B744
rw 		B743
rw 		B742
rw 		B741
rw 		B740
rw 		B739
rw 		B738
rw 		B737
rw 		B736
rw
Toggle fields

B736

Bit 0: B736.

B737

Bit 1: B737.

B738

Bit 2: B738.

B739

Bit 3: B739.

B740

Bit 4: B740.

B741

Bit 5: B741.

B742

Bit 6: B742.

B743

Bit 7: B743.

B744

Bit 8: B744.

B745

Bit 9: B745.

B746

Bit 10: B746.

B747

Bit 11: B747.

B748

Bit 12: B748.

B749

Bit 13: B749.

B750

Bit 14: B750.

B751

Bit 15: B751.

B752

Bit 16: B752.

B753

Bit 17: B753.

B754

Bit 18: B754.

B755

Bit 19: B755.

B756

Bit 20: B756.

B757

Bit 21: B757.

B758

Bit 22: B758.

B759

Bit 23: B759.

B760

Bit 24: B760.

B761

Bit 25: B761.

B762

Bit 26: B762.

B763

Bit 27: B763.

B764

Bit 28: B764.

B765

Bit 29: B765.

B766

Bit 30: B766.

B767

Bit 31: B767.

VCTR24

MPCBBx vector register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B799
rw 		B798
rw 		B797
rw 		B796
rw 		B795
rw 		B794
rw 		B793
rw 		B792
rw 		B791
rw 		B790
rw 		B789
rw 		B788
rw 		B787
rw 		B786
rw 		B785
rw 		B784
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B783
rw 		B782
rw 		B781
rw 		B780
rw 		B779
rw 		B778
rw 		B777
rw 		B776
rw 		B775
rw 		B774
rw 		B773
rw 		B772
rw 		B771
rw 		B770
rw 		B769
rw 		B768
rw
Toggle fields

B768

Bit 0: B768.

B769

Bit 1: B769.

B770

Bit 2: B770.

B771

Bit 3: B771.

B772

Bit 4: B772.

B773

Bit 5: B773.

B774

Bit 6: B774.

B775

Bit 7: B775.

B776

Bit 8: B776.

B777

Bit 9: B777.

B778

Bit 10: B778.

B779

Bit 11: B779.

B780

Bit 12: B780.

B781

Bit 13: B781.

B782

Bit 14: B782.

B783

Bit 15: B783.

B784

Bit 16: B784.

B785

Bit 17: B785.

B786

Bit 18: B786.

B787

Bit 19: B787.

B788

Bit 20: B788.

B789

Bit 21: B789.

B790

Bit 22: B790.

B791

Bit 23: B791.

B792

Bit 24: B792.

B793

Bit 25: B793.

B794

Bit 26: B794.

B795

Bit 27: B795.

B796

Bit 28: B796.

B797

Bit 29: B797.

B798

Bit 30: B798.

B799

Bit 31: B799.

VCTR25

MPCBBx vector register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B831
rw 		B830
rw 		B829
rw 		B828
rw 		B827
rw 		B826
rw 		B825
rw 		B824
rw 		B823
rw 		B822
rw 		B821
rw 		B820
rw 		B819
rw 		B818
rw 		B817
rw 		B816
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B815
rw 		B814
rw 		B813
rw 		B812
rw 		B811
rw 		B810
rw 		B809
rw 		B808
rw 		B807
rw 		B806
rw 		B805
rw 		B804
rw 		B803
rw 		B802
rw 		B801
rw 		B800
rw
Toggle fields

B800

Bit 0: B800.

B801

Bit 1: B801.

B802

Bit 2: B802.

B803

Bit 3: B803.

B804

Bit 4: B804.

B805

Bit 5: B805.

B806

Bit 6: B806.

B807

Bit 7: B807.

B808

Bit 8: B808.

B809

Bit 9: B809.

B810

Bit 10: B810.

B811

Bit 11: B811.

B812

Bit 12: B812.

B813

Bit 13: B813.

B814

Bit 14: B814.

B815

Bit 15: B815.

B816

Bit 16: B816.

B817

Bit 17: B817.

B818

Bit 18: B818.

B819

Bit 19: B819.

B820

Bit 20: B820.

B821

Bit 21: B821.

B822

Bit 22: B822.

B823

Bit 23: B823.

B824

Bit 24: B824.

B825

Bit 25: B825.

B826

Bit 26: B826.

B827

Bit 27: B827.

B828

Bit 28: B828.

B829

Bit 29: B829.

B830

Bit 30: B830.

B831

Bit 31: B831.

VCTR26

MPCBBx vector register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B863
rw 		B862
rw 		B861
rw 		B860
rw 		B859
rw 		B858
rw 		B857
rw 		B856
rw 		B855
rw 		B854
rw 		B853
rw 		B852
rw 		B851
rw 		B850
rw 		B849
rw 		B848
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B847
rw 		B846
rw 		B845
rw 		B844
rw 		B843
rw 		B842
rw 		B841
rw 		B840
rw 		B839
rw 		B838
rw 		B837
rw 		B836
rw 		B835
rw 		B834
rw 		B833
rw 		B832
rw
Toggle fields

B832

Bit 0: B832.

B833

Bit 1: B833.

B834

Bit 2: B834.

B835

Bit 3: B835.

B836

Bit 4: B836.

B837

Bit 5: B837.

B838

Bit 6: B838.

B839

Bit 7: B839.

B840

Bit 8: B840.

B841

Bit 9: B841.

B842

Bit 10: B842.

B843

Bit 11: B843.

B844

Bit 12: B844.

B845

Bit 13: B845.

B846

Bit 14: B846.

B847

Bit 15: B847.

B848

Bit 16: B848.

B849

Bit 17: B849.

B850

Bit 18: B850.

B851

Bit 19: B851.

B852

Bit 20: B852.

B853

Bit 21: B853.

B854

Bit 22: B854.

B855

Bit 23: B855.

B856

Bit 24: B856.

B857

Bit 25: B857.

B858

Bit 26: B858.

B859

Bit 27: B859.

B860

Bit 28: B860.

B861

Bit 29: B861.

B862

Bit 30: B862.

B863

Bit 31: B863.

VCTR27

MPCBBx vector register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B895
rw 		B894
rw 		B893
rw 		B892
rw 		B891
rw 		B890
rw 		B889
rw 		B888
rw 		B887
rw 		B886
rw 		B885
rw 		B884
rw 		B883
rw 		B882
rw 		B881
rw 		B880
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B879
rw 		B878
rw 		B877
rw 		B876
rw 		B875
rw 		B874
rw 		B873
rw 		B872
rw 		B871
rw 		B870
rw 		B869
rw 		B868
rw 		B867
rw 		B866
rw 		B865
rw 		B864
rw
Toggle fields

B864

Bit 0: B864.

B865

Bit 1: B865.

B866

Bit 2: B866.

B867

Bit 3: B867.

B868

Bit 4: B868.

B869

Bit 5: B869.

B870

Bit 6: B870.

B871

Bit 7: B871.

B872

Bit 8: B872.

B873

Bit 9: B873.

B874

Bit 10: B874.

B875

Bit 11: B875.

B876

Bit 12: B876.

B877

Bit 13: B877.

B878

Bit 14: B878.

B879

Bit 15: B879.

B880

Bit 16: B880.

B881

Bit 17: B881.

B882

Bit 18: B882.

B883

Bit 19: B883.

B884

Bit 20: B884.

B885

Bit 21: B885.

B886

Bit 22: B886.

B887

Bit 23: B887.

B888

Bit 24: B888.

B889

Bit 25: B889.

B890

Bit 26: B890.

B891

Bit 27: B891.

B892

Bit 28: B892.

B893

Bit 29: B893.

B894

Bit 30: B894.

B895

Bit 31: B895.

VCTR28

MPCBBx vector register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B927
rw 		B926
rw 		B925
rw 		B924
rw 		B923
rw 		B922
rw 		B921
rw 		B920
rw 		B919
rw 		B918
rw 		B917
rw 		B916
rw 		B915
rw 		B914
rw 		B913
rw 		B912
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B911
rw 		B910
rw 		B909
rw 		B908
rw 		B907
rw 		B906
rw 		B905
rw 		B904
rw 		B903
rw 		B902
rw 		B901
rw 		B900
rw 		B899
rw 		B898
rw 		B897
rw 		B896
rw
Toggle fields

B896

Bit 0: B896.

B897

Bit 1: B897.

B898

Bit 2: B898.

B899

Bit 3: B899.

B900

Bit 4: B900.

B901

Bit 5: B901.

B902

Bit 6: B902.

B903

Bit 7: B903.

B904

Bit 8: B904.

B905

Bit 9: B905.

B906

Bit 10: B906.

B907

Bit 11: B907.

B908

Bit 12: B908.

B909

Bit 13: B909.

B910

Bit 14: B910.

B911

Bit 15: B911.

B912

Bit 16: B912.

B913

Bit 17: B913.

B914

Bit 18: B914.

B915

Bit 19: B915.

B916

Bit 20: B916.

B917

Bit 21: B917.

B918

Bit 22: B918.

B919

Bit 23: B919.

B920

Bit 24: B920.

B921

Bit 25: B921.

B922

Bit 26: B922.

B923

Bit 27: B923.

B924

Bit 28: B924.

B925

Bit 29: B925.

B926

Bit 30: B926.

B927

Bit 31: B927.

VCTR29

MPCBBx vector register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B959
rw 		B958
rw 		B957
rw 		B956
rw 		B955
rw 		B954
rw 		B953
rw 		B952
rw 		B951
rw 		B950
rw 		B949
rw 		B948
rw 		B947
rw 		B946
rw 		B945
rw 		B944
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B943
rw 		B942
rw 		B941
rw 		B940
rw 		B939
rw 		B938
rw 		B937
rw 		B936
rw 		B935
rw 		B934
rw 		B933
rw 		B932
rw 		B931
rw 		B930
rw 		B929
rw 		B928
rw
Toggle fields

B928

Bit 0: B928.

B929

Bit 1: B929.

B930

Bit 2: B930.

B931

Bit 3: B931.

B932

Bit 4: B932.

B933

Bit 5: B933.

B934

Bit 6: B934.

B935

Bit 7: B935.

B936

Bit 8: B936.

B937

Bit 9: B937.

B938

Bit 10: B938.

B939

Bit 11: B939.

B940

Bit 12: B940.

B941

Bit 13: B941.

B942

Bit 14: B942.

B943

Bit 15: B943.

B944

Bit 16: B944.

B945

Bit 17: B945.

B946

Bit 18: B946.

B947

Bit 19: B947.

B948

Bit 20: B948.

B949

Bit 21: B949.

B950

Bit 22: B950.

B951

Bit 23: B951.

B952

Bit 24: B952.

B953

Bit 25: B953.

B954

Bit 26: B954.

B955

Bit 27: B955.

B956

Bit 28: B956.

B957

Bit 29: B957.

B958

Bit 30: B958.

B959

Bit 31: B959.

VCTR30

MPCBBx vector register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B991
rw 		B990
rw 		B989
rw 		B988
rw 		B987
rw 		B986
rw 		B985
rw 		B984
rw 		B983
rw 		B982
rw 		B981
rw 		B980
rw 		B979
rw 		B978
rw 		B977
rw 		B976
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B975
rw 		B974
rw 		B973
rw 		B972
rw 		B971
rw 		B970
rw 		B969
rw 		B968
rw 		B967
rw 		B966
rw 		B965
rw 		B964
rw 		B963
rw 		B962
rw 		B961
rw 		B960
rw
Toggle fields

B960

Bit 0: B960.

B961

Bit 1: B961.

B962

Bit 2: B962.

B963

Bit 3: B963.

B964

Bit 4: B964.

B965

Bit 5: B965.

B966

Bit 6: B966.

B967

Bit 7: B967.

B968

Bit 8: B968.

B969

Bit 9: B969.

B970

Bit 10: B970.

B971

Bit 11: B971.

B972

Bit 12: B972.

B973

Bit 13: B973.

B974

Bit 14: B974.

B975

Bit 15: B975.

B976

Bit 16: B976.

B977

Bit 17: B977.

B978

Bit 18: B978.

B979

Bit 19: B979.

B980

Bit 20: B980.

B981

Bit 21: B981.

B982

Bit 22: B982.

B983

Bit 23: B983.

B984

Bit 24: B984.

B985

Bit 25: B985.

B986

Bit 26: B986.

B987

Bit 27: B987.

B988

Bit 28: B988.

B989

Bit 29: B989.

B990

Bit 30: B990.

B991

Bit 31: B991.

VCTR31

MPCBBx vector register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1023
rw 		B1022
rw 		B1021
rw 		B1020
rw 		B1019
rw 		B1018
rw 		B1017
rw 		B1016
rw 		B1015
rw 		B1014
rw 		B1013
rw 		B1012
rw 		B1011
rw 		B1010
rw 		B1009
rw 		B1008
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1007
rw 		B1006
rw 		B1005
rw 		B1004
rw 		B1003
rw 		B1002
rw 		B1001
rw 		B1000
rw 		B999
rw 		B998
rw 		B997
rw 		B996
rw 		B995
rw 		B994
rw 		B993
rw 		B992
rw
Toggle fields

B992

Bit 0: B992.

B993

Bit 1: B993.

B994

Bit 2: B994.

B995

Bit 3: B995.

B996

Bit 4: B996.

B997

Bit 5: B997.

B998

Bit 6: B998.

B999

Bit 7: B999.

B1000

Bit 8: B1000.

B1001

Bit 9: B1001.

B1002

Bit 10: B1002.

B1003

Bit 11: B1003.

B1004

Bit 12: B1004.

B1005

Bit 13: B1005.

B1006

Bit 14: B1006.

B1007

Bit 15: B1007.

B1008

Bit 16: B1008.

B1009

Bit 17: B1009.

B1010

Bit 18: B1010.

B1011

Bit 19: B1011.

B1012

Bit 20: B1012.

B1013

Bit 21: B1013.

B1014

Bit 22: B1014.

B1015

Bit 23: B1015.

B1016

Bit 24: B1016.

B1017

Bit 25: B1017.

B1018

Bit 26: B1018.

B1019

Bit 27: B1019.

B1020

Bit 28: B1020.

B1021

Bit 29: B1021.

B1022

Bit 30: B1022.

B1023

Bit 31: B1023.

VCTR32

MPCBBx vector register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1055
rw 		B1054
rw 		B1053
rw 		B1052
rw 		B1051
rw 		B1050
rw 		B1049
rw 		B1048
rw 		B1047
rw 		B1046
rw 		B1045
rw 		B1044
rw 		B1043
rw 		B1042
rw 		B1041
rw 		B1040
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1039
rw 		B1038
rw 		B1037
rw 		B1036
rw 		B1035
rw 		B1034
rw 		B1033
rw 		B1032
rw 		B1031
rw 		B1030
rw 		B1029
rw 		B1028
rw 		B1027
rw 		B1026
rw 		B1025
rw 		B1024
rw
Toggle fields

B1024

Bit 0: B1024.

B1025

Bit 1: B1025.

B1026

Bit 2: B1026.

B1027

Bit 3: B1027.

B1028

Bit 4: B1028.

B1029

Bit 5: B1029.

B1030

Bit 6: B1030.

B1031

Bit 7: B1031.

B1032

Bit 8: B1032.

B1033

Bit 9: B1033.

B1034

Bit 10: B1034.

B1035

Bit 11: B1035.

B1036

Bit 12: B1036.

B1037

Bit 13: B1037.

B1038

Bit 14: B1038.

B1039

Bit 15: B1039.

B1040

Bit 16: B1040.

B1041

Bit 17: B1041.

B1042

Bit 18: B1042.

B1043

Bit 19: B1043.

B1044

Bit 20: B1044.

B1045

Bit 21: B1045.

B1046

Bit 22: B1046.

B1047

Bit 23: B1047.

B1048

Bit 24: B1048.

B1049

Bit 25: B1049.

B1050

Bit 26: B1050.

B1051

Bit 27: B1051.

B1052

Bit 28: B1052.

B1053

Bit 29: B1053.

B1054

Bit 30: B1054.

B1055

Bit 31: B1055.

VCTR33

MPCBBx vector register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1087
rw 		B1086
rw 		B1085
rw 		B1084
rw 		B1083
rw 		B1082
rw 		B1081
rw 		B1080
rw 		B1079
rw 		B1078
rw 		B1077
rw 		B1076
rw 		B1075
rw 		B1074
rw 		B1073
rw 		B1072
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1071
rw 		B1070
rw 		B1069
rw 		B1068
rw 		B1067
rw 		B1066
rw 		B1065
rw 		B1064
rw 		B1063
rw 		B1062
rw 		B1061
rw 		B1060
rw 		B1059
rw 		B1058
rw 		B1057
rw 		B1056
rw
Toggle fields

B1056

Bit 0: B1056.

B1057

Bit 1: B1057.

B1058

Bit 2: B1058.

B1059

Bit 3: B1059.

B1060

Bit 4: B1060.

B1061

Bit 5: B1061.

B1062

Bit 6: B1062.

B1063

Bit 7: B1063.

B1064

Bit 8: B1064.

B1065

Bit 9: B1065.

B1066

Bit 10: B1066.

B1067

Bit 11: B1067.

B1068

Bit 12: B1068.

B1069

Bit 13: B1069.

B1070

Bit 14: B1070.

B1071

Bit 15: B1071.

B1072

Bit 16: B1072.

B1073

Bit 17: B1073.

B1074

Bit 18: B1074.

B1075

Bit 19: B1075.

B1076

Bit 20: B1076.

B1077

Bit 21: B1077.

B1078

Bit 22: B1078.

B1079

Bit 23: B1079.

B1080

Bit 24: B1080.

B1081

Bit 25: B1081.

B1082

Bit 26: B1082.

B1083

Bit 27: B1083.

B1084

Bit 28: B1084.

B1085

Bit 29: B1085.

B1086

Bit 30: B1086.

B1087

Bit 31: B1087.

VCTR34

MPCBBx vector register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1119
rw 		B1118
rw 		B1117
rw 		B1116
rw 		B1115
rw 		B1114
rw 		B1113
rw 		B1112
rw 		B1111
rw 		B1110
rw 		B1109
rw 		B1108
rw 		B1107
rw 		B1106
rw 		B1105
rw 		B1104
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1103
rw 		B1102
rw 		B1101
rw 		B1100
rw 		B1099
rw 		B1098
rw 		B1097
rw 		B1096
rw 		B1095
rw 		B1094
rw 		B1093
rw 		B1092
rw 		B1091
rw 		B1090
rw 		B1089
rw 		B1088
rw
Toggle fields

B1088

Bit 0: B1088.

B1089

Bit 1: B1089.

B1090

Bit 2: B1090.

B1091

Bit 3: B1091.

B1092

Bit 4: B1092.

B1093

Bit 5: B1093.

B1094

Bit 6: B1094.

B1095

Bit 7: B1095.

B1096

Bit 8: B1096.

B1097

Bit 9: B1097.

B1098

Bit 10: B1098.

B1099

Bit 11: B1099.

B1100

Bit 12: B1100.

B1101

Bit 13: B1101.

B1102

Bit 14: B1102.

B1103

Bit 15: B1103.

B1104

Bit 16: B1104.

B1105

Bit 17: B1105.

B1106

Bit 18: B1106.

B1107

Bit 19: B1107.

B1108

Bit 20: B1108.

B1109

Bit 21: B1109.

B1110

Bit 22: B1110.

B1111

Bit 23: B1111.

B1112

Bit 24: B1112.

B1113

Bit 25: B1113.

B1114

Bit 26: B1114.

B1115

Bit 27: B1115.

B1116

Bit 28: B1116.

B1117

Bit 29: B1117.

B1118

Bit 30: B1118.

B1119

Bit 31: B1119.

VCTR35

MPCBBx vector register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1151
rw 		B1150
rw 		B1149
rw 		B1148
rw 		B1147
rw 		B1146
rw 		B1145
rw 		B1144
rw 		B1143
rw 		B1142
rw 		B1141
rw 		B1140
rw 		B1139
rw 		B1138
rw 		B1137
rw 		B1136
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1135
rw 		B1134
rw 		B1133
rw 		B1132
rw 		B1131
rw 		B1130
rw 		B1129
rw 		B1128
rw 		B1127
rw 		B1126
rw 		B1125
rw 		B1124
rw 		B1123
rw 		B1122
rw 		B1121
rw 		B1120
rw
Toggle fields

B1120

Bit 0: B1120.

B1121

Bit 1: B1121.

B1122

Bit 2: B1122.

B1123

Bit 3: B1123.

B1124

Bit 4: B1124.

B1125

Bit 5: B1125.

B1126

Bit 6: B1126.

B1127

Bit 7: B1127.

B1128

Bit 8: B1128.

B1129

Bit 9: B1129.

B1130

Bit 10: B1130.

B1131

Bit 11: B1131.

B1132

Bit 12: B1132.

B1133

Bit 13: B1133.

B1134

Bit 14: B1134.

B1135

Bit 15: B1135.

B1136

Bit 16: B1136.

B1137

Bit 17: B1137.

B1138

Bit 18: B1138.

B1139

Bit 19: B1139.

B1140

Bit 20: B1140.

B1141

Bit 21: B1141.

B1142

Bit 22: B1142.

B1143

Bit 23: B1143.

B1144

Bit 24: B1144.

B1145

Bit 25: B1145.

B1146

Bit 26: B1146.

B1147

Bit 27: B1147.

B1148

Bit 28: B1148.

B1149

Bit 29: B1149.

B1150

Bit 30: B1150.

B1151

Bit 31: B1151.

VCTR36

MPCBBx vector register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1183
rw 		B1182
rw 		B1181
rw 		B1180
rw 		B1179
rw 		B1178
rw 		B1177
rw 		B1176
rw 		B1175
rw 		B1174
rw 		B1173
rw 		B1172
rw 		B1171
rw 		B1170
rw 		B1169
rw 		B1168
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1167
rw 		B1166
rw 		B1165
rw 		B1164
rw 		B1163
rw 		B1162
rw 		B1161
rw 		B1160
rw 		B1159
rw 		B1158
rw 		B1157
rw 		B1156
rw 		B1155
rw 		B1154
rw 		B1153
rw 		B1152
rw
Toggle fields

B1152

Bit 0: B1152.

B1153

Bit 1: B1153.

B1154

Bit 2: B1154.

B1155

Bit 3: B1155.

B1156

Bit 4: B1156.

B1157

Bit 5: B1157.

B1158

Bit 6: B1158.

B1159

Bit 7: B1159.

B1160

Bit 8: B1160.

B1161

Bit 9: B1161.

B1162

Bit 10: B1162.

B1163

Bit 11: B1163.

B1164

Bit 12: B1164.

B1165

Bit 13: B1165.

B1166

Bit 14: B1166.

B1167

Bit 15: B1167.

B1168

Bit 16: B1168.

B1169

Bit 17: B1169.

B1170

Bit 18: B1170.

B1171

Bit 19: B1171.

B1172

Bit 20: B1172.

B1173

Bit 21: B1173.

B1174

Bit 22: B1174.

B1175

Bit 23: B1175.

B1176

Bit 24: B1176.

B1177

Bit 25: B1177.

B1178

Bit 26: B1178.

B1179

Bit 27: B1179.

B1180

Bit 28: B1180.

B1181

Bit 29: B1181.

B1182

Bit 30: B1182.

B1183

Bit 31: B1183.

VCTR37

MPCBBx vector register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1215
rw 		B1214
rw 		B1213
rw 		B1212
rw 		B1211
rw 		B1210
rw 		B1209
rw 		B1208
rw 		B1207
rw 		B1206
rw 		B1205
rw 		B1204
rw 		B1203
rw 		B1202
rw 		B1201
rw 		B1200
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1199
rw 		B1198
rw 		B1197
rw 		B1196
rw 		B1195
rw 		B1194
rw 		B1193
rw 		B1192
rw 		B1191
rw 		B1190
rw 		B1189
rw 		B1188
rw 		B1187
rw 		B1186
rw 		B1185
rw 		B1184
rw
Toggle fields

B1184

Bit 0: B1184.

B1185

Bit 1: B1185.

B1186

Bit 2: B1186.

B1187

Bit 3: B1187.

B1188

Bit 4: B1188.

B1189

Bit 5: B1189.

B1190

Bit 6: B1190.

B1191

Bit 7: B1191.

B1192

Bit 8: B1192.

B1193

Bit 9: B1193.

B1194

Bit 10: B1194.

B1195

Bit 11: B1195.

B1196

Bit 12: B1196.

B1197

Bit 13: B1197.

B1198

Bit 14: B1198.

B1199

Bit 15: B1199.

B1200

Bit 16: B1200.

B1201

Bit 17: B1201.

B1202

Bit 18: B1202.

B1203

Bit 19: B1203.

B1204

Bit 20: B1204.

B1205

Bit 21: B1205.

B1206

Bit 22: B1206.

B1207

Bit 23: B1207.

B1208

Bit 24: B1208.

B1209

Bit 25: B1209.

B1210

Bit 26: B1210.

B1211

Bit 27: B1211.

B1212

Bit 28: B1212.

B1213

Bit 29: B1213.

B1214

Bit 30: B1214.

B1215

Bit 31: B1215.

VCTR38

MPCBBx vector register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1247
rw 		B1246
rw 		B1245
rw 		B1244
rw 		B1243
rw 		B1242
rw 		B1241
rw 		B1240
rw 		B1239
rw 		B1238
rw 		B1237
rw 		B1236
rw 		B1235
rw 		B1234
rw 		B1233
rw 		B1232
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1231
rw 		B1230
rw 		B1229
rw 		B1228
rw 		B1227
rw 		B1226
rw 		B1225
rw 		B1224
rw 		B1223
rw 		B1222
rw 		B1221
rw 		B1220
rw 		B1219
rw 		B1218
rw 		B1217
rw 		B1216
rw
Toggle fields

B1216

Bit 0: B1216.

B1217

Bit 1: B1217.

B1218

Bit 2: B1218.

B1219

Bit 3: B1219.

B1220

Bit 4: B1220.

B1221

Bit 5: B1221.

B1222

Bit 6: B1222.

B1223

Bit 7: B1223.

B1224

Bit 8: B1224.

B1225

Bit 9: B1225.

B1226

Bit 10: B1226.

B1227

Bit 11: B1227.

B1228

Bit 12: B1228.

B1229

Bit 13: B1229.

B1230

Bit 14: B1230.

B1231

Bit 15: B1231.

B1232

Bit 16: B1232.

B1233

Bit 17: B1233.

B1234

Bit 18: B1234.

B1235

Bit 19: B1235.

B1236

Bit 20: B1236.

B1237

Bit 21: B1237.

B1238

Bit 22: B1238.

B1239

Bit 23: B1239.

B1240

Bit 24: B1240.

B1241

Bit 25: B1241.

B1242

Bit 26: B1242.

B1243

Bit 27: B1243.

B1244

Bit 28: B1244.

B1245

Bit 29: B1245.

B1246

Bit 30: B1246.

B1247

Bit 31: B1247.

VCTR39

MPCBBx vector register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1279
rw 		B1278
rw 		B1277
rw 		B1276
rw 		B1275
rw 		B1274
rw 		B1273
rw 		B1272
rw 		B1271
rw 		B1270
rw 		B1269
rw 		B1268
rw 		B1267
rw 		B1266
rw 		B1265
rw 		B1264
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1263
rw 		B1262
rw 		B1261
rw 		B1260
rw 		B1259
rw 		B1258
rw 		B1257
rw 		B1256
rw 		B1255
rw 		B1254
rw 		B1253
rw 		B1252
rw 		B1251
rw 		B1250
rw 		B1249
rw 		B1248
rw
Toggle fields

B1248

Bit 0: B1248.

B1249

Bit 1: B1249.

B1250

Bit 2: B1250.

B1251

Bit 3: B1251.

B1252

Bit 4: B1252.

B1253

Bit 5: B1253.

B1254

Bit 6: B1254.

B1255

Bit 7: B1255.

B1256

Bit 8: B1256.

B1257

Bit 9: B1257.

B1258

Bit 10: B1258.

B1259

Bit 11: B1259.

B1260

Bit 12: B1260.

B1261

Bit 13: B1261.

B1262

Bit 14: B1262.

B1263

Bit 15: B1263.

B1264

Bit 16: B1264.

B1265

Bit 17: B1265.

B1266

Bit 18: B1266.

B1267

Bit 19: B1267.

B1268

Bit 20: B1268.

B1269

Bit 21: B1269.

B1270

Bit 22: B1270.

B1271

Bit 23: B1271.

B1272

Bit 24: B1272.

B1273

Bit 25: B1273.

B1274

Bit 26: B1274.

B1275

Bit 27: B1275.

B1276

Bit 28: B1276.

B1277

Bit 29: B1277.

B1278

Bit 30: B1278.

B1279

Bit 31: B1279.

VCTR40

MPCBBx vector register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1311
rw 		B1310
rw 		B1309
rw 		B1308
rw 		B1307
rw 		B1306
rw 		B1305
rw 		B1304
rw 		B1303
rw 		B1302
rw 		B1301
rw 		B1300
rw 		B1299
rw 		B1298
rw 		B1297
rw 		B1296
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1295
rw 		B1294
rw 		B1293
rw 		B1292
rw 		B1291
rw 		B1290
rw 		B1289
rw 		B1288
rw 		B1287
rw 		B1286
rw 		B1285
rw 		B1284
rw 		B1283
rw 		B1282
rw 		B1281
rw 		B1280
rw
Toggle fields

B1280

Bit 0: B1280.

B1281

Bit 1: B1281.

B1282

Bit 2: B1282.

B1283

Bit 3: B1283.

B1284

Bit 4: B1284.

B1285

Bit 5: B1285.

B1286

Bit 6: B1286.

B1287

Bit 7: B1287.

B1288

Bit 8: B1288.

B1289

Bit 9: B1289.

B1290

Bit 10: B1290.

B1291

Bit 11: B1291.

B1292

Bit 12: B1292.

B1293

Bit 13: B1293.

B1294

Bit 14: B1294.

B1295

Bit 15: B1295.

B1296

Bit 16: B1296.

B1297

Bit 17: B1297.

B1298

Bit 18: B1298.

B1299

Bit 19: B1299.

B1300

Bit 20: B1300.

B1301

Bit 21: B1301.

B1302

Bit 22: B1302.

B1303

Bit 23: B1303.

B1304

Bit 24: B1304.

B1305

Bit 25: B1305.

B1306

Bit 26: B1306.

B1307

Bit 27: B1307.

B1308

Bit 28: B1308.

B1309

Bit 29: B1309.

B1310

Bit 30: B1310.

B1311

Bit 31: B1311.

VCTR41

MPCBBx vector register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1343
rw 		B1342
rw 		B1341
rw 		B1340
rw 		B1339
rw 		B1338
rw 		B1337
rw 		B1336
rw 		B1335
rw 		B1334
rw 		B1333
rw 		B1332
rw 		B1331
rw 		B1330
rw 		B1329
rw 		B1328
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1327
rw 		B1326
rw 		B1325
rw 		B1324
rw 		B1323
rw 		B1322
rw 		B1321
rw 		B1320
rw 		B1319
rw 		B1318
rw 		B1317
rw 		B1316
rw 		B1315
rw 		B1314
rw 		B1313
rw 		B1312
rw
Toggle fields

B1312

Bit 0: B1312.

B1313

Bit 1: B1313.

B1314

Bit 2: B1314.

B1315

Bit 3: B1315.

B1316

Bit 4: B1316.

B1317

Bit 5: B1317.

B1318

Bit 6: B1318.

B1319

Bit 7: B1319.

B1320

Bit 8: B1320.

B1321

Bit 9: B1321.

B1322

Bit 10: B1322.

B1323

Bit 11: B1323.

B1324

Bit 12: B1324.

B1325

Bit 13: B1325.

B1326

Bit 14: B1326.

B1327

Bit 15: B1327.

B1328

Bit 16: B1328.

B1329

Bit 17: B1329.

B1330

Bit 18: B1330.

B1331

Bit 19: B1331.

B1332

Bit 20: B1332.

B1333

Bit 21: B1333.

B1334

Bit 22: B1334.

B1335

Bit 23: B1335.

B1336

Bit 24: B1336.

B1337

Bit 25: B1337.

B1338

Bit 26: B1338.

B1339

Bit 27: B1339.

B1340

Bit 28: B1340.

B1341

Bit 29: B1341.

B1342

Bit 30: B1342.

B1343

Bit 31: B1343.

VCTR42

MPCBBx vector register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1375
rw 		B1374
rw 		B1373
rw 		B1372
rw 		B1371
rw 		B1370
rw 		B1369
rw 		B1368
rw 		B1367
rw 		B1366
rw 		B1365
rw 		B1364
rw 		B1363
rw 		B1362
rw 		B1361
rw 		B1360
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1359
rw 		B1358
rw 		B1357
rw 		B1356
rw 		B1355
rw 		B1354
rw 		B1353
rw 		B1352
rw 		B1351
rw 		B1350
rw 		B1349
rw 		B1348
rw 		B1347
rw 		B1346
rw 		B1345
rw 		B1344
rw
Toggle fields

B1344

Bit 0: B1344.

B1345

Bit 1: B1345.

B1346

Bit 2: B1346.

B1347

Bit 3: B1347.

B1348

Bit 4: B1348.

B1349

Bit 5: B1349.

B1350

Bit 6: B1350.

B1351

Bit 7: B1351.

B1352

Bit 8: B1352.

B1353

Bit 9: B1353.

B1354

Bit 10: B1354.

B1355

Bit 11: B1355.

B1356

Bit 12: B1356.

B1357

Bit 13: B1357.

B1358

Bit 14: B1358.

B1359

Bit 15: B1359.

B1360

Bit 16: B1360.

B1361

Bit 17: B1361.

B1362

Bit 18: B1362.

B1363

Bit 19: B1363.

B1364

Bit 20: B1364.

B1365

Bit 21: B1365.

B1366

Bit 22: B1366.

B1367

Bit 23: B1367.

B1368

Bit 24: B1368.

B1369

Bit 25: B1369.

B1370

Bit 26: B1370.

B1371

Bit 27: B1371.

B1372

Bit 28: B1372.

B1373

Bit 29: B1373.

B1374

Bit 30: B1374.

B1375

Bit 31: B1375.

VCTR43

MPCBBx vector register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1407
rw 		B1406
rw 		B1405
rw 		B1404
rw 		B1403
rw 		B1402
rw 		B1401
rw 		B1400
rw 		B1399
rw 		B1398
rw 		B1397
rw 		B1396
rw 		B1395
rw 		B1394
rw 		B1393
rw 		B1392
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1391
rw 		B1390
rw 		B1389
rw 		B1388
rw 		B1387
rw 		B1386
rw 		B1385
rw 		B1384
rw 		B1383
rw 		B1382
rw 		B1381
rw 		B1380
rw 		B1379
rw 		B1378
rw 		B1377
rw 		B1376
rw
Toggle fields

B1376

Bit 0: B1376.

B1377

Bit 1: B1377.

B1378

Bit 2: B1378.

B1379

Bit 3: B1379.

B1380

Bit 4: B1380.

B1381

Bit 5: B1381.

B1382

Bit 6: B1382.

B1383

Bit 7: B1383.

B1384

Bit 8: B1384.

B1385

Bit 9: B1385.

B1386

Bit 10: B1386.

B1387

Bit 11: B1387.

B1388

Bit 12: B1388.

B1389

Bit 13: B1389.

B1390

Bit 14: B1390.

B1391

Bit 15: B1391.

B1392

Bit 16: B1392.

B1393

Bit 17: B1393.

B1394

Bit 18: B1394.

B1395

Bit 19: B1395.

B1396

Bit 20: B1396.

B1397

Bit 21: B1397.

B1398

Bit 22: B1398.

B1399

Bit 23: B1399.

B1400

Bit 24: B1400.

B1401

Bit 25: B1401.

B1402

Bit 26: B1402.

B1403

Bit 27: B1403.

B1404

Bit 28: B1404.

B1405

Bit 29: B1405.

B1406

Bit 30: B1406.

B1407

Bit 31: B1407.

VCTR44

MPCBBx vector register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1439
rw 		B1438
rw 		B1437
rw 		B1436
rw 		B1435
rw 		B1434
rw 		B1433
rw 		B1432
rw 		B1431
rw 		B1430
rw 		B1429
rw 		B1428
rw 		B1427
rw 		B1426
rw 		B1425
rw 		B1424
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1423
rw 		B1422
rw 		B1421
rw 		B1420
rw 		B1419
rw 		B1418
rw 		B1417
rw 		B1416
rw 		B1415
rw 		B1414
rw 		B1413
rw 		B1412
rw 		B1411
rw 		B1410
rw 		B1409
rw 		B1408
rw
Toggle fields

B1408

Bit 0: B1408.

B1409

Bit 1: B1409.

B1410

Bit 2: B1410.

B1411

Bit 3: B1411.

B1412

Bit 4: B1412.

B1413

Bit 5: B1413.

B1414

Bit 6: B1414.

B1415

Bit 7: B1415.

B1416

Bit 8: B1416.

B1417

Bit 9: B1417.

B1418

Bit 10: B1418.

B1419

Bit 11: B1419.

B1420

Bit 12: B1420.

B1421

Bit 13: B1421.

B1422

Bit 14: B1422.

B1423

Bit 15: B1423.

B1424

Bit 16: B1424.

B1425

Bit 17: B1425.

B1426

Bit 18: B1426.

B1427

Bit 19: B1427.

B1428

Bit 20: B1428.

B1429

Bit 21: B1429.

B1430

Bit 22: B1430.

B1431

Bit 23: B1431.

B1432

Bit 24: B1432.

B1433

Bit 25: B1433.

B1434

Bit 26: B1434.

B1435

Bit 27: B1435.

B1436

Bit 28: B1436.

B1437

Bit 29: B1437.

B1438

Bit 30: B1438.

B1439

Bit 31: B1439.

VCTR45

MPCBBx vector register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1471
rw 		B1470
rw 		B1469
rw 		B1468
rw 		B1467
rw 		B1466
rw 		B1465
rw 		B1464
rw 		B1463
rw 		B1462
rw 		B1461
rw 		B1460
rw 		B1459
rw 		B1458
rw 		B1457
rw 		B1456
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1455
rw 		B1454
rw 		B1453
rw 		B1452
rw 		B1451
rw 		B1450
rw 		B1449
rw 		B1448
rw 		B1447
rw 		B1446
rw 		B1445
rw 		B1444
rw 		B1443
rw 		B1442
rw 		B1441
rw 		B1440
rw
Toggle fields

B1440

Bit 0: B1440.

B1441

Bit 1: B1441.

B1442

Bit 2: B1442.

B1443

Bit 3: B1443.

B1444

Bit 4: B1444.

B1445

Bit 5: B1445.

B1446

Bit 6: B1446.

B1447

Bit 7: B1447.

B1448

Bit 8: B1448.

B1449

Bit 9: B1449.

B1450

Bit 10: B1450.

B1451

Bit 11: B1451.

B1452

Bit 12: B1452.

B1453

Bit 13: B1453.

B1454

Bit 14: B1454.

B1455

Bit 15: B1455.

B1456

Bit 16: B1456.

B1457

Bit 17: B1457.

B1458

Bit 18: B1458.

B1459

Bit 19: B1459.

B1460

Bit 20: B1460.

B1461

Bit 21: B1461.

B1462

Bit 22: B1462.

B1463

Bit 23: B1463.

B1464

Bit 24: B1464.

B1465

Bit 25: B1465.

B1466

Bit 26: B1466.

B1467

Bit 27: B1467.

B1468

Bit 28: B1468.

B1469

Bit 29: B1469.

B1470

Bit 30: B1470.

B1471

Bit 31: B1471.

VCTR46

MPCBBx vector register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1503
rw 		B1502
rw 		B1501
rw 		B1500
rw 		B1499
rw 		B1498
rw 		B1497
rw 		B1496
rw 		B1495
rw 		B1494
rw 		B1493
rw 		B1492
rw 		B1491
rw 		B1490
rw 		B1489
rw 		B1488
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1487
rw 		B1486
rw 		B1485
rw 		B1484
rw 		B1483
rw 		B1482
rw 		B1481
rw 		B1480
rw 		B1479
rw 		B1478
rw 		B1477
rw 		B1476
rw 		B1475
rw 		B1474
rw 		B1473
rw 		B1472
rw
Toggle fields

B1472

Bit 0: B1472.

B1473

Bit 1: B1473.

B1474

Bit 2: B1474.

B1475

Bit 3: B1475.

B1476

Bit 4: B1476.

B1477

Bit 5: B1477.

B1478

Bit 6: B1478.

B1479

Bit 7: B1479.

B1480

Bit 8: B1480.

B1481

Bit 9: B1481.

B1482

Bit 10: B1482.

B1483

Bit 11: B1483.

B1484

Bit 12: B1484.

B1485

Bit 13: B1485.

B1486

Bit 14: B1486.

B1487

Bit 15: B1487.

B1488

Bit 16: B1488.

B1489

Bit 17: B1489.

B1490

Bit 18: B1490.

B1491

Bit 19: B1491.

B1492

Bit 20: B1492.

B1493

Bit 21: B1493.

B1494

Bit 22: B1494.

B1495

Bit 23: B1495.

B1496

Bit 24: B1496.

B1497

Bit 25: B1497.

B1498

Bit 26: B1498.

B1499

Bit 27: B1499.

B1500

Bit 28: B1500.

B1501

Bit 29: B1501.

B1502

Bit 30: B1502.

B1503

Bit 31: B1503.

VCTR47

MPCBBx vector register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1535
rw 		B1534
rw 		B1533
rw 		B1532
rw 		B1531
rw 		B1530
rw 		B1529
rw 		B1528
rw 		B1527
rw 		B1526
rw 		B1525
rw 		B1524
rw 		B1523
rw 		B1522
rw 		B1521
rw 		B1520
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1519
rw 		B1518
rw 		B1517
rw 		B1516
rw 		B1515
rw 		B1514
rw 		B1513
rw 		B1512
rw 		B1511
rw 		B1510
rw 		B1509
rw 		B1508
rw 		B1507
rw 		B1506
rw 		B1505
rw 		B1504
rw
Toggle fields

B1504

Bit 0: B1504.

B1505

Bit 1: B1505.

B1506

Bit 2: B1506.

B1507

Bit 3: B1507.

B1508

Bit 4: B1508.

B1509

Bit 5: B1509.

B1510

Bit 6: B1510.

B1511

Bit 7: B1511.

B1512

Bit 8: B1512.

B1513

Bit 9: B1513.

B1514

Bit 10: B1514.

B1515

Bit 11: B1515.

B1516

Bit 12: B1516.

B1517

Bit 13: B1517.

B1518

Bit 14: B1518.

B1519

Bit 15: B1519.

B1520

Bit 16: B1520.

B1521

Bit 17: B1521.

B1522

Bit 18: B1522.

B1523

Bit 19: B1523.

B1524

Bit 20: B1524.

B1525

Bit 21: B1525.

B1526

Bit 22: B1526.

B1527

Bit 23: B1527.

B1528

Bit 24: B1528.

B1529

Bit 25: B1529.

B1530

Bit 26: B1530.

B1531

Bit 27: B1531.

B1532

Bit 28: B1532.

B1533

Bit 29: B1533.

B1534

Bit 30: B1534.

B1535

Bit 31: B1535.

VCTR48

MPCBBx vector register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1567
rw 		B1566
rw 		B1565
rw 		B1564
rw 		B1563
rw 		B1562
rw 		B1561
rw 		B1560
rw 		B1559
rw 		B1558
rw 		B1557
rw 		B1556
rw 		B1555
rw 		B1554
rw 		B1553
rw 		B1552
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1551
rw 		B1550
rw 		B1549
rw 		B1548
rw 		B1547
rw 		B1546
rw 		B1545
rw 		B1544
rw 		B1543
rw 		B1542
rw 		B1541
rw 		B1540
rw 		B1539
rw 		B1538
rw 		B1537
rw 		B1536
rw
Toggle fields

B1536

Bit 0: B1536.

B1537

Bit 1: B1537.

B1538

Bit 2: B1538.

B1539

Bit 3: B1539.

B1540

Bit 4: B1540.

B1541

Bit 5: B1541.

B1542

Bit 6: B1542.

B1543

Bit 7: B1543.

B1544

Bit 8: B1544.

B1545

Bit 9: B1545.

B1546

Bit 10: B1546.

B1547

Bit 11: B1547.

B1548

Bit 12: B1548.

B1549

Bit 13: B1549.

B1550

Bit 14: B1550.

B1551

Bit 15: B1551.

B1552

Bit 16: B1552.

B1553

Bit 17: B1553.

B1554

Bit 18: B1554.

B1555

Bit 19: B1555.

B1556

Bit 20: B1556.

B1557

Bit 21: B1557.

B1558

Bit 22: B1558.

B1559

Bit 23: B1559.

B1560

Bit 24: B1560.

B1561

Bit 25: B1561.

B1562

Bit 26: B1562.

B1563

Bit 27: B1563.

B1564

Bit 28: B1564.

B1565

Bit 29: B1565.

B1566

Bit 30: B1566.

B1567

Bit 31: B1567.

VCTR49

MPCBBx vector register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1599
rw 		B1598
rw 		B1597
rw 		B1596
rw 		B1595
rw 		B1594
rw 		B1593
rw 		B1592
rw 		B1591
rw 		B1590
rw 		B1589
rw 		B1588
rw 		B1587
rw 		B1586
rw 		B1585
rw 		B1584
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1583
rw 		B1582
rw 		B1581
rw 		B1580
rw 		B1579
rw 		B1578
rw 		B1577
rw 		B1576
rw 		B1575
rw 		B1574
rw 		B1573
rw 		B1572
rw 		B1571
rw 		B1570
rw 		B1569
rw 		B1568
rw
Toggle fields

B1568

Bit 0: B1568.

B1569

Bit 1: B1569.

B1570

Bit 2: B1570.

B1571

Bit 3: B1571.

B1572

Bit 4: B1572.

B1573

Bit 5: B1573.

B1574

Bit 6: B1574.

B1575

Bit 7: B1575.

B1576

Bit 8: B1576.

B1577

Bit 9: B1577.

B1578

Bit 10: B1578.

B1579

Bit 11: B1579.

B1580

Bit 12: B1580.

B1581

Bit 13: B1581.

B1582

Bit 14: B1582.

B1583

Bit 15: B1583.

B1584

Bit 16: B1584.

B1585

Bit 17: B1585.

B1586

Bit 18: B1586.

B1587

Bit 19: B1587.

B1588

Bit 20: B1588.

B1589

Bit 21: B1589.

B1590

Bit 22: B1590.

B1591

Bit 23: B1591.

B1592

Bit 24: B1592.

B1593

Bit 25: B1593.

B1594

Bit 26: B1594.

B1595

Bit 27: B1595.

B1596

Bit 28: B1596.

B1597

Bit 29: B1597.

B1598

Bit 30: B1598.

B1599

Bit 31: B1599.

VCTR50

MPCBBx vector register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1631
rw 		B1630
rw 		B1629
rw 		B1628
rw 		B1627
rw 		B1626
rw 		B1625
rw 		B1624
rw 		B1623
rw 		B1622
rw 		B1621
rw 		B1620
rw 		B1619
rw 		B1618
rw 		B1617
rw 		B1616
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1615
rw 		B1614
rw 		B1613
rw 		B1612
rw 		B1611
rw 		B1610
rw 		B1609
rw 		B1608
rw 		B1607
rw 		B1606
rw 		B1605
rw 		B1604
rw 		B1603
rw 		B1602
rw 		B1601
rw 		B1600
rw
Toggle fields

B1600

Bit 0: B1600.

B1601

Bit 1: B1601.

B1602

Bit 2: B1602.

B1603

Bit 3: B1603.

B1604

Bit 4: B1604.

B1605

Bit 5: B1605.

B1606

Bit 6: B1606.

B1607

Bit 7: B1607.

B1608

Bit 8: B1608.

B1609

Bit 9: B1609.

B1610

Bit 10: B1610.

B1611

Bit 11: B1611.

B1612

Bit 12: B1612.

B1613

Bit 13: B1613.

B1614

Bit 14: B1614.

B1615

Bit 15: B1615.

B1616

Bit 16: B1616.

B1617

Bit 17: B1617.

B1618

Bit 18: B1618.

B1619

Bit 19: B1619.

B1620

Bit 20: B1620.

B1621

Bit 21: B1621.

B1622

Bit 22: B1622.

B1623

Bit 23: B1623.

B1624

Bit 24: B1624.

B1625

Bit 25: B1625.

B1626

Bit 26: B1626.

B1627

Bit 27: B1627.

B1628

Bit 28: B1628.

B1629

Bit 29: B1629.

B1630

Bit 30: B1630.

B1631

Bit 31: B1631.

VCTR51

MPCBBx vector register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1663
rw 		B1662
rw 		B1661
rw 		B1660
rw 		B1659
rw 		B1658
rw 		B1657
rw 		B1656
rw 		B1655
rw 		B1654
rw 		B1653
rw 		B1652
rw 		B1651
rw 		B1650
rw 		B1649
rw 		B1648
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1647
rw 		B1646
rw 		B1645
rw 		B1644
rw 		B1643
rw 		B1642
rw 		B1641
rw 		B1640
rw 		B1639
rw 		B1638
rw 		B1637
rw 		B1636
rw 		B1635
rw 		B1634
rw 		B1633
rw 		B1632
rw
Toggle fields

B1632

Bit 0: B1632.

B1633

Bit 1: B1633.

B1634

Bit 2: B1634.

B1635

Bit 3: B1635.

B1636

Bit 4: B1636.

B1637

Bit 5: B1637.

B1638

Bit 6: B1638.

B1639

Bit 7: B1639.

B1640

Bit 8: B1640.

B1641

Bit 9: B1641.

B1642

Bit 10: B1642.

B1643

Bit 11: B1643.

B1644

Bit 12: B1644.

B1645

Bit 13: B1645.

B1646

Bit 14: B1646.

B1647

Bit 15: B1647.

B1648

Bit 16: B1648.

B1649

Bit 17: B1649.

B1650

Bit 18: B1650.

B1651

Bit 19: B1651.

B1652

Bit 20: B1652.

B1653

Bit 21: B1653.

B1654

Bit 22: B1654.

B1655

Bit 23: B1655.

B1656

Bit 24: B1656.

B1657

Bit 25: B1657.

B1658

Bit 26: B1658.

B1659

Bit 27: B1659.

B1660

Bit 28: B1660.

B1661

Bit 29: B1661.

B1662

Bit 30: B1662.

B1663

Bit 31: B1663.

VCTR52

MPCBBx vector register

Offset: 0x1d0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1695
rw 		B1694
rw 		B1693
rw 		B1692
rw 		B1691
rw 		B1690
rw 		B1689
rw 		B1688
rw 		B1687
rw 		B1686
rw 		B1685
rw 		B1684
rw 		B1683
rw 		B1682
rw 		B1681
rw 		B1680
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1679
rw 		B1678
rw 		B1677
rw 		B1676
rw 		B1675
rw 		B1674
rw 		B1673
rw 		B1672
rw 		B1671
rw 		B1670
rw 		B1669
rw 		B1668
rw 		B1667
rw 		B1666
rw 		B1665
rw 		B1664
rw
Toggle fields

B1664

Bit 0: B1664.

B1665

Bit 1: B1665.

B1666

Bit 2: B1666.

B1667

Bit 3: B1667.

B1668

Bit 4: B1668.

B1669

Bit 5: B1669.

B1670

Bit 6: B1670.

B1671

Bit 7: B1671.

B1672

Bit 8: B1672.

B1673

Bit 9: B1673.

B1674

Bit 10: B1674.

B1675

Bit 11: B1675.

B1676

Bit 12: B1676.

B1677

Bit 13: B1677.

B1678

Bit 14: B1678.

B1679

Bit 15: B1679.

B1680

Bit 16: B1680.

B1681

Bit 17: B1681.

B1682

Bit 18: B1682.

B1683

Bit 19: B1683.

B1684

Bit 20: B1684.

B1685

Bit 21: B1685.

B1686

Bit 22: B1686.

B1687

Bit 23: B1687.

B1688

Bit 24: B1688.

B1689

Bit 25: B1689.

B1690

Bit 26: B1690.

B1691

Bit 27: B1691.

B1692

Bit 28: B1692.

B1693

Bit 29: B1693.

B1694

Bit 30: B1694.

B1695

Bit 31: B1695.

VCTR53

MPCBBx vector register

Offset: 0x1d4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1727
rw 		B1726
rw 		B1725
rw 		B1724
rw 		B1723
rw 		B1722
rw 		B1721
rw 		B1720
rw 		B1719
rw 		B1718
rw 		B1717
rw 		B1716
rw 		B1715
rw 		B1714
rw 		B1713
rw 		B1712
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1711
rw 		B1710
rw 		B1709
rw 		B1708
rw 		B1707
rw 		B1706
rw 		B1705
rw 		B1704
rw 		B1703
rw 		B1702
rw 		B1701
rw 		B1700
rw 		B1699
rw 		B1698
rw 		B1697
rw 		B1696
rw
Toggle fields

B1696

Bit 0: B1696.

B1697

Bit 1: B1697.

B1698

Bit 2: B1698.

B1699

Bit 3: B1699.

B1700

Bit 4: B1700.

B1701

Bit 5: B1701.

B1702

Bit 6: B1702.

B1703

Bit 7: B1703.

B1704

Bit 8: B1704.

B1705

Bit 9: B1705.

B1706

Bit 10: B1706.

B1707

Bit 11: B1707.

B1708

Bit 12: B1708.

B1709

Bit 13: B1709.

B1710

Bit 14: B1710.

B1711

Bit 15: B1711.

B1712

Bit 16: B1712.

B1713

Bit 17: B1713.

B1714

Bit 18: B1714.

B1715

Bit 19: B1715.

B1716

Bit 20: B1716.

B1717

Bit 21: B1717.

B1718

Bit 22: B1718.

B1719

Bit 23: B1719.

B1720

Bit 24: B1720.

B1721

Bit 25: B1721.

B1722

Bit 26: B1722.

B1723

Bit 27: B1723.

B1724

Bit 28: B1724.

B1725

Bit 29: B1725.

B1726

Bit 30: B1726.

B1727

Bit 31: B1727.

VCTR54

MPCBBx vector register

Offset: 0x1d8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1759
rw 		B1758
rw 		B1757
rw 		B1756
rw 		B1755
rw 		B1754
rw 		B1753
rw 		B1752
rw 		B1751
rw 		B1750
rw 		B1749
rw 		B1748
rw 		B1747
rw 		B1746
rw 		B1745
rw 		B1744
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1743
rw 		B1742
rw 		B1741
rw 		B1740
rw 		B1739
rw 		B1738
rw 		B1737
rw 		B1736
rw 		B1735
rw 		B1734
rw 		B1733
rw 		B1732
rw 		B1731
rw 		B1730
rw 		B1729
rw 		B1728
rw
Toggle fields

B1728

Bit 0: B1728.

B1729

Bit 1: B1729.

B1730

Bit 2: B1730.

B1731

Bit 3: B1731.

B1732

Bit 4: B1732.

B1733

Bit 5: B1733.

B1734

Bit 6: B1734.

B1735

Bit 7: B1735.

B1736

Bit 8: B1736.

B1737

Bit 9: B1737.

B1738

Bit 10: B1738.

B1739

Bit 11: B1739.

B1740

Bit 12: B1740.

B1741

Bit 13: B1741.

B1742

Bit 14: B1742.

B1743

Bit 15: B1743.

B1744

Bit 16: B1744.

B1745

Bit 17: B1745.

B1746

Bit 18: B1746.

B1747

Bit 19: B1747.

B1748

Bit 20: B1748.

B1749

Bit 21: B1749.

B1750

Bit 22: B1750.

B1751

Bit 23: B1751.

B1752

Bit 24: B1752.

B1753

Bit 25: B1753.

B1754

Bit 26: B1754.

B1755

Bit 27: B1755.

B1756

Bit 28: B1756.

B1757

Bit 29: B1757.

B1758

Bit 30: B1758.

B1759

Bit 31: B1759.

VCTR55

MPCBBx vector register

Offset: 0x1dc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1791
rw 		B1790
rw 		B1789
rw 		B1788
rw 		B1787
rw 		B1786
rw 		B1785
rw 		B1784
rw 		B1783
rw 		B1782
rw 		B1781
rw 		B1780
rw 		B1779
rw 		B1778
rw 		B1777
rw 		B1776
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1775
rw 		B1774
rw 		B1773
rw 		B1772
rw 		B1771
rw 		B1770
rw 		B1769
rw 		B1768
rw 		B1767
rw 		B1766
rw 		B1765
rw 		B1764
rw 		B1763
rw 		B1762
rw 		B1761
rw 		B1760
rw
Toggle fields

B1760

Bit 0: B1760.

B1761

Bit 1: B1761.

B1762

Bit 2: B1762.

B1763

Bit 3: B1763.

B1764

Bit 4: B1764.

B1765

Bit 5: B1765.

B1766

Bit 6: B1766.

B1767

Bit 7: B1767.

B1768

Bit 8: B1768.

B1769

Bit 9: B1769.

B1770

Bit 10: B1770.

B1771

Bit 11: B1771.

B1772

Bit 12: B1772.

B1773

Bit 13: B1773.

B1774

Bit 14: B1774.

B1775

Bit 15: B1775.

B1776

Bit 16: B1776.

B1777

Bit 17: B1777.

B1778

Bit 18: B1778.

B1779

Bit 19: B1779.

B1780

Bit 20: B1780.

B1781

Bit 21: B1781.

B1782

Bit 22: B1782.

B1783

Bit 23: B1783.

B1784

Bit 24: B1784.

B1785

Bit 25: B1785.

B1786

Bit 26: B1786.

B1787

Bit 27: B1787.

B1788

Bit 28: B1788.

B1789

Bit 29: B1789.

B1790

Bit 30: B1790.

B1791

Bit 31: B1791.

VCTR56

MPCBBx vector register

Offset: 0x1e0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1823
rw 		B1822
rw 		B1821
rw 		B1820
rw 		B1819
rw 		B1818
rw 		B1817
rw 		B1816
rw 		B1815
rw 		B1814
rw 		B1813
rw 		B1812
rw 		B1811
rw 		B1810
rw 		B1809
rw 		B1808
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1807
rw 		B1806
rw 		B1805
rw 		B1804
rw 		B1803
rw 		B1802
rw 		B1801
rw 		B1800
rw 		B1799
rw 		B1798
rw 		B1797
rw 		B1796
rw 		B1795
rw 		B1794
rw 		B1793
rw 		B1792
rw
Toggle fields

B1792

Bit 0: B1792.

B1793

Bit 1: B1793.

B1794

Bit 2: B1794.

B1795

Bit 3: B1795.

B1796

Bit 4: B1796.

B1797

Bit 5: B1797.

B1798

Bit 6: B1798.

B1799

Bit 7: B1799.

B1800

Bit 8: B1800.

B1801

Bit 9: B1801.

B1802

Bit 10: B1802.

B1803

Bit 11: B1803.

B1804

Bit 12: B1804.

B1805

Bit 13: B1805.

B1806

Bit 14: B1806.

B1807

Bit 15: B1807.

B1808

Bit 16: B1808.

B1809

Bit 17: B1809.

B1810

Bit 18: B1810.

B1811

Bit 19: B1811.

B1812

Bit 20: B1812.

B1813

Bit 21: B1813.

B1814

Bit 22: B1814.

B1815

Bit 23: B1815.

B1816

Bit 24: B1816.

B1817

Bit 25: B1817.

B1818

Bit 26: B1818.

B1819

Bit 27: B1819.

B1820

Bit 28: B1820.

B1821

Bit 29: B1821.

B1822

Bit 30: B1822.

B1823

Bit 31: B1823.

VCTR57

MPCBBx vector register

Offset: 0x1e4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1855
rw 		B1854
rw 		B1853
rw 		B1852
rw 		B1851
rw 		B1850
rw 		B1849
rw 		B1848
rw 		B1847
rw 		B1846
rw 		B1845
rw 		B1844
rw 		B1843
rw 		B1842
rw 		B1841
rw 		B1840
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1839
rw 		B1838
rw 		B1837
rw 		B1836
rw 		B1835
rw 		B1834
rw 		B1833
rw 		B1832
rw 		B1831
rw 		B1830
rw 		B1829
rw 		B1828
rw 		B1827
rw 		B1826
rw 		B1825
rw 		B1824
rw
Toggle fields

B1824

Bit 0: B1824.

B1825

Bit 1: B1825.

B1826

Bit 2: B1826.

B1827

Bit 3: B1827.

B1828

Bit 4: B1828.

B1829

Bit 5: B1829.

B1830

Bit 6: B1830.

B1831

Bit 7: B1831.

B1832

Bit 8: B1832.

B1833

Bit 9: B1833.

B1834

Bit 10: B1834.

B1835

Bit 11: B1835.

B1836

Bit 12: B1836.

B1837

Bit 13: B1837.

B1838

Bit 14: B1838.

B1839

Bit 15: B1839.

B1840

Bit 16: B1840.

B1841

Bit 17: B1841.

B1842

Bit 18: B1842.

B1843

Bit 19: B1843.

B1844

Bit 20: B1844.

B1845

Bit 21: B1845.

B1846

Bit 22: B1846.

B1847

Bit 23: B1847.

B1848

Bit 24: B1848.

B1849

Bit 25: B1849.

B1850

Bit 26: B1850.

B1851

Bit 27: B1851.

B1852

Bit 28: B1852.

B1853

Bit 29: B1853.

B1854

Bit 30: B1854.

B1855

Bit 31: B1855.

VCTR58

MPCBBx vector register

Offset: 0x1e8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1887
rw 		B1886
rw 		B1885
rw 		B1884
rw 		B1883
rw 		B1882
rw 		B1881
rw 		B1880
rw 		B1879
rw 		B1878
rw 		B1877
rw 		B1876
rw 		B1875
rw 		B1874
rw 		B1873
rw 		B1872
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1871
rw 		B1870
rw 		B1869
rw 		B1868
rw 		B1867
rw 		B1866
rw 		B1865
rw 		B1864
rw 		B1863
rw 		B1862
rw 		B1861
rw 		B1860
rw 		B1859
rw 		B1858
rw 		B1857
rw 		B1856
rw
Toggle fields

B1856

Bit 0: B1856.

B1857

Bit 1: B1857.

B1858

Bit 2: B1858.

B1859

Bit 3: B1859.

B1860

Bit 4: B1860.

B1861

Bit 5: B1861.

B1862

Bit 6: B1862.

B1863

Bit 7: B1863.

B1864

Bit 8: B1864.

B1865

Bit 9: B1865.

B1866

Bit 10: B1866.

B1867

Bit 11: B1867.

B1868

Bit 12: B1868.

B1869

Bit 13: B1869.

B1870

Bit 14: B1870.

B1871

Bit 15: B1871.

B1872

Bit 16: B1872.

B1873

Bit 17: B1873.

B1874

Bit 18: B1874.

B1875

Bit 19: B1875.

B1876

Bit 20: B1876.

B1877

Bit 21: B1877.

B1878

Bit 22: B1878.

B1879

Bit 23: B1879.

B1880

Bit 24: B1880.

B1881

Bit 25: B1881.

B1882

Bit 26: B1882.

B1883

Bit 27: B1883.

B1884

Bit 28: B1884.

B1885

Bit 29: B1885.

B1886

Bit 30: B1886.

B1887

Bit 31: B1887.

VCTR59

MPCBBx vector register

Offset: 0x1ec, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1919
rw 		B1918
rw 		B1917
rw 		B1916
rw 		B1915
rw 		B1914
rw 		B1913
rw 		B1912
rw 		B1911
rw 		B1910
rw 		B1909
rw 		B1908
rw 		B1907
rw 		B1906
rw 		B1905
rw 		B1904
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1903
rw 		B1902
rw 		B1901
rw 		B1900
rw 		B1899
rw 		B1898
rw 		B1897
rw 		B1896
rw 		B1895
rw 		B1894
rw 		B1893
rw 		B1892
rw 		B1891
rw 		B1890
rw 		B1889
rw 		B1888
rw
Toggle fields

B1888

Bit 0: B1888.

B1889

Bit 1: B1889.

B1890

Bit 2: B1890.

B1891

Bit 3: B1891.

B1892

Bit 4: B1892.

B1893

Bit 5: B1893.

B1894

Bit 6: B1894.

B1895

Bit 7: B1895.

B1896

Bit 8: B1896.

B1897

Bit 9: B1897.

B1898

Bit 10: B1898.

B1899

Bit 11: B1899.

B1900

Bit 12: B1900.

B1901

Bit 13: B1901.

B1902

Bit 14: B1902.

B1903

Bit 15: B1903.

B1904

Bit 16: B1904.

B1905

Bit 17: B1905.

B1906

Bit 18: B1906.

B1907

Bit 19: B1907.

B1908

Bit 20: B1908.

B1909

Bit 21: B1909.

B1910

Bit 22: B1910.

B1911

Bit 23: B1911.

B1912

Bit 24: B1912.

B1913

Bit 25: B1913.

B1914

Bit 26: B1914.

B1915

Bit 27: B1915.

B1916

Bit 28: B1916.

B1917

Bit 29: B1917.

B1918

Bit 30: B1918.

B1919

Bit 31: B1919.

VCTR60

MPCBBx vector register

Offset: 0x1f0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1951
rw 		B1950
rw 		B1949
rw 		B1948
rw 		B1947
rw 		B1946
rw 		B1945
rw 		B1944
rw 		B1943
rw 		B1942
rw 		B1941
rw 		B1940
rw 		B1939
rw 		B1938
rw 		B1937
rw 		B1936
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1935
rw 		B1934
rw 		B1933
rw 		B1932
rw 		B1931
rw 		B1930
rw 		B1929
rw 		B1928
rw 		B1927
rw 		B1926
rw 		B1925
rw 		B1924
rw 		B1923
rw 		B1922
rw 		B1921
rw 		B1920
rw
Toggle fields

B1920

Bit 0: B1920.

B1921

Bit 1: B1921.

B1922

Bit 2: B1922.

B1923

Bit 3: B1923.

B1924

Bit 4: B1924.

B1925

Bit 5: B1925.

B1926

Bit 6: B1926.

B1927

Bit 7: B1927.

B1928

Bit 8: B1928.

B1929

Bit 9: B1929.

B1930

Bit 10: B1930.

B1931

Bit 11: B1931.

B1932

Bit 12: B1932.

B1933

Bit 13: B1933.

B1934

Bit 14: B1934.

B1935

Bit 15: B1935.

B1936

Bit 16: B1936.

B1937

Bit 17: B1937.

B1938

Bit 18: B1938.

B1939

Bit 19: B1939.

B1940

Bit 20: B1940.

B1941

Bit 21: B1941.

B1942

Bit 22: B1942.

B1943

Bit 23: B1943.

B1944

Bit 24: B1944.

B1945

Bit 25: B1945.

B1946

Bit 26: B1946.

B1947

Bit 27: B1947.

B1948

Bit 28: B1948.

B1949

Bit 29: B1949.

B1950

Bit 30: B1950.

B1951

Bit 31: B1951.

VCTR61

MPCBBx vector register

Offset: 0x1f4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1983
rw 		B1982
rw 		B1981
rw 		B1980
rw 		B1979
rw 		B1978
rw 		B1977
rw 		B1976
rw 		B1975
rw 		B1974
rw 		B1973
rw 		B1972
rw 		B1971
rw 		B1970
rw 		B1969
rw 		B1968
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1967
rw 		B1966
rw 		B1965
rw 		B1964
rw 		B1963
rw 		B1962
rw 		B1961
rw 		B1960
rw 		B1959
rw 		B1958
rw 		B1957
rw 		B1956
rw 		B1955
rw 		B1954
rw 		B1953
rw 		B1952
rw
Toggle fields

B1952

Bit 0: B1952.

B1953

Bit 1: B1953.

B1954

Bit 2: B1954.

B1955

Bit 3: B1955.

B1956

Bit 4: B1956.

B1957

Bit 5: B1957.

B1958

Bit 6: B1958.

B1959

Bit 7: B1959.

B1960

Bit 8: B1960.

B1961

Bit 9: B1961.

B1962

Bit 10: B1962.

B1963

Bit 11: B1963.

B1964

Bit 12: B1964.

B1965

Bit 13: B1965.

B1966

Bit 14: B1966.

B1967

Bit 15: B1967.

B1968

Bit 16: B1968.

B1969

Bit 17: B1969.

B1970

Bit 18: B1970.

B1971

Bit 19: B1971.

B1972

Bit 20: B1972.

B1973

Bit 21: B1973.

B1974

Bit 22: B1974.

B1975

Bit 23: B1975.

B1976

Bit 24: B1976.

B1977

Bit 25: B1977.

B1978

Bit 26: B1978.

B1979

Bit 27: B1979.

B1980

Bit 28: B1980.

B1981

Bit 29: B1981.

B1982

Bit 30: B1982.

B1983

Bit 31: B1983.

VCTR62

MPCBBx vector register

Offset: 0x1f8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B2015
rw 		B2014
rw 		B2013
rw 		B2012
rw 		B2011
rw 		B2010
rw 		B2009
rw 		B2008
rw 		B2007
rw 		B2006
rw 		B2005
rw 		B2004
rw 		B2003
rw 		B2002
rw 		B2001
rw 		B2000
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1999
rw 		B1998
rw 		B1997
rw 		B1996
rw 		B1995
rw 		B1994
rw 		B1993
rw 		B1992
rw 		B1991
rw 		B1990
rw 		B1989
rw 		B1988
rw 		B1987
rw 		B1986
rw 		B1985
rw 		B1984
rw
Toggle fields

B1984

Bit 0: B1984.

B1985

Bit 1: B1985.

B1986

Bit 2: B1986.

B1987

Bit 3: B1987.

B1988

Bit 4: B1988.

B1989

Bit 5: B1989.

B1990

Bit 6: B1990.

B1991

Bit 7: B1991.

B1992

Bit 8: B1992.

B1993

Bit 9: B1993.

B1994

Bit 10: B1994.

B1995

Bit 11: B1995.

B1996

Bit 12: B1996.

B1997

Bit 13: B1997.

B1998

Bit 14: B1998.

B1999

Bit 15: B1999.

B2000

Bit 16: B2000.

B2001

Bit 17: B2001.

B2002

Bit 18: B2002.

B2003

Bit 19: B2003.

B2004

Bit 20: B2004.

B2005

Bit 21: B2005.

B2006

Bit 22: B2006.

B2007

Bit 23: B2007.

B2008

Bit 24: B2008.

B2009

Bit 25: B2009.

B2010

Bit 26: B2010.

B2011

Bit 27: B2011.

B2012

Bit 28: B2012.

B2013

Bit 29: B2013.

B2014

Bit 30: B2014.

B2015

Bit 31: B2015.

VCTR63

MPCBBx vector register

Offset: 0x1fc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B2047
rw 		B2046
rw 		B2045
rw 		B2044
rw 		B2043
rw 		B2042
rw 		B2041
rw 		B2040
rw 		B2039
rw 		B2038
rw 		B2037
rw 		B2036
rw 		B2035
rw 		B2034
rw 		B2033
rw 		B2032
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2031
rw 		B2030
rw 		B2029
rw 		B2028
rw 		B2027
rw 		B2026
rw 		B2025
rw 		B2024
rw 		B2023
rw 		B2022
rw 		B2021
rw 		B2020
rw 		B2019
rw 		B2018
rw 		B2017
rw 		B2016
rw
Toggle fields

B2016

Bit 0: B2016.

B2017

Bit 1: B2017.

B2018

Bit 2: B2018.

B2019

Bit 3: B2019.

B2020

Bit 4: B2020.

B2021

Bit 5: B2021.

B2022

Bit 6: B2022.

B2023

Bit 7: B2023.

B2024

Bit 8: B2024.

B2025

Bit 9: B2025.

B2026

Bit 10: B2026.

B2027

Bit 11: B2027.

B2028

Bit 12: B2028.

B2029

Bit 13: B2029.

B2030

Bit 14: B2030.

B2031

Bit 15: B2031.

B2032

Bit 16: B2032.

B2033

Bit 17: B2033.

B2034

Bit 18: B2034.

B2035

Bit 19: B2035.

B2036

Bit 20: B2036.

B2037

Bit 21: B2037.

B2038

Bit 22: B2038.

B2039

Bit 23: B2039.

B2040

Bit 24: B2040.

B2041

Bit 25: B2041.

B2042

Bit 26: B2042.

B2043

Bit 27: B2043.

B2044

Bit 28: B2044.

B2045

Bit 29: B2045.

B2046

Bit 30: B2046.

B2047

Bit 31: B2047.

GTZC_TZIC

0x40032800: GTZC_TZIC

32/210 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IER1
0x4 IER2
0x8 IER3
0x10 SR1
0x14 SR2
0x18 SR3
0x20 FCR1
0x24 FCR2
0x28 FCR3
Toggle registers

IER1

TZIC interrupt enable register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1IE
rw 		TIM1IE
rw 		COMPIE
rw 		VREFBUFIE
rw 		UCPD1IE
rw 		USBFSIE
rw 		FDCAN1IE
rw 		LPTIM3IE
rw 		LPTIM2IE
rw 		I2C4IE
rw 		LPUART1IE
rw 		LPTIM1IE
rw 		OPAMPIE
rw 		DACIE
rw 		CRSIE
rw 		I2C3IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2IE
rw 		I2C1IE
rw 		UART5IE
rw 		UART4IE
rw 		USART3IE
rw 		USART2IE
rw 		SPI3IE
rw 		SPI2IE
rw 		IWDGIE
rw 		WWDGIE
rw 		TIM7IE
rw 		TIM6IE
rw 		TIM5IE
rw 		TIM4IE
rw 		TIM3IE
rw 		TIM2IE
rw
Toggle fields

TIM2IE

Bit 0: TIM2IE.

TIM3IE

Bit 1: TIM3IE.

TIM4IE

Bit 2: TIM4IE.

TIM5IE

Bit 3: TIM5IE.

TIM6IE

Bit 4: TIM6IE.

TIM7IE

Bit 5: TIM7IE.

WWDGIE

Bit 6: WWDGIE.

IWDGIE

Bit 7: IWDGIE.

SPI2IE

Bit 8: SPI2IE.

SPI3IE

Bit 9: SPI3IE.

USART2IE

Bit 10: USART2IE.

USART3IE

Bit 11: USART3IE.

UART4IE

Bit 12: UART4IE.

UART5IE

Bit 13: UART5IE.

I2C1IE

Bit 14: I2C1IE.

I2C2IE

Bit 15: I2C2IE.

I2C3IE

Bit 16: I2C3IE.

CRSIE

Bit 17: CRSIE.

DACIE

Bit 18: DACIE.

OPAMPIE

Bit 19: OPAMPIE.

LPTIM1IE

Bit 20: LPTIM1IE.

LPUART1IE

Bit 21: LPUART1IE.

I2C4IE

Bit 22: I2C4IE.

LPTIM2IE

Bit 23: LPTIM2IE.

LPTIM3IE

Bit 24: LPTIM3IE.

FDCAN1IE

Bit 25: FDCAN1IE.

USBFSIE

Bit 26: USBFSIE.

UCPD1IE

Bit 27: UCPD1IE.

VREFBUFIE

Bit 28: VREFBUFIE.

COMPIE

Bit 29: COMPIE.

TIM1IE

Bit 30: TIM1IE.

SPI1IE

Bit 31: SPI1IE.

IER2

TZIC interrupt enable register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTFDEC1IE
rw 		EXTIIE
rw 		FLASH_REGIE
rw 		FLASHIE
rw 		RCCIE
rw 		DMAMUX1IE
rw 		DMA2IE
rw 		DMA1IE
rw 		SYSCFGIE
rw 		PWRIE
rw 		RTCIE
rw 		OCTOSPI1_REGIE
rw 		FMC_REGIE
rw 		SDMMC1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAIE
rw 		RNGIE
rw 		HASHIE
rw 		AESIE
rw 		ADCIE
rw 		ICACHEIE
rw 		TSCIE
rw 		CRCIE
rw 		DFSDM1IE
rw 		SAI2IE
rw 		SAI1IE
rw 		TIM17IE
rw 		TIM16IE
rw 		TIM15IE
rw 		USART1IE
rw 		TIM8IE
rw
Toggle fields

TIM8IE

Bit 0: TIM8IE.

USART1IE

Bit 1: USART1IE.

TIM15IE

Bit 2: TIM15IE.

TIM16IE

Bit 3: TIM16IE.

TIM17IE

Bit 4: TIM17IE.

SAI1IE

Bit 5: SAI1IE.

SAI2IE

Bit 6: SAI2IE.

DFSDM1IE

Bit 7: DFSDM1IE.

CRCIE

Bit 8: CRCIE.

TSCIE

Bit 9: TSCIE.

ICACHEIE

Bit 10: ICACHEIE.

ADCIE

Bit 11: ADCIE.

AESIE

Bit 12: AESIE.

HASHIE

Bit 13: HASHIE.

RNGIE

Bit 14: RNGIE.

PKAIE

Bit 15: PKAIE.

SDMMC1IE

Bit 16: SDMMC1IE.

FMC_REGIE

Bit 17: FMC_REGIE.

OCTOSPI1_REGIE

Bit 18: OCTOSPI1_REGIE.

RTCIE

Bit 19: RTCIE.

PWRIE

Bit 20: PWRIE.

SYSCFGIE

Bit 21: SYSCFGIE.

DMA1IE

Bit 22: DMA1IE.

DMA2IE

Bit 23: DMA2IE.

DMAMUX1IE

Bit 24: DMAMUX1IE.

RCCIE

Bit 25: RCCIE.

FLASHIE

Bit 26: FLASHIE.

FLASH_REGIE

Bit 27: FLASH_REGIE.

EXTIIE

Bit 28: EXTIIE.

OTFDEC1IE

Bit 29: OTFDEC1IE.

IER3

TZIC interrupt enable register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPCBB2_REGIE
rw 		MPCBB2IE
rw 		MPCBB1_REGIE
rw 		MPCBB1IE
rw 		MPCWM2IE
rw 		MPCWM1IE
rw 		TZICIE
rw 		TZSCIE
rw
Toggle fields

TZSCIE

Bit 0: TZSCIE.

TZICIE

Bit 1: TZICIE.

MPCWM1IE

Bit 2: MPCWM1IE.

MPCWM2IE

Bit 3: MPCWM2IE.

MPCBB1IE

Bit 4: MPCBB1IE.

MPCBB1_REGIE

Bit 5: MPCBB1_REGIE.

MPCBB2IE

Bit 6: MPCBB2IE.

MPCBB2_REGIE

Bit 7: MPCBB2_REGIE.

SR1

TZIC interrupt status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1F
r 		TIM1F
r 		COMPF
r 		VREFBUFF
r 		UCPD1F
r 		USBFSF
r 		FDCAN1F
r 		LPTIM3F
r 		LPTIM2F
r 		I2C4F
r 		LPUART1F
r 		LPTIM1F
r 		OPAMPF
r 		DACF
r 		CRSF
r 		I2C3F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2F
r 		I2C1F
r 		UART5F
r 		UART4F
r 		USART3F
r 		USART2F
r 		SPI3F
r 		SPI2F
r 		IWDGF
r 		WWDGF
r 		TIM7F
r 		TIM6F
r 		TIM5F
r 		TIM4F
r 		TIM3F
r 		TIM2F
r
Toggle fields

TIM2F

Bit 0: TIM2F.

TIM3F

Bit 1: TIM3F.

TIM4F

Bit 2: TIM4F.

TIM5F

Bit 3: TIM5F.

TIM6F

Bit 4: TIM6F.

TIM7F

Bit 5: TIM7F.

WWDGF

Bit 6: WWDGF.

IWDGF

Bit 7: IWDGF.

SPI2F

Bit 8: SPI2F.

SPI3F

Bit 9: SPI3F.

USART2F

Bit 10: USART2F.

USART3F

Bit 11: USART3F.

UART4F

Bit 12: UART4F.

UART5F

Bit 13: UART5F.

I2C1F

Bit 14: I2C1F.

I2C2F

Bit 15: I2C2F.

I2C3F

Bit 16: I2C3F.

CRSF

Bit 17: CRSF.

DACF

Bit 18: DACF.

OPAMPF

Bit 19: OPAMPF.

LPTIM1F

Bit 20: LPTIM1F.

LPUART1F

Bit 21: LPUART1F.

I2C4F

Bit 22: I2C4F.

LPTIM2F

Bit 23: LPTIM2F.

LPTIM3F

Bit 24: LPTIM3F.

FDCAN1F

Bit 25: FDCAN1F.

USBFSF

Bit 26: USBFSF.

UCPD1F

Bit 27: UCPD1F.

VREFBUFF

Bit 28: VREFBUFF.

COMPF

Bit 29: COMPF.

TIM1F

Bit 30: TIM1F.

SPI1F

Bit 31: SPI1F.

SR2

TZIC interrupt status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTFDEC1F
rw 		EXTIF
rw 		FLASH_REGF
rw 		FLASHF
rw 		RCCF
rw 		DMAMUX1F
rw 		DMA2F
rw 		DMA1F
rw 		SYSCFGF
rw 		PWRF
rw 		RTCF
rw 		OCTOSPI1_REGF
rw 		FMC_REGF
rw 		SDMMC1F
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAF
rw 		RNGF
rw 		HASHF
rw 		AESF
rw 		ADCF
rw 		ICACHEF
rw 		TSCF
rw 		CRCF
rw 		DFSDM1F
rw 		SAI2F
rw 		SAI1F
rw 		TIM17F
rw 		TIM16F
rw 		TIM15F
rw 		USART1F
rw 		TIM8F
rw
Toggle fields

TIM8F

Bit 0: TIM8F.

USART1F

Bit 1: USART1F.

TIM15F

Bit 2: TIM15F.

TIM16F

Bit 3: TIM16F.

TIM17F

Bit 4: TIM17F.

SAI1F

Bit 5: SAI1F.

SAI2F

Bit 6: SAI2F.

DFSDM1F

Bit 7: DFSDM1F.

CRCF

Bit 8: CRCF.

TSCF

Bit 9: TSCF.

ICACHEF

Bit 10: ICACHEF.

ADCF

Bit 11: ADCF.

AESF

Bit 12: AESF.

HASHF

Bit 13: HASHF.

RNGF

Bit 14: RNGF.

PKAF

Bit 15: PKAF.

SDMMC1F

Bit 16: SDMMC1F.

FMC_REGF

Bit 17: FMC_REGF.

OCTOSPI1_REGF

Bit 18: OCTOSPI1_REGF.

RTCF

Bit 19: RTCF.

PWRF

Bit 20: PWRF.

SYSCFGF

Bit 21: SYSCFGF.

DMA1F

Bit 22: DMA1F.

DMA2F

Bit 23: DMA2F.

DMAMUX1F

Bit 24: DMAMUX1F.

RCCF

Bit 25: RCCF.

FLASHF

Bit 26: FLASHF.

FLASH_REGF

Bit 27: FLASH_REGF.

EXTIF

Bit 28: EXTIF.

OTFDEC1F

Bit 29: OTFDEC1F.

SR3

TZIC interrupt status register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPCBB2_REGF
rw 		MPCBB2F
rw 		MPCBB1_REGF
rw 		MPCBB1F
rw 		MPCWM2F
rw 		MPCWM1F
rw 		TZICF
rw 		TZSCF
rw
Toggle fields

TZSCF

Bit 0: TZSCF.

TZICF

Bit 1: TZICF.

MPCWM1F

Bit 2: MPCWM1F.

MPCWM2F

Bit 3: MPCWM2F.

MPCBB1F

Bit 4: MPCBB1F.

MPCBB1_REGF

Bit 5: MPCBB1_REGF.

MPCBB2F

Bit 6: MPCBB2F.

MPCBB2_REGF

Bit 7: MPCBB2_REGF.

FCR1

TZIC interrupt clear register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1FC
w 		TIM1FC
w 		COMPFC
w 		VREFBUFFC
w 		UCPD1FC
w 		USBFSFC
w 		FDCAN1FC
w 		LPTIM3FC
w 		LPTIM2FC
w 		I2C4FC
w 		LPUART1FC
w 		LPTIM1FC
w 		OPAMPFC
w 		DACFC
w 		CRSFC
w 		I2C3FC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2FC
w 		I2C1FC
w 		UART5FC
w 		UART4FC
w 		USART3FC
w 		USART2FC
w 		SPI3FC
w 		SPI2FC
w 		IWDGFC
w 		WWDGFC
w 		TIM7FC
w 		TIM6FC
w 		TIM5FC
w 		TIM4FC
w 		TIM3FC
w 		TIM2FC
w
Toggle fields

TIM2FC

Bit 0: TIM2FC.

TIM3FC

Bit 1: TIM3FC.

TIM4FC

Bit 2: TIM4FC.

TIM5FC

Bit 3: TIM5FC.

TIM6FC

Bit 4: TIM6FC.

TIM7FC

Bit 5: TIM7FC.

WWDGFC

Bit 6: WWDGFC.

IWDGFC

Bit 7: IWDGFC.

SPI2FC

Bit 8: SPI2FC.

SPI3FC

Bit 9: SPI3FC.

USART2FC

Bit 10: USART2FC.

USART3FC

Bit 11: USART3FC.

UART4FC

Bit 12: UART4FC.

UART5FC

Bit 13: UART5FC.

I2C1FC

Bit 14: I2C1FC.

I2C2FC

Bit 15: I2C2FC.

I2C3FC

Bit 16: I2C3FC.

CRSFC

Bit 17: CRSFC.

DACFC

Bit 18: DACFC.

OPAMPFC

Bit 19: OPAMPFC.

LPTIM1FC

Bit 20: LPTIM1FC.

LPUART1FC

Bit 21: LPUART1FC.

I2C4FC

Bit 22: I2C4FC.

LPTIM2FC

Bit 23: LPTIM2FC.

LPTIM3FC

Bit 24: LPTIM3FC.

FDCAN1FC

Bit 25: FDCAN1FC.

USBFSFC

Bit 26: USBFSFC.

UCPD1FC

Bit 27: UCPD1FC.

VREFBUFFC

Bit 28: VREFBUFFC.

COMPFC

Bit 29: COMPFC.

TIM1FC

Bit 30: TIM1FC.

SPI1FC

Bit 31: SPI1FC.

FCR2

TZIC interrupt clear register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTFDEC1FC
rw 		EXTIFC
rw 		FLASH_REGFC
rw 		FLASHFC
rw 		RCCFC
rw 		DMAMUX1FC
rw 		DMA2FC
rw 		DMA1FC
rw 		SYSCFGFC
rw 		PWRFC
rw 		RTCFC
rw 		OCTOSPI1_REGFC
rw 		FMC_REGFC
rw 		SDMMC1FC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAFC
rw 		RNGFC
rw 		HASHFC
rw 		AESFC
rw 		ADCFC
rw 		ICACHEFC
rw 		TSCFC
rw 		CRCFC
rw 		DFSDM1FC
rw 		SAI2FC
rw 		SAI1FC
rw 		TIM17FC
rw 		TIM16FC
rw 		TIM15FC
rw 		USART1FC
rw 		TIM8FC
rw
Toggle fields

TIM8FC

Bit 0: TIM8FC.

USART1FC

Bit 1: USART1FC.

TIM15FC

Bit 2: TIM15FC.

TIM16FC

Bit 3: TIM16FC.

TIM17FC

Bit 4: TIM17FC.

SAI1FC

Bit 5: SAI1FC.

SAI2FC

Bit 6: SAI2FC.

DFSDM1FC

Bit 7: DFSDM1FC.

CRCFC

Bit 8: CRCFC.

TSCFC

Bit 9: TSCFC.

ICACHEFC

Bit 10: ICACHEFC.

ADCFC

Bit 11: ADCFC.

AESFC

Bit 12: AESFC.

HASHFC

Bit 13: HASHFC.

RNGFC

Bit 14: RNGFC.

PKAFC

Bit 15: PKAFC.

SDMMC1FC

Bit 16: SDMMC1FC.

FMC_REGFC

Bit 17: FMC_REGFC.

OCTOSPI1_REGFC

Bit 18: OCTOSPI1_REGFC.

RTCFC

Bit 19: RTCFC.

PWRFC

Bit 20: PWRFC.

SYSCFGFC

Bit 21: SYSCFGFC.

DMA1FC

Bit 22: DMA1FC.

DMA2FC

Bit 23: DMA2FC.

DMAMUX1FC

Bit 24: DMAMUX1FC.

RCCFC

Bit 25: RCCFC.

FLASHFC

Bit 26: FLASHFC.

FLASH_REGFC

Bit 27: FLASH_REGFC.

EXTIFC

Bit 28: EXTIFC.

OTFDEC1FC

Bit 29: OTFDEC1FC.

FCR3

TZIC interrupt clear register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPCBB2_REGFC
rw 		MPCBB2FC
rw 		MPCBB1_REGFC
rw 		MPCBB1FC
rw 		MPCWM2FC
rw 		MPCWM1FC
rw 		TZICFC
rw 		TZSCFC
rw
Toggle fields

TZSCFC

Bit 0: TZSCFC.

TZICFC

Bit 1: TZICFC.

MPCWM1FC

Bit 2: MPCWM1FC.

MPCWM2FC

Bit 3: MPCWM2FC.

MPCBB1FC

Bit 4: MPCBB1FC.

MPCBB1_REGFC

Bit 5: MPCBB1_REGFC.

MPCBB2FC

Bit 6: MPCBB2FC.

MPCBB2_REGFC

Bit 7: MPCBB2_REGFC.

GTZC_TZSC

0x40032400: GTZC_TZSC

0/113 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 SECCFGR1
0x14 SECCFGR2
0x20 PRIVCFGR1
0x24 PRIVCFGR2
0x30 MPCWM1_NSWMR1
0x34 MPCWM1_NSWMR2
0x38 MPCWM2_NSWMR1
0x3c MPCWM2_NSWMR2
0x40 MPCWM3_NSWMR1
Toggle registers

CR

TZSC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

SECCFGR1

TZSC secure configuration register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1SEC
rw 		TIM1SEC
rw 		COMPSEC
rw 		VREFBUFSEC
rw 		UCPD1SEC
rw 		USBFSSEC
rw 		FDCAN1SEC
rw 		LPTIM3SEC
rw 		LPTIM2SEC
rw 		I2C4SEC
rw 		LPUART1SEC
rw 		LPTIM1SEC
rw 		OPAMPSEC
rw 		DACSEC
rw 		CRSSEC
rw 		I2C3SEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEC
rw 		I2C1SEC
rw 		UART5SEC
rw 		UART4SEC
rw 		USART3SEC
rw 		USART2SEC
rw 		SPI3SEC
rw 		SPI2SEC
rw 		IWDGSEC
rw 		WWDGSEC
rw 		TIM7SEC
rw 		TIM6SEC
rw 		TIM5SEC
rw 		TIM4SEC
rw 		TIM3SEC
rw 		TIM2SEC
rw
Toggle fields

TIM2SEC

Bit 0: TIM2SEC.

TIM3SEC

Bit 1: TIM3SEC.

TIM4SEC

Bit 2: TIM4SEC.

TIM5SEC

Bit 3: TIM5SEC.

TIM6SEC

Bit 4: TIM6SEC.

TIM7SEC

Bit 5: TIM7SEC.

WWDGSEC

Bit 6: WWDGSEC.

IWDGSEC

Bit 7: IWDGSEC.

SPI2SEC

Bit 8: SPI2SEC.

SPI3SEC

Bit 9: SPI3SEC.

USART2SEC

Bit 10: USART2SEC.

USART3SEC

Bit 11: USART3SEC.

UART4SEC

Bit 12: UART4SEC.

UART5SEC

Bit 13: UART5SEC.

I2C1SEC

Bit 14: I2C1SEC.

I2C2SEC

Bit 15: I2C2SEC.

I2C3SEC

Bit 16: I2C3SEC.

CRSSEC

Bit 17: CRSSEC.

DACSEC

Bit 18: DACSEC.

OPAMPSEC

Bit 19: OPAMPSEC.

LPTIM1SEC

Bit 20: LPTIM1SEC.

LPUART1SEC

Bit 21: LPUART1SEC.

I2C4SEC

Bit 22: I2C4SEC.

LPTIM2SEC

Bit 23: LPTIM2SEC.

LPTIM3SEC

Bit 24: LPTIM3SEC.

FDCAN1SEC

Bit 25: FDCAN1SEC.

USBFSSEC

Bit 26: USBFSSEC.

UCPD1SEC

Bit 27: UCPD1SEC.

VREFBUFSEC

Bit 28: VREFBUFSEC.

COMPSEC

Bit 29: COMPSEC.

TIM1SEC

Bit 30: TIM1SEC.

SPI1SEC

Bit 31: SPI1SEC.

SECCFGR2

TZSC secure configuration register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OCTOSPI1_REGSEC
rw 		FSMC_REGSEC
rw 		SDMMC1SEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKASEC
rw 		RNGSEC
rw 		HASHSEC
rw 		AESSEC
rw 		ADCSEC
rw 		ICACHESEC
rw 		TSCSEC
rw 		CRCSEC
rw 		DFSDM1SEC
rw 		SAI2SEC
rw 		SAI1SEC
rw 		TIM17SEC
rw 		TIM16SEC
rw 		TIM15SEC
rw 		USART1SEC
rw 		TIM8SEC
rw
Toggle fields

TIM8SEC

Bit 0: TIM8SEC.

USART1SEC

Bit 1: USART1SEC.

TIM15SEC

Bit 2: TIM15SEC.

TIM16SEC

Bit 3: TIM16SEC.

TIM17SEC

Bit 4: TIM17SEC.

SAI1SEC

Bit 5: SAI1SEC.

SAI2SEC

Bit 6: SAI2SEC.

DFSDM1SEC

Bit 7: DFSDM1SEC.

CRCSEC

Bit 8: CRCSEC.

TSCSEC

Bit 9: TSCSEC.

ICACHESEC

Bit 10: ICACHESEC.

ADCSEC

Bit 11: ADCSEC.

AESSEC

Bit 12: AESSEC.

HASHSEC

Bit 13: HASHSEC.

RNGSEC

Bit 14: RNGSEC.

PKASEC

Bit 15: PKASEC.

SDMMC1SEC

Bit 16: SDMMC1SEC.

FSMC_REGSEC

Bit 17: FSMC_REGSEC.

OCTOSPI1_REGSEC

Bit 18: OCTOSPI1_REGSEC.

PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1PRIV
rw 		TIM1PRIV
rw 		COMPPRIV
rw 		VREFBUFPRIV
rw 		UCPD1PRIV
rw 		USBFSPRIV
rw 		FDCAN1PRIV
rw 		LPTIM3PRIV
rw 		LPTIM2PRIV
rw 		I2C4PRIV
rw 		LPUART1PRIV
rw 		LPTIM1PRIV
rw 		OPAMPPRIV
rw 		DACPRIV
rw 		CRSPRIV
rw 		I2C3PRIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2PRIV
rw 		I2C1PRIV
rw 		UART5PRIV
rw 		UART4PRIV
rw 		USART3PRIV
rw 		USART2PRIV
rw 		SPI3PRIV
rw 		SPI2PRIV
rw 		IWDGPRIV
rw 		WWDGPRIV
rw 		TIM7PRIV
rw 		TIM6PRIV
rw 		TIM5PRIV
rw 		TIM4PRIV
rw 		TIM3PRIV
rw 		TIM2PRIV
rw
Toggle fields

TIM2PRIV

Bit 0: TIM2PRIV.

TIM3PRIV

Bit 1: TIM3PRIV.

TIM4PRIV

Bit 2: TIM4PRIV.

TIM5PRIV

Bit 3: TIM5PRIV.

TIM6PRIV

Bit 4: TIM6PRIV.

TIM7PRIV

Bit 5: TIM7PRIV.

WWDGPRIV

Bit 6: WWDGPRIV.

IWDGPRIV

Bit 7: IWDGPRIV.

SPI2PRIV

Bit 8: SPI2PRIV.

SPI3PRIV

Bit 9: SPI3PRIV.

USART2PRIV

Bit 10: USART2PRIV.

USART3PRIV

Bit 11: USART3PRIV.

UART4PRIV

Bit 12: UART4PRIV.

UART5PRIV

Bit 13: UART5PRIV.

I2C1PRIV

Bit 14: I2C1PRIV.

I2C2PRIV

Bit 15: I2C2PRIV.

I2C3PRIV

Bit 16: I2C3PRIV.

CRSPRIV

Bit 17: CRSPRIV.

DACPRIV

Bit 18: DACPRIV.

OPAMPPRIV

Bit 19: OPAMPPRIV.

LPTIM1PRIV

Bit 20: LPTIM1PRIV.

LPUART1PRIV

Bit 21: LPUART1PRIV.

I2C4PRIV

Bit 22: I2C4PRIV.

LPTIM2PRIV

Bit 23: LPTIM2PRIV.

LPTIM3PRIV

Bit 24: LPTIM3PRIV.

FDCAN1PRIV

Bit 25: FDCAN1PRIV.

USBFSPRIV

Bit 26: USBFSPRIV.

UCPD1PRIV

Bit 27: UCPD1PRIV.

VREFBUFPRIV

Bit 28: VREFBUFPRIV.

COMPPRIV

Bit 29: COMPPRIV.

TIM1PRIV

Bit 30: TIM1PRIV.

SPI1PRIV

Bit 31: SPI1PRIV.

PRIVCFGR2

TZSC privilege configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OCTOSPI1_REGPRIV
rw 		FSMC_REGPRIV
rw 		SDMMC1PRIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAPRIV
rw 		RNGPRIV
rw 		HASHPRIV
rw 		AESPRIV
rw 		ADCPRIV
rw 		ICACHEPRIV
rw 		TSCPRIV
rw 		CRCPRIV
rw 		DFSDM1PRIV
rw 		SAI2PRIV
rw 		SAI1PRIV
rw 		TIM17PRIV
rw 		TIM16PRIV
rw 		TIM15PRIV
rw 		USART1PRIV
rw 		TIM8PRIV
rw
Toggle fields

TIM8PRIV

Bit 0: TIM8PRIV.

USART1PRIV

Bit 1: USART1PRIV.

TIM15PRIV

Bit 2: TIM15PRIV.

TIM16PRIV

Bit 3: TIM16PRIV.

TIM17PRIV

Bit 4: TIM17PRIV.

SAI1PRIV

Bit 5: SAI1PRIV.

SAI2PRIV

Bit 6: SAI2PRIV.

DFSDM1PRIV

Bit 7: DFSDM1PRIV.

CRCPRIV

Bit 8: CRCPRIV.

TSCPRIV

Bit 9: TSCPRIV.

ICACHEPRIV

Bit 10: ICACHEPRIV.

ADCPRIV

Bit 11: ADCPRIV.

AESPRIV

Bit 12: AESPRIV.

HASHPRIV

Bit 13: HASHPRIV.

RNGPRIV

Bit 14: RNGPRIV.

PKAPRIV

Bit 15: PKAPRIV.

SDMMC1PRIV

Bit 16: SDMMC1PRIV.

FSMC_REGPRIV

Bit 17: FSMC_REGPRIV.

OCTOSPI1_REGPRIV

Bit 18: OCTOSPI1_REGRIV.

MPCWM1_NSWMR1

TZSC external memory non-secure watermark register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM1LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM1STRT
rw
Toggle fields

NSWM1STRT

Bits 0-10: NSWM1STRT.

NSWM1LGTH

Bits 16-27: NSWM1LGTH.

MPCWM1_NSWMR2

TZSC external memory non-secure watermark register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

MPCWM2_NSWMR1

TZSC external memory non-secure watermark register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM1LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM1STRT
rw
Toggle fields

NSWM1STRT

Bits 0-10: NSWM1STRT.

NSWM1LGTH

Bits 16-27: NSWM1LGTH.

MPCWM2_NSWMR2

TZSC external memory non-secure watermark register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

MPCWM3_NSWMR1

TZSC external memory non-secure watermark register 2

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

HASH

0x420c0400: Hash processor

17/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HRA0
0x10 HRA1
0x14 HRA2
0x18 HRA3
0x1c HRA4
0x20 IMR
0x24 SR
0xf8 CSR0
0xfc CSR1
0x100 CSR2
0x104 CSR3
0x108 CSR4
0x10c CSR5
0x110 CSR6
0x114 CSR7
0x118 CSR8
0x11c CSR9
0x120 CSR10
0x124 CSR11
0x128 CSR12
0x12c CSR13
0x130 CSR14
0x134 CSR15
0x138 CSR16
0x13c CSR17
0x140 CSR18
0x144 CSR19
0x148 CSR20
0x14c CSR21
0x150 CSR22
0x154 CSR23
0x158 CSR24
0x15c CSR25
0x160 CSR26
0x164 CSR27
0x168 CSR28
0x16c CSR29
0x170 CSR30
0x174 CSR31
0x178 CSR32
0x17c CSR33
0x180 CSR34
0x184 CSR35
0x188 CSR36
0x18c CSR37
0x190 CSR38
0x194 CSR39
0x198 CSR40
0x19c CSR41
0x1a0 CSR42
0x1a4 CSR43
0x1a8 CSR44
0x1ac CSR45
0x1b0 CSR46
0x1b4 CSR47
0x1b8 CSR48
0x1bc CSR49
0x1c0 CSR50
0x1c4 CSR51
0x1c8 CSR52
0x1cc CSR53
0x310 HR0
0x314 HR1
0x318 HR2
0x31c HR3
0x320 HR4
0x324 HR5
0x328 HR6
0x32c HR7
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw 		LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAT
rw 		DINNE
r 		NBW
r 		ALGO0
rw 		MODE
rw 		DATATYPE
rw 		DMAE
rw 		INIT
w
Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

ALGO0

Bit 7: Algorithm selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO1

Bit 18: Algorithm selection.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
rw 		NBLW
rw
Toggle fields

NBLW

Bits 0-4: Number of valid bits in the last word of the message.

DCAL

Bit 8: Digest calculation.

HRA0

HASH aliased digest register 0

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HRA1

HASH aliased digest register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HRA2

HASH aliased digest register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HRA3

HASH aliased digest register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HRA4

HASH aliased digest register 4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

IMR

interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw 		DINIE
rw
Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		DMAS
r 		DCIS
rw 		DINIS
rw
Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

CSR0

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR0
rw
Toggle fields

CSR0

Bits 0-31: CSR0.

CSR1

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR1
rw
Toggle fields

CSR1

Bits 0-31: CSR1.

CSR2

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR2
rw
Toggle fields

CSR2

Bits 0-31: CSR2.

CSR3

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR3
rw
Toggle fields

CSR3

Bits 0-31: CSR3.

CSR4

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR4
rw
Toggle fields

CSR4

Bits 0-31: CSR4.

CSR5

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR5
rw
Toggle fields

CSR5

Bits 0-31: CSR5.

CSR6

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR6
rw
Toggle fields

CSR6

Bits 0-31: CSR6.

CSR7

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR7
rw
Toggle fields

CSR7

Bits 0-31: CSR7.

CSR8

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR8
rw
Toggle fields

CSR8

Bits 0-31: CSR8.

CSR9

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR9
rw
Toggle fields

CSR9

Bits 0-31: CSR9.

CSR10

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR10
rw
Toggle fields

CSR10

Bits 0-31: CSR10.

CSR11

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR11
rw
Toggle fields

CSR11

Bits 0-31: CSR11.

CSR12

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR12
rw
Toggle fields

CSR12

Bits 0-31: CSR12.

CSR13

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR13
rw
Toggle fields

CSR13

Bits 0-31: CSR13.

CSR14

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR14
rw
Toggle fields

CSR14

Bits 0-31: CSR14.

CSR15

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR15
rw
Toggle fields

CSR15

Bits 0-31: CSR15.

CSR16

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR16
rw
Toggle fields

CSR16

Bits 0-31: CSR16.

CSR17

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR17
rw
Toggle fields

CSR17

Bits 0-31: CSR17.

CSR18

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR18
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR18
rw
Toggle fields

CSR18

Bits 0-31: CSR18.

CSR19

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR19
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR19
rw
Toggle fields

CSR19

Bits 0-31: CSR19.

CSR20

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR20
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR20
rw
Toggle fields

CSR20

Bits 0-31: CSR20.

CSR21

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR21
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR21
rw
Toggle fields

CSR21

Bits 0-31: CSR21.

CSR22

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR22
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR22
rw
Toggle fields

CSR22

Bits 0-31: CSR22.

CSR23

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR23
rw
Toggle fields

CSR23

Bits 0-31: CSR23.

CSR24

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR24
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR24
rw
Toggle fields

CSR24

Bits 0-31: CSR24.

CSR25

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR25
rw
Toggle fields

CSR25

Bits 0-31: CSR25.

CSR26

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR26
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR26
rw
Toggle fields

CSR26

Bits 0-31: CSR26.

CSR27

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR27
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR27
rw
Toggle fields

CSR27

Bits 0-31: CSR27.

CSR28

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR28
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR28
rw
Toggle fields

CSR28

Bits 0-31: CSR28.

CSR29

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR29
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR29
rw
Toggle fields

CSR29

Bits 0-31: CSR29.

CSR30

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR30
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR30
rw
Toggle fields

CSR30

Bits 0-31: CSR30.

CSR31

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR31
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR31
rw
Toggle fields

CSR31

Bits 0-31: CSR31.

CSR32

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR32
rw
Toggle fields

CSR32

Bits 0-31: CSR32.

CSR33

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR33
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR33
rw
Toggle fields

CSR33

Bits 0-31: CSR33.

CSR34

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR34
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR34
rw
Toggle fields

CSR34

Bits 0-31: CSR34.

CSR35

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR35
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR35
rw
Toggle fields

CSR35

Bits 0-31: CSR35.

CSR36

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR36
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR36
rw
Toggle fields

CSR36

Bits 0-31: CSR36.

CSR37

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR37
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR37
rw
Toggle fields

CSR37

Bits 0-31: CSR37.

CSR38

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR38
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR38
rw
Toggle fields

CSR38

Bits 0-31: CSR38.

CSR39

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR39
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR39
rw
Toggle fields

CSR39

Bits 0-31: CSR39.

CSR40

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR40
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR40
rw
Toggle fields

CSR40

Bits 0-31: CSR40.

CSR41

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR41
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR41
rw
Toggle fields

CSR41

Bits 0-31: CSR41.

CSR42

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR42
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR42
rw
Toggle fields

CSR42

Bits 0-31: CSR42.

CSR43

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR43
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR43
rw
Toggle fields

CSR43

Bits 0-31: CSR43.

CSR44

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR44
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR44
rw
Toggle fields

CSR44

Bits 0-31: CSR44.

CSR45

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR45
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR45
rw
Toggle fields

CSR45

Bits 0-31: CSR45.

CSR46

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR46
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR46
rw
Toggle fields

CSR46

Bits 0-31: CSR46.

CSR47

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR47
rw
Toggle fields

CSR47

Bits 0-31: CSR47.

CSR48

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR48
rw
Toggle fields

CSR48

Bits 0-31: CSR48.

CSR49

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR49
rw
Toggle fields

CSR49

Bits 0-31: CSR49.

CSR50

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR50
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR50
rw
Toggle fields

CSR50

Bits 0-31: CSR50.

CSR51

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR51
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR51
rw
Toggle fields

CSR51

Bits 0-31: CSR51.

CSR52

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR52
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR52
rw
Toggle fields

CSR52

Bits 0-31: CSR52.

CSR53

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR53
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR53
rw
Toggle fields

CSR53

Bits 0-31: CSR53.

HR0

digest register 0

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HR1

digest register 1

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HR2

digest register 4

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HR3

digest register 3

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HR4

digest register 4

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

HR5

supplementary digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H5
r
Toggle fields

H5

Bits 0-31: H5.

HR6

supplementary digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H6
r
Toggle fields

H6

Bits 0-31: H6.

HR7

supplementary digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H7
r
Toggle fields

H7

Bits 0-31: H7.

I2C1

0x40005400: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C2

0x40005800: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C3

0x40005c00: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C4

0x40008400: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

ICACHE

0x40030400: ICache

5/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 IER
0xc FCR
0x10 HMONR
0x14 MMONR
0x20 CRR[0]
0x24 CRR[1]
0x28 CRR[2]
0x2c CRR[3]
Toggle registers

CR

ICACHE control register

Offset: 0x0, size: 32, reset: 0x00000004, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISSMRST
rw 		HITMRST
rw 		MISSMEN
rw 		HITMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAYSEL
rw 		CACHEINV
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

CACHEINV

Bit 1: CACHEINV.

WAYSEL

Bit 2: WAYSEL.

HITMEN

Bit 16: HITMEN.

MISSMEN

Bit 17: MISSMEN.

HITMRST

Bit 18: HITMRST.

MISSMRST

Bit 19: MISSMRST.

SR

ICACHE status register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRF
r 		BSYENDF
r 		BUSYF
r
Toggle fields

BUSYF

Bit 0: BUSYF.

BSYENDF

Bit 1: BSYENDF.

ERRF

Bit 2: ERRF.

IER

ICACHE interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		BSYENDIE
rw
Toggle fields

BSYENDIE

Bit 1: BSYENDIE.

ERRIE

Bit 2: ERRIE.

FCR

ICACHE flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CERRF
w 		CBSYENDF
w
Toggle fields

CBSYENDF

Bit 1: CBSYENDF.

CERRF

Bit 2: CERRF.

HMONR

ICACHE hit monitor register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HITMON
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HITMON
r
Toggle fields

HITMON

Bits 0-31: HITMON.

MMONR

ICACHE miss monitor register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISSMON
r
Toggle fields

MISSMON

Bits 0-15: MISSMON.

CRR[0]

ICACHE region configuration register

Offset: 0x20, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw 		MSTSEL
rw 		REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw 		RSIZE
rw 		BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[1]

ICACHE region configuration register

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw 		MSTSEL
rw 		REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw 		RSIZE
rw 		BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[2]

ICACHE region configuration register

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw 		MSTSEL
rw 		REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw 		RSIZE
rw 		BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[3]

ICACHE region configuration register

Offset: 0x2c, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw 		MSTSEL
rw 		REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw 		RSIZE
rw 		BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

IWDG

0x40003000: Independent watchdog

3/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 KR
0x4 PR
0x8 RLR
0xc SR
0x10 WINR
Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

LPTIM1

0x40007c00: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw 		RSTARE
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

LPTIM2

0x40009400: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw 		RSTARE
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

LPTIM3

0x40009800: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw 		RSTARE
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

LPUART1

0x40008000: Universal synchronous asynchronous receiver transmitter

22/85 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		STOP
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

STOP

Bits 12-13: STOP bits.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		HDSEL
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

HDSEL

Bit 3: Half-duplex selection.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-19: BRR.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w
Toggle fields

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: TXFRQ.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r 		CTSIF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TCCF

Bit 6: Transmission complete clear flag.

CTSCF

Bit 9: CTS clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

NVIC

0xe000e100: Nested Vectored Interrupt Controller

3/99 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISER0
0x4 ISER1
0x8 ISER2
0xc ISER3
0x80 ICER0
0x84 ICER1
0x88 ICER2
0x8c ICER3
0x100 ISPR0
0x104 ISPR1
0x108 ISPR2
0x10c ISPR3
0x180 ICPR0
0x184 ICPR1
0x188 ICPR2
0x18c ICPR3
0x200 IABR0
0x204 IABR1
0x208 IABR2
0x20c IABR3
0x300 IPR0
0x304 IPR1
0x308 IPR2
0x30c IPR3
0x310 IPR4
0x314 IPR5
0x318 IPR6
0x31c IPR7
0x320 IPR8
0x324 IPR9
0x328 IPR10
0x32c IPR11
0x330 IPR12
0x334 IPR13
0x338 IPR14
0x33c IPR15
0x340 IPR16
0x344 IPR17
0x348 IPR18
0x34c IPR19
0x350 IPR20
0x354 IPR21
0x358 IPR22
0x35c IPR23
0x360 IPR24
0x364 IPR25
0x368 IPR26
0x36c IPR27
0x370 IPR28
0x374 IPR29
Toggle registers

ISER0

Interrupt Set-Enable Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set-Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER3

Interrupt Set-Enable Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

Toggle fields

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear-Enable Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER3

Interrupt Clear-Enable Register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

Toggle fields

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR3

Interrupt Set-Pending Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

Toggle fields

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR3

Interrupt Clear-Pending Register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IABR0

Interrupt Active Bit Register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR2

Interrupt Active Bit Register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR3

Interrupt Active Bit Register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR0

Interrupt Priority Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR18

Interrupt Priority Register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR19

Interrupt Priority Register

Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR20

Interrupt Priority Register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR21

IPR21

Offset: 0x354, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR22

IPR22

Offset: 0x358, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR23

IPR23

Offset: 0x35c, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR24

IPR24

Offset: 0x360, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR25

IPR25

Offset: 0x364, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR26

IPR26

Offset: 0x368, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR27

IPR27

Offset: 0x36c, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR28

IPR28

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR29

IPR29

Offset: 0x374, size: 32, reset: 0x00000000, access: read-write

Toggle fields

NVIC_STIR

0xe000ef00: Nested vectored interrupt controller

0/1 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 STIR
Toggle registers

STIR

Software trigger interrupt register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
rw
Toggle fields

INTID

Bits 0-8: Software generated interrupt ID.

OCTOSPI1

0x44021000: OctoSPI

0/96 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x8 DCR1
0xc DCR2
0x10 DCR3
0x14 DCR4
0x20 SR
0x24 FCR
0x40 DLR
0x48 AR
0x50 DR
0x80 PSMKR
0x88 PSMAR
0x90 PIR
0x100 CCR
0x108 TCR
0x110 IR
0x120 ABR
0x130 LPTR
0x140 WPCCR
0x148 WPTCR
0x150 WPIR
0x160 WPABR
0x180 WCCR
0x188 WTCR
0x190 WIR
0x1a0 WABR
0x200 HLCR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMODE
rw 		PMM
rw 		APMS
rw 		TOIE
rw 		SMIE
rw 		FTIE
rw 		TCIE
rw 		TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw 		FSEL
rw 		DQM
rw 		TCEN
rw 		DMAEN
rw 		ABORT
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTYP
rw 		DEVSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw 		FRCK
rw 		CKMODE
rw
Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

CSHT

Bits 8-10: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-25: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRAPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSBOUND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CSBOUND

Bits 16-20: CS boundary.

DCR4

DCR4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
rw 		BUSY
rw 		TOF
rw 		SMF
rw 		FTF
rw 		TCF
rw 		TEF
rw
Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-13: FIFO level.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w 		CSMF
w 		CTCF
w 		CTEF
w
Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: Data length.

DLR

data length register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: ADDRESS.

AR

address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

DR

data register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: Status mask.

PSMKR

polling status mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: Status match.

PSMAR

polling status match register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: Polling interval.

PIR

polling interval register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw 		DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

CCR

communication configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw 		DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

TCR

timing configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

IR

instruction register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

ABR

alternate bytes register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

LPTR

low-power timeout register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WPCCR

write communication configuration register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw 		DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

WPTCR

write timing configuration register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WPIR

write instruction register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

WPABR

write alternate bytes register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACC
rw 		WZL
rw 		LM
rw
Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

WCCR

WCCR

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH
rw
Toggle fields

REFRESH

Bits 0-15: REFRESH.

WTCR

WTCR

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: IMODE.

IDTR

Bit 3: IDTR.

ISIZE

Bits 4-5: ISIZE.

ADMODE

Bits 8-10: ADMODE.

ADDTR

Bit 11: ADDTR.

ADSIZE

Bits 12-13: ADSIZE.

ABMODE

Bits 16-18: ABMODE.

ABDTR

Bit 19: ABDTR.

ABSIZE

Bits 20-21: ABSIZE.

DMODE

Bits 24-26: DMODE.

DDTR

Bit 27: DDTR.

DQSE

Bit 29: DQSE.

WIR

WIR

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: DCYC.

WABR

WABR

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

HLCR

HyperBusTM latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

OPAMP

0x40007800: Operational amplifiers

0/29 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OPAMP1_CSR
0x4 OPAMP1_OTR
0x8 OPAMP1_LPOTR
0x10 OPAMP2_CRS
0x14 OPAMP2_OTR
0x18 OPAMP2_LPOTR
Toggle registers

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_RANGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw 		USERTRIM
rw 		CALSEL
rw 		CALON
rw 		VP_SEL
rw 		VM_SEL
rw 		PGA_GAIN
rw 		OPAMODE
rw 		OPALPM
rw 		OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: inverting input selection.

VP_SEL

Bit 10: non inverted input selection.

CALON

Bit 12: calibration mode enable.

CALSEL

Bit 13: calibration selection.

USERTRIM

Bit 14: User trimming enable.

CALOUT

Bit 15: Operational amplifier calibration output.

OPA_RANGE

Bit 31: Operational amplifier power supply range for stability.

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw 		TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_LPOTR

OPAMP1 offset trimming register in low-powe mode

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw 		TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_CRS

OPAMP2 control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw 		USERTRIM
rw 		CALSEL
rw 		CALON
rw 		VP_SEL
rw 		VM_SEL
rw 		PGA_GAIN
rw 		OPAMODE
rw 		OPALPM
rw 		OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: inverting input selection.

VP_SEL

Bit 10: non inverted input selection.

CALON

Bit 12: calibration mode enable.

CALSEL

Bit 13: calibration selection.

USERTRIM

Bit 14: User trimming enable.

CALOUT

Bit 15: Operational amplifier calibration output.

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw 		TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_LPOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw 		TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

PWR

0x40007000: Power control

17/322 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc CR4
0x10 SR1
0x14 SR2
0x18 SCR
0x20 PUCRA
0x24 PDCRA
0x28 PUCRB
0x2c PDCRB
0x30 PUCRC
0x34 PDCRC
0x38 PUCRD
0x3c PDCRD
0x40 PUCRE
0x44 PDCRE
0x48 PUCRF
0x4c PDCRF
0x50 PUCRG
0x54 PDCRG
0x58 PUCRH
0x5c PDCRH
0x78 SECCFGR
0x80 PRIVCFGR
Toggle registers

CR1

Power control register 1

Offset: 0x0, size: 32, reset: 0x00000400, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR
rw 		VOS
rw 		DBP
rw 		LPMS
rw
Toggle fields

LPMS

Bits 0-2: Low-power mode selection.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USV
rw 		IOSV
rw 		PVME4
rw 		PVME3
rw 		PVME2
rw 		PVME1
rw 		PLS
rw 		PVDE
rw
Toggle fields

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection.

PVME1

Bit 4: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V.

PVME2

Bit 5: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V.

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

PVME4

Bit 7: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V.

IOSV

Bit 9: VDDIO2 Independent I/Os supply valid.

USV

Bit 10: VDDUSB USB supply valid.

CR3

Power control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCPD_DBDIS
rw 		UCPD_STDBY
rw 		ULPMEN
rw 		APC
rw 		RRS
rw 		EWUP5
rw 		EWUP4
rw 		EWUP3
rw 		EWUP2
rw 		EWUP1
rw
Toggle fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable Wakeup pin WKUP5.

RRS

Bits 8-9: SRAM2 retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration.

ULPMEN

Bit 11: ULPMEN.

UCPD_STDBY

Bit 13: UCPD_STDBY.

UCPD_DBDIS

Bit 14: UCPD_DBDIS.

CR4

Power control register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSLPEN
rw 		SMPSFSTEN
rw 		EXTSMPSEN
rw 		SMPSBYP
rw 		VBRS
rw 		VBE
rw 		WUPP5
rw 		WUPP4
rw 		WUPP3
rw 		WUPP2
rw 		WUPP1
rw
Toggle fields

WUPP1

Bit 0: Wakeup pin WKUP1 polarity.

WUPP2

Bit 1: Wakeup pin WKUP2 polarity.

WUPP3

Bit 2: Wakeup pin WKUP3 polarity.

WUPP4

Bit 3: Wakeup pin WKUP4 polarity.

WUPP5

Bit 4: Wakeup pin WKUP5 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

SMPSBYP

Bit 12: SMPSBYP.

EXTSMPSEN

Bit 13: EXTSMPSEN.

SMPSFSTEN

Bit 14: SMPSFSTEN.

SMPSLPEN

Bit 15: SMPSLPEN.

SR1

Power status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSHPRDY
r 		EXTSMPSRDY
r 		SMPSBYPRDY
r 		SBF
r 		WUF5
r 		WUF4
r 		WUF3
r 		WUF2
r 		WUF1
r
Toggle fields

WUF1

Bit 0: Wakeup flag 1.

WUF2

Bit 1: Wakeup flag 2.

WUF3

Bit 2: Wakeup flag 3.

WUF4

Bit 3: Wakeup flag 4.

WUF5

Bit 4: Wakeup flag 5.

SBF

Bit 8: Standby flag.

SMPSBYPRDY

Bit 12: SMPSBYPRDY.

EXTSMPSRDY

Bit 13: EXTSMPSRDY.

SMPSHPRDY

Bit 15: SMPSHPRDY.

SR2

Power status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO4
r 		PVMO3
r 		PVMO2
r 		PVMO1
r 		PVDO
r 		VOSF
r 		REGLPF
r 		REGLPS
r
Toggle fields

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO1

Bit 12: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V.

PVMO2

Bit 13: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

PVMO4

Bit 15: Peripheral voltage monitoring output: VDDA vs. 2.2 V.

SCR

Power status clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSBF
w 		CWUF5
w 		CWUF4
w 		CWUF3
w 		CWUF2
w 		CWUF1
w
Toggle fields

CWUF1

Bit 0: Clear wakeup flag 1.

CWUF2

Bit 1: Clear wakeup flag 2.

CWUF3

Bit 2: Clear wakeup flag 3.

CWUF4

Bit 3: Clear wakeup flag 4.

CWUF5

Bit 4: Clear wakeup flag 5.

CSBF

Bit 8: Clear standby flag.

PUCRA

Power Port A pull-up control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU14

Bit 14: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD13

Bit 13: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PD15

Bit 15: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD4

Bit 4: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU7

Bit 7: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PU10

Bit 10: Port D pull-up bit y (y=0..15).

PU11

Bit 11: Port D pull-up bit y (y=0..15).

PU12

Bit 12: Port D pull-up bit y (y=0..15).

PU13

Bit 13: Port D pull-up bit y (y=0..15).

PU14

Bit 14: Port D pull-up bit y (y=0..15).

PU15

Bit 15: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD7

Bit 7: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PD10

Bit 10: Port D pull-down bit y (y=0..15).

PD11

Bit 11: Port D pull-down bit y (y=0..15).

PD12

Bit 12: Port D pull-down bit y (y=0..15).

PD13

Bit 13: Port D pull-down bit y (y=0..15).

PD14

Bit 14: Port D pull-down bit y (y=0..15).

PD15

Bit 15: Port D pull-down bit y (y=0..15).

PUCRE

Power Port E pull-up control register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port E pull-up bit y (y=0..15).

PU1

Bit 1: Port E pull-up bit y (y=0..15).

PU2

Bit 2: Port E pull-up bit y (y=0..15).

PU3

Bit 3: Port E pull-up bit y (y=0..15).

PU4

Bit 4: Port E pull-up bit y (y=0..15).

PU5

Bit 5: Port E pull-up bit y (y=0..15).

PU6

Bit 6: Port E pull-up bit y (y=0..15).

PU7

Bit 7: Port E pull-up bit y (y=0..15).

PU8

Bit 8: Port E pull-up bit y (y=0..15).

PU9

Bit 9: Port E pull-up bit y (y=0..15).

PU10

Bit 10: Port E pull-up bit y (y=0..15).

PU11

Bit 11: Port E pull-up bit y (y=0..15).

PU12

Bit 12: Port E pull-up bit y (y=0..15).

PU13

Bit 13: Port E pull-up bit y (y=0..15).

PU14

Bit 14: Port E pull-up bit y (y=0..15).

PU15

Bit 15: Port E pull-up bit y (y=0..15).

PDCRE

Power Port E pull-down control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port E pull-down bit y (y=0..15).

PD1

Bit 1: Port E pull-down bit y (y=0..15).

PD2

Bit 2: Port E pull-down bit y (y=0..15).

PD3

Bit 3: Port E pull-down bit y (y=0..15).

PD4

Bit 4: Port E pull-down bit y (y=0..15).

PD5

Bit 5: Port E pull-down bit y (y=0..15).

PD6

Bit 6: Port E pull-down bit y (y=0..15).

PD7

Bit 7: Port E pull-down bit y (y=0..15).

PD8

Bit 8: Port E pull-down bit y (y=0..15).

PD9

Bit 9: Port E pull-down bit y (y=0..15).

PD10

Bit 10: Port E pull-down bit y (y=0..15).

PD11

Bit 11: Port E pull-down bit y (y=0..15).

PD12

Bit 12: Port E pull-down bit y (y=0..15).

PD13

Bit 13: Port E pull-down bit y (y=0..15).

PD14

Bit 14: Port E pull-down bit y (y=0..15).

PD15

Bit 15: Port E pull-down bit y (y=0..15).

PUCRF

Power Port F pull-up control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port F pull-up bit y (y=0..15).

PU1

Bit 1: Port F pull-up bit y (y=0..15).

PU2

Bit 2: Port F pull-up bit y (y=0..15).

PU3

Bit 3: Port F pull-up bit y (y=0..15).

PU4

Bit 4: Port F pull-up bit y (y=0..15).

PU5

Bit 5: Port F pull-up bit y (y=0..15).

PU6

Bit 6: Port F pull-up bit y (y=0..15).

PU7

Bit 7: Port F pull-up bit y (y=0..15).

PU8

Bit 8: Port F pull-up bit y (y=0..15).

PU9

Bit 9: Port F pull-up bit y (y=0..15).

PU10

Bit 10: Port F pull-up bit y (y=0..15).

PU11

Bit 11: Port F pull-up bit y (y=0..15).

PU12

Bit 12: Port F pull-up bit y (y=0..15).

PU13

Bit 13: Port F pull-up bit y (y=0..15).

PU14

Bit 14: Port F pull-up bit y (y=0..15).

PU15

Bit 15: Port F pull-up bit y (y=0..15).

PDCRF

Power Port F pull-down control register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port F pull-down bit y (y=0..15).

PD1

Bit 1: Port F pull-down bit y (y=0..15).

PD2

Bit 2: Port F pull-down bit y (y=0..15).

PD3

Bit 3: Port F pull-down bit y (y=0..15).

PD4

Bit 4: Port F pull-down bit y (y=0..15).

PD5

Bit 5: Port F pull-down bit y (y=0..15).

PD6

Bit 6: Port F pull-down bit y (y=0..15).

PD7

Bit 7: Port F pull-down bit y (y=0..15).

PD8

Bit 8: Port F pull-down bit y (y=0..15).

PD9

Bit 9: Port F pull-down bit y (y=0..15).

PD10

Bit 10: Port F pull-down bit y (y=0..15).

PD11

Bit 11: Port F pull-down bit y (y=0..15).

PD12

Bit 12: Port F pull-down bit y (y=0..15).

PD13

Bit 13: Port F pull-down bit y (y=0..15).

PD14

Bit 14: Port F pull-down bit y (y=0..15).

PD15

Bit 15: Port F pull-down bit y (y=0..15).

PUCRG

Power Port G pull-up control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRG

Power Port G pull-down control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRH

Power Port H pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

SECCFGR

Power secure configuration register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APCSEC
rw 		VBSEC
rw 		VDMSEC
rw 		LPMSEC
rw 		WUP5SEC
rw 		WUP4SEC
rw 		WUP3SEC
rw 		WUP2SEC
rw 		WUP1SEC
rw
Toggle fields

WUP1SEC

Bit 0: WKUP1 pin security.

WUP2SEC

Bit 1: WKUP2 pin security.

WUP3SEC

Bit 2: WKUP3 pin security.

WUP4SEC

Bit 3: WKUP4 pin security.

WUP5SEC

Bit 4: WKUP5 pin security.

LPMSEC

Bit 8: LPMSEC.

VDMSEC

Bit 9: VDMSEC.

VBSEC

Bit 10: VBSEC.

APCSEC

Bit 11: APCSEC.

PRIVCFGR

Power privilege configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
Toggle fields

PRIV

Bit 0: PRIV.

RCC

0x40021000: Reset and clock control

245/421 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ICSCR
0x8 CFGR
0xc PLLCFGR
0x10 PLLSAI1CFGR
0x14 PLLSAI2CFGR
0x18 CIER
0x1c CIFR
0x20 CICR
0x28 AHB1RSTR
0x2c AHB2RSTR
0x30 AHB3RSTR
0x38 APB1RSTR1
0x3c APB1RSTR2
0x40 APB2RSTR
0x48 AHB1ENR
0x4c AHB2ENR
0x50 AHB3ENR
0x58 APB1ENR1
0x5c APB1ENR2
0x60 APB2ENR
0x68 AHB1SMENR
0x6c AHB2SMENR
0x70 AHB3SMENR
0x78 APB1SMENR1
0x7c APB1SMENR2
0x80 APB2SMENR
0x88 CCIPR1
0x90 BDCR
0x94 CSR
0x98 CRRCR
0x9c CCIPR2
0xb8 SECCFGR
0xbc SECSR
0xe8 AHB1SECSR
0xec AHB2SECSR
0xf0 AHB3SECSR
0xf8 APB1SECSR1
0xfc APB1SECSR2
0x100 APB2SECSR
Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000063, access: Unspecified

11/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		PLLSAI2RDY
r 		PLLSAI2ON
rw 		PLLSAI1RDY
r 		PLLSAI1ON
rw 		PLLRDY
r 		PLLON
rw 		CSSON
w 		HSEBYP
rw 		HSERDY
r 		HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIASFS
rw 		HSIRDY
r 		HSIKERON
rw 		HSION
rw 		MSIRANGE
rw 		MSIRGSEL
w 		MSIPLLEN
rw 		MSIRDY
r 		MSION
rw
Toggle fields

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRGSEL

Bit 3: MSI clock range selection.

MSIRANGE

Bits 4-7: MSI clock ranges.

HSION

Bit 8: HSI clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIKERON

Bit 9: HSI always enable for peripheral kernels.

HSIRDY

Bit 10: HSI clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSIASFS

Bit 11: HSI automatic start from Stop.

HSEON

Bit 16: HSE clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: HSE clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: HSE crystal oscillator bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock security system enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: Main PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: Main PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLSAI1ON

Bit 26: SAI1 PLL enable.

PLLSAI1RDY

Bit 27: SAI1 PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLSAI2ON

Bit 28: SAI2 PLL enable.

PLLSAI2RDY

Bit 29: SAI2 PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PRIV

Bit 31: PRIV.

ICSCR

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x40000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw 		HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM
rw 		MSICAL
r
Toggle fields

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI clock calibration.

HSITRIM

Bits 24-30: HSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
r 		MCOSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK
rw 		PPRE2
rw 		PPRE1
rw 		HPRE
rw 		SWS
r 		SW
rw
Toggle fields

SW

Bits 0-1: System clock switch.

Allowed values:
0: MSI: MSI selected as system clock
1: HSI: HSI selected as system clock
2: HSE: HSE selected as system clock
3: PLL: PLL selected as system clock

SWS

Bits 2-3: System clock switch status.

Allowed values:
0: MSI: MSI oscillator used as system clock
1: HSI: HSI oscillator used as system clock
2: HSE: HSE used as system clock
3: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
0: Div1: SYSCLK not divided
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512

PPRE1

Bits 8-10: PB low-speed prescaler (APB1).

Allowed values:
0: Div1: HCLK not divided
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

Allowed values:
0: Div1: HCLK not divided
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

Allowed values:
0: MSI: MSI oscillator selected as wakeup from stop clock and CSS backup clock
1: HSI: HSI oscillator selected as wakeup from stop clock and CSS backup clock

MCOSEL

Bits 24-27: Microcontroller clock output.

Allowed values:
0: None: MCO output disabled, no clock on MCO
1: SYSCLK: SYSCLK system clock selected
2: MSI: MSI clock selected
3: HSI: HSI clock selected
4: HSE: HSE clock selected
5: PLL: Main PLL clock selected
6: LSI: LSI clock selected
7: LSE: LSE clock selected
8: HSI48: Internal HSI48 clock selected

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

Allowed values:
0: Div1: MCO divided by 1
1: Div2: MCO divided by 2
2: Div4: MCO divided by 4
3: Div8: MCO divided by 8
4: Div16: MCO divided by 16

PLLCFGR

PLL configuration register

Offset: 0xc, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPDIV
rw 		PLLR
rw 		PLLREN
rw 		PLLQ
rw 		PLLQEN
rw 		PLLP
rw 		PLLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw 		PLLM
rw 		PLLSRC
rw
Toggle fields

PLLSRC

Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.

PLLM

Bits 4-7: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.

PLLN

Bits 8-14: Main PLL multiplication factor for VCO.

PLLPEN

Bit 16: Main PLL PLLSAI3CLK output enable.

PLLP

Bit 17: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).

PLLQEN

Bit 20: Main PLL PLLUSB1CLK output enable.

PLLQ

Bits 21-22: Main PLL division factor for PLLUSB1CLK(48 MHz clock).

PLLREN

Bit 24: Main PLL PLLCLK output enable.

PLLR

Bits 25-26: Main PLL division factor for PLLCLK (system clock).

PLLPDIV

Bits 27-31: Main PLL division factor for PLLSAI2CLK.

PLLSAI1CFGR

PLLSAI1 configuration register

Offset: 0x10, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI1PDIV
rw 		PLLSAI1R
rw 		PLLSAI1REN
rw 		PLLSAI1Q
rw 		PLLSAI1QEN
rw 		PLLSAI1P
rw 		PLLSAI1PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI1N
rw 		PLLSAI1M
rw 		PLLSAI1SRC
rw
Toggle fields

PLLSAI1SRC

Bits 0-1: PLLSAI1SRC.

PLLSAI1M

Bits 4-7: Division factor for PLLSAI1 input clock.

PLLSAI1N

Bits 8-14: SAI1PLL multiplication factor for VCO.

PLLSAI1PEN

Bit 16: SAI1PLL PLLSAI1CLK output enable.

PLLSAI1P

Bit 17: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).

PLLSAI1QEN

Bit 20: SAI1PLL PLLUSB2CLK output enable.

PLLSAI1Q

Bits 21-22: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock).

PLLSAI1REN

Bit 24: PLLSAI1 PLLADC1CLK output enable.

PLLSAI1R

Bits 25-26: PLLSAI1 division factor for PLLADC1CLK (ADC clock).

PLLSAI1PDIV

Bits 27-31: PLLSAI1 division factor for PLLSAI1CLK.

PLLSAI2CFGR

PLLSAI2 configuration register

Offset: 0x14, size: 32, reset: 0x00001000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI2PDIV
rw 		PLLSAI2P
rw 		PLLSAI2PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI2N
rw 		PLLSAI2M
rw 		PLLSAI2SRC
rw
Toggle fields

PLLSAI2SRC

Bits 0-1: PLLSAI2SRC.

PLLSAI2M

Bits 4-7: Division factor for PLLSAI2 input clock.

PLLSAI2N

Bits 8-14: SAI2PLL multiplication factor for VCO.

PLLSAI2PEN

Bit 16: SAI2PLL PLLSAI2CLK output enable.

PLLSAI2P

Bit 17: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock).

PLLSAI2PDIV

Bits 27-31: PLLSAI2 division factor for PLLSAI2CLK.

CIER

Clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYIE
rw 		LSECSSIE
rw 		PLLSAI2RDYIE
rw 		PLLSAI1RDYIE
rw 		PLLRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		MSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw
Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLRDYIE

Bit 5: PLL ready interrupt enable.

PLLSAI1RDYIE

Bit 6: PLLSAI1 ready interrupt enable.

PLLSAI2RDYIE

Bit 7: PLLSAI2 ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

HSI48RDYIE

Bit 10: HSI48 ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYF
r 		LSECSSF
r 		CSSF
r 		PLLSAI2RDYF
r 		PLLSAI1RDYF
r 		PLLRDYF
r 		HSERDYF
r 		HSIRDYF
r 		MSIRDYF
r 		LSERDYF
r 		LSIRDYF
r
Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

PLLSAI1RDYF

Bit 6: PLLSAI1 ready interrupt flag.

PLLSAI2RDYF

Bit 7: PLLSAI2 ready interrupt flag.

CSSF

Bit 8: Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

HSI48RDYF

Bit 10: HSI48 ready interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYC
w 		LSECSSC
w 		CSSC
w 		PLLSAI2RDYC
w 		PLLSAI1RDYC
w 		PLLRDYC
w 		HSERDYC
w 		HSIRDYC
w 		MSIRDYC
w 		LSERDYC
w 		LSIRDYC
w
Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

PLLSAI1RDYC

Bit 6: PLLSAI1 ready interrupt clear.

PLLSAI2RDYC

Bit 7: PLLSAI2 ready interrupt clear.

CSSC

Bit 8: Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

HSI48RDYC

Bit 10: HSI48 oscillator ready interrupt clear.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GTZCRST
rw 		TSCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw 		FLASHRST
rw 		DMAMUX1RST
rw 		DMA2RST
rw 		DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1 reset.

Allowed values:
1: Reset: Reset the selected module

DMA2RST

Bit 1: DMA2 reset.

Allowed values:
1: Reset: Reset the selected module

DMAMUX1RST

Bit 2: DMAMUXRST.

Allowed values:
1: Reset: Reset the selected module

FLASHRST

Bit 8: Flash memory interface reset.

Allowed values:
1: Reset: Reset the selected module

CRCRST

Bit 12: CRC reset.

Allowed values:
1: Reset: Reset the selected module

TSCRST

Bit 16: Touch Sensing Controller reset.

Allowed values:
1: Reset: Reset the selected module

GTZCRST

Bit 22: GTZC reset.

Allowed values:
1: Reset: Reset the selected module

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1RST
rw 		OTFDEC1RST
rw 		PKARST
rw 		RNGRST
rw 		HASHRST
rw 		AESRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCRST
rw 		GPIOHRST
rw 		GPIOGRST
rw 		GPIOFRST
rw 		GPIOERST
rw 		GPIODRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: IO port A reset.

Allowed values:
1: Reset: Reset the selected module

GPIOBRST

Bit 1: IO port B reset.

Allowed values:
1: Reset: Reset the selected module

GPIOCRST

Bit 2: IO port C reset.

Allowed values:
1: Reset: Reset the selected module

GPIODRST

Bit 3: IO port D reset.

Allowed values:
1: Reset: Reset the selected module

GPIOERST

Bit 4: IO port E reset.

Allowed values:
1: Reset: Reset the selected module

GPIOFRST

Bit 5: IO port F reset.

Allowed values:
1: Reset: Reset the selected module

GPIOGRST

Bit 6: IO port G reset.

Allowed values:
1: Reset: Reset the selected module

GPIOHRST

Bit 7: IO port H reset.

Allowed values:
1: Reset: Reset the selected module

ADCRST

Bit 13: ADC reset.

Allowed values:
1: Reset: Reset the selected module

AESRST

Bit 16: AES hardware accelerator reset.

Allowed values:
1: Reset: Reset the selected module

HASHRST

Bit 17: Hash reset.

Allowed values:
1: Reset: Reset the selected module

RNGRST

Bit 18: Random number generator reset.

Allowed values:
1: Reset: Reset the selected module

PKARST

Bit 19: PKARST.

Allowed values:
1: Reset: Reset the selected module

OTFDEC1RST

Bit 21: OTFDEC1RST.

Allowed values:
1: Reset: Reset the selected module

SDMMC1RST

Bit 22: SDMMC1 reset.

Allowed values:
1: Reset: Reset the selected module

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1RST
rw 		FMCRST
rw
Toggle fields

FMCRST

Bit 0: Flexible memory controller reset.

Allowed values:
1: Reset: Reset the selected module

OSPI1RST

Bit 8: OSPI1RST.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1RST
rw 		OPAMPRST
rw 		DAC1RST
rw 		PWRRST
rw 		CRSRST
rw 		I2C3RST
rw 		I2C2RST
rw 		I2C1RST
rw 		UART5RST
rw 		UART4RST
rw 		USART3RST
rw 		USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw 		SPI2RST
rw 		TIM7RST
rw 		TIM6RST
rw 		TIM5RST
rw 		TIM4RST
rw 		TIM3RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: TIM3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: TIM3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: TIM5 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: TIM6 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: TIM7 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI2 reset.

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI3 reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART2 reset.

Allowed values:
1: Reset: Reset the selected module

USART3RST

Bit 18: USART3 reset.

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 19: UART4 reset.

Allowed values:
1: Reset: Reset the selected module

UART5RST

Bit 20: UART5 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C2 reset.

Allowed values:
1: Reset: Reset the selected module

I2C3RST

Bit 23: I2C3 reset.

Allowed values:
1: Reset: Reset the selected module

CRSRST

Bit 24: CRS reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

DAC1RST

Bit 29: DAC1 interface reset.

Allowed values:
1: Reset: Reset the selected module

OPAMPRST

Bit 30: OPAMP interface reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1RST
rw 		USBFSRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1RST
rw 		LPTIM3RST
rw 		LPTIM2RST
rw 		I2C4RST
rw 		LPUART1RST
rw
Toggle fields

LPUART1RST

Bit 0: Low-power UART 1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C4RST

Bit 1: I2C4 reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM2RST

Bit 5: Low-power timer 2 reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM3RST

Bit 6: LPTIM3RST.

Allowed values:
1: Reset: Reset the selected module

FDCAN1RST

Bit 9: FDCAN1RST.

Allowed values:
1: Reset: Reset the selected module

USBFSRST

Bit 21: USBFSRST.

Allowed values:
1: Reset: Reset the selected module

UCPD1RST

Bit 23: UCPD1RST.

Allowed values:
1: Reset: Reset the selected module

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1RST
rw 		SAI2RST
rw 		SAI1RST
rw 		TIM17RST
rw 		TIM16RST
rw 		TIM15RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		TIM8RST
rw 		SPI1RST
rw 		TIM1RST
rw 		SYSCFGRST
rw
Toggle fields

SYSCFGRST

Bit 0: System configuration (SYSCFG) reset.

Allowed values:
1: Reset: Reset the selected module

TIM1RST

Bit 11: TIM1 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM8RST

Bit 13: TIM8 timer reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 14: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM15RST

Bit 16: TIM15 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM16RST

Bit 17: TIM16 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM17RST

Bit 18: TIM17 timer reset.

Allowed values:
1: Reset: Reset the selected module

SAI1RST

Bit 21: Serial audio interface 1 (SAI1) reset.

Allowed values:
1: Reset: Reset the selected module

SAI2RST

Bit 22: Serial audio interface 2 (SAI2) reset.

Allowed values:
1: Reset: Reset the selected module

DFSDM1RST

Bit 24: Digital filters for sigma-delata modulators (DFSDM) reset.

Allowed values:
1: Reset: Reset the selected module

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, size: 32, reset: 0x00000100, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GTZCEN
rw 		TSCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		FLASHEN
rw 		DMAMUX1EN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 1: DMA2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMAMUX1EN

Bit 2: DMAMUX clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FLASHEN

Bit 8: Flash memory interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 12: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TSCEN

Bit 16: Touch Sensing Controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GTZCEN

Bit 22: GTZCEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1EN
rw 		OTFDEC1EN
rw 		PKAEN
rw 		RNGEN
rw 		HASHEN
rw 		AESEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCEN
rw 		GPIOHEN
rw 		GPIOGEN
rw 		GPIOFEN
rw 		GPIOEEN
rw 		GPIODEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: IO port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOBEN

Bit 1: IO port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOCEN

Bit 2: IO port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIODEN

Bit 3: IO port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOEEN

Bit 4: IO port E clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOFEN

Bit 5: IO port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOGEN

Bit 6: IO port G clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOHEN

Bit 7: IO port H clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADCEN

Bit 13: ADC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AESEN

Bit 16: AES accelerator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

HASHEN

Bit 17: HASH clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RNGEN

Bit 18: Random Number Generator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PKAEN

Bit 19: PKAEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTFDEC1EN

Bit 21: OTFDEC1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDMMC1EN

Bit 22: SDMMC1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1EN
rw 		FMCEN
rw
Toggle fields

FMCEN

Bit 0: Flexible memory controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OSPI1EN

Bit 8: OSPI1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR1

APB1ENR1

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw 		OPAMPEN
rw 		DAC1EN
rw 		PWREN
rw 		CRSEN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		UART5EN
rw 		UART4EN
rw 		USART3EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP3EN
rw 		SPI2EN
rw 		WWDGEN
rw 		RTCAPBEN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: TIM3 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: TIM4 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: TIM5 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: TIM6 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: TIM7 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RTCAPBEN

Bit 10: RTC APB clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SP3EN

Bit 15: SPI3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 19: UART4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART5EN

Bit 20: UART5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C3EN

Bit 23: I2C3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRSEN

Bit 24: Clock Recovery System clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DAC1EN

Bit 29: DAC1 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OPAMPEN

Bit 30: OPAMP interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM1EN

Bit 31: Low power timer 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1EN
rw 		USBFSEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1EN
rw 		LPTIM3EN
rw 		LPTIM2EN
rw 		I2C4EN
rw 		LPUART1EN
rw
Toggle fields

LPUART1EN

Bit 0: Low power UART 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C4EN

Bit 1: I2C4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM2EN

Bit 5: LPTIM2EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM3EN

Bit 6: LPTIM3EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FDCAN1EN

Bit 9: FDCAN1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USBFSEN

Bit 21: USBFSEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UCPD1EN

Bit 23: UCPD1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2ENR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1EN
rw 		SAI2EN
rw 		SAI1EN
rw 		TIM17EN
rw 		TIM16EN
rw 		TIM15EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw 		TIM8EN
rw 		SPI1EN
rw 		TIM1EN
rw 		SYSCFGEN
rw
Toggle fields

SYSCFGEN

Bit 0: SYSCFG clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM1EN

Bit 11: TIM1 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM8EN

Bit 13: TIM8 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 14: USART1clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM15EN

Bit 16: TIM15 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM16EN

Bit 17: TIM16 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM17EN

Bit 18: TIM17 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI1EN

Bit 21: SAI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI2EN

Bit 22: SAI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DFSDM1EN

Bit 24: DFSDM timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x68, size: 32, reset: 0x00C11307, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESMEN
rw 		GTZCSMEN
rw 		TSCSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw 		SRAM1SMEN
rw 		FLASHSMEN
rw 		DMAMUX1SMEN
rw 		DMA2SMEN
rw 		DMA1SMEN
rw
Toggle fields

DMA1SMEN

Bit 0: DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: DMA2 clocks enable during Sleep and Stop modes.

DMAMUX1SMEN

Bit 2: DMAMUX clock enable during Sleep and Stop modes.

FLASHSMEN

Bit 8: Flash memory interface clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: SRAM1 interface clocks enable during Sleep and Stop modes.

CRCSMEN

Bit 12: CRCSMEN.

TSCSMEN

Bit 16: Touch Sensing Controller clocks enable during Sleep and Stop modes.

GTZCSMEN

Bit 22: GTZCSMEN.

ICACHESMEN

Bit 23: ICACHESMEN.

AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x6c, size: 32, reset: 0x006F22FF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SMEN
rw 		OTFDEC1SMEN
rw 		PKASMEN
rw 		RNGSMEN
rw 		HASHSMEN
rw 		AESSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCFSSMEN
rw 		SRAM2SMEN
rw 		GPIOHSMEN
rw 		GPIOGSMEN
rw 		GPIOFSMEN
rw 		GPIOESMEN
rw 		GPIODSMEN
rw 		GPIOCSMEN
rw 		GPIOBSMEN
rw 		GPIOASMEN
rw
Toggle fields

GPIOASMEN

Bit 0: IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: IO port E clocks enable during Sleep and Stop modes.

GPIOFSMEN

Bit 5: IO port F clocks enable during Sleep and Stop modes.

GPIOGSMEN

Bit 6: IO port G clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: IO port H clocks enable during Sleep and Stop modes.

SRAM2SMEN

Bit 9: SRAM2 interface clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: ADC clocks enable during Sleep and Stop modes.

AESSMEN

Bit 16: AES accelerator clocks enable during Sleep and Stop modes.

HASHSMEN

Bit 17: HASH clock enable during Sleep and Stop modes.

RNGSMEN

Bit 18: Random Number Generator clocks enable during Sleep and Stop modes.

PKASMEN

Bit 19: PKASMEN.

OTFDEC1SMEN

Bit 21: OTFDEC1SMEN.

SDMMC1SMEN

Bit 22: SDMMC1 clocks enable during Sleep and Stop modes.

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, size: 32, reset: 0x00000101, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SMEN
rw 		FMCSMEN
rw
Toggle fields

FMCSMEN

Bit 0: Flexible memory controller clocks enable during Sleep and Stop modes.

OSPI1SMEN

Bit 8: OSPI1SMEN.

APB1SMENR1

APB1SMENR1

Offset: 0x78, size: 32, reset: 0xF1FECC3F, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SMEN
rw 		OPAMPSMEN
rw 		DAC1SMEN
rw 		PWRSMEN
rw 		CRSSMEN
rw 		I2C3SMEN
rw 		I2C2SMEN
rw 		I2C1SMEN
rw 		UART5SMEN
rw 		UART4SMEN
rw 		USART3SMEN
rw 		USART2SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP3SMEN
rw 		SPI2SMEN
rw 		WWDGSMEN
rw 		RTCAPBSMEN
rw 		TIM7SMEN
rw 		TIM6SMEN
rw 		TIM5SMEN
rw 		TIM4SMEN
rw 		TIM3SMEN
rw 		TIM2SMEN
rw
Toggle fields

TIM2SMEN

Bit 0: TIM2 timer clocks enable during Sleep and Stop modes.

TIM3SMEN

Bit 1: TIM3 timer clocks enable during Sleep and Stop modes.

TIM4SMEN

Bit 2: TIM4 timer clocks enable during Sleep and Stop modes.

TIM5SMEN

Bit 3: TIM5 timer clocks enable during Sleep and Stop modes.

TIM6SMEN

Bit 4: TIM6 timer clocks enable during Sleep and Stop modes.

TIM7SMEN

Bit 5: TIM7 timer clocks enable during Sleep and Stop modes.

RTCAPBSMEN

Bit 10: RTC APB clock enable during Sleep and Stop modes.

WWDGSMEN

Bit 11: Window watchdog clocks enable during Sleep and Stop modes.

SPI2SMEN

Bit 14: SPI2 clocks enable during Sleep and Stop modes.

SP3SMEN

Bit 15: SPI3 clocks enable during Sleep and Stop modes.

USART2SMEN

Bit 17: USART2 clocks enable during Sleep and Stop modes.

USART3SMEN

Bit 18: USART3 clocks enable during Sleep and Stop modes.

UART4SMEN

Bit 19: UART4 clocks enable during Sleep and Stop modes.

UART5SMEN

Bit 20: UART5 clocks enable during Sleep and Stop modes.

I2C1SMEN

Bit 21: I2C1 clocks enable during Sleep and Stop modes.

I2C2SMEN

Bit 22: I2C2 clocks enable during Sleep and Stop modes.

I2C3SMEN

Bit 23: I2C3 clocks enable during Sleep and Stop modes.

CRSSMEN

Bit 24: CRS clock enable during Sleep and Stop modes.

PWRSMEN

Bit 28: Power interface clocks enable during Sleep and Stop modes.

DAC1SMEN

Bit 29: DAC1 interface clocks enable during Sleep and Stop modes.

OPAMPSMEN

Bit 30: OPAMP interface clocks enable during Sleep and Stop modes.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during Sleep and Stop modes.

APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x7c, size: 32, reset: 0x00A00223, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1SMEN
rw 		USBFSSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1SMEN
rw 		LPTIM3SMEN
rw 		LPTIM2SMEN
rw 		I2C4SMEN
rw 		LPUART1SMEN
rw
Toggle fields

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during Sleep and Stop modes.

I2C4SMEN

Bit 1: I2C4 clocks enable during Sleep and Stop modes.

LPTIM2SMEN

Bit 5: LPTIM2SMEN.

LPTIM3SMEN

Bit 6: LPTIM3SMEN.

FDCAN1SMEN

Bit 9: FDCAN1SMEN.

USBFSSMEN

Bit 21: USBFSSMEN.

UCPD1SMEN

Bit 23: UCPD1SMEN.

APB2SMENR

APB2SMENR

Offset: 0x80, size: 32, reset: 0x01677801, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SMEN
rw 		SAI2SMEN
rw 		SAI1SMEN
rw 		TIM17SMEN
rw 		TIM16SMEN
rw 		TIM15SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw 		TIM8SMEN
rw 		SPI1SMEN
rw 		TIM1SMEN
rw 		SYSCFGSMEN
rw
Toggle fields

SYSCFGSMEN

Bit 0: SYSCFG clocks enable during Sleep and Stop modes.

TIM1SMEN

Bit 11: TIM1 timer clocks enable during Sleep and Stop modes.

SPI1SMEN

Bit 12: SPI1 clocks enable during Sleep and Stop modes.

TIM8SMEN

Bit 13: TIM8 timer clocks enable during Sleep and Stop modes.

USART1SMEN

Bit 14: USART1clocks enable during Sleep and Stop modes.

TIM15SMEN

Bit 16: TIM15 timer clocks enable during Sleep and Stop modes.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during Sleep and Stop modes.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during Sleep and Stop modes.

SAI1SMEN

Bit 21: SAI1 clocks enable during Sleep and Stop modes.

SAI2SMEN

Bit 22: SAI2 clocks enable during Sleep and Stop modes.

DFSDM1SMEN

Bit 24: DFSDM timer clocks enable during Sleep and Stop modes.

CCIPR1

CCIPR1

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCSEL
rw 		CLK48MSEL
rw 		FDCANSEL
rw 		LPTIM3SEL
rw 		LPTIM2SEL
rw 		LPTIM1SEL
rw 		I2C3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw 		I2C1SEL
rw 		LPUART1SEL
rw 		UART5SEL
rw 		UART4SEL
rw 		USART3SEL
rw 		USART2SEL
rw 		USART1SEL
rw
Toggle fields

USART1SEL

Bits 0-1: USART1 clock source selection.

USART2SEL

Bits 2-3: USART2 clock source selection.

USART3SEL

Bits 4-5: USART3 clock source selection.

UART4SEL

Bits 6-7: UART4 clock source selection.

UART5SEL

Bits 8-9: UART5 clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2C2SEL

Bits 14-15: I2C2 clock source selection.

I2C3SEL

Bits 16-17: I2C3 clock source selection.

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

LPTIM3SEL

Bits 22-23: Low-power timer 3 clock source selection.

FDCANSEL

Bits 24-25: FDCAN clock source selection.

CLK48MSEL

Bits 26-27: 48 MHz clock source selection.

ADCSEL

Bits 28-29: ADCs clock source selection.

BDCR

BDCR

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOSEL
rw 		LSCOEN
rw 		BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		LSESYSRDY
rw 		RTCSEL
rw 		LSESYSEN
rw 		LSECSSD
r 		LSECSSON
rw 		LSEDRV
rw 		LSEBYP
rw 		LSERDY
r 		LSEON
rw
Toggle fields

LSEON

Bit 0: LSE oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: LSE oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: LSE oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

LSEDRV

Bits 3-4: SE oscillator drive capability.

Allowed values:
0: Lower: 'Xtal mode' lower driving capability
1: MediumLow: 'Xtal mode' medium low driving capability
2: MediumHigh: 'Xtal mode' medium high driving capability
3: Higher: 'Xtal mode' higher driving capability

LSECSSON

Bit 5: LSECSSON.

Allowed values:
0: Off: CSS on LSE (32 kHz external oscillator) OFF
1: On: CSS on LSE (32 kHz external oscillator) ON

LSECSSD

Bit 6: LSECSSD.

Allowed values:
0: NoFailure: No failure detected on LSE (32 kHz oscillator)
1: Failure: Failure detected on LSE (32 kHz oscillator)

LSESYSEN

Bit 7: LSESYSEN.

Allowed values:
0: Disabled: LSESYS only enabled when requested by a peripheral or system function
1: Enabled: LSESYS enabled always generated by RCC

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

LSESYSRDY

Bit 11: LSESYSRDY.

Allowed values:
0: NotReady: LSESYS clock not ready
1: Ready: LSESYS clock ready

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

LSCOEN

Bit 24: Low speed clock output enable.

Allowed values:
0: Disabled: LSCO disabled
1: Enabled: LSCO enabled

LSCOSEL

Bit 25: Low speed clock output selection.

Allowed values:
0: LSI: LSI clock selected"
1: LSE: LSE clock selected

CSR

CSR

Offset: 0x94, size: 32, reset: 0x0C000600, access: Unspecified

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRSTF
r 		WWDGRSTF
r 		IWWDGRSTF
r 		SFTRSTF
r 		BORRSTF
r 		PINRSTF
r 		OBLRSTF
r 		RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSISRANGE
rw 		LSIPREDIV
rw 		LSIRDY
r 		LSION
rw
Toggle fields

LSION

Bit 0: LSI oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: LSI oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

LSIPREDIV

Bit 4: LSIPREDIV.

MSISRANGE

Bits 8-11: SI range after Standby mode.

RMVF

Bit 23: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

OBLRSTF

Bit 25: Option byte loader reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PINRSTF

Bit 26: Pin reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

BORRSTF

Bit 27: BOR flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

IWWDGRSTF

Bit 29: Independent window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

CRRCR

Clock recovery RC register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48CAL
r 		HSI48RDY
r 		HSI48ON
rw
Toggle fields

HSI48ON

Bit 0: HSI48 clock enable.

HSI48RDY

Bit 1: HSI48 clock ready flag.

HSI48CAL

Bits 7-15: HSI48 clock calibration.

CCIPR2

Peripherals independent clock configuration register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPISEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMCSEL
rw 		SAI2SEL
rw 		SAI1SEL
rw 		ADFSDMSEL
rw 		DFSDMSEL
rw 		I2C4SEL
rw
Toggle fields

I2C4SEL

Bits 0-1: I2C4 clock source selection.

DFSDMSEL

Bit 2: Digital filter for sigma delta modulator kernel clock source selection.

ADFSDMSEL

Bits 3-4: Digital filter for sigma delta modulator audio clock source selection.

SAI1SEL

Bits 5-7: SAI1 clock source selection.

SAI2SEL

Bits 8-10: SAI2 clock source selection.

SDMMCSEL

Bit 14: SDMMC clock selection.

OSPISEL

Bits 20-21: Octospi clock source selection.

SECCFGR

RCC secure configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMVFSEC
rw 		HSI48SEC
rw 		CLK48MSEC
rw 		PLLSAI2SEC
rw 		PLLSAI1SEC
rw 		PLLSEC
rw 		PRESCSEC
rw 		SYSCLKSEC
rw 		LSESEC
rw 		LSISEC
rw 		MSISEC
rw 		HSESEC
rw 		HSISEC
rw
Toggle fields

HSISEC

Bit 0: HSISEC.

HSESEC

Bit 1: HSESEC.

MSISEC

Bit 2: MSISEC.

LSISEC

Bit 3: LSISEC.

LSESEC

Bit 4: LSESEC.

SYSCLKSEC

Bit 5: SYSCLKSEC.

PRESCSEC

Bit 6: PRESCSEC.

PLLSEC

Bit 7: PLLSEC.

PLLSAI1SEC

Bit 8: PLLSAI1SEC.

PLLSAI2SEC

Bit 9: PLLSAI2SEC.

CLK48MSEC

Bit 10: CLK48MSEC.

HSI48SEC

Bit 11: HSI48SEC.

RMVFSEC

Bit 12: RMVFSEC.

SECSR

RCC secure status register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMVFSECF
rw 		HSI48SECF
rw 		CLK48MSECF
rw 		PLLSAI2SECF
rw 		PLLSAI1SECF
rw 		PLLSECF
rw 		PRESCSECF
rw 		SYSCLKSECF
rw 		LSESECF
rw 		LSISECF
rw 		MSISECF
rw 		HSESECF
rw 		HSISECF
rw
Toggle fields

HSISECF

Bit 0: HSISECF.

HSESECF

Bit 1: HSESECF.

MSISECF

Bit 2: MSISECF.

LSISECF

Bit 3: LSISECF.

LSESECF

Bit 4: LSESECF.

SYSCLKSECF

Bit 5: SYSCLKSECF.

PRESCSECF

Bit 6: PRESCSECF.

PLLSECF

Bit 7: PLLSECF.

PLLSAI1SECF

Bit 8: PLLSAI1SECF.

PLLSAI2SECF

Bit 9: PLLSAI2SECF.

CLK48MSECF

Bit 10: CLK48MSECF.

HSI48SECF

Bit 11: HSI48SECF.

RMVFSECF

Bit 12: RMVFSECF.

AHB1SECSR

RCC AHB1 security status register

Offset: 0xe8, size: 32, reset: 0x00400300, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESECF
r 		GTZCSECF
r 		TSCSECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSECF
r 		SRAM1SECF
r 		FLASHSECF
r 		DMAMUX1SECF
r 		DMA2SECF
r 		DMA1SECF
r
Toggle fields

DMA1SECF

Bit 0: DMA1SECF.

DMA2SECF

Bit 1: DMA2SECF.

DMAMUX1SECF

Bit 2: DMAMUX1SECF.

FLASHSECF

Bit 8: FLASHSECF.

SRAM1SECF

Bit 9: SRAM1SECF.

CRCSECF

Bit 12: CRCSECF.

TSCSECF

Bit 16: TSCSECF.

GTZCSECF

Bit 22: GTZCSECF.

ICACHESECF

Bit 23: ICACHESECF.

AHB2SECSR

RCC AHB2 security status register

Offset: 0xec, size: 32, reset: 0x002002FF, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SECF
r 		OTFDEC1SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2SECF
r 		GPIOHSECF
r 		GPIOGSECF
r 		GPIOFSECF
r 		GPIOESECF
r 		GPIODSECF
r 		GPIOCSECF
r 		GPIOBSECF
r 		GPIOASECF
r
Toggle fields

GPIOASECF

Bit 0: GPIOASECF.

GPIOBSECF

Bit 1: GPIOBSECF.

GPIOCSECF

Bit 2: GPIOCSECF.

GPIODSECF

Bit 3: GPIODSECF.

GPIOESECF

Bit 4: GPIOESECF.

GPIOFSECF

Bit 5: GPIOFSECF.

GPIOGSECF

Bit 6: GPIOGSECF.

GPIOHSECF

Bit 7: GPIOHSECF.

SRAM2SECF

Bit 9: SRAM2SECF.

OTFDEC1SECF

Bit 21: OTFDEC1SECF.

SDMMC1SECF

Bit 22: SDMMC1SECF.

AHB3SECSR

RCC AHB3 security status register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SECF
r 		FSMCSECF
r
Toggle fields

FSMCSECF

Bit 0: FSMCSECF.

OSPI1SECF

Bit 8: OSPI1SECF.

APB1SECSR1

RCC APB1 security status register 1

Offset: 0xf8, size: 32, reset: 0x00000400, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SECF
r 		OPAMPSECF
r 		DACSECF
r 		PWRSECF
r 		CRSSECF
r 		I2C3SECF
r 		I2C2SECF
r 		I2C1SECF
r 		UART5SECF
r 		UART4SECF
r 		UART3SECF
r 		UART2SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3SECF
r 		SPI2SECF
r 		WWDGSECF
r 		RTCAPBSECF
r 		TIM7SECF
r 		TIM6SECF
r 		TIM5SECF
r 		TIM4SECF
r 		TIM3SECF
r 		TIM2SECF
r
Toggle fields

TIM2SECF

Bit 0: TIM2SECF.

TIM3SECF

Bit 1: TIM3SECF.

TIM4SECF

Bit 2: TIM4SECF.

TIM5SECF

Bit 3: TIM5SECF.

TIM6SECF

Bit 4: TIM6SECF.

TIM7SECF

Bit 5: TIM7SECF.

RTCAPBSECF

Bit 10: RTCAPBSECF.

WWDGSECF

Bit 11: WWDGSECF.

SPI2SECF

Bit 14: SPI2SECF.

SPI3SECF

Bit 15: SPI3SECF.

UART2SECF

Bit 17: UART2SECF.

UART3SECF

Bit 18: UART3SECF.

UART4SECF

Bit 19: UART4SECF.

UART5SECF

Bit 20: UART5SECF.

I2C1SECF

Bit 21: I2C1SECF.

I2C2SECF

Bit 22: I2C2SECF.

I2C3SECF

Bit 23: I2C3SECF.

CRSSECF

Bit 24: CRSSECF.

PWRSECF

Bit 28: PWRSECF.

DACSECF

Bit 29: DACSECF.

OPAMPSECF

Bit 30: OPAMPSECF.

LPTIM1SECF

Bit 31: LPTIM1SECF.

APB1SECSR2

RCC APB1 security status register 2

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1SECF
r 		USBFSSECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1SECF
r 		LPTIM3SECF
r 		LPTIM2SECF
r 		I2C4SECF
r 		LPUART1SECF
r
Toggle fields

LPUART1SECF

Bit 0: LPUART1SECF.

I2C4SECF

Bit 1: I2C4SECF.

LPTIM2SECF

Bit 5: LPTIM2SECF.

LPTIM3SECF

Bit 6: LPTIM3SECF.

FDCAN1SECF

Bit 9: FDCAN1SECF.

USBFSSECF

Bit 21: USBFSSECF.

UCPD1SECF

Bit 23: UCPD1SECF.

APB2SECSR

RCC APB2 security status register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SECF
r 		SAI2SECF
r 		SAI1SECF
r 		TIM17SECF
r 		TIM16SECF
r 		TIM15SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SECF
r 		TIM8SECF
r 		SPI1SECF
r 		TIM1SECF
r 		SYSCFGSECF
r
Toggle fields

SYSCFGSECF

Bit 0: SYSCFGSECF.

TIM1SECF

Bit 11: TIM1SECF.

SPI1SECF

Bit 12: SPI1SECF.

TIM8SECF

Bit 13: TIM8SECF.

USART1SECF

Bit 14: USART1SECF.

TIM15SECF

Bit 16: TIM15SECF.

TIM16SECF

Bit 17: TIM16SECF.

TIM17SECF

Bit 18: TIM17SECF.

SAI1SECF

Bit 21: SAI1SECF.

SAI2SECF

Bit 22: SAI2SECF.

DFSDM1SECF

Bit 24: DFSDM1SECF.

RNG

0x420c0800: RNG

4/17 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
0x10 HTCR
Toggle registers

CR

RNG control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONFIGLOCK
rw 		CONDRST
rw 		RNG_CONFIG1
rw 		CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG_CONFIG2
rw 		NISTC
rw 		RNG_CONFIG3
rw 		CED
rw 		IE
rw 		RNGEN
rw
Toggle fields

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

CED

Bit 5: Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled..

RNG_CONFIG3

Bits 8-11: RNG configuration 3.

NISTC

Bit 12: Non NIST compliant.

RNG_CONFIG2

Bits 13-15: RNG configuration 2.

CLKDIV

Bits 16-19: Clock divider factor.

RNG_CONFIG1

Bits 20-25: RNG configuration 1.

CONDRST

Bit 30: Conditioning soft reset.

CONFIGLOCK

Bit 31: RNG Config Lock.

SR

RNG status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw 		CEIS
rw 		SECS
r 		CECS
r 		DRDY
r
Toggle fields

DRDY

Bit 0: Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated..

CECS

Bit 1: Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SECS

Bit 2: Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01).

CEIS

Bit 5: Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SEIS

Bit 6: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register..

DR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: Random data 32-bit random data which are valid when DRDY=1..

HTCR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x10, size: 32, reset: 0x000CAA74, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTCFG
rw
Toggle fields

HTCFG

Bits 0-31: health test configuration.

RTC

0x40002800: Real-time clock

26/147 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 SSR
0xc ICSR
0x10 PRER
0x14 WUTR
0x18 CR
0x1c PRIVCR
0x20 SMCR
0x24 WPR
0x28 CALR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x40 ALRM[A]R
0x44 ALRM[A]SSR
0x48 ALRM[B]R
0x4c ALRM[B]SSR
0x50 SR
0x54 MISR
0x58 SMISR
0x5c SCR
Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

ICSR

RTC initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw 		INITF
r 		RSF
rw 		INITS
r 		SHPF
rw 		WUTWF
r 		ALRBWF
r 		ALRAWF
r
Toggle fields

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUTOCLR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

WUTOCLR

Bits 16-31: WUTOCLR.

CR

RTC control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2EN
rw 		TAMPALRM_TYPE
rw 		TAMPALRM_PU
rw 		TAMPOE
rw 		TAMPTS
rw 		ITSE
rw 		COE
rw 		OSEL
rw 		POL
rw 		COSEL
rw 		BKP
rw 		SUB1H
rw 		ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALRBIE
rw 		ALRAIE
rw 		TSE
rw 		WUTE
rw 		ALRBE
rw 		ALRAE
rw 		FMT
rw 		BYPSHAD
rw 		REFCKON
rw 		TSEDGE
rw 		WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: WUCKSEL.

TSEDGE

Bit 3: TSEDGE.

REFCKON

Bit 4: REFCKON.

BYPSHAD

Bit 5: BYPSHAD.

FMT

Bit 6: FMT.

ALRAE

Bit 8: ALRAE.

ALRBE

Bit 9: ALRBE.

WUTE

Bit 10: WUTE.

TSE

Bit 11: TSE.

ALRAIE

Bit 12: ALRAIE.

ALRBIE

Bit 13: ALRBIE.

WUTIE

Bit 14: WUTIE.

TSIE

Bit 15: TSIE.

ADD1H

Bit 16: ADD1H.

SUB1H

Bit 17: SUB1H.

BKP

Bit 18: BKP.

COSEL

Bit 19: COSEL.

POL

Bit 20: POL.

OSEL

Bits 21-22: OSEL.

COE

Bit 23: COE.

ITSE

Bit 24: ITSE.

TAMPTS

Bit 25: TAMPTS.

TAMPOE

Bit 26: TAMPOE.

TAMPALRM_PU

Bit 29: TAMPALRM_PU.

TAMPALRM_TYPE

Bit 30: TAMPALRM_TYPE.

OUT2EN

Bit 31: OUT2EN.

PRIVCR

RTC privilege mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw 		INITPRIV
rw 		CALPRIV
rw 		TSPRIV
rw 		WUTPRIV
rw 		ALRBPRIV
rw 		ALRAPRIV
rw
Toggle fields

ALRAPRIV

Bit 0: ALRAPRIV.

ALRBPRIV

Bit 1: ALRBPRIV.

WUTPRIV

Bit 2: WUTPRIV.

TSPRIV

Bit 3: TSPRIV.

CALPRIV

Bit 13: CALPRIV.

INITPRIV

Bit 14: INITPRIV.

PRIV

Bit 15: PRIV.

SMCR

RTC secure mode control register

Offset: 0x20, size: 32, reset: 0x0000E00F, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT
rw 		INITDPROT
rw 		CALDPROT
rw 		TSDPROT
rw 		WUTDPROT
rw 		ALRBDPROT
rw 		ALRADPROT
rw
Toggle fields

ALRADPROT

Bit 0: ALRADPROT.

ALRBDPROT

Bit 1: ALRBDPROT.

WUTDPROT

Bit 2: WUTDPROT.

TSDPROT

Bit 3: TSDPROT.

CALDPROT

Bit 13: CALDPROT.

INITDPROT

Bit 14: INITDPROT.

DECPROT

Bit 15: DECPROT.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

CALR

calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		LPCAL
rw 		CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

LPCAL

Bit 12: LPCAL.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

ALRM[A]R

Alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRM[B]R

Alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

SR

RTC status register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSF
r 		TSOVF
r 		TSF
r 		WUTF
r 		ALRBF
r 		ALRAF
r
Toggle fields

ALRAF

Bit 0: ALRAF.

ALRBF

Bit 1: ALRBF.

WUTF

Bit 2: WUTF.

TSF

Bit 3: TSF.

TSOVF

Bit 4: TSOVF.

ITSF

Bit 5: ITSF.

MISR

RTC non-secure masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r 		TSOVMF
r 		TSMF
r 		WUTMF
r 		ALRBMF
r 		ALRAMF
r
Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SMISR

RTC secure masked interrupt status register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r 		TSOVMF
r 		TSMF
r 		WUTMF
r 		ALRBMF
r 		ALRAMF
r
Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SCR

RTC status clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CITSF
w 		CTSOVF
w 		CTSF
w 		CWUTF
w 		CALRBF
w 		CALRAF
w
Toggle fields

CALRAF

Bit 0: CALRAF.

CALRBF

Bit 1: CALRBF.

CWUTF

Bit 2: CWUTF.

CTSF

Bit 3: CTSF.

CTSOVF

Bit 4: CTSOVF.

CITSF

Bit 5: CITSF.

SAI1

0x40015400: Serial audio interface

84/118 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw 		SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN2
rw 		CKEN1
rw 		MICNBR
rw 		PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw 		DLYM[4]L
rw 		DLYM[3]R
rw 		DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw 		DLYM[2]L
rw 		DLYM[1]R
rw 		DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SAI2

0x40015800: Serial audio interface

84/118 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw 		SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN2
rw 		CKEN1
rw 		MICNBR
rw 		PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw 		DLYM[4]L
rw 		DLYM[3]R
rw 		DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw 		DLYM[2]L
rw 		DLYM[1]R
rw 		DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SDMMC1

0x420c8000: SDMMC1

38/125 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SDMMC_POWER
0x4 SDMMC_CLKCR
0x8 SDMMC_ARGR
0xc SDMMC_CMDR
0x10 SDMMC_RESPCMDR
0x14 SDMMC_RESP1R
0x18 SDMMC_RESP2R
0x1c SDMMC_RESP3R
0x20 SDMMC_RESP4R
0x24 SDMMC_DTIMER
0x28 SDMMC_DLENR
0x2c SDMMC_DCTRL
0x30 SDMMC_DCNTR
0x34 SDMMC_STAR
0x38 SDMMC_ICR
0x3c SDMMC_MASKR
0x40 SDMMC_ACKTIMER
0x50 SDMMC_IDMACTRLR
0x54 SDMMC_IDMABSIZER
0x58 SDMMC_IDMABASE0R
0x5c SDMMC_IDMABASE1R
0x80 SDMMC_FIFOR
0x3f4 SDMMC_VER
0x3f8 SDMMC_ID
Toggle registers

SDMMC_POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw 		VSWITCHEN
rw 		VSWITCH
rw 		PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11..

VSWITCH

Bit 2: Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:.

VSWITCHEN

Bit 3: Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:.

DIRPOL

Bit 4: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)..

SDMMC_CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw 		BUSSPEED
rw 		DDR
rw 		HWFC_EN
rw 		NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw 		PWRSAV
rw 		CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc...

PWRSAV

Bit 12: Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:.

WIDBUS

Bits 14-15: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

NEGEDGE

Bit 16: SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge..

HWFC_EN

Bit 17: Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11..

DDR

Bit 18: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0).

BUSSPEED

Bit 19: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

SELCLKRX

Bits 20-21: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

SDMMC_ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register..

SDMMC_CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw 		BOOTMODE
rw 		DTHOLD
rw 		CPSMEN
rw 		WAITPEND
rw 		WAITINT
rw 		WAITRESP
rw 		CMDSTOP
rw 		CMDTRANS
rw 		CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message..

CMDTRANS

Bit 6: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent..

CMDSTOP

Bit 7: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent..

WAITRESP

Bits 8-9: Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response..

WAITINT

Bit 10: CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode..

WAITPEND

Bit 11: CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card..

CPSMEN

Bit 12: Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0..

DTHOLD

Bit 13: Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state..

BOOTMODE

Bit 14: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0).

BOOTEN

Bit 15: Enable boot mode procedure..

CMDSUSPEND

Bit 16: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1..

SDMMC_RESPCMDR

SDMMC command response register

Offset: 0x10, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

SDMMC_RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: see Table 432.

SDMMC_RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: see Table404..

SDMMC_RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: see Table404..

SDMMC_RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: see Table404..

SDMMC_DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods..

SDMMC_DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0..

SDMMC_DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw 		BOOTACKEN
rw 		SDIOEN
rw 		RWMOD
rw 		RWSTOP
rw 		RWSTART
rw 		DBLOCKSIZE
rw 		DTMODE
rw 		DTDIR
rw 		DTEN
rw
Toggle fields

DTEN

Bit 0: Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards..

DTDIR

Bit 1: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DTMODE

Bits 2-3: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DBLOCKSIZE

Bits 4-7: Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered).

RWSTART

Bit 8: Read wait start. If this bit is set, read wait operation starts..

RWSTOP

Bit 9: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state..

RWMOD

Bit 10: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

SDIOEN

Bit 11: SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation..

BOOTACKEN

Bit 12: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

FIFORST

Bit 13: FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs..

SDMMC_DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect..

SDMMC_STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTC
r 		IDMATE
r 		CKSTOP
r 		VSWEND
r 		ACKTIMEOUT
r 		ACKFAIL
r 		SDIOIT
r 		BUSYD0END
r 		BUSYD0
r 		RXFIFOE
r 		TXFIFOE
r 		RXFIFOF
r 		TXFIFOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHF
r 		TXFIFOHE
r 		CPSMACT
r 		DPSMACT
r 		DABORT
r 		DBCKEND
r 		DHOLD
r 		DATAEND
r 		CMDSENT
r 		CMDREND
r 		RXOVERR
r 		TXUNDERR
r 		DTIMEOUT
r 		CTIMEOUT
r 		DCRCFAIL
r 		CCRCFAIL
r
Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CTIMEOUT

Bit 2: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods..

DTIMEOUT

Bit 3: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

TXUNDERR

Bit 4: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

RXOVERR

Bit 5: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDREND

Bit 6: Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDSENT

Bit 7: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DATAEND

Bit 8: Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DHOLD

Bit 9: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DBCKEND

Bit 10: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DABORT

Bit 11: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DPSMACT

Bit 12: Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

CPSMACT

Bit 13: Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

TXFIFOHE

Bit 14: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full..

RXFIFOHF

Bit 15: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty..

TXFIFOF

Bit 16: Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty..

RXFIFOF

Bit 17: Receive FIFO full This bit is cleared when one FIFO location becomes empty..

TXFIFOE

Bit 18: Transmit FIFO empty This bit is cleared when one FIFO location becomes full..

RXFIFOE

Bit 19: Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full..

BUSYD0

Bit 20: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt..

BUSYD0END

Bit 21: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

SDIOIT

Bit 22: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKFAIL

Bit 23: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKTIMEOUT

Bit 24: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

VSWEND

Bit 25: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CKSTOP

Bit 26: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMATE

Bit 27: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMABTC

Bit 28: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

SDMMC_ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCC
rw 		IDMATEC
rw 		CKSTOPC
rw 		VSWENDC
rw 		ACKTIMEOUTC
rw 		ACKFAILC
rw 		SDIOITC
rw 		BUSYD0ENDC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DABORTC
rw 		DBCKENDC
rw 		DHOLDC
rw 		DATAENDC
rw 		CMDSENTC
rw 		CMDRENDC
rw 		RXOVERRC
rw 		TXUNDERRC
rw 		DTIMEOUTC
rw 		CTIMEOUTC
rw 		DCRCFAILC
rw 		CCRCFAILC
rw
Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag..

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag..

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag..

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag..

TXUNDERRC

Bit 4: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag..

RXOVERRC

Bit 5: RXOVERR flag clear bit Set by software to clear the RXOVERR flag..

CMDRENDC

Bit 6: CMDREND flag clear bit Set by software to clear the CMDREND flag..

CMDSENTC

Bit 7: CMDSENT flag clear bit Set by software to clear the CMDSENT flag..

DATAENDC

Bit 8: DATAEND flag clear bit Set by software to clear the DATAEND flag..

DHOLDC

Bit 9: DHOLD flag clear bit Set by software to clear the DHOLD flag..

DBCKENDC

Bit 10: DBCKEND flag clear bit Set by software to clear the DBCKEND flag..

DABORTC

Bit 11: DABORT flag clear bit Set by software to clear the DABORT flag..

BUSYD0ENDC

Bit 21: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag..

SDIOITC

Bit 22: SDIOIT flag clear bit Set by software to clear the SDIOIT flag..

ACKFAILC

Bit 23: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag..

ACKTIMEOUTC

Bit 24: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag..

VSWENDC

Bit 25: VSWEND flag clear bit Set by software to clear the VSWEND flag..

CKSTOPC

Bit 26: CKSTOP flag clear bit Set by software to clear the CKSTOP flag..

IDMATEC

Bit 27: IDMA transfer error clear bit Set by software to clear the IDMATE flag..

IDMABTCC

Bit 28: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag..

SDMMC_MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCIE
rw 		CKSTOPIE
rw 		VSWENDIE
rw 		ACKTIMEOUTIE
rw 		ACKFAILIE
rw 		SDIOITIE
rw 		BUSYD0ENDIE
rw 		TXFIFOEIE
rw 		RXFIFOFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHFIE
rw 		TXFIFOHEIE
rw 		DABORTIE
rw 		DBCKENDIE
rw 		DHOLDIE
rw 		DATAENDIE
rw 		CMDSENTIE
rw 		CMDRENDIE
rw 		RXOVERRIE
rw 		TXUNDERRIE
rw 		DTIMEOUTIE
rw 		CTIMEOUTIE
rw 		DCRCFAILIE
rw 		CCRCFAILIE
rw
Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure..

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure..

CTIMEOUTIE

Bit 2: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout..

DTIMEOUTIE

Bit 3: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout..

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error..

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error..

CMDRENDIE

Bit 6: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response..

CMDSENTIE

Bit 7: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command..

DATAENDIE

Bit 8: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end..

DHOLDIE

Bit 9: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state..

DBCKENDIE

Bit 10: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end..

DABORTIE

Bit 11: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted..

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty..

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full..

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full..

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty..

BUSYD0ENDIE

Bit 21: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response..

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt..

ACKFAILIE

Bit 23: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail..

ACKTIMEOUTIE

Bit 24: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout..

VSWENDIE

Bit 25: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion..

CKSTOPIE

Bit 26: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped..

IDMABTCIE

Bit 28: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer..

SDMMC_ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods..

SDMMC_IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABACT
rw 		IDMABMODE
rw 		IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABMODE

Bit 1: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABACT

Bit 2: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware..

SDMMC_IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
Toggle fields

IDMABNDT

Bits 5-12: Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

SDMMC_IDMABASE0R

The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE0
rw
Toggle fields

IDMABASE0

Bits 0-31: Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)..

SDMMC_IDMABASE1R

The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE1
rw
Toggle fields

IDMABASE1

Bits 0-31: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)..

SDMMC_FIFOR

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words..

SDMMC_VER

SDMMC IP version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: IP minor revision number..

MAJREV

Bits 4-7: IP major revision number..

SDMMC_ID

SDMMC IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: SDMMC IP identification..

SEC_ADC1

0x52028000: Analog-to-Digital Converter

7/130 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
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12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		DEEPPWD
rw 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw 		AWDCH1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		DMACFG
rw 		DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 3-4: RES.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWDCH1CH

Bits 26-30: AWDCH1CH.

JQDIS

Bit 31: JQDIS.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		JOVSE
rw 		ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

JOVSE

Bit 1: DMACFG.

OVSR

Bits 2-4: RES.

OVSS

Bits 5-8: ALIGN.

TOVS

Bit 9: EXTSEL.

ROVSM

Bit 10: EXTEN.

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

HT2

Bits 16-23: HT2.

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

HT3

Bits 16-23: HT3.

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: L.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: regularDATA.

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-5: JEXTSEL.

JEXTEN

Bits 6-7: JEXTEN.

JSQ1

Bits 8-12: JSQ1.

JSQ2

Bits 14-18: JSQ2.

JSQ3

Bits 20-24: JSQ3.

JSQ4

Bits 26-30: JSQ4.

OFR1

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw 		OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-11: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

OFFSET1_EN

Bit 31: OFFSET1_EN.

OFR2

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw 		OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-11: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

OFFSET2_EN

Bit 31: OFFSET2_EN.

OFR3

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw 		OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-11: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

OFFSET3_EN

Bit 31: OFFSET3_EN.

OFR4

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw 		OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-11: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

OFFSET4_EN

Bit 31: OFFSET4_EN.

JDR1

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle fields

AWD2CH

Bits 0-18: AWD2CH.

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle fields

AWD3CH

Bits 0-18: AWD3CH.

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_16_18
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_1_15
rw 		DIFSEL_0
r
Toggle fields

DIFSEL_0

Bit 0: Differential mode for channel 0.

DIFSEL_1_15

Bits 1-15: Differential mode for channels 15 to 1.

DIFSEL_16_18

Bits 16-18: Differential mode for channels 18 to 16.

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

CALFACT_D

Bits 16-22: CALFACT_D.

SEC_ADC2

0x52028100: Analog-to-Digital Converter

7/130 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		DEEPPWD
rw 		ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw 		AWDCH1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		ALIGN
rw 		RES
rw 		DMACFG
rw 		DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 3-4: RES.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWDCH1CH

Bits 26-30: AWDCH1CH.

JQDIS

Bit 31: JQDIS.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		JOVSE
rw 		ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

JOVSE

Bit 1: DMACFG.

OVSR

Bits 2-4: RES.

OVSS

Bits 5-8: ALIGN.

TOVS

Bit 9: EXTSEL.

ROVSM

Bit 10: EXTEN.

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

HT2

Bits 16-23: HT2.

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

HT3

Bits 16-23: HT3.

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: L.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: regularDATA.

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-5: JEXTSEL.

JEXTEN

Bits 6-7: JEXTEN.

JSQ1

Bits 8-12: JSQ1.

JSQ2

Bits 14-18: JSQ2.

JSQ3

Bits 20-24: JSQ3.

JSQ4

Bits 26-30: JSQ4.

OFR1

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw 		OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-11: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

OFFSET1_EN

Bit 31: OFFSET1_EN.

OFR2

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw 		OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-11: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

OFFSET2_EN

Bit 31: OFFSET2_EN.

OFR3

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw 		OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-11: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

OFFSET3_EN

Bit 31: OFFSET3_EN.

OFR4

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw 		OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-11: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

OFFSET4_EN

Bit 31: OFFSET4_EN.

JDR1

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle fields

AWD2CH

Bits 0-18: AWD2CH.

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle fields

AWD3CH

Bits 0-18: AWD3CH.

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_16_18
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_1_15
rw 		DIFSEL_0
r
Toggle fields

DIFSEL_0

Bit 0: Differential mode for channel 0.

DIFSEL_1_15

Bits 1-15: Differential mode for channels 15 to 1.

DIFSEL_16_18

Bits 16-18: Differential mode for channels 18 to 16.

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

CALFACT_D

Bits 16-22: CALFACT_D.

SEC_ADC_Common

0x52028300: Analog-to-Digital Converter

24/33 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x8 CCR
0xc CDR
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQOVF_SLV
r 		AWD3_SLV
r 		AWD2_SLV
r 		AWD1_SLV
r 		JEOS_SLV
r 		JEOC_SLV
r 		OVR_SLV
r 		EOS_SLV
r 		EOC_SLV
r 		EOSMP_SLV
r 		ADRDY_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF_MST
r 		AWD3_MST
r 		AWD2_MST
r 		AWD1_MST
r 		JEOS_MST
r 		JEOC_MST
r 		OVR_MST
r 		EOS_MST
r 		EOC_MST
r 		EOSMP_MST
r 		ADDRDY_MST
r
Toggle fields

ADDRDY_MST

Bit 0: ADDRDY_MST.

EOSMP_MST

Bit 1: EOSMP_MST.

EOC_MST

Bit 2: EOC_MST.

EOS_MST

Bit 3: EOS_MST.

OVR_MST

Bit 4: OVR_MST.

JEOC_MST

Bit 5: JEOC_MST.

JEOS_MST

Bit 6: JEOS_MST.

AWD1_MST

Bit 7: AWD1_MST.

AWD2_MST

Bit 8: AWD2_MST.

AWD3_MST

Bit 9: AWD3_MST.

JQOVF_MST

Bit 10: JQOVF_MST.

ADRDY_SLV

Bit 16: ADRDY_SLV.

EOSMP_SLV

Bit 17: EOSMP_SLV.

EOC_SLV

Bit 18: EOC_SLV.

EOS_SLV

Bit 19: EOS_SLV.

OVR_SLV

Bit 20: OVR_SLV.

JEOC_SLV

Bit 21: JEOC_SLV.

JEOS_SLV

Bit 22: JEOS_SLV.

AWD1_SLV

Bit 23: AWD1_SLV.

AWD2_SLV

Bit 24: AWD2_SLV.

AWD3_SLV

Bit 25: AWD3_SLV.

JQOVF_SLV

Bit 26: JQOVF_SLV.

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH18SEL
rw 		CH17SEL
rw 		VREFEN
rw 		PRESC
rw 		CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMA
rw 		DMACFG
rw 		DELAY
rw 		DUAL
rw
Toggle fields

DUAL

Bits 0-4: DUAL.

DELAY

Bits 8-10: DELAY.

DMACFG

Bit 13: DMACFG.

MDMA

Bits 14-15: MDMA.

CKMODE

Bits 16-17: ADC clock mode.

PRESC

Bits 18-21: ADC prescaler.

VREFEN

Bit 22: VREFINT enable.

CH17SEL

Bit 23: CH17SEL.

CH18SEL

Bit 24: CH18SEL.

CDR

Common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle fields

RDATA_MST

Bits 0-15: RDATA_MST.

RDATA_SLV

Bits 16-31: RDATA_SLV.

SEC_COMP

0x50010200: Comparator

2/23 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 COMP1_CSR
0x4 COMP2_CSR
Toggle registers

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP1_LOCK
w 		COMP1_VALUE
r 		COMP1_SCALEN
rw 		COMP1_BRGEN
rw 		COMP1_BLANKING
rw 		COMP1_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP1_POLARITY
rw 		COMP1_INPSEL
rw 		COMP1_INMSEL
rw 		COMP1_PWRMODE
rw 		COMP1_EN
rw
Toggle fields

COMP1_EN

Bit 0: Comparator 1 enable bit.

COMP1_PWRMODE

Bits 2-3: Power Mode of the comparator 1.

COMP1_INMSEL

Bits 4-6: Comparator 1 Input Minus connection configuration bit.

COMP1_INPSEL

Bit 7: Comparator1 input plus selection bit.

COMP1_POLARITY

Bit 15: Comparator 1 polarity selection bit.

COMP1_HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

COMP1_BLANKING

Bits 18-20: Comparator 1 blanking source selection bits.

COMP1_BRGEN

Bit 22: Scaler bridge enable.

COMP1_SCALEN

Bit 23: Voltage scaler enable bit.

COMP1_VALUE

Bit 30: Comparator 1 output status bit.

COMP1_LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP2_LOCK
w 		COMP2_VALUE
r 		COMP2_SCALEN
rw 		COMP2_BRGEN
rw 		COMP2_BLANKING
rw 		COMP2_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP2_POLARITY
rw 		COMP2_WINMODE
rw 		COMP2_INPSEL
rw 		COMP2_INMSEL
rw 		COMP2_PWRMODE
rw 		COMP2_EN
rw
Toggle fields

COMP2_EN

Bit 0: Comparator 2 enable bit.

COMP2_PWRMODE

Bits 2-3: Power Mode of the comparator 2.

COMP2_INMSEL

Bits 4-6: Comparator 2 Input Minus connection configuration bit.

COMP2_INPSEL

Bit 7: Comparator 2 Input Plus connection configuration bit.

COMP2_WINMODE

Bit 9: Windows mode selection bit.

COMP2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COMP2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

COMP2_BRGEN

Bit 22: Scaler bridge enable.

COMP2_SCALEN

Bit 23: Voltage scaler enable bit.

COMP2_VALUE

Bit 30: Comparator 2 output status bit.

COMP2_LOCK

Bit 31: COMP2_CSR register lock bit.

SEC_CRC

0x50023000: Cyclic redundancy check calculation unit

0/8 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-7: General-purpose 8-bit data register bits.

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
w
Toggle fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle fields

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Polynomialcoefficients
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Polynomialcoefficients
rw
Toggle fields

Polynomialcoefficients

Bits 0-31: Programmable polynomial.

SEC_CRS

0x50006000: Clock recovery system

9/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 ISR
0xc ICR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00004000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw 		SWSYNC
rw 		AUTOTRIMEN
rw 		CEN
rw 		ESYNCIE
rw 		ERRIE
rw 		SYNCWARNIE
rw 		SYNCOKIE
rw
Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-14: HSI48 oscillator smooth trimming.

CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL
rw 		SYNCSRC
rw 		SYNCDIV
rw 		FELIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEDIR
r 		TRIMOVF
r 		SYNCMISS
r 		SYNCERR
r 		ESYNCF
r 		ERRF
r 		SYNCWARNF
r 		SYNCOKF
r
Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ESYNCC
rw 		ERRC
rw 		SYNCWARNC
rw 		SYNCOKC
rw
Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

SEC_DAC

0x50007400: DAC

6/55 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRGR
0x8 DHR12R1
0xc DHR12L1
0x10 DHR8R1
0x14 DHR12R2
0x18 DHR12L2
0x1c DHR8R2
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR1
0x30 DOR2
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR1
0x44 SHSR2
0x48 SHHR
0x4c SHRR
Toggle registers

CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN2
rw 		DMAUDRIE2
rw 		DMAEN2
rw 		MAMP2
rw 		WAVE2
rw 		TSEL23
rw 		TSEL22
rw 		TSEL21
rw 		TSEL20
rw 		TEN2
rw 		EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HFSEL
rw 		CEN1
rw 		DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL13
rw 		TSEL12
rw 		TSEL11
rw 		TSEL10
rw 		TEN1
rw 		EN1
rw
Toggle fields

EN1

Bit 0: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1..

TEN1

Bit 1: DAC channel1 trigger enable.

TSEL10

Bit 2: TSEL10.

TSEL11

Bit 3: TSEL11.

TSEL12

Bit 4: TSEL12.

TSEL13

Bit 5: TSEL13.

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

DMAEN1

Bit 12: DAC channel1 DMA enable This bit is set and cleared by software..

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software..

CEN1

Bit 14: DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

HFSEL

Bit 15: HFSEL.

EN2

Bit 16: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2..

TEN2

Bit 17: DAC channel2 trigger enable.

TSEL20

Bit 18: TSEL20.

TSEL21

Bit 19: TSEL21.

TSEL22

Bit 20: TSEL22.

TSEL23

Bit 21: TSEL23.

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

DMAEN2

Bit 28: DAC channel2 DMA enable This bit is set and cleared by software..

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software..

CEN2

Bit 30: DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w 		SWTRIG1
w
Toggle fields

SWTRIG1

Bit 0: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register..

SWTRIG2

Bit 1: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register..

DHR12R1

DAC channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DHR12L1

DAC channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DHR8R1

DAC channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DHR12R2

DAC channel2 12-bit right aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DHR12L2

DAC channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2..

DHR8R2

DAC channel2 8-bit right-aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw 		DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DOR1

DAC channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle fields

DACC1DOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

DOR2

DAC channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle fields

DACC2DOR

Bits 0-11: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2..

SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST2
r 		CAL_FLAG2
r 		DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST1
r 		CAL_FLAG1
r 		DMAUDR1
rw
Toggle fields

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

CAL_FLAG1

Bit 14: DAC Channel 1 calibration offset status This bit is set and cleared by hardware.

BWST1

Bit 15: DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization)..

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

CAL_FLAG2

Bit 30: DAC Channel 2 calibration offset status This bit is set and cleared by hardware.

BWST2

Bit 31: DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization)..

CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM1
rw
Toggle fields

OTRIM1

Bits 0-4: DAC Channel 1 offset trimming value.

OTRIM2

Bits 16-20: DAC Channel 2 offset trimming value.

MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE1
rw
Toggle fields

MODE1

Bits 0-2: DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode.

MODE2

Bits 16-18: DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode.

SHSR1

DAC Sample and Hold sample time register 1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE1
rw
Toggle fields

TSAMPLE1

Bits 0-9: DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

SHSR2

DAC Sample and Hold sample time register 2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE2
rw
Toggle fields

TSAMPLE2

Bits 0-9: DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored..

SHHR

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD1
rw
Toggle fields

THOLD1

Bits 0-9: DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI.

THOLD2

Bits 16-25: DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI.

SHRR

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH1
rw
Toggle fields

TREFRESH1

Bits 0-7: DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI.

TREFRESH2

Bits 16-23: DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI.

SEC_DFSDM1

0x50016000: Digital filter for sigma delta modulators

84/400 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CH0CFGR1
0x4 CH0CFGR2
0x8 CH0AWSCDR
0xc CH0WDATR
0x10 CH0DATINR
0x14 CH0DLYR
0x20 CH1CFGR1
0x24 CH1CFGR2
0x28 CH1AWSCDR
0x2c CH1WDATR
0x30 CH1DATINR
0x34 CH1DLYR
0x40 CH2CFGR1
0x44 CH2CFGR2
0x48 CH2AWSCDR
0x4c CH2WDATR
0x50 CH2DATINR
0x54 CH2DLYR
0x60 CH3CFGR1
0x64 CH3CFGR2
0x68 CH3AWSCDR
0x6c CH3WDATR
0x70 CH3DATINR
0x74 CH3DLYR
0x80 CH4CFGR1
0x84 CH4CFGR2
0x88 CH4AWSCDR
0x8c CH4WDATR
0x90 CH4DATINR
0x94 CH4DLYR
0xa0 CH5CFGR1
0xa4 CH5CFGR2
0xa8 CH5AWSCDR
0xac CH5WDATR
0xb0 CH5DATINR
0xb4 CH5DLYR
0xc0 CH6CFGR1
0xc4 CH6CFGR2
0xc8 CH6AWSCDR
0xcc CH6WDATR
0xd0 CH6DATINR
0xd4 CH6DLYR
0xe0 CH7CFGR1
0xe4 CH7CFGR2
0xe8 CH7AWSCDR
0xec CH7WDATR
0xf0 CH7DATINR
0xf4 CH7DLYR
0x100 FLT0CR1
0x104 FLT0CR2
0x108 FLT0ISR
0x10c FLT0ICR
0x110 FLT0JCHGR
0x114 FLT0FCR
0x118 FLT0JDATAR
0x11c FLT0RDATAR
0x120 FLT0AWHTR
0x124 FLT0AWLTR
0x128 FLT0AWSR
0x12c FLT0AWCFR
0x130 FLT0EXMAX
0x134 FLT0EXMIN
0x138 FLT0CNVTIMR
0x180 FLT1CR1
0x184 FLT1CR2
0x188 FLT1ISR
0x18c FLT1ICR
0x190 FLT1JCHGR
0x194 FLT1FCR
0x198 FLT1JDATAR
0x19c FLT1RDATAR
0x1a4 FLT1AWLTR
0x1a8 FLT1AWSR
0x1ac FLT1AWCFR
0x1ac FLT1AWHTR
0x1b0 FLT1EXMAX
0x1b4 FLT1EXMIN
0x1b8 FLT1CNVTIMR
0x200 FLT2CR1
0x204 FLT2CR2
0x208 FLT2ISR
0x20c FLT2ICR
0x210 FLT2JCHGR
0x214 FLT2FCR
0x218 FLT2JDATAR
0x21c FLT2RDATAR
0x220 FLT2AWHTR
0x224 FLT2AWLTR
0x228 FLT2AWSR
0x22c FLT2AWCFR
0x230 FLT2EXMAX
0x234 FLT2EXMIN
0x238 FLT2CNVTIMR
0x280 FLT3CR1
0x284 FLT3CR2
0x288 FLT3ISR
0x28c FLT3ICR
0x290 FLT3JCHGR
0x294 FLT3FCR
0x298 FLT3JDATAR
0x29c FLT3RDATAR
0x2a0 FLT3AWHTR
0x2a4 FLT3AWLTR
0x2a8 FLT3AWSR
0x2ac FLT3AWCFR
0x2b0 FLT3EXMAX
0x2b4 FLT3EXMIN
0x2b8 FLT3CNVTIMR
Toggle registers

CH0CFGR1

channel configuration y register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH0CFGR2

channel configuration y register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH0AWSCDR

analog watchdog and short-circuit detector register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH0WDATR

channel watchdog filter data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH0DATINR

channel data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH0DLYR

DFSDM channel y delay register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function.

CH1CFGR1

CHCFG1R1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH1CFGR2

CHCFG1R2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH1AWSCDR

AWSCD1R

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH1WDATR

CHWDAT1R

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH1DATINR

CHDATIN1R

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH1DLYR

DFSDM channel y delay register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH2CFGR1

CHCFG2R1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH2CFGR2

CHCFG2R2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH2AWSCDR

AWSCD2R

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH2WDATR

CHWDAT2R

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH2DATINR

CHDATIN2R

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH2DLYR

DFSDM channel y delay register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH3CFGR1

CHCFG3R1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH3CFGR2

CHCFG3R2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH3AWSCDR

AWSCD3R

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH3WDATR

CHWDAT3R

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH3DATINR

CHDATIN3R

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH3DLYR

DFSDM channel y delay register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH4CFGR1

CHCFG4R1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH4CFGR2

CHCFG4R2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH4AWSCDR

AWSCD4R

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH4WDATR

CHWDAT4R

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH4DATINR

CHDATIN4R

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH4DLYR

DFSDM channel y delay register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH5CFGR1

CHCFG5R1

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH5CFGR2

CHCFG5R2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH5AWSCDR

AWSCD5R

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH5WDATR

CHWDAT5R

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH5DATINR

CHDATIN5R

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH5DLYR

DFSDM channel y delay register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: read-only.

CH6CFGR1

CHCFG6R1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH6CFGR2

CH6CFGR2

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH6AWSCDR

AWSCD6R

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH6WDATR

CHWDAT6R

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH6DATINR

CHDATIN6R

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH6DLYR

DFSDM channel y delay register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH7CFGR1

CHCFG7R1

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH7CFGR2

CHCFG7R2

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH7AWSCDR

AWSCD7R

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH7WDATR

CHWDAT7R

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH7DATINR

CHDATIN7R

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH7DLYR

DFSDM channel y delay register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

FLT0CR1

control register 1

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT0CR2

control register 2

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT0ISR

interrupt and status register

Offset: 0x108, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT0ICR

interrupt flag clear register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT0JCHGR

injected channel group selection register

Offset: 0x110, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT0FCR

filter control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT0JDATAR

data register for injected group

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT0RDATAR

data register for the regular channel

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT0AWHTR

analog watchdog high threshold register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT0AWLTR

analog watchdog low threshold register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT0AWSR

analog watchdog status register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT0AWCFR

analog watchdog clear flag register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT0EXMAX

Extremes detector maximum register

Offset: 0x130, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT0EXMIN

Extremes detector minimum register

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT0CNVTIMR

conversion timer register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT1CR1

control register 1

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT1CR2

control register 2

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT1ISR

interrupt and status register

Offset: 0x188, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT1ICR

interrupt flag clear register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT1JCHGR

injected channel group selection register

Offset: 0x190, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT1FCR

filter control register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT1JDATAR

data register for injected group

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT1RDATAR

data register for the regular channel

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT1AWLTR

analog watchdog low threshold register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT1AWSR

analog watchdog status register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT1AWCFR

analog watchdog clear flag register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT1AWHTR

analog watchdog high threshold register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT1EXMAX

Extremes detector maximum register

Offset: 0x1b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT1EXMIN

Extremes detector minimum register

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT1CNVTIMR

conversion timer register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT2CR1

control register 1

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT2CR2

control register 2

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT2ISR

interrupt and status register

Offset: 0x208, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT2ICR

interrupt flag clear register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT2JCHGR

injected channel group selection register

Offset: 0x210, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT2FCR

filter control register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT2JDATAR

data register for injected group

Offset: 0x218, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT2RDATAR

data register for the regular channel

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT2AWHTR

analog watchdog high threshold register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT2AWLTR

analog watchdog low threshold register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT2AWSR

analog watchdog status register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT2AWCFR

analog watchdog clear flag register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT2EXMAX

Extremes detector maximum register

Offset: 0x230, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT2EXMIN

Extremes detector minimum register

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT2CNVTIMR

conversion timer register

Offset: 0x238, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT3CR1

control register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT3CR2

control register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT3ISR

interrupt and status register

Offset: 0x288, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT3ICR

interrupt flag clear register

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT3JCHGR

injected channel group selection register

Offset: 0x290, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT3FCR

filter control register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT3JDATAR

data register for injected group

Offset: 0x298, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT3RDATAR

data register for the regular channel

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT3AWHTR

analog watchdog high threshold register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT3AWLTR

analog watchdog low threshold register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT3AWSR

analog watchdog status register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT3AWCFR

analog watchdog clear flag register

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT3EXMAX

Extremes detector maximum register

Offset: 0x2b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT3EXMIN

Extremes detector minimum register

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT3CNVTIMR

conversion timer register

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

SEC_DMA1

0x50020000: Direct memory access controller

32/241 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 M0AR [1]
0x18 M1AR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 M0AR [2]
0x2c M1AR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c M0AR [3]
0x40 M1AR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 M0AR [4]
0x54 M1AR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 M0AR [5]
0x68 M1AR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 M0AR [6]
0x7c M1AR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c M0AR [7]
0x90 M1AR [7]
0x94 CR [8]
0x98 NDTR [8]
0x9c PAR [8]
0xa0 M0AR [8]
0xa4 M1AR [8]
0xa8 CSELR
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF8
r 		HTIF8
r 		TCIF8
r 		GIF8
r 		TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle fields

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

GIF8

Bit 28: global interrupt flag for channel 8.

TCIF8

Bit 29: transfer complete (TC) flag for channel 8.

HTIF8

Bit 30: half transfer (HT) flag for channel 8.

TEIF8

Bit 31: transfer error (TE) flag for channel 8.

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF8
w 		CHTIF8
w 		CTCIF8
w 		CGIF8
w 		CTEIF7
w 		CHTIF7
w 		CTCIF7
w 		CGIF7
w 		CTEIF6
w 		CHTIF6
w 		CTCIF6
w 		CGIF6
w 		CTEIF5
w 		CHTIF5
w 		CTCIF5
w 		CGIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4
w 		CHTIF4
w 		CTCIF4
w 		CGIF4
w 		CTEIF3
w 		CHTIF3
w 		CTCIF3
w 		CGIF3
w 		CTEIF2
w 		CHTIF2
w 		CTCIF2
w 		CGIF2
w 		CTEIF1
w 		CHTIF1
w 		CTCIF1
w 		CGIF1
w
Toggle fields

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CGIF8

Bit 28: global interrupt flag clear for channel 8.

CTCIF8

Bit 29: transfer complete flag clear for channel 8.

CHTIF8

Bit 30: half transfer flag clear for channel 8.

CTEIF8

Bit 31: transfer error flag clear for channel 8.

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [1]

channel x memory address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [2]

channel x memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [3]

channel x memory address register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [4]

channel x memory address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [5]

channel x memory address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [6]

channel x memory address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [7]

channel x memory address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [8]

channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [8]

channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [8]

channel x peripheral address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [8]

channel x memory address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [8]

channel x memory address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CSELR

channel selection register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

SEC_DMA2

0x50020400: Direct memory access controller

32/241 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 M0AR [1]
0x18 M1AR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 M0AR [2]
0x2c M1AR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c M0AR [3]
0x40 M1AR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 M0AR [4]
0x54 M1AR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 M0AR [5]
0x68 M1AR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 M0AR [6]
0x7c M1AR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c M0AR [7]
0x90 M1AR [7]
0x94 CR [8]
0x98 NDTR [8]
0x9c PAR [8]
0xa0 M0AR [8]
0xa4 M1AR [8]
0xa8 CSELR
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF8
r 		HTIF8
r 		TCIF8
r 		GIF8
r 		TEIF7
r 		HTIF7
r 		TCIF7
r 		GIF7
r 		TEIF6
r 		HTIF6
r 		TCIF6
r 		GIF6
r 		TEIF5
r 		HTIF5
r 		TCIF5
r 		GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r 		HTIF4
r 		TCIF4
r 		GIF4
r 		TEIF3
r 		HTIF3
r 		TCIF3
r 		GIF3
r 		TEIF2
r 		HTIF2
r 		TCIF2
r 		GIF2
r 		TEIF1
r 		HTIF1
r 		TCIF1
r 		GIF1
r
Toggle fields

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

GIF8

Bit 28: global interrupt flag for channel 8.

TCIF8

Bit 29: transfer complete (TC) flag for channel 8.

HTIF8

Bit 30: half transfer (HT) flag for channel 8.

TEIF8

Bit 31: transfer error (TE) flag for channel 8.

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF8
w 		CHTIF8
w 		CTCIF8
w 		CGIF8
w 		CTEIF7
w 		CHTIF7
w 		CTCIF7
w 		CGIF7
w 		CTEIF6
w 		CHTIF6
w 		CTCIF6
w 		CGIF6
w 		CTEIF5
w 		CHTIF5
w 		CTCIF5
w 		CGIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4
w 		CHTIF4
w 		CTCIF4
w 		CGIF4
w 		CTEIF3
w 		CHTIF3
w 		CTCIF3
w 		CGIF3
w 		CTEIF2
w 		CHTIF2
w 		CTCIF2
w 		CGIF2
w 		CTEIF1
w 		CHTIF1
w 		CTCIF1
w 		CGIF1
w
Toggle fields

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CGIF8

Bit 28: global interrupt flag clear for channel 8.

CTCIF8

Bit 29: transfer complete flag clear for channel 8.

CHTIF8

Bit 30: half transfer flag clear for channel 8.

CTEIF8

Bit 31: transfer error flag clear for channel 8.

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [1]

channel x memory address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [2]

channel x memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [3]

channel x memory address register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [4]

channel x memory address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [5]

channel x memory address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [6]

channel x memory address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [7]

channel x memory address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [8]

channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		DSEC
rw 		SSEC
rw 		SECM
rw 		CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw 		MEM2MEM
rw 		PL
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		TEIE
rw 		HTIE
rw 		TCIE
rw 		EN
rw
Toggle fields

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [8]

channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

PAR [8]

channel x peripheral address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [8]

channel x memory address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [8]

channel x memory address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CSELR

channel selection register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

SEC_DMAMUX1

0x50020800: Direct memory access Multiplexer

4/172 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR[0]
0x4 CCR[1]
0x8 CCR[2]
0xc CCR[3]
0x10 CCR[4]
0x14 CCR[5]
0x18 CCR[6]
0x1c CCR[7]
0x20 CCR[8]
0x24 CCR[9]
0x28 CCR[10]
0x2c CCR[11]
0x30 CCR[12]
0x34 CCR[13]
0x38 CCR[14]
0x3c CCR[15]
0x80 CSR
0x84 CCFR
0x100 RGCR[0]
0x104 RGCR[1]
0x108 RGCR[2]
0x10c RGCR[3]
0x140 RGSR
0x144 RGCFR
Toggle registers

CCR[0]

DMA Multiplexer Channel 0 Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[1]

DMA Multiplexer Channel 1 Control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[2]

DMA Multiplexer Channel 2 Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[3]

DMA Multiplexer Channel 3 Control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[4]

DMA Multiplexer Channel 4 Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[5]

DMA Multiplexer Channel 5 Control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[6]

DMA Multiplexer Channel 6 Control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[7]

DMA Multiplexer Channel 7 Control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[8]

DMA Multiplexer Channel 8 Control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[9]

DMA Multiplexer Channel 9 Control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[10]

DMA Multiplexer Channel 10 Control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[11]

DMA Multiplexer Channel 11 Control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[12]

DMA Multiplexer Channel 12 Control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[13]

DMA Multiplexer Channel 13 Control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[14]

DMA Multiplexer Channel 14 Control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[15]

DMA Multiplexer Channel 15 Control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CSR

DMA Multiplexer Channel Status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF15
rw 		SOF14
rw 		SOF13
rw 		SOF12
rw 		SOF11
rw 		SOF10
rw 		SOF9
rw 		SOF8
rw 		SOF7
rw 		SOF6
rw 		SOF5
rw 		SOF4
rw 		SOF3
rw 		SOF2
rw 		SOF1
rw 		SOF0
rw
Toggle fields

SOF0

Bit 0: Synchronization Overrun Flag 0.

SOF1

Bit 1: Synchronization Overrun Flag 1.

SOF2

Bit 2: Synchronization Overrun Flag 2.

SOF3

Bit 3: Synchronization Overrun Flag 3.

SOF4

Bit 4: Synchronization Overrun Flag 4.

SOF5

Bit 5: Synchronization Overrun Flag 5.

SOF6

Bit 6: Synchronization Overrun Flag 6.

SOF7

Bit 7: Synchronization Overrun Flag 7.

SOF8

Bit 8: Synchronization Overrun Flag 8.

SOF9

Bit 9: Synchronization Overrun Flag 9.

SOF10

Bit 10: Synchronization Overrun Flag 10.

SOF11

Bit 11: Synchronization Overrun Flag 11.

SOF12

Bit 12: Synchronization Overrun Flag 12.

SOF13

Bit 13: Synchronization Overrun Flag 13.

SOF14

Bit 14: Synchronization Overrun Flag 13.

SOF15

Bit 15: Synchronization Overrun Flag 13.

CCFR

DMA Channel Clear Flag Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF15
rw 		CSOF14
rw 		CSOF13
rw 		CSOF12
rw 		CSOF11
rw 		CSOF10
rw 		CSOF9
rw 		CSOF8
rw 		CSOF7
rw 		CSOF6
rw 		CSOF5
rw 		CSOF4
rw 		CSOF3
rw 		CSOF2
rw 		CSOF1
rw 		CSOF0
rw
Toggle fields

CSOF0

Bit 0: Synchronization Clear Overrun Flag 0.

CSOF1

Bit 1: Synchronization Clear Overrun Flag 1.

CSOF2

Bit 2: Synchronization Clear Overrun Flag 2.

CSOF3

Bit 3: Synchronization Clear Overrun Flag 3.

CSOF4

Bit 4: Synchronization Clear Overrun Flag 4.

CSOF5

Bit 5: Synchronization Clear Overrun Flag 5.

CSOF6

Bit 6: Synchronization Clear Overrun Flag 6.

CSOF7

Bit 7: Synchronization Clear Overrun Flag 7.

CSOF8

Bit 8: Synchronization Clear Overrun Flag 8.

CSOF9

Bit 9: Synchronization Clear Overrun Flag 9.

CSOF10

Bit 10: Synchronization Clear Overrun Flag 10.

CSOF11

Bit 11: Synchronization Clear Overrun Flag 11.

CSOF12

Bit 12: Synchronization Clear Overrun Flag 12.

CSOF13

Bit 13: Synchronization Clear Overrun Flag 13.

CSOF14

Bit 14: Synchronization Clear Overrun Flag 13.

CSOF15

Bit 15: Synchronization Clear Overrun Flag 13.

RGCR[0]

DMA Request Generator 0 Control Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[1]

DMA Request Generator 1 Control Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[2]

DMA Request Generator 2 Control Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGCR[3]

DMA Request Generator 3 Control Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGSR

DMA Request Generator Status Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF3
r 		OF2
r 		OF1
r 		OF0
r
Toggle fields

OF0

Bit 0: Generator Overrun Flag 0.

OF1

Bit 1: Generator Overrun Flag 1.

OF2

Bit 2: Generator Overrun Flag 2.

OF3

Bit 3: Generator Overrun Flag 3.

RGCFR

DMA Request Generator Clear Flag Register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF3
rw 		CSOF2
rw 		CSOF1
rw 		CSOF0
rw
Toggle fields

CSOF0

Bit 0: Generator Clear Overrun Flag 0.

CSOF1

Bit 1: Generator Clear Overrun Flag 1.

CSOF2

Bit 2: Generator Clear Overrun Flag 2.

CSOF3

Bit 3: Generator Clear Overrun Flag 3.

SEC_EXTI

0x5002f400: External interrupt/event controller

0/302 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 RTSR1
0x4 FTSR1
0x8 SWIER1
0xc RPR1
0x10 FPR1
0x14 SECCFGR1
0x18 PRIVCFGR1
0x20 RTSR2
0x24 FTSR2
0x28 SWIER2
0x2c RPR2
0x30 FPR2
0x34 PRIVCFGR2
0x38 SECCFGR2
0x60 EXTICR1
0x64 EXTICR2
0x68 EXTICR3
0x6c EXTICR4
0x70 LOCKRG
0x80 IMR1
0x84 EMR1
0x90 IMR2
0x94 EMR2
Toggle registers

RTSR1

EXTI rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT22
rw 		RT21
rw 		RT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT15
rw 		RT14
rw 		RT13
rw 		RT12
rw 		RT11
rw 		RT10
rw 		RT9
rw 		RT8
rw 		RT7
rw 		RT6
rw 		RT5
rw 		RT4
rw 		RT3
rw 		RT2
rw 		RT1
rw 		RT0
rw
Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of configurable event input x.

RT1

Bit 1: Rising trigger event configuration bit of configurable event input x.

RT2

Bit 2: Rising trigger event configuration bit of configurable event input x.

RT3

Bit 3: Rising trigger event configuration bit of configurable event input x.

RT4

Bit 4: Rising trigger event configuration bit of configurable event input x.

RT5

Bit 5: Rising trigger event configuration bit of configurable event input x.

RT6

Bit 6: Rising trigger event configuration bit of configurable event input x.

RT7

Bit 7: Rising trigger event configuration bit of configurable event input x.

RT8

Bit 8: Rising trigger event configuration bit of configurable event input x.

RT9

Bit 9: Rising trigger event configuration bit of configurable event input x.

RT10

Bit 10: Rising trigger event configuration bit of configurable event input x.

RT11

Bit 11: Rising trigger event configuration bit of configurable event input x.

RT12

Bit 12: Rising trigger event configuration bit of configurable event input x.

RT13

Bit 13: Rising trigger event configuration bit of configurable event input x.

RT14

Bit 14: Rising trigger event configuration bit of configurable event input x.

RT15

Bit 15: Rising trigger event configuration bit of configurable event input x.

RT16

Bit 16: Rising trigger event configuration bit of configurable event input x.

RT21

Bit 21: Rising trigger event configuration bit of configurable event input x.

RT22

Bit 22: Rising trigger event configuration bit of configurable event input x.

FTSR1

EXTI falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FT22
rw 		FT21
rw 		FT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT15
rw 		FT14
rw 		FT13
rw 		FT12
rw 		FT11
rw 		FT10
rw 		FT9
rw 		FT8
rw 		FT7
rw 		FT6
rw 		FT5
rw 		FT4
rw 		FT3
rw 		FT2
rw 		FT1
rw 		FT0
rw
Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of configurable event input x.

FT1

Bit 1: Falling trigger event configuration bit of configurable event input x.

FT2

Bit 2: Falling trigger event configuration bit of configurable event input x.

FT3

Bit 3: Falling trigger event configuration bit of configurable event input x.

FT4

Bit 4: Falling trigger event configuration bit of configurable event input x.

FT5

Bit 5: Falling trigger event configuration bit of configurable event input x.

FT6

Bit 6: Falling trigger event configuration bit of configurable event input x.

FT7

Bit 7: Falling trigger event configuration bit of configurable event input x.

FT8

Bit 8: Falling trigger event configuration bit of configurable event input x.

FT9

Bit 9: Falling trigger event configuration bit of configurable event input x.

FT10

Bit 10: Falling trigger event configuration bit of configurable event input x.

FT11

Bit 11: Falling trigger event configuration bit of configurable event input x.

FT12

Bit 12: Falling trigger event configuration bit of configurable event input x.

FT13

Bit 13: Falling trigger event configuration bit of configurable event input x.

FT14

Bit 14: Falling trigger event configuration bit of configurable event input x.

FT15

Bit 15: Falling trigger event configuration bit of configurable event input x.

FT16

Bit 16: Falling trigger event configuration bit of configurable event input x.

FT21

Bit 21: Falling trigger event configuration bit of configurable event input x.

FT22

Bit 22: Falling trigger event configuration bit of configurable event input x.

SWIER1

EXTI software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI22
rw 		SWI21
rw 		SWI16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI15
rw 		SWI14
rw 		SWI13
rw 		SWI12
rw 		SWI11
rw 		SWI10
rw 		SWI9
rw 		SWI8
rw 		SWI7
rw 		SWI6
rw 		SWI5
rw 		SWI4
rw 		SWI3
rw 		SWI2
rw 		SWI1
rw 		SWI0
rw
Toggle fields

SWI0

Bit 0: Software interrupt on event x.

SWI1

Bit 1: Software interrupt on event x.

SWI2

Bit 2: Software interrupt on event x.

SWI3

Bit 3: Software interrupt on event x.

SWI4

Bit 4: Software interrupt on event x.

SWI5

Bit 5: Software interrupt on event x.

SWI6

Bit 6: Software interrupt on event x.

SWI7

Bit 7: Software interrupt on event x.

SWI8

Bit 8: Software interrupt on event x.

SWI9

Bit 9: Software interrupt on event x.

SWI10

Bit 10: Software interrupt on event x.

SWI11

Bit 11: Software interrupt on event x.

SWI12

Bit 12: Software interrupt on event x.

SWI13

Bit 13: Software interrupt on event x.

SWI14

Bit 14: Software interrupt on event x.

SWI15

Bit 15: Software interrupt on event x.

SWI16

Bit 16: Software interrupt on event x.

SWI21

Bit 21: Software interrupt on event x.

SWI22

Bit 22: Software interrupt on event x.

RPR1

EXTI rising edge pending register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPIF22
rw 		RPIF21
rw 		RPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF15
rw 		RPIF14
rw 		RPIF13
rw 		RPIF12
rw 		RPIF11
rw 		RPIF10
rw 		RPIF9
rw 		RPIF8
rw 		RPIF7
rw 		RPIF6
rw 		RPIF5
rw 		RPIF4
rw 		RPIF3
rw 		RPIF2
rw 		RPIF1
rw 		RPIF0
rw
Toggle fields

RPIF0

Bit 0: configurable event inputs x rising edge pending bit.

RPIF1

Bit 1: configurable event inputs x rising edge pending bit.

RPIF2

Bit 2: configurable event inputs x rising edge pending bit.

RPIF3

Bit 3: configurable event inputs x rising edge pending bit.

RPIF4

Bit 4: configurable event inputs x rising edge pending bit.

RPIF5

Bit 5: configurable event inputs x rising edge pending bit.

RPIF6

Bit 6: configurable event inputs x rising edge pending bit.

RPIF7

Bit 7: configurable event inputs x rising edge pending bit.

RPIF8

Bit 8: configurable event inputs x rising edge pending bit.

RPIF9

Bit 9: configurable event inputs x rising edge pending bit.

RPIF10

Bit 10: configurable event inputs x rising edge pending bit.

RPIF11

Bit 11: configurable event inputs x rising edge pending bit.

RPIF12

Bit 12: configurable event inputs x rising edge pending bit.

RPIF13

Bit 13: configurable event inputs x rising edge pending bit.

RPIF14

Bit 14: configurable event inputs x rising edge pending bit.

RPIF15

Bit 15: configurable event inputs x rising edge pending bit.

RPIF16

Bit 16: configurable event inputs x rising edge pending bit.

RPIF21

Bit 21: configurable event inputs x rising edge pending bit.

RPIF22

Bit 22: configurable event inputs x rising edge pending bit.

FPR1

EXTI falling edge pending register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPIF22
rw 		FPIF21
rw 		FPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF15
rw 		FPIF14
rw 		FPIF13
rw 		FPIF12
rw 		FPIF11
rw 		FPIF10
rw 		FPIF9
rw 		FPIF8
rw 		FPIF7
rw 		FPIF6
rw 		FPIF5
rw 		FPIF4
rw 		FPIF3
rw 		FPIF2
rw 		FPIF1
rw 		FPIF0
rw
Toggle fields

FPIF0

Bit 0: configurable event inputs x falling edge pending bit..

FPIF1

Bit 1: configurable event inputs x falling edge pending bit..

FPIF2

Bit 2: configurable event inputs x falling edge pending bit..

FPIF3

Bit 3: configurable event inputs x falling edge pending bit..

FPIF4

Bit 4: configurable event inputs x falling edge pending bit..

FPIF5

Bit 5: configurable event inputs x falling edge pending bit..

FPIF6

Bit 6: configurable event inputs x falling edge pending bit..

FPIF7

Bit 7: configurable event inputs x falling edge pending bit..

FPIF8

Bit 8: configurable event inputs x falling edge pending bit..

FPIF9

Bit 9: configurable event inputs x falling edge pending bit..

FPIF10

Bit 10: configurable event inputs x falling edge pending bit..

FPIF11

Bit 11: configurable event inputs x falling edge pending bit..

FPIF12

Bit 12: configurable event inputs x falling edge pending bit..

FPIF13

Bit 13: configurable event inputs x falling edge pending bit..

FPIF14

Bit 14: configurable event inputs x falling edge pending bit..

FPIF15

Bit 15: configurable event inputs x falling edge pending bit..

FPIF16

Bit 16: configurable event inputs x falling edge pending bit..

FPIF21

Bit 21: configurable event inputs x falling edge pending bit..

FPIF22

Bit 22: configurable event inputs x falling edge pending bit..

SECCFGR1

EXTI security configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEC31
rw 		SEC30
rw 		SEC29
rw 		SEC28
rw 		SEC27
rw 		SEC26
rw 		SEC25
rw 		SEC24
rw 		SEC23
rw 		SEC22
rw 		SEC21
rw 		SEC20
rw 		SEC19
rw 		SEC18
rw 		SEC17
rw 		SEC16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
rw 		SEC14
rw 		SEC13
rw 		SEC12
rw 		SEC11
rw 		SEC10
rw 		SEC9
rw 		SEC8
rw 		SEC7
rw 		SEC6
rw 		SEC5
rw 		SEC4
rw 		SEC3
rw 		SEC2
rw 		SEC1
rw 		SEC0
rw
Toggle fields

SEC0

Bit 0: Security enable on event input x.

SEC1

Bit 1: Security enable on event input x.

SEC2

Bit 2: Security enable on event input x.

SEC3

Bit 3: Security enable on event input x.

SEC4

Bit 4: Security enable on event input x.

SEC5

Bit 5: Security enable on event input x.

SEC6

Bit 6: Security enable on event input x.

SEC7

Bit 7: Security enable on event input x.

SEC8

Bit 8: Security enable on event input x.

SEC9

Bit 9: Security enable on event input x.

SEC10

Bit 10: Security enable on event input x.

SEC11

Bit 11: Security enable on event input x.

SEC12

Bit 12: Security enable on event input x.

SEC13

Bit 13: Security enable on event input x.

SEC14

Bit 14: Security enable on event input x.

SEC15

Bit 15: Security enable on event input x.

SEC16

Bit 16: Security enable on event input x.

SEC17

Bit 17: Security enable on event input x.

SEC18

Bit 18: Security enable on event input x.

SEC19

Bit 19: Security enable on event input x.

SEC20

Bit 20: Security enable on event input x.

SEC21

Bit 21: Security enable on event input x.

SEC22

Bit 22: Security enable on event input x.

SEC23

Bit 23: Security enable on event input x.

SEC24

Bit 24: Security enable on event input x.

SEC25

Bit 25: Security enable on event input x.

SEC26

Bit 26: Security enable on event input x.

SEC27

Bit 27: Security enable on event input x.

SEC28

Bit 28: Security enable on event input x.

SEC29

Bit 29: Security enable on event input x.

SEC30

Bit 30: Security enable on event input x.

SEC31

Bit 31: Security enable on event input x.

PRIVCFGR1

EXTI privilege configuration register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV31
rw 		PRIV30
rw 		PRIV29
rw 		PRIV28
rw 		PRIV27
rw 		PRIV26
rw 		PRIV25
rw 		PRIV24
rw 		PRIV23
rw 		PRIV22
rw 		PRIV21
rw 		PRIV20
rw 		PRIV19
rw 		PRIV18
rw 		PRIV17
rw 		PRIV16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV15
rw 		PRIV14
rw 		PRIV13
rw 		PRIV12
rw 		PRIV11
rw 		PRIV10
rw 		PRIV9
rw 		PRIV8
rw 		PRIV7
rw 		PRIV6
rw 		PRIV5
rw 		PRIV4
rw 		PRIV3
rw 		PRIV2
rw 		PRIV1
rw 		PRIV0
rw
Toggle fields

PRIV0

Bit 0: Security enable on event input x.

PRIV1

Bit 1: Security enable on event input x.

PRIV2

Bit 2: Security enable on event input x.

PRIV3

Bit 3: Security enable on event input x.

PRIV4

Bit 4: Security enable on event input x.

PRIV5

Bit 5: Security enable on event input x.

PRIV6

Bit 6: Security enable on event input x.

PRIV7

Bit 7: Security enable on event input x.

PRIV8

Bit 8: Security enable on event input x.

PRIV9

Bit 9: Security enable on event input x.

PRIV10

Bit 10: Security enable on event input x.

PRIV11

Bit 11: Security enable on event input x.

PRIV12

Bit 12: Security enable on event input x.

PRIV13

Bit 13: Security enable on event input x.

PRIV14

Bit 14: Security enable on event input x.

PRIV15

Bit 15: Security enable on event input x.

PRIV16

Bit 16: Security enable on event input x.

PRIV17

Bit 17: Security enable on event input x.

PRIV18

Bit 18: Security enable on event input x.

PRIV19

Bit 19: Security enable on event input x.

PRIV20

Bit 20: Security enable on event input x.

PRIV21

Bit 21: Security enable on event input x.

PRIV22

Bit 22: Security enable on event input x.

PRIV23

Bit 23: Security enable on event input x.

PRIV24

Bit 24: Security enable on event input x.

PRIV25

Bit 25: Security enable on event input x.

PRIV26

Bit 26: Security enable on event input x.

PRIV27

Bit 27: Security enable on event input x.

PRIV28

Bit 28: Security enable on event input x.

PRIV29

Bit 29: Security enable on event input x.

PRIV30

Bit 30: Security enable on event input x.

PRIV31

Bit 31: Security enable on event input x.

RTSR2

EXTI rising trigger selection register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT38
rw 		RT37
rw 		RT36
rw 		RT35
rw
Toggle fields

RT35

Bit 3: Rising trigger event configuration bit of configurable event input x.

RT36

Bit 4: Rising trigger event configuration bit of configurable event input x.

RT37

Bit 5: Rising trigger event configuration bit of configurable event input x.

RT38

Bit 6: Rising trigger event configuration bit of configurable event input x.

FTSR2

EXTI falling trigger selection register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT38
rw 		FT37
rw 		FT36
rw 		FT35
rw
Toggle fields

FT35

Bit 3: FT35.

FT36

Bit 4: FT36.

FT37

Bit 5: FT37.

FT38

Bit 6: FT38.

SWIER2

EXTI software interrupt event register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI38
rw 		SWI37
rw 		SWI36
rw 		SWI35
rw
Toggle fields

SWI35

Bit 3: SWI35.

SWI36

Bit 4: SWI36.

SWI37

Bit 5: SWI37.

SWI38

Bit 6: SWI38.

RPR2

EXTI rising edge pending register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF38
rw 		RPIF37
rw 		RPIF36
rw 		RPIF35
rw
Toggle fields

RPIF35

Bit 3: RPIF35.

RPIF36

Bit 4: RPIF36.

RPIF37

Bit 5: RPIF37.

RPIF38

Bit 6: RPIF38.

FPR2

EXTI falling edge pending register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF38
rw 		FPIF37
rw 		FPIF36
rw 		FPIF35
rw
Toggle fields

FPIF35

Bit 3: FPIF35.

FPIF36

Bit 4: FPIF36.

FPIF37

Bit 5: FPIF37.

FPIF38

Bit 6: FPIF38.

PRIVCFGR2

EXTI security enable register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV42
rw 		PRIV41
rw 		PRIV40
rw 		PRIV39
rw 		PRIV38
rw 		PRIV37
rw 		PRIV36
rw 		PRIV35
rw 		PRIV34
rw 		PRIV33
rw 		PRIV32
rw
Toggle fields

PRIV32

Bit 0: PRIV32.

PRIV33

Bit 1: PRIV33.

PRIV34

Bit 2: PRIV34.

PRIV35

Bit 3: PRIV35.

PRIV36

Bit 4: PRIV36.

PRIV37

Bit 5: PRIV37.

PRIV38

Bit 6: PRIV38.

PRIV39

Bit 7: PRIV39.

PRIV40

Bit 8: PRIV40.

PRIV41

Bit 9: PRIV41.

PRIV42

Bit 10: PRIV42.

SECCFGR2

EXTI security enable register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC42
rw 		SEC41
rw 		SEC40
rw 		SEC39
rw 		SEC38
rw 		SEC37
rw 		SEC36
rw 		SEC35
rw 		SEC34
rw 		SEC33
rw 		SEC32
rw
Toggle fields

SEC32

Bit 0: SEC32.

SEC33

Bit 1: SEC33.

SEC34

Bit 2: SEC34.

SEC35

Bit 3: SEC35.

SEC36

Bit 4: SEC36.

SEC37

Bit 5: SEC37.

SEC38

Bit 6: SEC38.

SEC39

Bit 7: SEC39.

SEC40

Bit 8: SEC40.

SEC41

Bit 9: SEC41.

SEC42

Bit 10: SEC42.

EXTICR1

EXTI external interrupt selection register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI24_31
rw 		EXTI16_23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI8_15
rw 		EXTI0_7
rw
Toggle fields

EXTI0_7

Bits 0-7: EXTIm GPIO port selection.

EXTI8_15

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI16_23

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI24_31

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR2

EXTI external interrupt selection register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI24_31
rw 		EXTI16_23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI8_15
rw 		EXTI0_7
rw
Toggle fields

EXTI0_7

Bits 0-7: EXTIm GPIO port selection.

EXTI8_15

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI16_23

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI24_31

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR3

EXTI external interrupt selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI24_31
rw 		EXTI16_23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI8_15
rw 		EXTI0_7
rw
Toggle fields

EXTI0_7

Bits 0-7: EXTIm GPIO port selection.

EXTI8_15

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI16_23

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI24_31

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR4

EXTI external interrupt selection register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI24_31
rw 		EXTI16_23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI8_15
rw 		EXTI0_7
rw
Toggle fields

EXTI0_7

Bits 0-7: EXTIm GPIO port selection.

EXTI8_15

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI16_23

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI24_31

Bits 24-31: EXTIm+3 GPIO port selection.

LOCKRG

EXTI lock register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
rw
Toggle fields

LOCK

Bit 0: LOCK.

IMR1

EXTI CPU wakeup with interrupt mask register

Offset: 0x80, size: 32, reset: 0xFF9E0000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31
rw 		IM30
rw 		IM29
rw 		IM28
rw 		IM27
rw 		IM26
rw 		IM25
rw 		IM24
rw 		IM23
rw 		IM22
rw 		IM21
rw 		IM20
rw 		IM19
rw 		IM18
rw 		IM17
rw 		IM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15
rw 		IM14
rw 		IM13
rw 		IM12
rw 		IM11
rw 		IM10
rw 		IM9
rw 		IM8
rw 		IM7
rw 		IM6
rw 		IM5
rw 		IM4
rw 		IM3
rw 		IM2
rw 		IM1
rw 		IM0
rw
Toggle fields

IM0

Bit 0: CPU wakeup with interrupt mask on event input.

IM1

Bit 1: CPU wakeup with interrupt mask on event input.

IM2

Bit 2: CPU wakeup with interrupt mask on event input.

IM3

Bit 3: CPU wakeup with interrupt mask on event input.

IM4

Bit 4: CPU wakeup with interrupt mask on event input.

IM5

Bit 5: CPU wakeup with interrupt mask on event input.

IM6

Bit 6: CPU wakeup with interrupt mask on event input.

IM7

Bit 7: CPU wakeup with interrupt mask on event input.

IM8

Bit 8: CPU wakeup with interrupt mask on event input.

IM9

Bit 9: CPU wakeup with interrupt mask on event input.

IM10

Bit 10: CPU wakeup with interrupt mask on event input.

IM11

Bit 11: CPU wakeup with interrupt mask on event input.

IM12

Bit 12: CPU wakeup with interrupt mask on event input.

IM13

Bit 13: CPU wakeup with interrupt mask on event input.

IM14

Bit 14: CPU wakeup with interrupt mask on event input.

IM15

Bit 15: CPU wakeup with interrupt mask on event input.

IM16

Bit 16: CPU wakeup with interrupt mask on event input.

IM17

Bit 17: CPU wakeup with interrupt mask on event input.

IM18

Bit 18: CPU wakeup with interrupt mask on event input.

IM19

Bit 19: CPU wakeup with interrupt mask on event input.

IM20

Bit 20: CPU wakeup with interrupt mask on event input.

IM21

Bit 21: CPU wakeup with interrupt mask on event input.

IM22

Bit 22: CPU wakeup with interrupt mask on event input.

IM23

Bit 23: CPU wakeup with interrupt mask on event input.

IM24

Bit 24: CPU wakeup with interrupt mask on event input.

IM25

Bit 25: CPU wakeup with interrupt mask on event input.

IM26

Bit 26: CPU wakeup with interrupt mask on event input.

IM27

Bit 27: CPU wakeup with interrupt mask on event input.

IM28

Bit 28: CPU wakeup with interrupt mask on event input.

IM29

Bit 29: CPU wakeup with interrupt mask on event input.

IM30

Bit 30: CPU wakeup with interrupt mask on event input.

IM31

Bit 31: CPU wakeup with interrupt mask on event input.

EMR1

EXTI CPU wakeup with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM31
rw 		EM30
rw 		EM29
rw 		EM28
rw 		EM27
rw 		EM26
rw 		EM25
rw 		EM24
rw 		EM23
rw 		EM22
rw 		EM21
rw 		EM20
rw 		EM19
rw 		EM18
rw 		EM17
rw 		EM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw 		EM14
rw 		EM13
rw 		EM12
rw 		EM11
rw 		EM10
rw 		EM9
rw 		EM8
rw 		EM7
rw 		EM6
rw 		EM5
rw 		EM4
rw 		EM3
rw 		EM2
rw 		EM1
rw 		EM0
rw
Toggle fields

EM0

Bit 0: CPU wakeup with interrupt mask on event input.

EM1

Bit 1: CPU wakeup with interrupt mask on event input.

EM2

Bit 2: CPU wakeup with interrupt mask on event input.

EM3

Bit 3: CPU wakeup with interrupt mask on event input.

EM4

Bit 4: CPU wakeup with interrupt mask on event input.

EM5

Bit 5: CPU wakeup with interrupt mask on event input.

EM6

Bit 6: CPU wakeup with interrupt mask on event input.

EM7

Bit 7: CPU wakeup with interrupt mask on event input.

EM8

Bit 8: CPU wakeup with interrupt mask on event input.

EM9

Bit 9: CPU wakeup with interrupt mask on event input.

EM10

Bit 10: CPU wakeup with interrupt mask on event input.

EM11

Bit 11: CPU wakeup with interrupt mask on event input.

EM12

Bit 12: CPU wakeup with interrupt mask on event input.

EM13

Bit 13: CPU wakeup with interrupt mask on event input.

EM14

Bit 14: CPU wakeup with interrupt mask on event input.

EM15

Bit 15: CPU wakeup with interrupt mask on event input.

EM16

Bit 16: CPU wakeup with interrupt mask on event input.

EM17

Bit 17: CPU wakeup with interrupt mask on event input.

EM18

Bit 18: CPU wakeup with interrupt mask on event input.

EM19

Bit 19: CPU wakeup with interrupt mask on event input.

EM20

Bit 20: CPU wakeup with interrupt mask on event input.

EM21

Bit 21: CPU wakeup with interrupt mask on event input.

EM22

Bit 22: CPU wakeup with interrupt mask on event input.

EM23

Bit 23: CPU wakeup with interrupt mask on event input.

EM24

Bit 24: CPU wakeup with interrupt mask on event input.

EM25

Bit 25: CPU wakeup with interrupt mask on event input.

EM26

Bit 26: CPU wakeup with interrupt mask on event input.

EM27

Bit 27: CPU wakeup with interrupt mask on event input.

EM28

Bit 28: CPU wakeup with interrupt mask on event input.

EM29

Bit 29: CPU wakeup with interrupt mask on event input.

EM30

Bit 30: CPU wakeup with interrupt mask on event input.

EM31

Bit 31: CPU wakeup with interrupt mask on event input.

IMR2

EXTI CPUm wakeup with interrupt mask register

Offset: 0x90, size: 32, reset: 0x00000787, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM42
rw 		IM41
rw 		IM40
rw 		IM38
rw 		IM37
rw 		IM36
rw 		IM35
rw 		IM34
rw 		IM33
rw 		IM32
rw
Toggle fields

IM32

Bit 0: CPU wakeup with interrupt mask on event input.

IM33

Bit 1: CPU wakeup with interrupt mask on event input.

IM34

Bit 2: CPU wakeup with interrupt mask on event input.

IM35

Bit 3: CPU wakeup with interrupt mask on event input.

IM36

Bit 4: CPU wakeup with interrupt mask on event input.

IM37

Bit 5: CPU wakeup with interrupt mask on event input.

IM38

Bit 6: CPU wakeup with interrupt mask on event input.

IM40

Bit 8: CPU wakeup with interrupt mask on event input.

IM41

Bit 9: CPU wakeup with interrupt mask on event input.

IM42

Bit 10: CPU wakeup with interrupt mask on event input.

EMR2

EXTI CPU wakeup with event mask register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM42
rw 		EM41
rw 		EM40
rw 		EM38
rw 		EM37
rw 		EM36
rw 		EM35
rw 		EM34
rw 		EM33
rw 		EM32
rw
Toggle fields

EM32

Bit 0: CPU wakeup with interrupt mask on event input.

EM33

Bit 1: CPU wakeup with interrupt mask on event input.

EM34

Bit 2: CPU wakeup with interrupt mask on event input.

EM35

Bit 3: CPU wakeup with interrupt mask on event input.

EM36

Bit 4: CPU wakeup with interrupt mask on event input.

EM37

Bit 5: CPU wakeup with interrupt mask on event input.

EM38

Bit 6: CPU wakeup with interrupt mask on event input.

EM40

Bit 8: CPU wakeup with interrupt mask on event input.

EM41

Bit 9: CPU wakeup with interrupt mask on event input.

EM42

Bit 10: CPU wakeup with interrupt mask on event input.

SEC_FDCAN1

0x5000a400: FDCAN1

36/159 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 FDCAN_CREL
0x4 FDCAN_ENDN
0xc FDCAN_DBTP
0x10 FDCAN_TEST
0x14 FDCAN_RWD
0x18 FDCAN_CCCR
0x1c FDCAN_NBTP
0x20 FDCAN_TSCC
0x24 FDCAN_TSCV
0x28 FDCAN_TOCC
0x2c FDCAN_TOCV
0x40 FDCAN_ECR
0x44 FDCAN_PSR
0x48 FDCAN_TDCR
0x50 FDCAN_IR
0x54 FDCAN_IE
0x58 FDCAN_ILS
0x5c FDCAN_ILE
0x80 FDCAN_RXGFC
0x84 FDCAN_XIDAM
0x88 FDCAN_HPMS
0x90 FDCAN_RXF0S
0x94 FDCAN_RXF0A
0x98 FDCAN_RXF1S
0x9c FDCAN_RXF1A
0xc0 FDCAN_TXBC
0xc4 FDCAN_TXFQS
0xc8 FDCAN_TXBRP
0xcc FDCAN_TXBAR
0xd0 FDCAN_TXBCR
0xd4 FDCAN_TXBTO
0xd8 FDCAN_TXBCF
0xdc FDCAN_TXBTIE
0xe0 FDCAN_TXBCIE
0xe4 FDCAN_TXEFS
0xe8 FDCAN_TXEFA
0x100 FDCAN_CKDIV
Toggle registers

FDCAN_CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r 		STEP
r 		SUBSTEP
r 		YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r 		DAY
r
Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

FDCAN_ENDN

FDCAN Core Release Register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
r
Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

FDCAN_DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDC
rw 		DBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEG1
rw 		DTSEG2
rw 		DSJW
rw
Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

FDCAN_TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000010, access: Unspecified

1/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r 		TX
rw 		LBCK
rw
Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

FDCAN_RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDV
r 		WDC
rw
Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

FDCAN_CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NISO
rw 		TXP
rw 		EFBI
rw 		PXHD
rw 		BSE
rw 		FDOE
rw 		TEST
rw 		DAR
rw 		MON
rw 		CSR
rw 		CSA
rw 		ASM
rw 		CCE
rw 		INIT
rw
Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

FDCAN_NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x06000A03, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSJW
rw 		NBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTSEG1
rw 		TSEG2
rw
Toggle fields

TSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: NSJW: Nominal (Re)Synchronization Jump Width.

FDCAN_TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

FDCAN_TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSC
rw
Toggle fields

TSC

Bits 0-15: Timestamp Counter.

FDCAN_TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOS
rw 		ETOC
rw
Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

FDCAN_TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOC
rw
Toggle fields

TOC

Bits 0-15: Timeout Counter.

FDCAN_ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP
rw 		REC
r 		TEC
r
Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

FDCAN_PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PXE
rw 		REDL
rw 		RBRS
rw 		RESI
rw 		DLEC
rw 		BO
r 		EW
r 		EP
r 		ACT
r 		LEC
rw
Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

FDCAN_TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCO
rw 		TDCF
rw
Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

FDCAN_IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARA
rw 		PED
rw 		PEA
rw 		WDI
rw 		BO
rw 		EW
rw 		EP
rw 		ELO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOO
rw 		MRAF
rw 		TSW
rw 		TEFL
rw 		TEFF
rw 		TEFN
rw 		TFE
rw 		TCF
rw 		TC
rw 		HPM
rw 		RF1L
rw 		RF1F
rw 		RF1N
rw 		RF0L
rw 		RF0F
rw 		RF0N
rw
Toggle fields

RF0N

Bit 0: RF0N.

RF0F

Bit 1: RF0F.

RF0L

Bit 2: RF0L.

RF1N

Bit 3: RF1N.

RF1F

Bit 4: RF1F.

RF1L

Bit 5: RF1L.

HPM

Bit 6: HPM.

TC

Bit 7: TC.

TCF

Bit 8: TCF.

TFE

Bit 9: TFE.

TEFN

Bit 10: TEFN.

TEFF

Bit 11: TEFF.

TEFL

Bit 12: TEFL.

TSW

Bit 13: TSW.

MRAF

Bit 14: MRAF.

TOO

Bit 15: TOO.

ELO

Bit 16: ELO.

EP

Bit 17: EP.

EW

Bit 18: EW.

BO

Bit 19: BO.

WDI

Bit 20: WDI.

PEA

Bit 21: PEA.

PED

Bit 22: PED.

ARA

Bit 23: ARA.

FDCAN_IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAE
rw 		PEDE
rw 		PEAE
rw 		WDIE
rw 		BOE
rw 		EWE
rw 		EPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELOE
rw 		TOOE
rw 		MRAFE
rw 		TEFLE
rw 		TEFFE
rw 		TEFNE
rw 		TEFE
rw 		TCFE
rw 		TCE
rw 		HPME
rw 		RF1LE
rw 		RF1FE
rw 		RF1NE
rw 		RF0LE
rw 		RF0FE
rw 		RF0NE
rw
Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0FE

Bit 1: Rx FIFO 0 Full Enable.

RF0LE

Bit 2: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 3: Rx FIFO 1 New Message Enable.

RF1FE

Bit 4: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 5: Rx FIFO 1 Message Lost Enable.

HPME

Bit 6: High Priority Message Enable.

TCE

Bit 7: Transmission Completed Enable.

TCFE

Bit 8: Transmission Cancellation Finished Enable.

TEFE

Bit 9: Tx FIFO Empty Enable.

TEFNE

Bit 10: Tx Event FIFO New Entry Enable.

TEFFE

Bit 11: Tx Event FIFO Full Enable.

TEFLE

Bit 12: Tx Event FIFO Element Lost Enable.

MRAFE

Bit 13: Message RAM Access Failure Enable.

TOOE

Bit 14: Timeout Occurred Enable.

ELOE

Bit 15: Error Logging Overflow Enable.

EPE

Bit 16: Error Passive Enable.

EWE

Bit 17: Warning Status Enable.

BOE

Bit 18: Bus_Off Status Enable.

WDIE

Bit 19: Watchdog Interrupt Enable.

PEAE

Bit 20: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 21: Protocol Error in Data Phase Enable.

ARAE

Bit 22: Access to Reserved Address Enable.

FDCAN_ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERR
rw 		BERR
rw 		MISC
rw 		TFERR
rw 		SMSG
rw 		RxFIFO1
rw 		RxFIFO0
rw
Toggle fields

RxFIFO0

Bit 0: RxFIFO0.

RxFIFO1

Bit 1: RxFIFO1.

SMSG

Bit 2: SMSG.

TFERR

Bit 3: TFERR.

MISC

Bit 4: MISC.

BERR

Bit 5: BERR.

PERR

Bit 6: PERR.

FDCAN_ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EINT1
rw 		EINT0
rw
Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

FDCAN_RXGFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE
rw 		LSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0OM
rw 		F1OM
rw 		ANFS
rw 		ANFE
rw 		RRFS
rw 		RRFE
rw
Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

F1OM

Bit 8: F1OM.

F0OM

Bit 9: F0OM.

LSS

Bits 16-20: LSS.

LSE

Bits 24-27: LSE.

FDCAN_XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x84, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIDM
rw
Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

FDCAN_HPMS

FDCAN High Priority Message Status Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLST
r 		FIDX
r 		MSI
r 		BIDX
r
Toggle fields

BIDX

Bits 0-2: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-12: Filter Index.

FLST

Bit 15: Filter List.

FDCAN_RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF0L
rw 		F0F
rw 		F0PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0GI
rw 		F0FL
rw
Toggle fields

F0FL

Bits 0-3: Rx FIFO 0 Fill Level.

F0GI

Bits 8-9: Rx FIFO 0 Get Index.

F0PI

Bits 16-17: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

FDCAN_RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0AI
rw
Toggle fields

F0AI

Bits 0-2: Rx FIFO 0 Acknowledge Index.

FDCAN_RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF1L
r 		F1F
r 		F1PI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1GI
r 		F1FL
rw
Toggle fields

F1FL

Bits 0-3: Rx FIFO 1 Fill Level.

F1GI

Bits 8-9: Rx FIFO 1 Get Index.

F1PI

Bits 16-17: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

FDCAN_RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1AI
rw
Toggle fields

F1AI

Bits 0-2: Rx FIFO 1 Acknowledge Index.

FDCAN_TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

TFQM

Bit 24: Tx FIFO/Queue Mode.

FDCAN_TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000003, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQF
r 		TFQPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFGI
r 		TFFL
r
Toggle fields

TFFL

Bits 0-2: Tx FIFO Free Level.

TFGI

Bits 8-9: TFGI.

TFQPI

Bits 16-17: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

FDCAN_TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRP
r
Toggle fields

TRP

Bits 0-2: Transmission Request Pending.

FDCAN_TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
rw
Toggle fields

AR

Bits 0-2: Add Request.

FDCAN_TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
rw
Toggle fields

CR

Bits 0-2: Cancellation Request.

FDCAN_TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
r
Toggle fields

TO

Bits 0-2: Transmission Occurred..

FDCAN_TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
r
Toggle fields

CF

Bits 0-2: Cancellation Finished.

FDCAN_TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
Toggle fields

TIE

Bits 0-2: Transmission Interrupt Enable.

FDCAN_TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
rw
Toggle fields

CF

Bits 0-2: Cancellation Finished Interrupt Enable.

FDCAN_TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEFL
r 		EFF
r 		EFPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFGI
r 		EFFL
r
Toggle fields

EFFL

Bits 0-2: Event FIFO Fill Level.

EFGI

Bits 8-9: Event FIFO Get Index..

EFPI

Bits 16-17: Event FIFO Put Index.

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

FDCAN_TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFAI
rw
Toggle fields

EFAI

Bits 0-1: Event FIFO Acknowledge Index.

FDCAN_CKDIV

FDCAN TT Trigger Memory Configuration Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDIV
rw
Toggle fields

PDIV

Bits 0-3: PDIV.

SEC_FLASH

0x50022000: Flash

5/114 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 PDKEYR
0x8 NSKEYR
0xc SECKEYR
0x10 OPTKEYR
0x14 LVEKEYR
0x20 NSSR
0x24 SECSR
0x28 NSCR
0x2c SECCR
0x30 ECCR
0x40 OPTR
0x44 NSBOOTADD0R
0x48 NSBOOTADD1R
0x4c SECBOOTADD0R
0x50 SECWM1R1
0x54 SECWM1R2
0x58 WRP1AR
0x5c WRP1BR
0x60 SECWM2R1
0x64 SECWM2R2
0x68 WRP2AR
0x6c WRP2BR
0x80 SECBB1R[1]
0x84 SECBB1R[2]
0x88 SECBB1R[3]
0x8c SECBB1R[4]
0xa0 SECBB2R[1]
0xa4 SECBB2R[2]
0xa8 SECBB2R[3]
0xac SECBB2R[4]
0xc0 SECHDPCR
0xc4 PRIVCFGR
Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEN
rw 		SLEEP_PD
rw 		RUN_PD
rw 		LATENCY
rw
Toggle fields

LATENCY

Bits 0-3: Latency.

RUN_PD

Bit 13: Flash Power-down mode during Low-power run mode.

SLEEP_PD

Bit 14: Flash Power-down mode during Low-power sleep mode.

LVEN

Bit 15: LVEN.

PDKEYR

Power down key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR
w
Toggle fields

PDKEYR

Bits 0-31: RUN_PD in FLASH_ACR key.

NSKEYR

Flash non-secure key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSKEYR
w
Toggle fields

NSKEYR

Bits 0-31: NSKEYR.

SECKEYR

Flash secure key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECKEYR
w
Toggle fields

SECKEYR

Bits 0-31: SECKEYR.

OPTKEYR

Flash option key register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle fields

OPTKEYR

Bits 0-31: OPTKEYR.

LVEKEYR

Flash low voltage key register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVEKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEKEYR
w
Toggle fields

LVEKEYR

Bits 0-31: LVEKEYR.

NSSR

Flash status register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR
rw 		OPTWERR
rw 		NSPGSERR
rw 		NSSIZERR
rw 		NSPGAERR
rw 		NSWRPERR
rw 		NSPROGERR
rw 		NSOPERR
rw 		NSEOP
rw
Toggle fields

NSEOP

Bit 0: NSEOP.

NSOPERR

Bit 1: NSOPERR.

NSPROGERR

Bit 3: NSPROGERR.

NSWRPERR

Bit 4: NSWRPERR.

NSPGAERR

Bit 5: NSPGAERR.

NSSIZERR

Bit 6: NSSIZERR.

NSPGSERR

Bit 7: NSPGSERR.

OPTWERR

Bit 13: OPTWERR.

OPTVERR

Bit 15: OPTVERR.

NSBSY

Bit 16: NSBusy.

SECSR

Flash status register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECRDERR
rw 		SECPGSERR
rw 		SECSIZERR
rw 		SECPGAERR
rw 		SECWRPERR
rw 		SECPROGERR
rw 		SECOPERR
rw 		SECEOP
rw
Toggle fields

SECEOP

Bit 0: SECEOP.

SECOPERR

Bit 1: SECOPERR.

SECPROGERR

Bit 3: SECPROGERR.

SECWRPERR

Bit 4: SECWRPERR.

SECPGAERR

Bit 5: SECPGAERR.

SECSIZERR

Bit 6: SECSIZERR.

SECPGSERR

Bit 7: SECPGSERR.

SECRDERR

Bit 14: Secure read protection error.

SECBSY

Bit 16: SECBusy.

NSCR

Flash non-secure control register

Offset: 0x28, size: 32, reset: 0xC0000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSLOCK
rw 		OPTLOCK
rw 		OBL_LAUNCH
rw 		NSERRIE
rw 		NSEOPIE
rw 		OPTSTRT
rw 		NSSTRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSMER2
rw 		NSBKER
rw 		NSPNB
rw 		NSMER1
rw 		NSPER
rw 		NSPG
rw
Toggle fields

NSPG

Bit 0: NSPG.

NSPER

Bit 1: NSPER.

NSMER1

Bit 2: NSMER1.

NSPNB

Bits 3-9: NSPNB.

NSBKER

Bit 11: NSBKER.

NSMER2

Bit 15: NSMER2.

NSSTRT

Bit 16: Options modification start.

OPTSTRT

Bit 17: Options modification start.

NSEOPIE

Bit 24: NSEOPIE.

NSERRIE

Bit 25: NSERRIE.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

NSLOCK

Bit 31: NSLOCK.

SECCR

Flash secure control register

Offset: 0x2c, size: 32, reset: 0x80000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECLOCK
rw 		SECINV
rw 		SECRDERRIE
rw 		SECERRIE
rw 		SECEOPIE
rw 		SECSTRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECMER2
rw 		SECBKER
rw 		SECPNB
rw 		SECMER1
rw 		SECPER
rw 		SECPG
rw
Toggle fields

SECPG

Bit 0: SECPG.

SECPER

Bit 1: SECPER.

SECMER1

Bit 2: SECMER1.

SECPNB

Bits 3-9: SECPNB.

SECBKER

Bit 11: SECBKER.

SECMER2

Bit 15: SECMER2.

SECSTRT

Bit 16: SECSTRT.

SECEOPIE

Bit 24: SECEOPIE.

SECERRIE

Bit 25: SECERRIE.

SECRDERRIE

Bit 26: SECRDERRIE.

SECINV

Bit 29: SECINV.

SECLOCK

Bit 31: SECLOCK.

ECCR

Flash ECC register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD
rw 		ECCC
rw 		ECCD2
rw 		ECCC2
rw 		ECCIE
rw 		SYSF_ECC
r 		BK_ECC
r 		ADDR_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC
r
Toggle fields

ADDR_ECC

Bits 0-18: ECC fail address.

BK_ECC

Bit 21: BK_ECC.

SYSF_ECC

Bit 22: SYSF_ECC.

ECCIE

Bit 24: ECC correction interrupt enable.

ECCC2

Bit 28: ECCC2.

ECCD2

Bit 29: ECCD2.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZEN
rw 		PA15_PUPEN
rw 		nBOOT0
rw 		nSWBOOT0
rw 		SRAM2_RST
rw 		SRAM2_PE
rw 		DBANK
rw 		DB256K
rw 		SWAP_BANK
rw 		WWDG_SW
rw 		IWDG_STDBY
rw 		IWDG_STOP
rw 		IWDG_SW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_SHDW
rw 		nRST_STDBY
rw 		nRST_STOP
rw 		BOR_LEV
rw 		RDP
rw
Toggle fields

RDP

Bits 0-7: Read protection level.

BOR_LEV

Bits 8-10: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

nRST_SHDW

Bit 14: nRST_SHDW.

IWDG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

SWAP_BANK

Bit 20: SWAP_BANK.

DB256K

Bit 21: DB256K.

DBANK

Bit 22: DBANK.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: nSWBOOT0.

nBOOT0

Bit 27: nBOOT0.

PA15_PUPEN

Bit 28: PA15_PUPEN.

TZEN

Bit 31: TZEN.

NSBOOTADD0R

Flash non-secure boot address 0 register

Offset: 0x44, size: 32, reset: 0x0000000F, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD0
w
Toggle fields

NSBOOTADD0

Bits 7-31: NSBOOTADD0.

NSBOOTADD1R

Flash non-secure boot address 1 register

Offset: 0x48, size: 32, reset: 0x0000000F, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD1
w
Toggle fields

NSBOOTADD1

Bits 7-31: NSBOOTADD1.

SECBOOTADD0R

FFlash secure boot address 0 register

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBOOTADD0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBOOTADD0
w 		BOOT_LOCK
rw
Toggle fields

BOOT_LOCK

Bit 0: BOOT_LOCK.

SECBOOTADD0

Bits 7-31: SECBOOTADD0.

SECWM1R1

Flash bank 1 secure watermak1 register

Offset: 0x50, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECWM1_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECWM1_PSTRT
rw
Toggle fields

SECWM1_PSTRT

Bits 0-6: SECWM1_PSTRT.

SECWM1_PEND

Bits 16-22: SECWM1_PEND.

SECWM1R2

Flash secure watermak1 register 2

Offset: 0x54, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP1EN
rw 		HDP1_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1EN
rw 		PCROP1_PSTRT
rw
Toggle fields

PCROP1_PSTRT

Bits 0-6: PCROP1_PSTRT.

PCROP1EN

Bit 15: PCROP1EN.

HDP1_PEND

Bits 16-22: HDP1_PEND.

HDP1EN

Bit 31: HDP1EN.

WRP1AR

Flash Bank 1 WRP area A address register

Offset: 0x58, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1A_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1A_PSTRT
rw
Toggle fields

WRP1A_PSTRT

Bits 0-6: WRP1A_PSTRT.

WRP1A_PEND

Bits 16-22: WRP1A_PEND.

WRP1BR

Flash Bank 1 WRP area B address register

Offset: 0x5c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1B_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1B_PSTRT
rw
Toggle fields

WRP1B_PSTRT

Bits 0-6: WRP1B_PSTRT.

WRP1B_PEND

Bits 16-22: WRP1B_PEND.

SECWM2R1

Flash secure watermak2 register

Offset: 0x60, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECWM2_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECWM2_PSTRT
rw
Toggle fields

SECWM2_PSTRT

Bits 0-6: SECWM2_PSTRT.

SECWM2_PEND

Bits 16-22: SECWM2_PEND.

SECWM2R2

Flash secure watermak2 register2

Offset: 0x64, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP2EN
rw 		HDP2_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2EN
rw 		PCROP2_PSTRT
rw
Toggle fields

PCROP2_PSTRT

Bits 0-6: PCROP2_PSTRT.

PCROP2EN

Bit 15: PCROP2EN.

HDP2_PEND

Bits 16-22: HDP2_PEND.

HDP2EN

Bit 31: HDP2EN.

WRP2AR

Flash WPR2 area A address register

Offset: 0x68, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2A_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2A_PSTRT
rw
Toggle fields

WRP2A_PSTRT

Bits 0-6: WRP2A_PSTRT.

WRP2A_PEND

Bits 16-22: WRP2A_PEND.

WRP2BR

Flash WPR2 area B address register

Offset: 0x6c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2B_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2B_PSTRT
rw
Toggle fields

WRP2B_PSTRT

Bits 0-6: WRP2B_PSTRT.

WRP2B_PEND

Bits 16-22: WRP2B_PEND.

SECBB1R[1]

FLASH secure block based bank 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[2]

FLASH secure block based bank 1

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[3]

FLASH secure block based bank 1

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[4]

FLASH secure block based bank 1

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB2R[1]

FLASH secure block based bank 2

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[2]

FLASH secure block based bank 2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[3]

FLASH secure block based bank 2

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[4]

FLASH secure block based bank 2

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECHDPCR

FLASH secure HDP control register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDP2_ACCDIS
rw 		HDP1_ACCDIS
rw
Toggle fields

HDP1_ACCDIS

Bit 0: HDP1_ACCDIS.

HDP2_ACCDIS

Bit 1: HDP2_ACCDIS.

PRIVCFGR

Power privilege configuration register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
Toggle fields

PRIV

Bit 0: PRIV.

SEC_FMC

0x54020000: FMC

2/149 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
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15
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0
0x0 BCR1
0x4 BTR1
0x8 BCR2
0xc BTR2
0x10 BCR3
0x14 BTR3
0x18 BCR4
0x1c BTR4
0x20 PCSCNTR
0x80 PCR
0x84 SR
0x88 PMEM
0x8c PATT
0x94 ECCR
0x104 BWTR1
0x10c BWTR2
0x114 BWTR3
0x11c BWTR4
Toggle registers

BCR1

FMC_BCR1

Offset: 0x0, size: 32, reset: 0x000030DB, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw 		WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

NBLSET

Bits 22-23: NBLSET.

BTR1

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0x4, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

DATAHLD

Bits 30-31: DATAHLD.

BCR2

FMC_BCR2

Offset: 0x8, size: 32, reset: 0x000030D2, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw 		WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

NBLSET

Bits 22-23: NBLSET.

BTR2

FMC_BTR2

Offset: 0xc, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

DATAHLD

Bits 30-31: DATAHLD.

BCR3

>FMC_BCR3

Offset: 0x10, size: 32, reset: 0x000030D2, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw 		WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

NBLSET

Bits 22-23: NBLSET.

BTR3

FMC_BTR3

Offset: 0x14, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

DATAHLD

Bits 30-31: DATAHLD.

BCR4

>FMC_BCR4

Offset: 0x18, size: 32, reset: 0x000030D2, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw 		WFDIS
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

NBLSET

Bits 22-23: NBLSET.

BTR4

FMC_BTR4

Offset: 0x1c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

DATAHLD

Bits 30-31: DATAHLD.

PCSCNTR

PCSCNTR

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTB4EN
rw 		CNTB3EN
rw 		CNTB2EN
rw 		CNTB1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCOUNT
rw
Toggle fields

CSCOUNT

Bits 0-15: Chip select counter.

CNTB1EN

Bit 16: Counter Bank 1 enable.

CNTB2EN

Bit 17: Counter Bank 2 enable.

CNTB3EN

Bit 18: Counter Bank 3 enable.

CNTB4EN

Bit 19: Counter Bank 4 enable.

PCR

NAND Flash control registers

Offset: 0x80, size: 32, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw 		TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw 		TCLR
rw 		ECCEN
rw 		PWID
rw 		PTYP
rw 		PBKEN
rw 		PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:.

PBKEN

Bit 2: NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus.

PTYP

Bit 3: Memory type.

PWID

Bits 4-5: Data bus width. These bits define the external memory device width..

ECCEN

Bit 6: ECC computation logic enable bit.

TCLR

Bits 9-12: CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

TAR

Bits 13-16: ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

ECCPS

Bits 17-19: ECC page size. These bits define the page size for the extended ECC:.

SR

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Offset: 0x84, size: 32, reset: 0x00000040, access: Unspecified

1/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r 		IFEN
rw 		ILEN
rw 		IREN
rw 		IFS
rw 		ILS
rw 		IRS
rw
Toggle fields

IRS

Bit 0: Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

ILS

Bit 1: Interrupt high-level status The flag is set by hardware and reset by software..

IFS

Bit 2: Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

IREN

Bit 3: Interrupt rising edge detection enable bit.

ILEN

Bit 4: Interrupt high-level detection enable bit.

IFEN

Bit 5: Interrupt falling edge detection enable bit.

FEMPT

Bit 6: FIFO empty. Read-only bit that provides the status of the FIFO.

PMEM

The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.

Offset: 0x88, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw 		MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw 		MEMSET
rw
Toggle fields

MEMSET

Bits 0-7: Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:.

MEMWAIT

Bits 8-15: Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

MEMHOLD

Bits 16-23: Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:.

MEMHIZ

Bits 24-31: Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:.

PATT

The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

Offset: 0x8c, size: 32, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle fields

ATTSET

Bits 0-7: Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

ATTWAIT

Bits 8-15: Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

ATTHOLD

Bits 16-23: Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

ATTHIZ

Bits 24-31: Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:.

ECCR

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle fields

ECC

Bits 0-31: ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields..

BWTR1

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

BWTR2

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

BWTR3

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x114, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

BWTR4

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x11c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

SEC_GPIOA

0x52020000: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

SEC_GPIOB

0x52020400: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

SEC_GPIOC

0x52020800: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

SEC_GPIOD

0x52020c00: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

SEC_GPIOE

0x52021000: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

SEC_GPIOF

0x52021400: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

SEC_GPIOG

0x52021800: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

SEC_GPIOH

0x52021c00: General-purpose I/Os

177/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x0000000F, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7
rw 		AFSEL6
rw 		AFSEL5
rw 		AFSEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3
rw 		AFSEL2
rw 		AFSEL1
rw 		AFSEL0
rw
Toggle fields

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15
rw 		AFSEL14
rw 		AFSEL13
rw 		AFSEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11
rw 		AFSEL10
rw 		AFSEL9
rw 		AFSEL8
rw
Toggle fields

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR1

Bit 1: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR2

Bit 2: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR3

Bit 3: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR4

Bit 4: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR5

Bit 5: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR6

Bit 6: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR7

Bit 7: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR8

Bit 8: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR9

Bit 9: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR10

Bit 10: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR11

Bit 11: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR12

Bit 12: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR13

Bit 13: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR14

Bit 14: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR15

Bit 15: Port x reset IO pin y.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
w 		SEC14
w 		SEC13
w 		SEC12
w 		SEC11
w 		SEC10
w 		SEC9
w 		SEC8
w 		SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

SEC1

Bit 1: I/O pin of Port x secure bit enable.

SEC2

Bit 2: I/O pin of Port x secure bit enable.

SEC3

Bit 3: I/O pin of Port x secure bit enable.

SEC4

Bit 4: I/O pin of Port x secure bit enable.

SEC5

Bit 5: I/O pin of Port x secure bit enable.

SEC6

Bit 6: I/O pin of Port x secure bit enable.

SEC7

Bit 7: I/O pin of Port x secure bit enable.

SEC8

Bit 8: I/O pin of Port x secure bit enable.

SEC9

Bit 9: I/O pin of Port x secure bit enable.

SEC10

Bit 10: I/O pin of Port x secure bit enable.

SEC11

Bit 11: I/O pin of Port x secure bit enable.

SEC12

Bit 12: I/O pin of Port x secure bit enable.

SEC13

Bit 13: I/O pin of Port x secure bit enable.

SEC14

Bit 14: I/O pin of Port x secure bit enable.

SEC15

Bit 15: I/O pin of Port x secure bit enable.

SEC_GTZC_MPCBB1

0x50032c00: SEC_GTZC_MPCBB1

0/2115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MPCBB1_CR
0x10 MPCBB1_LCKVTR1
0x14 MPCBB1_LCKVTR2
0x100 MPCBB1_VCTR0
0x104 MPCBB1_VCTR1
0x108 MPCBB1_VCTR2
0x10c MPCBB1_VCTR3
0x110 MPCBB1_VCTR4
0x114 MPCBB1_VCTR5
0x118 MPCBB1_VCTR6
0x11c MPCBB1_VCTR7
0x120 MPCBB1_VCTR8
0x124 MPCBB1_VCTR9
0x128 MPCBB1_VCTR10
0x12c MPCBB1_VCTR11
0x130 MPCBB1_VCTR12
0x134 MPCBB1_VCTR13
0x138 MPCBB1_VCTR14
0x13c MPCBB1_VCTR15
0x140 MPCBB1_VCTR16
0x144 MPCBB1_VCTR17
0x148 MPCBB1_VCTR18
0x14c MPCBB1_VCTR19
0x150 MPCBB1_VCTR20
0x154 MPCBB1_VCTR21
0x158 MPCBB1_VCTR22
0x15c MPCBB1_VCTR23
0x160 MPCBB1_VCTR24
0x164 MPCBB1_VCTR25
0x168 MPCBB1_VCTR26
0x16c MPCBB1_VCTR27
0x170 MPCBB1_VCTR28
0x174 MPCBB1_VCTR29
0x178 MPCBB1_VCTR30
0x17c MPCBB1_VCTR31
0x180 MPCBB1_VCTR32
0x184 MPCBB1_VCTR33
0x188 MPCBB1_VCTR34
0x18c MPCBB1_VCTR35
0x190 MPCBB1_VCTR36
0x194 MPCBB1_VCTR37
0x198 MPCBB1_VCTR38
0x19c MPCBB1_VCTR39
0x1a0 MPCBB1_VCTR40
0x1a4 MPCBB1_VCTR41
0x1a8 MPCBB1_VCTR42
0x1ac MPCBB1_VCTR43
0x1b0 MPCBB1_VCTR44
0x1b4 MPCBB1_VCTR45
0x1b8 MPCBB1_VCTR46
0x1bc MPCBB1_VCTR47
0x1c0 MPCBB1_VCTR48
0x1c4 MPCBB1_VCTR49
0x1c8 MPCBB1_VCTR50
0x1cc MPCBB1_VCTR51
0x1d0 MPCBB1_VCTR52
0x1d4 MPCBB1_VCTR53
0x1d8 MPCBB1_VCTR54
0x1dc MPCBB1_VCTR55
0x1e0 MPCBB1_VCTR56
0x1e4 MPCBB1_VCTR57
0x1e8 MPCBB1_VCTR58
0x1ec MPCBB1_VCTR59
0x1f0 MPCBB1_VCTR60
0x1f4 MPCBB1_VCTR61
0x1f8 MPCBB1_VCTR62
0x1fc MPCBB1_VCTR63
Toggle registers

MPCBB1_CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRWILADIS
rw 		INVSECSTATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

INVSECSTATE

Bit 30: INVSECSTATE.

SRWILADIS

Bit 31: SRWILADIS.

MPCBB1_LCKVTR1

MPCBB control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKSB31
rw 		LCKSB30
rw 		LCKSB29
rw 		LCKSB28
rw 		LCKSB27
rw 		LCKSB26
rw 		LCKSB25
rw 		LCKSB24
rw 		LCKSB23
rw 		LCKSB22
rw 		LCKSB21
rw 		LCKSB20
rw 		LCKSB19
rw 		LCKSB18
rw 		LCKSB17
rw 		LCKSB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB15
rw 		LCKSB14
rw 		LCKSB13
rw 		LCKSB12
rw 		LCKSB11
rw 		LCKSB10
rw 		LCKSB9
rw 		LCKSB8
rw 		LCKSB7
rw 		LCKSB6
rw 		LCKSB5
rw 		LCKSB4
rw 		LCKSB3
rw 		LCKSB2
rw 		LCKSB1
rw 		LCKSB0
rw
Toggle fields

LCKSB0

Bit 0: LCKSB0.

LCKSB1

Bit 1: LCKSB1.

LCKSB2

Bit 2: LCKSB2.

LCKSB3

Bit 3: LCKSB3.

LCKSB4

Bit 4: LCKSB4.

LCKSB5

Bit 5: LCKSB5.

LCKSB6

Bit 6: LCKSB6.

LCKSB7

Bit 7: LCKSB7.

LCKSB8

Bit 8: LCKSB8.

LCKSB9

Bit 9: LCKSB9.

LCKSB10

Bit 10: LCKSB10.

LCKSB11

Bit 11: LCKSB11.

LCKSB12

Bit 12: LCKSB12.

LCKSB13

Bit 13: LCKSB13.

LCKSB14

Bit 14: LCKSB14.

LCKSB15

Bit 15: LCKSB15.

LCKSB16

Bit 16: LCKSB16.

LCKSB17

Bit 17: LCKSB17.

LCKSB18

Bit 18: LCKSB18.

LCKSB19

Bit 19: LCKSB19.

LCKSB20

Bit 20: LCKSB20.

LCKSB21

Bit 21: LCKSB21.

LCKSB22

Bit 22: LCKSB22.

LCKSB23

Bit 23: LCKSB23.

LCKSB24

Bit 24: LCKSB24.

LCKSB25

Bit 25: LCKSB25.

LCKSB26

Bit 26: LCKSB26.

LCKSB27

Bit 27: LCKSB27.

LCKSB28

Bit 28: LCKSB28.

LCKSB29

Bit 29: LCKSB29.

LCKSB30

Bit 30: LCKSB30.

LCKSB31

Bit 31: LCKSB31.

MPCBB1_LCKVTR2

MPCBB control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKSB63
rw 		LCKSB62
rw 		LCKSB61
rw 		LCKSB60
rw 		LCKSB59
rw 		LCKSB58
rw 		LCKSB57
rw 		LCKSB56
rw 		LCKSB55
rw 		LCKSB54
rw 		LCKSB53
rw 		LCKSB52
rw 		LCKSB51
rw 		LCKSB50
rw 		LCKSB49
rw 		LCKSB48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB47
rw 		LCKSB46
rw 		LCKSB45
rw 		LCKSB44
rw 		LCKSB43
rw 		LCKSB42
rw 		LCKSB41
rw 		LCKSB40
rw 		LCKSB39
rw 		LCKSB38
rw 		LCKSB37
rw 		LCKSB36
rw 		LCKSB35
rw 		LCKSB34
rw 		LCKSB33
rw 		LCKSB32
rw
Toggle fields

LCKSB32

Bit 0: LCKSB32.

LCKSB33

Bit 1: LCKSB33.

LCKSB34

Bit 2: LCKSB34.

LCKSB35

Bit 3: LCKSB35.

LCKSB36

Bit 4: LCKSB36.

LCKSB37

Bit 5: LCKSB37.

LCKSB38

Bit 6: LCKSB38.

LCKSB39

Bit 7: LCKSB39.

LCKSB40

Bit 8: LCKSB40.

LCKSB41

Bit 9: LCKSB41.

LCKSB42

Bit 10: LCKSB42.

LCKSB43

Bit 11: LCKSB43.

LCKSB44

Bit 12: LCKSB44.

LCKSB45

Bit 13: LCKSB45.

LCKSB46

Bit 14: LCKSB46.

LCKSB47

Bit 15: LCKSB47.

LCKSB48

Bit 16: LCKSB48.

LCKSB49

Bit 17: LCKSB49.

LCKSB50

Bit 18: LCKSB50.

LCKSB51

Bit 19: LCKSB51.

LCKSB52

Bit 20: LCKSB52.

LCKSB53

Bit 21: LCKSB53.

LCKSB54

Bit 22: LCKSB54.

LCKSB55

Bit 23: LCKSB55.

LCKSB56

Bit 24: LCKSB56.

LCKSB57

Bit 25: LCKSB57.

LCKSB58

Bit 26: LCKSB58.

LCKSB59

Bit 27: LCKSB59.

LCKSB60

Bit 28: LCKSB60.

LCKSB61

Bit 29: LCKSB61.

LCKSB62

Bit 30: LCKSB62.

LCKSB63

Bit 31: LCKSB63.

MPCBB1_VCTR0

MPCBBx vector register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw 		B30
rw 		B29
rw 		B28
rw 		B27
rw 		B26
rw 		B25
rw 		B24
rw 		B23
rw 		B22
rw 		B21
rw 		B20
rw 		B19
rw 		B18
rw 		B17
rw 		B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw 		B14
rw 		B13
rw 		B12
rw 		B11
rw 		B10
rw 		B9
rw 		B8
rw 		B7
rw 		B6
rw 		B5
rw 		B4
rw 		B3
rw 		B2
rw 		B1
rw 		B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

MPCBB1_VCTR1

MPCBBx vector register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B63
rw 		B62
rw 		B61
rw 		B60
rw 		B59
rw 		B58
rw 		B57
rw 		B56
rw 		B55
rw 		B54
rw 		B53
rw 		B52
rw 		B51
rw 		B50
rw 		B49
rw 		B48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B47
rw 		B46
rw 		B45
rw 		B44
rw 		B43
rw 		B42
rw 		B41
rw 		B40
rw 		B39
rw 		B38
rw 		B37
rw 		B36
rw 		B35
rw 		B34
rw 		B33
rw 		B32
rw
Toggle fields

B32

Bit 0: B32.

B33

Bit 1: B33.

B34

Bit 2: B34.

B35

Bit 3: B35.

B36

Bit 4: B36.

B37

Bit 5: B37.

B38

Bit 6: B38.

B39

Bit 7: B39.

B40

Bit 8: B40.

B41

Bit 9: B41.

B42

Bit 10: B42.

B43

Bit 11: B43.

B44

Bit 12: B44.

B45

Bit 13: B45.

B46

Bit 14: B46.

B47

Bit 15: B47.

B48

Bit 16: B48.

B49

Bit 17: B49.

B50

Bit 18: B50.

B51

Bit 19: B51.

B52

Bit 20: B52.

B53

Bit 21: B53.

B54

Bit 22: B54.

B55

Bit 23: B55.

B56

Bit 24: B56.

B57

Bit 25: B57.

B58

Bit 26: B58.

B59

Bit 27: B59.

B60

Bit 28: B60.

B61

Bit 29: B61.

B62

Bit 30: B62.

B63

Bit 31: B63.

MPCBB1_VCTR2

MPCBBx vector register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B95
rw 		B94
rw 		B93
rw 		B92
rw 		B91
rw 		B90
rw 		B89
rw 		B88
rw 		B87
rw 		B86
rw 		B85
rw 		B84
rw 		B83
rw 		B82
rw 		B81
rw 		B80
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B79
rw 		B78
rw 		B77
rw 		B76
rw 		B75
rw 		B74
rw 		B73
rw 		B72
rw 		B71
rw 		B70
rw 		B69
rw 		B68
rw 		B67
rw 		B66
rw 		B65
rw 		B64
rw
Toggle fields

B64

Bit 0: B64.

B65

Bit 1: B65.

B66

Bit 2: B66.

B67

Bit 3: B67.

B68

Bit 4: B68.

B69

Bit 5: B69.

B70

Bit 6: B70.

B71

Bit 7: B71.

B72

Bit 8: B72.

B73

Bit 9: B73.

B74

Bit 10: B74.

B75

Bit 11: B75.

B76

Bit 12: B76.

B77

Bit 13: B77.

B78

Bit 14: B78.

B79

Bit 15: B79.

B80

Bit 16: B80.

B81

Bit 17: B81.

B82

Bit 18: B82.

B83

Bit 19: B83.

B84

Bit 20: B84.

B85

Bit 21: B85.

B86

Bit 22: B86.

B87

Bit 23: B87.

B88

Bit 24: B88.

B89

Bit 25: B89.

B90

Bit 26: B90.

B91

Bit 27: B91.

B92

Bit 28: B92.

B93

Bit 29: B93.

B94

Bit 30: B94.

B95

Bit 31: B95.

MPCBB1_VCTR3

MPCBBx vector register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B127
rw 		B126
rw 		B125
rw 		B124
rw 		B123
rw 		B122
rw 		B121
rw 		B120
rw 		B119
rw 		B118
rw 		B117
rw 		B116
rw 		B115
rw 		B114
rw 		B113
rw 		B112
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B111
rw 		B110
rw 		B109
rw 		B108
rw 		B107
rw 		B106
rw 		B105
rw 		B104
rw 		B103
rw 		B102
rw 		B101
rw 		B100
rw 		B99
rw 		B98
rw 		B97
rw 		B96
rw
Toggle fields

B96

Bit 0: B96.

B97

Bit 1: B97.

B98

Bit 2: B98.

B99

Bit 3: B99.

B100

Bit 4: B100.

B101

Bit 5: B101.

B102

Bit 6: B102.

B103

Bit 7: B103.

B104

Bit 8: B104.

B105

Bit 9: B105.

B106

Bit 10: B106.

B107

Bit 11: B107.

B108

Bit 12: B108.

B109

Bit 13: B109.

B110

Bit 14: B110.

B111

Bit 15: B111.

B112

Bit 16: B112.

B113

Bit 17: B113.

B114

Bit 18: B114.

B115

Bit 19: B115.

B116

Bit 20: B116.

B117

Bit 21: B117.

B118

Bit 22: B118.

B119

Bit 23: B119.

B120

Bit 24: B120.

B121

Bit 25: B121.

B122

Bit 26: B122.

B123

Bit 27: B123.

B124

Bit 28: B124.

B125

Bit 29: B125.

B126

Bit 30: B126.

B127

Bit 31: B127.

MPCBB1_VCTR4

MPCBBx vector register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B159
rw 		B158
rw 		B157
rw 		B156
rw 		B155
rw 		B154
rw 		B153
rw 		B152
rw 		B151
rw 		B150
rw 		B149
rw 		B148
rw 		B147
rw 		B146
rw 		B145
rw 		B144
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B143
rw 		B142
rw 		B141
rw 		B140
rw 		B139
rw 		B138
rw 		B137
rw 		B136
rw 		B135
rw 		B134
rw 		B133
rw 		B132
rw 		B131
rw 		B130
rw 		B129
rw 		B128
rw
Toggle fields

B128

Bit 0: B128.

B129

Bit 1: B129.

B130

Bit 2: B130.

B131

Bit 3: B131.

B132

Bit 4: B132.

B133

Bit 5: B133.

B134

Bit 6: B134.

B135

Bit 7: B135.

B136

Bit 8: B136.

B137

Bit 9: B137.

B138

Bit 10: B138.

B139

Bit 11: B139.

B140

Bit 12: B140.

B141

Bit 13: B141.

B142

Bit 14: B142.

B143

Bit 15: B143.

B144

Bit 16: B144.

B145

Bit 17: B145.

B146

Bit 18: B146.

B147

Bit 19: B147.

B148

Bit 20: B148.

B149

Bit 21: B149.

B150

Bit 22: B150.

B151

Bit 23: B151.

B152

Bit 24: B152.

B153

Bit 25: B153.

B154

Bit 26: B154.

B155

Bit 27: B155.

B156

Bit 28: B156.

B157

Bit 29: B157.

B158

Bit 30: B158.

B159

Bit 31: B159.

MPCBB1_VCTR5

MPCBBx vector register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B191
rw 		B190
rw 		B189
rw 		B188
rw 		B187
rw 		B186
rw 		B185
rw 		B184
rw 		B183
rw 		B182
rw 		B181
rw 		B180
rw 		B179
rw 		B178
rw 		B177
rw 		B176
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B175
rw 		B174
rw 		B173
rw 		B172
rw 		B171
rw 		B170
rw 		B169
rw 		B168
rw 		B167
rw 		B166
rw 		B165
rw 		B164
rw 		B163
rw 		B162
rw 		B161
rw 		B160
rw
Toggle fields

B160

Bit 0: B160.

B161

Bit 1: B161.

B162

Bit 2: B162.

B163

Bit 3: B163.

B164

Bit 4: B164.

B165

Bit 5: B165.

B166

Bit 6: B166.

B167

Bit 7: B167.

B168

Bit 8: B168.

B169

Bit 9: B169.

B170

Bit 10: B170.

B171

Bit 11: B171.

B172

Bit 12: B172.

B173

Bit 13: B173.

B174

Bit 14: B174.

B175

Bit 15: B175.

B176

Bit 16: B176.

B177

Bit 17: B177.

B178

Bit 18: B178.

B179

Bit 19: B179.

B180

Bit 20: B180.

B181

Bit 21: B181.

B182

Bit 22: B182.

B183

Bit 23: B183.

B184

Bit 24: B184.

B185

Bit 25: B185.

B186

Bit 26: B186.

B187

Bit 27: B187.

B188

Bit 28: B188.

B189

Bit 29: B189.

B190

Bit 30: B190.

B191

Bit 31: B191.

MPCBB1_VCTR6

MPCBBx vector register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B223
rw 		B222
rw 		B221
rw 		B220
rw 		B219
rw 		B218
rw 		B217
rw 		B216
rw 		B215
rw 		B214
rw 		B213
rw 		B212
rw 		B211
rw 		B210
rw 		B209
rw 		B208
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B207
rw 		B206
rw 		B205
rw 		B204
rw 		B203
rw 		B202
rw 		B201
rw 		B200
rw 		B199
rw 		B198
rw 		B197
rw 		B196
rw 		B195
rw 		B194
rw 		B193
rw 		B192
rw
Toggle fields

B192

Bit 0: B192.

B193

Bit 1: B193.

B194

Bit 2: B194.

B195

Bit 3: B195.

B196

Bit 4: B196.

B197

Bit 5: B197.

B198

Bit 6: B198.

B199

Bit 7: B199.

B200

Bit 8: B200.

B201

Bit 9: B201.

B202

Bit 10: B202.

B203

Bit 11: B203.

B204

Bit 12: B204.

B205

Bit 13: B205.

B206

Bit 14: B206.

B207

Bit 15: B207.

B208

Bit 16: B208.

B209

Bit 17: B209.

B210

Bit 18: B210.

B211

Bit 19: B211.

B212

Bit 20: B212.

B213

Bit 21: B213.

B214

Bit 22: B214.

B215

Bit 23: B215.

B216

Bit 24: B216.

B217

Bit 25: B217.

B218

Bit 26: B218.

B219

Bit 27: B219.

B220

Bit 28: B220.

B221

Bit 29: B221.

B222

Bit 30: B222.

B223

Bit 31: B223.

MPCBB1_VCTR7

MPCBBx vector register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B255
rw 		B254
rw 		B253
rw 		B252
rw 		B251
rw 		B250
rw 		B249
rw 		B248
rw 		B247
rw 		B246
rw 		B245
rw 		B244
rw 		B243
rw 		B242
rw 		B241
rw 		B240
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B239
rw 		B238
rw 		B237
rw 		B236
rw 		B235
rw 		B234
rw 		B233
rw 		B232
rw 		B231
rw 		B230
rw 		B229
rw 		B228
rw 		B227
rw 		B226
rw 		B225
rw 		B224
rw
Toggle fields

B224

Bit 0: B224.

B225

Bit 1: B225.

B226

Bit 2: B226.

B227

Bit 3: B227.

B228

Bit 4: B228.

B229

Bit 5: B229.

B230

Bit 6: B230.

B231

Bit 7: B231.

B232

Bit 8: B232.

B233

Bit 9: B233.

B234

Bit 10: B234.

B235

Bit 11: B235.

B236

Bit 12: B236.

B237

Bit 13: B237.

B238

Bit 14: B238.

B239

Bit 15: B239.

B240

Bit 16: B240.

B241

Bit 17: B241.

B242

Bit 18: B242.

B243

Bit 19: B243.

B244

Bit 20: B244.

B245

Bit 21: B245.

B246

Bit 22: B246.

B247

Bit 23: B247.

B248

Bit 24: B248.

B249

Bit 25: B249.

B250

Bit 26: B250.

B251

Bit 27: B251.

B252

Bit 28: B252.

B253

Bit 29: B253.

B254

Bit 30: B254.

B255

Bit 31: B255.

MPCBB1_VCTR8

MPCBBx vector register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B287
rw 		B286
rw 		B285
rw 		B284
rw 		B283
rw 		B282
rw 		B281
rw 		B280
rw 		B279
rw 		B278
rw 		B277
rw 		B276
rw 		B275
rw 		B274
rw 		B273
rw 		B272
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B271
rw 		B270
rw 		B269
rw 		B268
rw 		B267
rw 		B266
rw 		B265
rw 		B264
rw 		B263
rw 		B262
rw 		B261
rw 		B260
rw 		B259
rw 		B258
rw 		B257
rw 		B256
rw
Toggle fields

B256

Bit 0: B256.

B257

Bit 1: B257.

B258

Bit 2: B258.

B259

Bit 3: B259.

B260

Bit 4: B260.

B261

Bit 5: B261.

B262

Bit 6: B262.

B263

Bit 7: B263.

B264

Bit 8: B264.

B265

Bit 9: B265.

B266

Bit 10: B266.

B267

Bit 11: B267.

B268

Bit 12: B268.

B269

Bit 13: B269.

B270

Bit 14: B270.

B271

Bit 15: B271.

B272

Bit 16: B272.

B273

Bit 17: B273.

B274

Bit 18: B274.

B275

Bit 19: B275.

B276

Bit 20: B276.

B277

Bit 21: B277.

B278

Bit 22: B278.

B279

Bit 23: B279.

B280

Bit 24: B280.

B281

Bit 25: B281.

B282

Bit 26: B282.

B283

Bit 27: B283.

B284

Bit 28: B284.

B285

Bit 29: B285.

B286

Bit 30: B286.

B287

Bit 31: B287.

MPCBB1_VCTR9

MPCBBx vector register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B319
rw 		B318
rw 		B317
rw 		B316
rw 		B315
rw 		B314
rw 		B313
rw 		B312
rw 		B311
rw 		B310
rw 		B309
rw 		B308
rw 		B307
rw 		B306
rw 		B305
rw 		B304
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B303
rw 		B302
rw 		B301
rw 		B300
rw 		B299
rw 		B298
rw 		B297
rw 		B296
rw 		B295
rw 		B294
rw 		B293
rw 		B292
rw 		B291
rw 		B290
rw 		B289
rw 		B288
rw
Toggle fields

B288

Bit 0: B288.

B289

Bit 1: B289.

B290

Bit 2: B290.

B291

Bit 3: B291.

B292

Bit 4: B292.

B293

Bit 5: B293.

B294

Bit 6: B294.

B295

Bit 7: B295.

B296

Bit 8: B296.

B297

Bit 9: B297.

B298

Bit 10: B298.

B299

Bit 11: B299.

B300

Bit 12: B300.

B301

Bit 13: B301.

B302

Bit 14: B302.

B303

Bit 15: B303.

B304

Bit 16: B304.

B305

Bit 17: B305.

B306

Bit 18: B306.

B307

Bit 19: B307.

B308

Bit 20: B308.

B309

Bit 21: B309.

B310

Bit 22: B310.

B311

Bit 23: B311.

B312

Bit 24: B312.

B313

Bit 25: B313.

B314

Bit 26: B314.

B315

Bit 27: B315.

B316

Bit 28: B316.

B317

Bit 29: B317.

B318

Bit 30: B318.

B319

Bit 31: B319.

MPCBB1_VCTR10

MPCBBx vector register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B351
rw 		B350
rw 		B349
rw 		B348
rw 		B347
rw 		B346
rw 		B345
rw 		B344
rw 		B343
rw 		B342
rw 		B341
rw 		B340
rw 		B339
rw 		B338
rw 		B337
rw 		B336
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B335
rw 		B334
rw 		B333
rw 		B332
rw 		B331
rw 		B330
rw 		B329
rw 		B328
rw 		B327
rw 		B326
rw 		B325
rw 		B324
rw 		B323
rw 		B322
rw 		B321
rw 		B320
rw
Toggle fields

B320

Bit 0: B320.

B321

Bit 1: B321.

B322

Bit 2: B322.

B323

Bit 3: B323.

B324

Bit 4: B324.

B325

Bit 5: B325.

B326

Bit 6: B326.

B327

Bit 7: B327.

B328

Bit 8: B328.

B329

Bit 9: B329.

B330

Bit 10: B330.

B331

Bit 11: B331.

B332

Bit 12: B332.

B333

Bit 13: B333.

B334

Bit 14: B334.

B335

Bit 15: B335.

B336

Bit 16: B336.

B337

Bit 17: B337.

B338

Bit 18: B338.

B339

Bit 19: B339.

B340

Bit 20: B340.

B341

Bit 21: B341.

B342

Bit 22: B342.

B343

Bit 23: B343.

B344

Bit 24: B344.

B345

Bit 25: B345.

B346

Bit 26: B346.

B347

Bit 27: B347.

B348

Bit 28: B348.

B349

Bit 29: B349.

B350

Bit 30: B350.

B351

Bit 31: B351.

MPCBB1_VCTR11

MPCBBx vector register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B383
rw 		B382
rw 		B381
rw 		B380
rw 		B379
rw 		B378
rw 		B377
rw 		B376
rw 		B375
rw 		B374
rw 		B373
rw 		B372
rw 		B371
rw 		B370
rw 		B369
rw 		B368
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B367
rw 		B366
rw 		B365
rw 		B364
rw 		B363
rw 		B362
rw 		B361
rw 		B360
rw 		B359
rw 		B358
rw 		B357
rw 		B356
rw 		B355
rw 		B354
rw 		B353
rw 		B352
rw
Toggle fields

B352

Bit 0: B352.

B353

Bit 1: B353.

B354

Bit 2: B354.

B355

Bit 3: B355.

B356

Bit 4: B356.

B357

Bit 5: B357.

B358

Bit 6: B358.

B359

Bit 7: B359.

B360

Bit 8: B360.

B361

Bit 9: B361.

B362

Bit 10: B362.

B363

Bit 11: B363.

B364

Bit 12: B364.

B365

Bit 13: B365.

B366

Bit 14: B366.

B367

Bit 15: B367.

B368

Bit 16: B368.

B369

Bit 17: B369.

B370

Bit 18: B370.

B371

Bit 19: B371.

B372

Bit 20: B372.

B373

Bit 21: B373.

B374

Bit 22: B374.

B375

Bit 23: B375.

B376

Bit 24: B376.

B377

Bit 25: B377.

B378

Bit 26: B378.

B379

Bit 27: B379.

B380

Bit 28: B380.

B381

Bit 29: B381.

B382

Bit 30: B382.

B383

Bit 31: B383.

MPCBB1_VCTR12

MPCBBx vector register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B415
rw 		B414
rw 		B413
rw 		B412
rw 		B411
rw 		B410
rw 		B409
rw 		B408
rw 		B407
rw 		B406
rw 		B405
rw 		B404
rw 		B403
rw 		B402
rw 		B401
rw 		B400
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B399
rw 		B398
rw 		B397
rw 		B396
rw 		B395
rw 		B394
rw 		B393
rw 		B392
rw 		B391
rw 		B390
rw 		B389
rw 		B388
rw 		B387
rw 		B386
rw 		B385
rw 		B384
rw
Toggle fields

B384

Bit 0: B384.

B385

Bit 1: B385.

B386

Bit 2: B386.

B387

Bit 3: B387.

B388

Bit 4: B388.

B389

Bit 5: B389.

B390

Bit 6: B390.

B391

Bit 7: B391.

B392

Bit 8: B392.

B393

Bit 9: B393.

B394

Bit 10: B394.

B395

Bit 11: B395.

B396

Bit 12: B396.

B397

Bit 13: B397.

B398

Bit 14: B398.

B399

Bit 15: B399.

B400

Bit 16: B400.

B401

Bit 17: B401.

B402

Bit 18: B402.

B403

Bit 19: B403.

B404

Bit 20: B404.

B405

Bit 21: B405.

B406

Bit 22: B406.

B407

Bit 23: B407.

B408

Bit 24: B408.

B409

Bit 25: B409.

B410

Bit 26: B410.

B411

Bit 27: B411.

B412

Bit 28: B412.

B413

Bit 29: B413.

B414

Bit 30: B414.

B415

Bit 31: B415.

MPCBB1_VCTR13

MPCBBx vector register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B447
rw 		B446
rw 		B445
rw 		B444
rw 		B443
rw 		B442
rw 		B441
rw 		B440
rw 		B439
rw 		B438
rw 		B437
rw 		B436
rw 		B435
rw 		B434
rw 		B433
rw 		B432
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B431
rw 		B430
rw 		B429
rw 		B428
rw 		B427
rw 		B426
rw 		B425
rw 		B424
rw 		B423
rw 		B422
rw 		B421
rw 		B420
rw 		B419
rw 		B418
rw 		B417
rw 		B416
rw
Toggle fields

B416

Bit 0: B416.

B417

Bit 1: B417.

B418

Bit 2: B418.

B419

Bit 3: B419.

B420

Bit 4: B420.

B421

Bit 5: B421.

B422

Bit 6: B422.

B423

Bit 7: B423.

B424

Bit 8: B424.

B425

Bit 9: B425.

B426

Bit 10: B426.

B427

Bit 11: B427.

B428

Bit 12: B428.

B429

Bit 13: B429.

B430

Bit 14: B430.

B431

Bit 15: B431.

B432

Bit 16: B432.

B433

Bit 17: B433.

B434

Bit 18: B434.

B435

Bit 19: B435.

B436

Bit 20: B436.

B437

Bit 21: B437.

B438

Bit 22: B438.

B439

Bit 23: B439.

B440

Bit 24: B440.

B441

Bit 25: B441.

B442

Bit 26: B442.

B443

Bit 27: B443.

B444

Bit 28: B444.

B445

Bit 29: B445.

B446

Bit 30: B446.

B447

Bit 31: B447.

MPCBB1_VCTR14

MPCBBx vector register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B479
rw 		B478
rw 		B477
rw 		B476
rw 		B475
rw 		B474
rw 		B473
rw 		B472
rw 		B471
rw 		B470
rw 		B469
rw 		B468
rw 		B467
rw 		B466
rw 		B465
rw 		B464
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B463
rw 		B462
rw 		B461
rw 		B460
rw 		B459
rw 		B458
rw 		B457
rw 		B456
rw 		B455
rw 		B454
rw 		B453
rw 		B452
rw 		B451
rw 		B450
rw 		B449
rw 		B448
rw
Toggle fields

B448

Bit 0: B448.

B449

Bit 1: B449.

B450

Bit 2: B450.

B451

Bit 3: B451.

B452

Bit 4: B452.

B453

Bit 5: B453.

B454

Bit 6: B454.

B455

Bit 7: B455.

B456

Bit 8: B456.

B457

Bit 9: B457.

B458

Bit 10: B458.

B459

Bit 11: B459.

B460

Bit 12: B460.

B461

Bit 13: B461.

B462

Bit 14: B462.

B463

Bit 15: B463.

B464

Bit 16: B464.

B465

Bit 17: B465.

B466

Bit 18: B466.

B467

Bit 19: B467.

B468

Bit 20: B468.

B469

Bit 21: B469.

B470

Bit 22: B470.

B471

Bit 23: B471.

B472

Bit 24: B472.

B473

Bit 25: B473.

B474

Bit 26: B474.

B475

Bit 27: B475.

B476

Bit 28: B476.

B477

Bit 29: B477.

B478

Bit 30: B478.

B479

Bit 31: B479.

MPCBB1_VCTR15

MPCBBx vector register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B511
rw 		B510
rw 		B509
rw 		B508
rw 		B507
rw 		B506
rw 		B505
rw 		B504
rw 		B503
rw 		B502
rw 		B501
rw 		B500
rw 		B499
rw 		B498
rw 		B497
rw 		B496
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B495
rw 		B494
rw 		B493
rw 		B492
rw 		B491
rw 		B490
rw 		B489
rw 		B488
rw 		B487
rw 		B486
rw 		B485
rw 		B484
rw 		B483
rw 		B482
rw 		B481
rw 		B480
rw
Toggle fields

B480

Bit 0: B480.

B481

Bit 1: B481.

B482

Bit 2: B482.

B483

Bit 3: B483.

B484

Bit 4: B484.

B485

Bit 5: B485.

B486

Bit 6: B486.

B487

Bit 7: B487.

B488

Bit 8: B488.

B489

Bit 9: B489.

B490

Bit 10: B490.

B491

Bit 11: B491.

B492

Bit 12: B492.

B493

Bit 13: B493.

B494

Bit 14: B494.

B495

Bit 15: B495.

B496

Bit 16: B496.

B497

Bit 17: B497.

B498

Bit 18: B498.

B499

Bit 19: B499.

B500

Bit 20: B500.

B501

Bit 21: B501.

B502

Bit 22: B502.

B503

Bit 23: B503.

B504

Bit 24: B504.

B505

Bit 25: B505.

B506

Bit 26: B506.

B507

Bit 27: B507.

B508

Bit 28: B508.

B509

Bit 29: B509.

B510

Bit 30: B510.

B511

Bit 31: B511.

MPCBB1_VCTR16

MPCBBx vector register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B543
rw 		B542
rw 		B541
rw 		B540
rw 		B539
rw 		B538
rw 		B537
rw 		B536
rw 		B535
rw 		B534
rw 		B533
rw 		B532
rw 		B531
rw 		B530
rw 		B529
rw 		B528
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B527
rw 		B526
rw 		B525
rw 		B524
rw 		B523
rw 		B522
rw 		B521
rw 		B520
rw 		B519
rw 		B518
rw 		B517
rw 		B516
rw 		B515
rw 		B514
rw 		B513
rw 		B512
rw
Toggle fields

B512

Bit 0: B512.

B513

Bit 1: B513.

B514

Bit 2: B514.

B515

Bit 3: B515.

B516

Bit 4: B516.

B517

Bit 5: B517.

B518

Bit 6: B518.

B519

Bit 7: B519.

B520

Bit 8: B520.

B521

Bit 9: B521.

B522

Bit 10: B522.

B523

Bit 11: B523.

B524

Bit 12: B524.

B525

Bit 13: B525.

B526

Bit 14: B526.

B527

Bit 15: B527.

B528

Bit 16: B528.

B529

Bit 17: B529.

B530

Bit 18: B530.

B531

Bit 19: B531.

B532

Bit 20: B532.

B533

Bit 21: B533.

B534

Bit 22: B534.

B535

Bit 23: B535.

B536

Bit 24: B536.

B537

Bit 25: B537.

B538

Bit 26: B538.

B539

Bit 27: B539.

B540

Bit 28: B540.

B541

Bit 29: B541.

B542

Bit 30: B542.

B543

Bit 31: B543.

MPCBB1_VCTR17

MPCBBx vector register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B575
rw 		B574
rw 		B573
rw 		B572
rw 		B571
rw 		B570
rw 		B569
rw 		B568
rw 		B567
rw 		B566
rw 		B565
rw 		B564
rw 		B563
rw 		B562
rw 		B561
rw 		B560
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B559
rw 		B558
rw 		B557
rw 		B556
rw 		B555
rw 		B554
rw 		B553
rw 		B552
rw 		B551
rw 		B550
rw 		B549
rw 		B548
rw 		B547
rw 		B546
rw 		B545
rw 		B544
rw
Toggle fields

B544

Bit 0: B544.

B545

Bit 1: B545.

B546

Bit 2: B546.

B547

Bit 3: B547.

B548

Bit 4: B548.

B549

Bit 5: B549.

B550

Bit 6: B550.

B551

Bit 7: B551.

B552

Bit 8: B552.

B553

Bit 9: B553.

B554

Bit 10: B554.

B555

Bit 11: B555.

B556

Bit 12: B556.

B557

Bit 13: B557.

B558

Bit 14: B558.

B559

Bit 15: B559.

B560

Bit 16: B560.

B561

Bit 17: B561.

B562

Bit 18: B562.

B563

Bit 19: B563.

B564

Bit 20: B564.

B565

Bit 21: B565.

B566

Bit 22: B566.

B567

Bit 23: B567.

B568

Bit 24: B568.

B569

Bit 25: B569.

B570

Bit 26: B570.

B571

Bit 27: B571.

B572

Bit 28: B572.

B573

Bit 29: B573.

B574

Bit 30: B574.

B575

Bit 31: B575.

MPCBB1_VCTR18

MPCBBx vector register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B607
rw 		B606
rw 		B605
rw 		B604
rw 		B603
rw 		B602
rw 		B601
rw 		B600
rw 		B599
rw 		B598
rw 		B597
rw 		B596
rw 		B595
rw 		B594
rw 		B593
rw 		B592
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B591
rw 		B590
rw 		B589
rw 		B588
rw 		B587
rw 		B586
rw 		B585
rw 		B584
rw 		B583
rw 		B582
rw 		B581
rw 		B580
rw 		B579
rw 		B578
rw 		B577
rw 		B576
rw
Toggle fields

B576

Bit 0: B576.

B577

Bit 1: B577.

B578

Bit 2: B578.

B579

Bit 3: B579.

B580

Bit 4: B580.

B581

Bit 5: B581.

B582

Bit 6: B582.

B583

Bit 7: B583.

B584

Bit 8: B584.

B585

Bit 9: B585.

B586

Bit 10: B586.

B587

Bit 11: B587.

B588

Bit 12: B588.

B589

Bit 13: B589.

B590

Bit 14: B590.

B591

Bit 15: B591.

B592

Bit 16: B592.

B593

Bit 17: B593.

B594

Bit 18: B594.

B595

Bit 19: B595.

B596

Bit 20: B596.

B597

Bit 21: B597.

B598

Bit 22: B598.

B599

Bit 23: B599.

B600

Bit 24: B600.

B601

Bit 25: B601.

B602

Bit 26: B602.

B603

Bit 27: B603.

B604

Bit 28: B604.

B605

Bit 29: B605.

B606

Bit 30: B606.

B607

Bit 31: B607.

MPCBB1_VCTR19

MPCBBx vector register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B639
rw 		B638
rw 		B637
rw 		B636
rw 		B635
rw 		B634
rw 		B633
rw 		B632
rw 		B631
rw 		B630
rw 		B629
rw 		B628
rw 		B627
rw 		B626
rw 		B625
rw 		B624
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B623
rw 		B622
rw 		B621
rw 		B620
rw 		B619
rw 		B618
rw 		B617
rw 		B616
rw 		B615
rw 		B614
rw 		B613
rw 		B612
rw 		B611
rw 		B610
rw 		B609
rw 		B608
rw
Toggle fields

B608

Bit 0: B608.

B609

Bit 1: B609.

B610

Bit 2: B610.

B611

Bit 3: B611.

B612

Bit 4: B612.

B613

Bit 5: B613.

B614

Bit 6: B614.

B615

Bit 7: B615.

B616

Bit 8: B616.

B617

Bit 9: B617.

B618

Bit 10: B618.

B619

Bit 11: B619.

B620

Bit 12: B620.

B621

Bit 13: B621.

B622

Bit 14: B622.

B623

Bit 15: B623.

B624

Bit 16: B624.

B625

Bit 17: B625.

B626

Bit 18: B626.

B627

Bit 19: B627.

B628

Bit 20: B628.

B629

Bit 21: B629.

B630

Bit 22: B630.

B631

Bit 23: B631.

B632

Bit 24: B632.

B633

Bit 25: B633.

B634

Bit 26: B634.

B635

Bit 27: B635.

B636

Bit 28: B636.

B637

Bit 29: B637.

B638

Bit 30: B638.

B639

Bit 31: B639.

MPCBB1_VCTR20

MPCBBx vector register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B671
rw 		B670
rw 		B669
rw 		B668
rw 		B667
rw 		B666
rw 		B665
rw 		B664
rw 		B663
rw 		B662
rw 		B661
rw 		B660
rw 		B659
rw 		B658
rw 		B657
rw 		B656
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B655
rw 		B654
rw 		B653
rw 		B652
rw 		B651
rw 		B650
rw 		B649
rw 		B648
rw 		B647
rw 		B646
rw 		B645
rw 		B644
rw 		B643
rw 		B642
rw 		B641
rw 		B640
rw
Toggle fields

B640

Bit 0: B640.

B641

Bit 1: B641.

B642

Bit 2: B642.

B643

Bit 3: B643.

B644

Bit 4: B644.

B645

Bit 5: B645.

B646

Bit 6: B646.

B647

Bit 7: B647.

B648

Bit 8: B648.

B649

Bit 9: B649.

B650

Bit 10: B650.

B651

Bit 11: B651.

B652

Bit 12: B652.

B653

Bit 13: B653.

B654

Bit 14: B654.

B655

Bit 15: B655.

B656

Bit 16: B656.

B657

Bit 17: B657.

B658

Bit 18: B658.

B659

Bit 19: B659.

B660

Bit 20: B660.

B661

Bit 21: B661.

B662

Bit 22: B662.

B663

Bit 23: B663.

B664

Bit 24: B664.

B665

Bit 25: B665.

B666

Bit 26: B666.

B667

Bit 27: B667.

B668

Bit 28: B668.

B669

Bit 29: B669.

B670

Bit 30: B670.

B671

Bit 31: B671.

MPCBB1_VCTR21

MPCBBx vector register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B703
rw 		B702
rw 		B701
rw 		B700
rw 		B699
rw 		B698
rw 		B697
rw 		B696
rw 		B695
rw 		B694
rw 		B693
rw 		B692
rw 		B691
rw 		B690
rw 		B689
rw 		B688
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B687
rw 		B686
rw 		B685
rw 		B684
rw 		B683
rw 		B682
rw 		B681
rw 		B680
rw 		B679
rw 		B678
rw 		B677
rw 		B676
rw 		B675
rw 		B674
rw 		B673
rw 		B672
rw
Toggle fields

B672

Bit 0: B672.

B673

Bit 1: B673.

B674

Bit 2: B674.

B675

Bit 3: B675.

B676

Bit 4: B676.

B677

Bit 5: B677.

B678

Bit 6: B678.

B679

Bit 7: B679.

B680

Bit 8: B680.

B681

Bit 9: B681.

B682

Bit 10: B682.

B683

Bit 11: B683.

B684

Bit 12: B684.

B685

Bit 13: B685.

B686

Bit 14: B686.

B687

Bit 15: B687.

B688

Bit 16: B688.

B689

Bit 17: B689.

B690

Bit 18: B690.

B691

Bit 19: B691.

B692

Bit 20: B692.

B693

Bit 21: B693.

B694

Bit 22: B694.

B695

Bit 23: B695.

B696

Bit 24: B696.

B697

Bit 25: B697.

B698

Bit 26: B698.

B699

Bit 27: B699.

B700

Bit 28: B700.

B701

Bit 29: B701.

B702

Bit 30: B702.

B703

Bit 31: B703.

MPCBB1_VCTR22

MPCBBx vector register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B735
rw 		B734
rw 		B733
rw 		B732
rw 		B731
rw 		B730
rw 		B729
rw 		B728
rw 		B727
rw 		B726
rw 		B725
rw 		B724
rw 		B723
rw 		B722
rw 		B721
rw 		B720
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B719
rw 		B718
rw 		B717
rw 		B716
rw 		B715
rw 		B714
rw 		B713
rw 		B712
rw 		B711
rw 		B710
rw 		B709
rw 		B708
rw 		B707
rw 		B706
rw 		B705
rw 		B704
rw
Toggle fields

B704

Bit 0: B704.

B705

Bit 1: B705.

B706

Bit 2: B706.

B707

Bit 3: B707.

B708

Bit 4: B708.

B709

Bit 5: B709.

B710

Bit 6: B710.

B711

Bit 7: B711.

B712

Bit 8: B712.

B713

Bit 9: B713.

B714

Bit 10: B714.

B715

Bit 11: B715.

B716

Bit 12: B716.

B717

Bit 13: B717.

B718

Bit 14: B718.

B719

Bit 15: B719.

B720

Bit 16: B720.

B721

Bit 17: B721.

B722

Bit 18: B722.

B723

Bit 19: B723.

B724

Bit 20: B724.

B725

Bit 21: B725.

B726

Bit 22: B726.

B727

Bit 23: B727.

B728

Bit 24: B728.

B729

Bit 25: B729.

B730

Bit 26: B730.

B731

Bit 27: B731.

B732

Bit 28: B732.

B733

Bit 29: B733.

B734

Bit 30: B734.

B735

Bit 31: B735.

MPCBB1_VCTR23

MPCBBx vector register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B767
rw 		B766
rw 		B765
rw 		B764
rw 		B763
rw 		B762
rw 		B761
rw 		B760
rw 		B759
rw 		B758
rw 		B757
rw 		B756
rw 		B755
rw 		B754
rw 		B753
rw 		B752
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B751
rw 		B750
rw 		B749
rw 		B748
rw 		B747
rw 		B746
rw 		B745
rw 		B744
rw 		B743
rw 		B742
rw 		B741
rw 		B740
rw 		B739
rw 		B738
rw 		B737
rw 		B736
rw
Toggle fields

B736

Bit 0: B736.

B737

Bit 1: B737.

B738

Bit 2: B738.

B739

Bit 3: B739.

B740

Bit 4: B740.

B741

Bit 5: B741.

B742

Bit 6: B742.

B743

Bit 7: B743.

B744

Bit 8: B744.

B745

Bit 9: B745.

B746

Bit 10: B746.

B747

Bit 11: B747.

B748

Bit 12: B748.

B749

Bit 13: B749.

B750

Bit 14: B750.

B751

Bit 15: B751.

B752

Bit 16: B752.

B753

Bit 17: B753.

B754

Bit 18: B754.

B755

Bit 19: B755.

B756

Bit 20: B756.

B757

Bit 21: B757.

B758

Bit 22: B758.

B759

Bit 23: B759.

B760

Bit 24: B760.

B761

Bit 25: B761.

B762

Bit 26: B762.

B763

Bit 27: B763.

B764

Bit 28: B764.

B765

Bit 29: B765.

B766

Bit 30: B766.

B767

Bit 31: B767.

MPCBB1_VCTR24

MPCBBx vector register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B799
rw 		B798
rw 		B797
rw 		B796
rw 		B795
rw 		B794
rw 		B793
rw 		B792
rw 		B791
rw 		B790
rw 		B789
rw 		B788
rw 		B787
rw 		B786
rw 		B785
rw 		B784
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B783
rw 		B782
rw 		B781
rw 		B780
rw 		B779
rw 		B778
rw 		B777
rw 		B776
rw 		B775
rw 		B774
rw 		B773
rw 		B772
rw 		B771
rw 		B770
rw 		B769
rw 		B768
rw
Toggle fields

B768

Bit 0: B768.

B769

Bit 1: B769.

B770

Bit 2: B770.

B771

Bit 3: B771.

B772

Bit 4: B772.

B773

Bit 5: B773.

B774

Bit 6: B774.

B775

Bit 7: B775.

B776

Bit 8: B776.

B777

Bit 9: B777.

B778

Bit 10: B778.

B779

Bit 11: B779.

B780

Bit 12: B780.

B781

Bit 13: B781.

B782

Bit 14: B782.

B783

Bit 15: B783.

B784

Bit 16: B784.

B785

Bit 17: B785.

B786

Bit 18: B786.

B787

Bit 19: B787.

B788

Bit 20: B788.

B789

Bit 21: B789.

B790

Bit 22: B790.

B791

Bit 23: B791.

B792

Bit 24: B792.

B793

Bit 25: B793.

B794

Bit 26: B794.

B795

Bit 27: B795.

B796

Bit 28: B796.

B797

Bit 29: B797.

B798

Bit 30: B798.

B799

Bit 31: B799.

MPCBB1_VCTR25

MPCBBx vector register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B831
rw 		B830
rw 		B829
rw 		B828
rw 		B827
rw 		B826
rw 		B825
rw 		B824
rw 		B823
rw 		B822
rw 		B821
rw 		B820
rw 		B819
rw 		B818
rw 		B817
rw 		B816
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B815
rw 		B814
rw 		B813
rw 		B812
rw 		B811
rw 		B810
rw 		B809
rw 		B808
rw 		B807
rw 		B806
rw 		B805
rw 		B804
rw 		B803
rw 		B802
rw 		B801
rw 		B800
rw
Toggle fields

B800

Bit 0: B800.

B801

Bit 1: B801.

B802

Bit 2: B802.

B803

Bit 3: B803.

B804

Bit 4: B804.

B805

Bit 5: B805.

B806

Bit 6: B806.

B807

Bit 7: B807.

B808

Bit 8: B808.

B809

Bit 9: B809.

B810

Bit 10: B810.

B811

Bit 11: B811.

B812

Bit 12: B812.

B813

Bit 13: B813.

B814

Bit 14: B814.

B815

Bit 15: B815.

B816

Bit 16: B816.

B817

Bit 17: B817.

B818

Bit 18: B818.

B819

Bit 19: B819.

B820

Bit 20: B820.

B821

Bit 21: B821.

B822

Bit 22: B822.

B823

Bit 23: B823.

B824

Bit 24: B824.

B825

Bit 25: B825.

B826

Bit 26: B826.

B827

Bit 27: B827.

B828

Bit 28: B828.

B829

Bit 29: B829.

B830

Bit 30: B830.

B831

Bit 31: B831.

MPCBB1_VCTR26

MPCBBx vector register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B863
rw 		B862
rw 		B861
rw 		B860
rw 		B859
rw 		B858
rw 		B857
rw 		B856
rw 		B855
rw 		B854
rw 		B853
rw 		B852
rw 		B851
rw 		B850
rw 		B849
rw 		B848
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B847
rw 		B846
rw 		B845
rw 		B844
rw 		B843
rw 		B842
rw 		B841
rw 		B840
rw 		B839
rw 		B838
rw 		B837
rw 		B836
rw 		B835
rw 		B834
rw 		B833
rw 		B832
rw
Toggle fields

B832

Bit 0: B832.

B833

Bit 1: B833.

B834

Bit 2: B834.

B835

Bit 3: B835.

B836

Bit 4: B836.

B837

Bit 5: B837.

B838

Bit 6: B838.

B839

Bit 7: B839.

B840

Bit 8: B840.

B841

Bit 9: B841.

B842

Bit 10: B842.

B843

Bit 11: B843.

B844

Bit 12: B844.

B845

Bit 13: B845.

B846

Bit 14: B846.

B847

Bit 15: B847.

B848

Bit 16: B848.

B849

Bit 17: B849.

B850

Bit 18: B850.

B851

Bit 19: B851.

B852

Bit 20: B852.

B853

Bit 21: B853.

B854

Bit 22: B854.

B855

Bit 23: B855.

B856

Bit 24: B856.

B857

Bit 25: B857.

B858

Bit 26: B858.

B859

Bit 27: B859.

B860

Bit 28: B860.

B861

Bit 29: B861.

B862

Bit 30: B862.

B863

Bit 31: B863.

MPCBB1_VCTR27

MPCBBx vector register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B895
rw 		B894
rw 		B893
rw 		B892
rw 		B891
rw 		B890
rw 		B889
rw 		B888
rw 		B887
rw 		B886
rw 		B885
rw 		B884
rw 		B883
rw 		B882
rw 		B881
rw 		B880
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B879
rw 		B878
rw 		B877
rw 		B876
rw 		B875
rw 		B874
rw 		B873
rw 		B872
rw 		B871
rw 		B870
rw 		B869
rw 		B868
rw 		B867
rw 		B866
rw 		B865
rw 		B864
rw
Toggle fields

B864

Bit 0: B864.

B865

Bit 1: B865.

B866

Bit 2: B866.

B867

Bit 3: B867.

B868

Bit 4: B868.

B869

Bit 5: B869.

B870

Bit 6: B870.

B871

Bit 7: B871.

B872

Bit 8: B872.

B873

Bit 9: B873.

B874

Bit 10: B874.

B875

Bit 11: B875.

B876

Bit 12: B876.

B877

Bit 13: B877.

B878

Bit 14: B878.

B879

Bit 15: B879.

B880

Bit 16: B880.

B881

Bit 17: B881.

B882

Bit 18: B882.

B883

Bit 19: B883.

B884

Bit 20: B884.

B885

Bit 21: B885.

B886

Bit 22: B886.

B887

Bit 23: B887.

B888

Bit 24: B888.

B889

Bit 25: B889.

B890

Bit 26: B890.

B891

Bit 27: B891.

B892

Bit 28: B892.

B893

Bit 29: B893.

B894

Bit 30: B894.

B895

Bit 31: B895.

MPCBB1_VCTR28

MPCBBx vector register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B927
rw 		B926
rw 		B925
rw 		B924
rw 		B923
rw 		B922
rw 		B921
rw 		B920
rw 		B919
rw 		B918
rw 		B917
rw 		B916
rw 		B915
rw 		B914
rw 		B913
rw 		B912
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B911
rw 		B910
rw 		B909
rw 		B908
rw 		B907
rw 		B906
rw 		B905
rw 		B904
rw 		B903
rw 		B902
rw 		B901
rw 		B900
rw 		B899
rw 		B898
rw 		B897
rw 		B896
rw
Toggle fields

B896

Bit 0: B896.

B897

Bit 1: B897.

B898

Bit 2: B898.

B899

Bit 3: B899.

B900

Bit 4: B900.

B901

Bit 5: B901.

B902

Bit 6: B902.

B903

Bit 7: B903.

B904

Bit 8: B904.

B905

Bit 9: B905.

B906

Bit 10: B906.

B907

Bit 11: B907.

B908

Bit 12: B908.

B909

Bit 13: B909.

B910

Bit 14: B910.

B911

Bit 15: B911.

B912

Bit 16: B912.

B913

Bit 17: B913.

B914

Bit 18: B914.

B915

Bit 19: B915.

B916

Bit 20: B916.

B917

Bit 21: B917.

B918

Bit 22: B918.

B919

Bit 23: B919.

B920

Bit 24: B920.

B921

Bit 25: B921.

B922

Bit 26: B922.

B923

Bit 27: B923.

B924

Bit 28: B924.

B925

Bit 29: B925.

B926

Bit 30: B926.

B927

Bit 31: B927.

MPCBB1_VCTR29

MPCBBx vector register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B959
rw 		B958
rw 		B957
rw 		B956
rw 		B955
rw 		B954
rw 		B953
rw 		B952
rw 		B951
rw 		B950
rw 		B949
rw 		B948
rw 		B947
rw 		B946
rw 		B945
rw 		B944
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B943
rw 		B942
rw 		B941
rw 		B940
rw 		B939
rw 		B938
rw 		B937
rw 		B936
rw 		B935
rw 		B934
rw 		B933
rw 		B932
rw 		B931
rw 		B930
rw 		B929
rw 		B928
rw
Toggle fields

B928

Bit 0: B928.

B929

Bit 1: B929.

B930

Bit 2: B930.

B931

Bit 3: B931.

B932

Bit 4: B932.

B933

Bit 5: B933.

B934

Bit 6: B934.

B935

Bit 7: B935.

B936

Bit 8: B936.

B937

Bit 9: B937.

B938

Bit 10: B938.

B939

Bit 11: B939.

B940

Bit 12: B940.

B941

Bit 13: B941.

B942

Bit 14: B942.

B943

Bit 15: B943.

B944

Bit 16: B944.

B945

Bit 17: B945.

B946

Bit 18: B946.

B947

Bit 19: B947.

B948

Bit 20: B948.

B949

Bit 21: B949.

B950

Bit 22: B950.

B951

Bit 23: B951.

B952

Bit 24: B952.

B953

Bit 25: B953.

B954

Bit 26: B954.

B955

Bit 27: B955.

B956

Bit 28: B956.

B957

Bit 29: B957.

B958

Bit 30: B958.

B959

Bit 31: B959.

MPCBB1_VCTR30

MPCBBx vector register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B991
rw 		B990
rw 		B989
rw 		B988
rw 		B987
rw 		B986
rw 		B985
rw 		B984
rw 		B983
rw 		B982
rw 		B981
rw 		B980
rw 		B979
rw 		B978
rw 		B977
rw 		B976
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B975
rw 		B974
rw 		B973
rw 		B972
rw 		B971
rw 		B970
rw 		B969
rw 		B968
rw 		B967
rw 		B966
rw 		B965
rw 		B964
rw 		B963
rw 		B962
rw 		B961
rw 		B960
rw
Toggle fields

B960

Bit 0: B960.

B961

Bit 1: B961.

B962

Bit 2: B962.

B963

Bit 3: B963.

B964

Bit 4: B964.

B965

Bit 5: B965.

B966

Bit 6: B966.

B967

Bit 7: B967.

B968

Bit 8: B968.

B969

Bit 9: B969.

B970

Bit 10: B970.

B971

Bit 11: B971.

B972

Bit 12: B972.

B973

Bit 13: B973.

B974

Bit 14: B974.

B975

Bit 15: B975.

B976

Bit 16: B976.

B977

Bit 17: B977.

B978

Bit 18: B978.

B979

Bit 19: B979.

B980

Bit 20: B980.

B981

Bit 21: B981.

B982

Bit 22: B982.

B983

Bit 23: B983.

B984

Bit 24: B984.

B985

Bit 25: B985.

B986

Bit 26: B986.

B987

Bit 27: B987.

B988

Bit 28: B988.

B989

Bit 29: B989.

B990

Bit 30: B990.

B991

Bit 31: B991.

MPCBB1_VCTR31

MPCBBx vector register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1023
rw 		B1022
rw 		B1021
rw 		B1020
rw 		B1019
rw 		B1018
rw 		B1017
rw 		B1016
rw 		B1015
rw 		B1014
rw 		B1013
rw 		B1012
rw 		B1011
rw 		B1010
rw 		B1009
rw 		B1008
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1007
rw 		B1006
rw 		B1005
rw 		B1004
rw 		B1003
rw 		B1002
rw 		B1001
rw 		B1000
rw 		B999
rw 		B998
rw 		B997
rw 		B996
rw 		B995
rw 		B994
rw 		B993
rw 		B992
rw
Toggle fields

B992

Bit 0: B992.

B993

Bit 1: B993.

B994

Bit 2: B994.

B995

Bit 3: B995.

B996

Bit 4: B996.

B997

Bit 5: B997.

B998

Bit 6: B998.

B999

Bit 7: B999.

B1000

Bit 8: B1000.

B1001

Bit 9: B1001.

B1002

Bit 10: B1002.

B1003

Bit 11: B1003.

B1004

Bit 12: B1004.

B1005

Bit 13: B1005.

B1006

Bit 14: B1006.

B1007

Bit 15: B1007.

B1008

Bit 16: B1008.

B1009

Bit 17: B1009.

B1010

Bit 18: B1010.

B1011

Bit 19: B1011.

B1012

Bit 20: B1012.

B1013

Bit 21: B1013.

B1014

Bit 22: B1014.

B1015

Bit 23: B1015.

B1016

Bit 24: B1016.

B1017

Bit 25: B1017.

B1018

Bit 26: B1018.

B1019

Bit 27: B1019.

B1020

Bit 28: B1020.

B1021

Bit 29: B1021.

B1022

Bit 30: B1022.

B1023

Bit 31: B1023.

MPCBB1_VCTR32

MPCBBx vector register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1055
rw 		B1054
rw 		B1053
rw 		B1052
rw 		B1051
rw 		B1050
rw 		B1049
rw 		B1048
rw 		B1047
rw 		B1046
rw 		B1045
rw 		B1044
rw 		B1043
rw 		B1042
rw 		B1041
rw 		B1040
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1039
rw 		B1038
rw 		B1037
rw 		B1036
rw 		B1035
rw 		B1034
rw 		B1033
rw 		B1032
rw 		B1031
rw 		B1030
rw 		B1029
rw 		B1028
rw 		B1027
rw 		B1026
rw 		B1025
rw 		B1024
rw
Toggle fields

B1024

Bit 0: B1024.

B1025

Bit 1: B1025.

B1026

Bit 2: B1026.

B1027

Bit 3: B1027.

B1028

Bit 4: B1028.

B1029

Bit 5: B1029.

B1030

Bit 6: B1030.

B1031

Bit 7: B1031.

B1032

Bit 8: B1032.

B1033

Bit 9: B1033.

B1034

Bit 10: B1034.

B1035

Bit 11: B1035.

B1036

Bit 12: B1036.

B1037

Bit 13: B1037.

B1038

Bit 14: B1038.

B1039

Bit 15: B1039.

B1040

Bit 16: B1040.

B1041

Bit 17: B1041.

B1042

Bit 18: B1042.

B1043

Bit 19: B1043.

B1044

Bit 20: B1044.

B1045

Bit 21: B1045.

B1046

Bit 22: B1046.

B1047

Bit 23: B1047.

B1048

Bit 24: B1048.

B1049

Bit 25: B1049.

B1050

Bit 26: B1050.

B1051

Bit 27: B1051.

B1052

Bit 28: B1052.

B1053

Bit 29: B1053.

B1054

Bit 30: B1054.

B1055

Bit 31: B1055.

MPCBB1_VCTR33

MPCBBx vector register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1087
rw 		B1086
rw 		B1085
rw 		B1084
rw 		B1083
rw 		B1082
rw 		B1081
rw 		B1080
rw 		B1079
rw 		B1078
rw 		B1077
rw 		B1076
rw 		B1075
rw 		B1074
rw 		B1073
rw 		B1072
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1071
rw 		B1070
rw 		B1069
rw 		B1068
rw 		B1067
rw 		B1066
rw 		B1065
rw 		B1064
rw 		B1063
rw 		B1062
rw 		B1061
rw 		B1060
rw 		B1059
rw 		B1058
rw 		B1057
rw 		B1056
rw
Toggle fields

B1056

Bit 0: B1056.

B1057

Bit 1: B1057.

B1058

Bit 2: B1058.

B1059

Bit 3: B1059.

B1060

Bit 4: B1060.

B1061

Bit 5: B1061.

B1062

Bit 6: B1062.

B1063

Bit 7: B1063.

B1064

Bit 8: B1064.

B1065

Bit 9: B1065.

B1066

Bit 10: B1066.

B1067

Bit 11: B1067.

B1068

Bit 12: B1068.

B1069

Bit 13: B1069.

B1070

Bit 14: B1070.

B1071

Bit 15: B1071.

B1072

Bit 16: B1072.

B1073

Bit 17: B1073.

B1074

Bit 18: B1074.

B1075

Bit 19: B1075.

B1076

Bit 20: B1076.

B1077

Bit 21: B1077.

B1078

Bit 22: B1078.

B1079

Bit 23: B1079.

B1080

Bit 24: B1080.

B1081

Bit 25: B1081.

B1082

Bit 26: B1082.

B1083

Bit 27: B1083.

B1084

Bit 28: B1084.

B1085

Bit 29: B1085.

B1086

Bit 30: B1086.

B1087

Bit 31: B1087.

MPCBB1_VCTR34

MPCBBx vector register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1119
rw 		B1118
rw 		B1117
rw 		B1116
rw 		B1115
rw 		B1114
rw 		B1113
rw 		B1112
rw 		B1111
rw 		B1110
rw 		B1109
rw 		B1108
rw 		B1107
rw 		B1106
rw 		B1105
rw 		B1104
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1103
rw 		B1102
rw 		B1101
rw 		B1100
rw 		B1099
rw 		B1098
rw 		B1097
rw 		B1096
rw 		B1095
rw 		B1094
rw 		B1093
rw 		B1092
rw 		B1091
rw 		B1090
rw 		B1089
rw 		B1088
rw
Toggle fields

B1088

Bit 0: B1088.

B1089

Bit 1: B1089.

B1090

Bit 2: B1090.

B1091

Bit 3: B1091.

B1092

Bit 4: B1092.

B1093

Bit 5: B1093.

B1094

Bit 6: B1094.

B1095

Bit 7: B1095.

B1096

Bit 8: B1096.

B1097

Bit 9: B1097.

B1098

Bit 10: B1098.

B1099

Bit 11: B1099.

B1100

Bit 12: B1100.

B1101

Bit 13: B1101.

B1102

Bit 14: B1102.

B1103

Bit 15: B1103.

B1104

Bit 16: B1104.

B1105

Bit 17: B1105.

B1106

Bit 18: B1106.

B1107

Bit 19: B1107.

B1108

Bit 20: B1108.

B1109

Bit 21: B1109.

B1110

Bit 22: B1110.

B1111

Bit 23: B1111.

B1112

Bit 24: B1112.

B1113

Bit 25: B1113.

B1114

Bit 26: B1114.

B1115

Bit 27: B1115.

B1116

Bit 28: B1116.

B1117

Bit 29: B1117.

B1118

Bit 30: B1118.

B1119

Bit 31: B1119.

MPCBB1_VCTR35

MPCBBx vector register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1151
rw 		B1150
rw 		B1149
rw 		B1148
rw 		B1147
rw 		B1146
rw 		B1145
rw 		B1144
rw 		B1143
rw 		B1142
rw 		B1141
rw 		B1140
rw 		B1139
rw 		B1138
rw 		B1137
rw 		B1136
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1135
rw 		B1134
rw 		B1133
rw 		B1132
rw 		B1131
rw 		B1130
rw 		B1129
rw 		B1128
rw 		B1127
rw 		B1126
rw 		B1125
rw 		B1124
rw 		B1123
rw 		B1122
rw 		B1121
rw 		B1120
rw
Toggle fields

B1120

Bit 0: B1120.

B1121

Bit 1: B1121.

B1122

Bit 2: B1122.

B1123

Bit 3: B1123.

B1124

Bit 4: B1124.

B1125

Bit 5: B1125.

B1126

Bit 6: B1126.

B1127

Bit 7: B1127.

B1128

Bit 8: B1128.

B1129

Bit 9: B1129.

B1130

Bit 10: B1130.

B1131

Bit 11: B1131.

B1132

Bit 12: B1132.

B1133

Bit 13: B1133.

B1134

Bit 14: B1134.

B1135

Bit 15: B1135.

B1136

Bit 16: B1136.

B1137

Bit 17: B1137.

B1138

Bit 18: B1138.

B1139

Bit 19: B1139.

B1140

Bit 20: B1140.

B1141

Bit 21: B1141.

B1142

Bit 22: B1142.

B1143

Bit 23: B1143.

B1144

Bit 24: B1144.

B1145

Bit 25: B1145.

B1146

Bit 26: B1146.

B1147

Bit 27: B1147.

B1148

Bit 28: B1148.

B1149

Bit 29: B1149.

B1150

Bit 30: B1150.

B1151

Bit 31: B1151.

MPCBB1_VCTR36

MPCBBx vector register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1183
rw 		B1182
rw 		B1181
rw 		B1180
rw 		B1179
rw 		B1178
rw 		B1177
rw 		B1176
rw 		B1175
rw 		B1174
rw 		B1173
rw 		B1172
rw 		B1171
rw 		B1170
rw 		B1169
rw 		B1168
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1167
rw 		B1166
rw 		B1165
rw 		B1164
rw 		B1163
rw 		B1162
rw 		B1161
rw 		B1160
rw 		B1159
rw 		B1158
rw 		B1157
rw 		B1156
rw 		B1155
rw 		B1154
rw 		B1153
rw 		B1152
rw
Toggle fields

B1152

Bit 0: B1152.

B1153

Bit 1: B1153.

B1154

Bit 2: B1154.

B1155

Bit 3: B1155.

B1156

Bit 4: B1156.

B1157

Bit 5: B1157.

B1158

Bit 6: B1158.

B1159

Bit 7: B1159.

B1160

Bit 8: B1160.

B1161

Bit 9: B1161.

B1162

Bit 10: B1162.

B1163

Bit 11: B1163.

B1164

Bit 12: B1164.

B1165

Bit 13: B1165.

B1166

Bit 14: B1166.

B1167

Bit 15: B1167.

B1168

Bit 16: B1168.

B1169

Bit 17: B1169.

B1170

Bit 18: B1170.

B1171

Bit 19: B1171.

B1172

Bit 20: B1172.

B1173

Bit 21: B1173.

B1174

Bit 22: B1174.

B1175

Bit 23: B1175.

B1176

Bit 24: B1176.

B1177

Bit 25: B1177.

B1178

Bit 26: B1178.

B1179

Bit 27: B1179.

B1180

Bit 28: B1180.

B1181

Bit 29: B1181.

B1182

Bit 30: B1182.

B1183

Bit 31: B1183.

MPCBB1_VCTR37

MPCBBx vector register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1215
rw 		B1214
rw 		B1213
rw 		B1212
rw 		B1211
rw 		B1210
rw 		B1209
rw 		B1208
rw 		B1207
rw 		B1206
rw 		B1205
rw 		B1204
rw 		B1203
rw 		B1202
rw 		B1201
rw 		B1200
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1199
rw 		B1198
rw 		B1197
rw 		B1196
rw 		B1195
rw 		B1194
rw 		B1193
rw 		B1192
rw 		B1191
rw 		B1190
rw 		B1189
rw 		B1188
rw 		B1187
rw 		B1186
rw 		B1185
rw 		B1184
rw
Toggle fields

B1184

Bit 0: B1184.

B1185

Bit 1: B1185.

B1186

Bit 2: B1186.

B1187

Bit 3: B1187.

B1188

Bit 4: B1188.

B1189

Bit 5: B1189.

B1190

Bit 6: B1190.

B1191

Bit 7: B1191.

B1192

Bit 8: B1192.

B1193

Bit 9: B1193.

B1194

Bit 10: B1194.

B1195

Bit 11: B1195.

B1196

Bit 12: B1196.

B1197

Bit 13: B1197.

B1198

Bit 14: B1198.

B1199

Bit 15: B1199.

B1200

Bit 16: B1200.

B1201

Bit 17: B1201.

B1202

Bit 18: B1202.

B1203

Bit 19: B1203.

B1204

Bit 20: B1204.

B1205

Bit 21: B1205.

B1206

Bit 22: B1206.

B1207

Bit 23: B1207.

B1208

Bit 24: B1208.

B1209

Bit 25: B1209.

B1210

Bit 26: B1210.

B1211

Bit 27: B1211.

B1212

Bit 28: B1212.

B1213

Bit 29: B1213.

B1214

Bit 30: B1214.

B1215

Bit 31: B1215.

MPCBB1_VCTR38

MPCBBx vector register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1247
rw 		B1246
rw 		B1245
rw 		B1244
rw 		B1243
rw 		B1242
rw 		B1241
rw 		B1240
rw 		B1239
rw 		B1238
rw 		B1237
rw 		B1236
rw 		B1235
rw 		B1234
rw 		B1233
rw 		B1232
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1231
rw 		B1230
rw 		B1229
rw 		B1228
rw 		B1227
rw 		B1226
rw 		B1225
rw 		B1224
rw 		B1223
rw 		B1222
rw 		B1221
rw 		B1220
rw 		B1219
rw 		B1218
rw 		B1217
rw 		B1216
rw
Toggle fields

B1216

Bit 0: B1216.

B1217

Bit 1: B1217.

B1218

Bit 2: B1218.

B1219

Bit 3: B1219.

B1220

Bit 4: B1220.

B1221

Bit 5: B1221.

B1222

Bit 6: B1222.

B1223

Bit 7: B1223.

B1224

Bit 8: B1224.

B1225

Bit 9: B1225.

B1226

Bit 10: B1226.

B1227

Bit 11: B1227.

B1228

Bit 12: B1228.

B1229

Bit 13: B1229.

B1230

Bit 14: B1230.

B1231

Bit 15: B1231.

B1232

Bit 16: B1232.

B1233

Bit 17: B1233.

B1234

Bit 18: B1234.

B1235

Bit 19: B1235.

B1236

Bit 20: B1236.

B1237

Bit 21: B1237.

B1238

Bit 22: B1238.

B1239

Bit 23: B1239.

B1240

Bit 24: B1240.

B1241

Bit 25: B1241.

B1242

Bit 26: B1242.

B1243

Bit 27: B1243.

B1244

Bit 28: B1244.

B1245

Bit 29: B1245.

B1246

Bit 30: B1246.

B1247

Bit 31: B1247.

MPCBB1_VCTR39

MPCBBx vector register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1279
rw 		B1278
rw 		B1277
rw 		B1276
rw 		B1275
rw 		B1274
rw 		B1273
rw 		B1272
rw 		B1271
rw 		B1270
rw 		B1269
rw 		B1268
rw 		B1267
rw 		B1266
rw 		B1265
rw 		B1264
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1263
rw 		B1262
rw 		B1261
rw 		B1260
rw 		B1259
rw 		B1258
rw 		B1257
rw 		B1256
rw 		B1255
rw 		B1254
rw 		B1253
rw 		B1252
rw 		B1251
rw 		B1250
rw 		B1249
rw 		B1248
rw
Toggle fields

B1248

Bit 0: B1248.

B1249

Bit 1: B1249.

B1250

Bit 2: B1250.

B1251

Bit 3: B1251.

B1252

Bit 4: B1252.

B1253

Bit 5: B1253.

B1254

Bit 6: B1254.

B1255

Bit 7: B1255.

B1256

Bit 8: B1256.

B1257

Bit 9: B1257.

B1258

Bit 10: B1258.

B1259

Bit 11: B1259.

B1260

Bit 12: B1260.

B1261

Bit 13: B1261.

B1262

Bit 14: B1262.

B1263

Bit 15: B1263.

B1264

Bit 16: B1264.

B1265

Bit 17: B1265.

B1266

Bit 18: B1266.

B1267

Bit 19: B1267.

B1268

Bit 20: B1268.

B1269

Bit 21: B1269.

B1270

Bit 22: B1270.

B1271

Bit 23: B1271.

B1272

Bit 24: B1272.

B1273

Bit 25: B1273.

B1274

Bit 26: B1274.

B1275

Bit 27: B1275.

B1276

Bit 28: B1276.

B1277

Bit 29: B1277.

B1278

Bit 30: B1278.

B1279

Bit 31: B1279.

MPCBB1_VCTR40

MPCBBx vector register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1311
rw 		B1310
rw 		B1309
rw 		B1308
rw 		B1307
rw 		B1306
rw 		B1305
rw 		B1304
rw 		B1303
rw 		B1302
rw 		B1301
rw 		B1300
rw 		B1299
rw 		B1298
rw 		B1297
rw 		B1296
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1295
rw 		B1294
rw 		B1293
rw 		B1292
rw 		B1291
rw 		B1290
rw 		B1289
rw 		B1288
rw 		B1287
rw 		B1286
rw 		B1285
rw 		B1284
rw 		B1283
rw 		B1282
rw 		B1281
rw 		B1280
rw
Toggle fields

B1280

Bit 0: B1280.

B1281

Bit 1: B1281.

B1282

Bit 2: B1282.

B1283

Bit 3: B1283.

B1284

Bit 4: B1284.

B1285

Bit 5: B1285.

B1286

Bit 6: B1286.

B1287

Bit 7: B1287.

B1288

Bit 8: B1288.

B1289

Bit 9: B1289.

B1290

Bit 10: B1290.

B1291

Bit 11: B1291.

B1292

Bit 12: B1292.

B1293

Bit 13: B1293.

B1294

Bit 14: B1294.

B1295

Bit 15: B1295.

B1296

Bit 16: B1296.

B1297

Bit 17: B1297.

B1298

Bit 18: B1298.

B1299

Bit 19: B1299.

B1300

Bit 20: B1300.

B1301

Bit 21: B1301.

B1302

Bit 22: B1302.

B1303

Bit 23: B1303.

B1304

Bit 24: B1304.

B1305

Bit 25: B1305.

B1306

Bit 26: B1306.

B1307

Bit 27: B1307.

B1308

Bit 28: B1308.

B1309

Bit 29: B1309.

B1310

Bit 30: B1310.

B1311

Bit 31: B1311.

MPCBB1_VCTR41

MPCBBx vector register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1343
rw 		B1342
rw 		B1341
rw 		B1340
rw 		B1339
rw 		B1338
rw 		B1337
rw 		B1336
rw 		B1335
rw 		B1334
rw 		B1333
rw 		B1332
rw 		B1331
rw 		B1330
rw 		B1329
rw 		B1328
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1327
rw 		B1326
rw 		B1325
rw 		B1324
rw 		B1323
rw 		B1322
rw 		B1321
rw 		B1320
rw 		B1319
rw 		B1318
rw 		B1317
rw 		B1316
rw 		B1315
rw 		B1314
rw 		B1313
rw 		B1312
rw
Toggle fields

B1312

Bit 0: B1312.

B1313

Bit 1: B1313.

B1314

Bit 2: B1314.

B1315

Bit 3: B1315.

B1316

Bit 4: B1316.

B1317

Bit 5: B1317.

B1318

Bit 6: B1318.

B1319

Bit 7: B1319.

B1320

Bit 8: B1320.

B1321

Bit 9: B1321.

B1322

Bit 10: B1322.

B1323

Bit 11: B1323.

B1324

Bit 12: B1324.

B1325

Bit 13: B1325.

B1326

Bit 14: B1326.

B1327

Bit 15: B1327.

B1328

Bit 16: B1328.

B1329

Bit 17: B1329.

B1330

Bit 18: B1330.

B1331

Bit 19: B1331.

B1332

Bit 20: B1332.

B1333

Bit 21: B1333.

B1334

Bit 22: B1334.

B1335

Bit 23: B1335.

B1336

Bit 24: B1336.

B1337

Bit 25: B1337.

B1338

Bit 26: B1338.

B1339

Bit 27: B1339.

B1340

Bit 28: B1340.

B1341

Bit 29: B1341.

B1342

Bit 30: B1342.

B1343

Bit 31: B1343.

MPCBB1_VCTR42

MPCBBx vector register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1375
rw 		B1374
rw 		B1373
rw 		B1372
rw 		B1371
rw 		B1370
rw 		B1369
rw 		B1368
rw 		B1367
rw 		B1366
rw 		B1365
rw 		B1364
rw 		B1363
rw 		B1362
rw 		B1361
rw 		B1360
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1359
rw 		B1358
rw 		B1357
rw 		B1356
rw 		B1355
rw 		B1354
rw 		B1353
rw 		B1352
rw 		B1351
rw 		B1350
rw 		B1349
rw 		B1348
rw 		B1347
rw 		B1346
rw 		B1345
rw 		B1344
rw
Toggle fields

B1344

Bit 0: B1344.

B1345

Bit 1: B1345.

B1346

Bit 2: B1346.

B1347

Bit 3: B1347.

B1348

Bit 4: B1348.

B1349

Bit 5: B1349.

B1350

Bit 6: B1350.

B1351

Bit 7: B1351.

B1352

Bit 8: B1352.

B1353

Bit 9: B1353.

B1354

Bit 10: B1354.

B1355

Bit 11: B1355.

B1356

Bit 12: B1356.

B1357

Bit 13: B1357.

B1358

Bit 14: B1358.

B1359

Bit 15: B1359.

B1360

Bit 16: B1360.

B1361

Bit 17: B1361.

B1362

Bit 18: B1362.

B1363

Bit 19: B1363.

B1364

Bit 20: B1364.

B1365

Bit 21: B1365.

B1366

Bit 22: B1366.

B1367

Bit 23: B1367.

B1368

Bit 24: B1368.

B1369

Bit 25: B1369.

B1370

Bit 26: B1370.

B1371

Bit 27: B1371.

B1372

Bit 28: B1372.

B1373

Bit 29: B1373.

B1374

Bit 30: B1374.

B1375

Bit 31: B1375.

MPCBB1_VCTR43

MPCBBx vector register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1407
rw 		B1406
rw 		B1405
rw 		B1404
rw 		B1403
rw 		B1402
rw 		B1401
rw 		B1400
rw 		B1399
rw 		B1398
rw 		B1397
rw 		B1396
rw 		B1395
rw 		B1394
rw 		B1393
rw 		B1392
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1391
rw 		B1390
rw 		B1389
rw 		B1388
rw 		B1387
rw 		B1386
rw 		B1385
rw 		B1384
rw 		B1383
rw 		B1382
rw 		B1381
rw 		B1380
rw 		B1379
rw 		B1378
rw 		B1377
rw 		B1376
rw
Toggle fields

B1376

Bit 0: B1376.

B1377

Bit 1: B1377.

B1378

Bit 2: B1378.

B1379

Bit 3: B1379.

B1380

Bit 4: B1380.

B1381

Bit 5: B1381.

B1382

Bit 6: B1382.

B1383

Bit 7: B1383.

B1384

Bit 8: B1384.

B1385

Bit 9: B1385.

B1386

Bit 10: B1386.

B1387

Bit 11: B1387.

B1388

Bit 12: B1388.

B1389

Bit 13: B1389.

B1390

Bit 14: B1390.

B1391

Bit 15: B1391.

B1392

Bit 16: B1392.

B1393

Bit 17: B1393.

B1394

Bit 18: B1394.

B1395

Bit 19: B1395.

B1396

Bit 20: B1396.

B1397

Bit 21: B1397.

B1398

Bit 22: B1398.

B1399

Bit 23: B1399.

B1400

Bit 24: B1400.

B1401

Bit 25: B1401.

B1402

Bit 26: B1402.

B1403

Bit 27: B1403.

B1404

Bit 28: B1404.

B1405

Bit 29: B1405.

B1406

Bit 30: B1406.

B1407

Bit 31: B1407.

MPCBB1_VCTR44

MPCBBx vector register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1439
rw 		B1438
rw 		B1437
rw 		B1436
rw 		B1435
rw 		B1434
rw 		B1433
rw 		B1432
rw 		B1431
rw 		B1430
rw 		B1429
rw 		B1428
rw 		B1427
rw 		B1426
rw 		B1425
rw 		B1424
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1423
rw 		B1422
rw 		B1421
rw 		B1420
rw 		B1419
rw 		B1418
rw 		B1417
rw 		B1416
rw 		B1415
rw 		B1414
rw 		B1413
rw 		B1412
rw 		B1411
rw 		B1410
rw 		B1409
rw 		B1408
rw
Toggle fields

B1408

Bit 0: B1408.

B1409

Bit 1: B1409.

B1410

Bit 2: B1410.

B1411

Bit 3: B1411.

B1412

Bit 4: B1412.

B1413

Bit 5: B1413.

B1414

Bit 6: B1414.

B1415

Bit 7: B1415.

B1416

Bit 8: B1416.

B1417

Bit 9: B1417.

B1418

Bit 10: B1418.

B1419

Bit 11: B1419.

B1420

Bit 12: B1420.

B1421

Bit 13: B1421.

B1422

Bit 14: B1422.

B1423

Bit 15: B1423.

B1424

Bit 16: B1424.

B1425

Bit 17: B1425.

B1426

Bit 18: B1426.

B1427

Bit 19: B1427.

B1428

Bit 20: B1428.

B1429

Bit 21: B1429.

B1430

Bit 22: B1430.

B1431

Bit 23: B1431.

B1432

Bit 24: B1432.

B1433

Bit 25: B1433.

B1434

Bit 26: B1434.

B1435

Bit 27: B1435.

B1436

Bit 28: B1436.

B1437

Bit 29: B1437.

B1438

Bit 30: B1438.

B1439

Bit 31: B1439.

MPCBB1_VCTR45

MPCBBx vector register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1471
rw 		B1470
rw 		B1469
rw 		B1468
rw 		B1467
rw 		B1466
rw 		B1465
rw 		B1464
rw 		B1463
rw 		B1462
rw 		B1461
rw 		B1460
rw 		B1459
rw 		B1458
rw 		B1457
rw 		B1456
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1455
rw 		B1454
rw 		B1453
rw 		B1452
rw 		B1451
rw 		B1450
rw 		B1449
rw 		B1448
rw 		B1447
rw 		B1446
rw 		B1445
rw 		B1444
rw 		B1443
rw 		B1442
rw 		B1441
rw 		B1440
rw
Toggle fields

B1440

Bit 0: B1440.

B1441

Bit 1: B1441.

B1442

Bit 2: B1442.

B1443

Bit 3: B1443.

B1444

Bit 4: B1444.

B1445

Bit 5: B1445.

B1446

Bit 6: B1446.

B1447

Bit 7: B1447.

B1448

Bit 8: B1448.

B1449

Bit 9: B1449.

B1450

Bit 10: B1450.

B1451

Bit 11: B1451.

B1452

Bit 12: B1452.

B1453

Bit 13: B1453.

B1454

Bit 14: B1454.

B1455

Bit 15: B1455.

B1456

Bit 16: B1456.

B1457

Bit 17: B1457.

B1458

Bit 18: B1458.

B1459

Bit 19: B1459.

B1460

Bit 20: B1460.

B1461

Bit 21: B1461.

B1462

Bit 22: B1462.

B1463

Bit 23: B1463.

B1464

Bit 24: B1464.

B1465

Bit 25: B1465.

B1466

Bit 26: B1466.

B1467

Bit 27: B1467.

B1468

Bit 28: B1468.

B1469

Bit 29: B1469.

B1470

Bit 30: B1470.

B1471

Bit 31: B1471.

MPCBB1_VCTR46

MPCBBx vector register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1503
rw 		B1502
rw 		B1501
rw 		B1500
rw 		B1499
rw 		B1498
rw 		B1497
rw 		B1496
rw 		B1495
rw 		B1494
rw 		B1493
rw 		B1492
rw 		B1491
rw 		B1490
rw 		B1489
rw 		B1488
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1487
rw 		B1486
rw 		B1485
rw 		B1484
rw 		B1483
rw 		B1482
rw 		B1481
rw 		B1480
rw 		B1479
rw 		B1478
rw 		B1477
rw 		B1476
rw 		B1475
rw 		B1474
rw 		B1473
rw 		B1472
rw
Toggle fields

B1472

Bit 0: B1472.

B1473

Bit 1: B1473.

B1474

Bit 2: B1474.

B1475

Bit 3: B1475.

B1476

Bit 4: B1476.

B1477

Bit 5: B1477.

B1478

Bit 6: B1478.

B1479

Bit 7: B1479.

B1480

Bit 8: B1480.

B1481

Bit 9: B1481.

B1482

Bit 10: B1482.

B1483

Bit 11: B1483.

B1484

Bit 12: B1484.

B1485

Bit 13: B1485.

B1486

Bit 14: B1486.

B1487

Bit 15: B1487.

B1488

Bit 16: B1488.

B1489

Bit 17: B1489.

B1490

Bit 18: B1490.

B1491

Bit 19: B1491.

B1492

Bit 20: B1492.

B1493

Bit 21: B1493.

B1494

Bit 22: B1494.

B1495

Bit 23: B1495.

B1496

Bit 24: B1496.

B1497

Bit 25: B1497.

B1498

Bit 26: B1498.

B1499

Bit 27: B1499.

B1500

Bit 28: B1500.

B1501

Bit 29: B1501.

B1502

Bit 30: B1502.

B1503

Bit 31: B1503.

MPCBB1_VCTR47

MPCBBx vector register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1535
rw 		B1534
rw 		B1533
rw 		B1532
rw 		B1531
rw 		B1530
rw 		B1529
rw 		B1528
rw 		B1527
rw 		B1526
rw 		B1525
rw 		B1524
rw 		B1523
rw 		B1522
rw 		B1521
rw 		B1520
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1519
rw 		B1518
rw 		B1517
rw 		B1516
rw 		B1515
rw 		B1514
rw 		B1513
rw 		B1512
rw 		B1511
rw 		B1510
rw 		B1509
rw 		B1508
rw 		B1507
rw 		B1506
rw 		B1505
rw 		B1504
rw
Toggle fields

B1504

Bit 0: B1504.

B1505

Bit 1: B1505.

B1506

Bit 2: B1506.

B1507

Bit 3: B1507.

B1508

Bit 4: B1508.

B1509

Bit 5: B1509.

B1510

Bit 6: B1510.

B1511

Bit 7: B1511.

B1512

Bit 8: B1512.

B1513

Bit 9: B1513.

B1514

Bit 10: B1514.

B1515

Bit 11: B1515.

B1516

Bit 12: B1516.

B1517

Bit 13: B1517.

B1518

Bit 14: B1518.

B1519

Bit 15: B1519.

B1520

Bit 16: B1520.

B1521

Bit 17: B1521.

B1522

Bit 18: B1522.

B1523

Bit 19: B1523.

B1524

Bit 20: B1524.

B1525

Bit 21: B1525.

B1526

Bit 22: B1526.

B1527

Bit 23: B1527.

B1528

Bit 24: B1528.

B1529

Bit 25: B1529.

B1530

Bit 26: B1530.

B1531

Bit 27: B1531.

B1532

Bit 28: B1532.

B1533

Bit 29: B1533.

B1534

Bit 30: B1534.

B1535

Bit 31: B1535.

MPCBB1_VCTR48

MPCBBx vector register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1567
rw 		B1566
rw 		B1565
rw 		B1564
rw 		B1563
rw 		B1562
rw 		B1561
rw 		B1560
rw 		B1559
rw 		B1558
rw 		B1557
rw 		B1556
rw 		B1555
rw 		B1554
rw 		B1553
rw 		B1552
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1551
rw 		B1550
rw 		B1549
rw 		B1548
rw 		B1547
rw 		B1546
rw 		B1545
rw 		B1544
rw 		B1543
rw 		B1542
rw 		B1541
rw 		B1540
rw 		B1539
rw 		B1538
rw 		B1537
rw 		B1536
rw
Toggle fields

B1536

Bit 0: B1536.

B1537

Bit 1: B1537.

B1538

Bit 2: B1538.

B1539

Bit 3: B1539.

B1540

Bit 4: B1540.

B1541

Bit 5: B1541.

B1542

Bit 6: B1542.

B1543

Bit 7: B1543.

B1544

Bit 8: B1544.

B1545

Bit 9: B1545.

B1546

Bit 10: B1546.

B1547

Bit 11: B1547.

B1548

Bit 12: B1548.

B1549

Bit 13: B1549.

B1550

Bit 14: B1550.

B1551

Bit 15: B1551.

B1552

Bit 16: B1552.

B1553

Bit 17: B1553.

B1554

Bit 18: B1554.

B1555

Bit 19: B1555.

B1556

Bit 20: B1556.

B1557

Bit 21: B1557.

B1558

Bit 22: B1558.

B1559

Bit 23: B1559.

B1560

Bit 24: B1560.

B1561

Bit 25: B1561.

B1562

Bit 26: B1562.

B1563

Bit 27: B1563.

B1564

Bit 28: B1564.

B1565

Bit 29: B1565.

B1566

Bit 30: B1566.

B1567

Bit 31: B1567.

MPCBB1_VCTR49

MPCBBx vector register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1599
rw 		B1598
rw 		B1597
rw 		B1596
rw 		B1595
rw 		B1594
rw 		B1593
rw 		B1592
rw 		B1591
rw 		B1590
rw 		B1589
rw 		B1588
rw 		B1587
rw 		B1586
rw 		B1585
rw 		B1584
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1583
rw 		B1582
rw 		B1581
rw 		B1580
rw 		B1579
rw 		B1578
rw 		B1577
rw 		B1576
rw 		B1575
rw 		B1574
rw 		B1573
rw 		B1572
rw 		B1571
rw 		B1570
rw 		B1569
rw 		B1568
rw
Toggle fields

B1568

Bit 0: B1568.

B1569

Bit 1: B1569.

B1570

Bit 2: B1570.

B1571

Bit 3: B1571.

B1572

Bit 4: B1572.

B1573

Bit 5: B1573.

B1574

Bit 6: B1574.

B1575

Bit 7: B1575.

B1576

Bit 8: B1576.

B1577

Bit 9: B1577.

B1578

Bit 10: B1578.

B1579

Bit 11: B1579.

B1580

Bit 12: B1580.

B1581

Bit 13: B1581.

B1582

Bit 14: B1582.

B1583

Bit 15: B1583.

B1584

Bit 16: B1584.

B1585

Bit 17: B1585.

B1586

Bit 18: B1586.

B1587

Bit 19: B1587.

B1588

Bit 20: B1588.

B1589

Bit 21: B1589.

B1590

Bit 22: B1590.

B1591

Bit 23: B1591.

B1592

Bit 24: B1592.

B1593

Bit 25: B1593.

B1594

Bit 26: B1594.

B1595

Bit 27: B1595.

B1596

Bit 28: B1596.

B1597

Bit 29: B1597.

B1598

Bit 30: B1598.

B1599

Bit 31: B1599.

MPCBB1_VCTR50

MPCBBx vector register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1631
rw 		B1630
rw 		B1629
rw 		B1628
rw 		B1627
rw 		B1626
rw 		B1625
rw 		B1624
rw 		B1623
rw 		B1622
rw 		B1621
rw 		B1620
rw 		B1619
rw 		B1618
rw 		B1617
rw 		B1616
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1615
rw 		B1614
rw 		B1613
rw 		B1612
rw 		B1611
rw 		B1610
rw 		B1609
rw 		B1608
rw 		B1607
rw 		B1606
rw 		B1605
rw 		B1604
rw 		B1603
rw 		B1602
rw 		B1601
rw 		B1600
rw
Toggle fields

B1600

Bit 0: B1600.

B1601

Bit 1: B1601.

B1602

Bit 2: B1602.

B1603

Bit 3: B1603.

B1604

Bit 4: B1604.

B1605

Bit 5: B1605.

B1606

Bit 6: B1606.

B1607

Bit 7: B1607.

B1608

Bit 8: B1608.

B1609

Bit 9: B1609.

B1610

Bit 10: B1610.

B1611

Bit 11: B1611.

B1612

Bit 12: B1612.

B1613

Bit 13: B1613.

B1614

Bit 14: B1614.

B1615

Bit 15: B1615.

B1616

Bit 16: B1616.

B1617

Bit 17: B1617.

B1618

Bit 18: B1618.

B1619

Bit 19: B1619.

B1620

Bit 20: B1620.

B1621

Bit 21: B1621.

B1622

Bit 22: B1622.

B1623

Bit 23: B1623.

B1624

Bit 24: B1624.

B1625

Bit 25: B1625.

B1626

Bit 26: B1626.

B1627

Bit 27: B1627.

B1628

Bit 28: B1628.

B1629

Bit 29: B1629.

B1630

Bit 30: B1630.

B1631

Bit 31: B1631.

MPCBB1_VCTR51

MPCBBx vector register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1663
rw 		B1662
rw 		B1661
rw 		B1660
rw 		B1659
rw 		B1658
rw 		B1657
rw 		B1656
rw 		B1655
rw 		B1654
rw 		B1653
rw 		B1652
rw 		B1651
rw 		B1650
rw 		B1649
rw 		B1648
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1647
rw 		B1646
rw 		B1645
rw 		B1644
rw 		B1643
rw 		B1642
rw 		B1641
rw 		B1640
rw 		B1639
rw 		B1638
rw 		B1637
rw 		B1636
rw 		B1635
rw 		B1634
rw 		B1633
rw 		B1632
rw
Toggle fields

B1632

Bit 0: B1632.

B1633

Bit 1: B1633.

B1634

Bit 2: B1634.

B1635

Bit 3: B1635.

B1636

Bit 4: B1636.

B1637

Bit 5: B1637.

B1638

Bit 6: B1638.

B1639

Bit 7: B1639.

B1640

Bit 8: B1640.

B1641

Bit 9: B1641.

B1642

Bit 10: B1642.

B1643

Bit 11: B1643.

B1644

Bit 12: B1644.

B1645

Bit 13: B1645.

B1646

Bit 14: B1646.

B1647

Bit 15: B1647.

B1648

Bit 16: B1648.

B1649

Bit 17: B1649.

B1650

Bit 18: B1650.

B1651

Bit 19: B1651.

B1652

Bit 20: B1652.

B1653

Bit 21: B1653.

B1654

Bit 22: B1654.

B1655

Bit 23: B1655.

B1656

Bit 24: B1656.

B1657

Bit 25: B1657.

B1658

Bit 26: B1658.

B1659

Bit 27: B1659.

B1660

Bit 28: B1660.

B1661

Bit 29: B1661.

B1662

Bit 30: B1662.

B1663

Bit 31: B1663.

MPCBB1_VCTR52

MPCBBx vector register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1695
rw 		B1694
rw 		B1693
rw 		B1692
rw 		B1691
rw 		B1690
rw 		B1689
rw 		B1688
rw 		B1687
rw 		B1686
rw 		B1685
rw 		B1684
rw 		B1683
rw 		B1682
rw 		B1681
rw 		B1680
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1679
rw 		B1678
rw 		B1677
rw 		B1676
rw 		B1675
rw 		B1674
rw 		B1673
rw 		B1672
rw 		B1671
rw 		B1670
rw 		B1669
rw 		B1668
rw 		B1667
rw 		B1666
rw 		B1665
rw 		B1664
rw
Toggle fields

B1664

Bit 0: B1664.

B1665

Bit 1: B1665.

B1666

Bit 2: B1666.

B1667

Bit 3: B1667.

B1668

Bit 4: B1668.

B1669

Bit 5: B1669.

B1670

Bit 6: B1670.

B1671

Bit 7: B1671.

B1672

Bit 8: B1672.

B1673

Bit 9: B1673.

B1674

Bit 10: B1674.

B1675

Bit 11: B1675.

B1676

Bit 12: B1676.

B1677

Bit 13: B1677.

B1678

Bit 14: B1678.

B1679

Bit 15: B1679.

B1680

Bit 16: B1680.

B1681

Bit 17: B1681.

B1682

Bit 18: B1682.

B1683

Bit 19: B1683.

B1684

Bit 20: B1684.

B1685

Bit 21: B1685.

B1686

Bit 22: B1686.

B1687

Bit 23: B1687.

B1688

Bit 24: B1688.

B1689

Bit 25: B1689.

B1690

Bit 26: B1690.

B1691

Bit 27: B1691.

B1692

Bit 28: B1692.

B1693

Bit 29: B1693.

B1694

Bit 30: B1694.

B1695

Bit 31: B1695.

MPCBB1_VCTR53

MPCBBx vector register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1727
rw 		B1726
rw 		B1725
rw 		B1724
rw 		B1723
rw 		B1722
rw 		B1721
rw 		B1720
rw 		B1719
rw 		B1718
rw 		B1717
rw 		B1716
rw 		B1715
rw 		B1714
rw 		B1713
rw 		B1712
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1711
rw 		B1710
rw 		B1709
rw 		B1708
rw 		B1707
rw 		B1706
rw 		B1705
rw 		B1704
rw 		B1703
rw 		B1702
rw 		B1701
rw 		B1700
rw 		B1699
rw 		B1698
rw 		B1697
rw 		B1696
rw
Toggle fields

B1696

Bit 0: B1696.

B1697

Bit 1: B1697.

B1698

Bit 2: B1698.

B1699

Bit 3: B1699.

B1700

Bit 4: B1700.

B1701

Bit 5: B1701.

B1702

Bit 6: B1702.

B1703

Bit 7: B1703.

B1704

Bit 8: B1704.

B1705

Bit 9: B1705.

B1706

Bit 10: B1706.

B1707

Bit 11: B1707.

B1708

Bit 12: B1708.

B1709

Bit 13: B1709.

B1710

Bit 14: B1710.

B1711

Bit 15: B1711.

B1712

Bit 16: B1712.

B1713

Bit 17: B1713.

B1714

Bit 18: B1714.

B1715

Bit 19: B1715.

B1716

Bit 20: B1716.

B1717

Bit 21: B1717.

B1718

Bit 22: B1718.

B1719

Bit 23: B1719.

B1720

Bit 24: B1720.

B1721

Bit 25: B1721.

B1722

Bit 26: B1722.

B1723

Bit 27: B1723.

B1724

Bit 28: B1724.

B1725

Bit 29: B1725.

B1726

Bit 30: B1726.

B1727

Bit 31: B1727.

MPCBB1_VCTR54

MPCBBx vector register

Offset: 0x1d8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1759
rw 		B1758
rw 		B1757
rw 		B1756
rw 		B1755
rw 		B1754
rw 		B1753
rw 		B1752
rw 		B1751
rw 		B1750
rw 		B1749
rw 		B1748
rw 		B1747
rw 		B1746
rw 		B1745
rw 		B1744
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1743
rw 		B1742
rw 		B1741
rw 		B1740
rw 		B1739
rw 		B1738
rw 		B1737
rw 		B1736
rw 		B1735
rw 		B1734
rw 		B1733
rw 		B1732
rw 		B1731
rw 		B1730
rw 		B1729
rw 		B1728
rw
Toggle fields

B1728

Bit 0: B1728.

B1729

Bit 1: B1729.

B1730

Bit 2: B1730.

B1731

Bit 3: B1731.

B1732

Bit 4: B1732.

B1733

Bit 5: B1733.

B1734

Bit 6: B1734.

B1735

Bit 7: B1735.

B1736

Bit 8: B1736.

B1737

Bit 9: B1737.

B1738

Bit 10: B1738.

B1739

Bit 11: B1739.

B1740

Bit 12: B1740.

B1741

Bit 13: B1741.

B1742

Bit 14: B1742.

B1743

Bit 15: B1743.

B1744

Bit 16: B1744.

B1745

Bit 17: B1745.

B1746

Bit 18: B1746.

B1747

Bit 19: B1747.

B1748

Bit 20: B1748.

B1749

Bit 21: B1749.

B1750

Bit 22: B1750.

B1751

Bit 23: B1751.

B1752

Bit 24: B1752.

B1753

Bit 25: B1753.

B1754

Bit 26: B1754.

B1755

Bit 27: B1755.

B1756

Bit 28: B1756.

B1757

Bit 29: B1757.

B1758

Bit 30: B1758.

B1759

Bit 31: B1759.

MPCBB1_VCTR55

MPCBBx vector register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1791
rw 		B1790
rw 		B1789
rw 		B1788
rw 		B1787
rw 		B1786
rw 		B1785
rw 		B1784
rw 		B1783
rw 		B1782
rw 		B1781
rw 		B1780
rw 		B1779
rw 		B1778
rw 		B1777
rw 		B1776
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1775
rw 		B1774
rw 		B1773
rw 		B1772
rw 		B1771
rw 		B1770
rw 		B1769
rw 		B1768
rw 		B1767
rw 		B1766
rw 		B1765
rw 		B1764
rw 		B1763
rw 		B1762
rw 		B1761
rw 		B1760
rw
Toggle fields

B1760

Bit 0: B1760.

B1761

Bit 1: B1761.

B1762

Bit 2: B1762.

B1763

Bit 3: B1763.

B1764

Bit 4: B1764.

B1765

Bit 5: B1765.

B1766

Bit 6: B1766.

B1767

Bit 7: B1767.

B1768

Bit 8: B1768.

B1769

Bit 9: B1769.

B1770

Bit 10: B1770.

B1771

Bit 11: B1771.

B1772

Bit 12: B1772.

B1773

Bit 13: B1773.

B1774

Bit 14: B1774.

B1775

Bit 15: B1775.

B1776

Bit 16: B1776.

B1777

Bit 17: B1777.

B1778

Bit 18: B1778.

B1779

Bit 19: B1779.

B1780

Bit 20: B1780.

B1781

Bit 21: B1781.

B1782

Bit 22: B1782.

B1783

Bit 23: B1783.

B1784

Bit 24: B1784.

B1785

Bit 25: B1785.

B1786

Bit 26: B1786.

B1787

Bit 27: B1787.

B1788

Bit 28: B1788.

B1789

Bit 29: B1789.

B1790

Bit 30: B1790.

B1791

Bit 31: B1791.

MPCBB1_VCTR56

MPCBBx vector register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1823
rw 		B1822
rw 		B1821
rw 		B1820
rw 		B1819
rw 		B1818
rw 		B1817
rw 		B1816
rw 		B1815
rw 		B1814
rw 		B1813
rw 		B1812
rw 		B1811
rw 		B1810
rw 		B1809
rw 		B1808
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1807
rw 		B1806
rw 		B1805
rw 		B1804
rw 		B1803
rw 		B1802
rw 		B1801
rw 		B1800
rw 		B1799
rw 		B1798
rw 		B1797
rw 		B1796
rw 		B1795
rw 		B1794
rw 		B1793
rw 		B1792
rw
Toggle fields

B1792

Bit 0: B1792.

B1793

Bit 1: B1793.

B1794

Bit 2: B1794.

B1795

Bit 3: B1795.

B1796

Bit 4: B1796.

B1797

Bit 5: B1797.

B1798

Bit 6: B1798.

B1799

Bit 7: B1799.

B1800

Bit 8: B1800.

B1801

Bit 9: B1801.

B1802

Bit 10: B1802.

B1803

Bit 11: B1803.

B1804

Bit 12: B1804.

B1805

Bit 13: B1805.

B1806

Bit 14: B1806.

B1807

Bit 15: B1807.

B1808

Bit 16: B1808.

B1809

Bit 17: B1809.

B1810

Bit 18: B1810.

B1811

Bit 19: B1811.

B1812

Bit 20: B1812.

B1813

Bit 21: B1813.

B1814

Bit 22: B1814.

B1815

Bit 23: B1815.

B1816

Bit 24: B1816.

B1817

Bit 25: B1817.

B1818

Bit 26: B1818.

B1819

Bit 27: B1819.

B1820

Bit 28: B1820.

B1821

Bit 29: B1821.

B1822

Bit 30: B1822.

B1823

Bit 31: B1823.

MPCBB1_VCTR57

MPCBBx vector register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1855
rw 		B1854
rw 		B1853
rw 		B1852
rw 		B1851
rw 		B1850
rw 		B1849
rw 		B1848
rw 		B1847
rw 		B1846
rw 		B1845
rw 		B1844
rw 		B1843
rw 		B1842
rw 		B1841
rw 		B1840
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1839
rw 		B1838
rw 		B1837
rw 		B1836
rw 		B1835
rw 		B1834
rw 		B1833
rw 		B1832
rw 		B1831
rw 		B1830
rw 		B1829
rw 		B1828
rw 		B1827
rw 		B1826
rw 		B1825
rw 		B1824
rw
Toggle fields

B1824

Bit 0: B1824.

B1825

Bit 1: B1825.

B1826

Bit 2: B1826.

B1827

Bit 3: B1827.

B1828

Bit 4: B1828.

B1829

Bit 5: B1829.

B1830

Bit 6: B1830.

B1831

Bit 7: B1831.

B1832

Bit 8: B1832.

B1833

Bit 9: B1833.

B1834

Bit 10: B1834.

B1835

Bit 11: B1835.

B1836

Bit 12: B1836.

B1837

Bit 13: B1837.

B1838

Bit 14: B1838.

B1839

Bit 15: B1839.

B1840

Bit 16: B1840.

B1841

Bit 17: B1841.

B1842

Bit 18: B1842.

B1843

Bit 19: B1843.

B1844

Bit 20: B1844.

B1845

Bit 21: B1845.

B1846

Bit 22: B1846.

B1847

Bit 23: B1847.

B1848

Bit 24: B1848.

B1849

Bit 25: B1849.

B1850

Bit 26: B1850.

B1851

Bit 27: B1851.

B1852

Bit 28: B1852.

B1853

Bit 29: B1853.

B1854

Bit 30: B1854.

B1855

Bit 31: B1855.

MPCBB1_VCTR58

MPCBBx vector register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1887
rw 		B1886
rw 		B1885
rw 		B1884
rw 		B1883
rw 		B1882
rw 		B1881
rw 		B1880
rw 		B1879
rw 		B1878
rw 		B1877
rw 		B1876
rw 		B1875
rw 		B1874
rw 		B1873
rw 		B1872
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1871
rw 		B1870
rw 		B1869
rw 		B1868
rw 		B1867
rw 		B1866
rw 		B1865
rw 		B1864
rw 		B1863
rw 		B1862
rw 		B1861
rw 		B1860
rw 		B1859
rw 		B1858
rw 		B1857
rw 		B1856
rw
Toggle fields

B1856

Bit 0: B1856.

B1857

Bit 1: B1857.

B1858

Bit 2: B1858.

B1859

Bit 3: B1859.

B1860

Bit 4: B1860.

B1861

Bit 5: B1861.

B1862

Bit 6: B1862.

B1863

Bit 7: B1863.

B1864

Bit 8: B1864.

B1865

Bit 9: B1865.

B1866

Bit 10: B1866.

B1867

Bit 11: B1867.

B1868

Bit 12: B1868.

B1869

Bit 13: B1869.

B1870

Bit 14: B1870.

B1871

Bit 15: B1871.

B1872

Bit 16: B1872.

B1873

Bit 17: B1873.

B1874

Bit 18: B1874.

B1875

Bit 19: B1875.

B1876

Bit 20: B1876.

B1877

Bit 21: B1877.

B1878

Bit 22: B1878.

B1879

Bit 23: B1879.

B1880

Bit 24: B1880.

B1881

Bit 25: B1881.

B1882

Bit 26: B1882.

B1883

Bit 27: B1883.

B1884

Bit 28: B1884.

B1885

Bit 29: B1885.

B1886

Bit 30: B1886.

B1887

Bit 31: B1887.

MPCBB1_VCTR59

MPCBBx vector register

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1919
rw 		B1918
rw 		B1917
rw 		B1916
rw 		B1915
rw 		B1914
rw 		B1913
rw 		B1912
rw 		B1911
rw 		B1910
rw 		B1909
rw 		B1908
rw 		B1907
rw 		B1906
rw 		B1905
rw 		B1904
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1903
rw 		B1902
rw 		B1901
rw 		B1900
rw 		B1899
rw 		B1898
rw 		B1897
rw 		B1896
rw 		B1895
rw 		B1894
rw 		B1893
rw 		B1892
rw 		B1891
rw 		B1890
rw 		B1889
rw 		B1888
rw
Toggle fields

B1888

Bit 0: B1888.

B1889

Bit 1: B1889.

B1890

Bit 2: B1890.

B1891

Bit 3: B1891.

B1892

Bit 4: B1892.

B1893

Bit 5: B1893.

B1894

Bit 6: B1894.

B1895

Bit 7: B1895.

B1896

Bit 8: B1896.

B1897

Bit 9: B1897.

B1898

Bit 10: B1898.

B1899

Bit 11: B1899.

B1900

Bit 12: B1900.

B1901

Bit 13: B1901.

B1902

Bit 14: B1902.

B1903

Bit 15: B1903.

B1904

Bit 16: B1904.

B1905

Bit 17: B1905.

B1906

Bit 18: B1906.

B1907

Bit 19: B1907.

B1908

Bit 20: B1908.

B1909

Bit 21: B1909.

B1910

Bit 22: B1910.

B1911

Bit 23: B1911.

B1912

Bit 24: B1912.

B1913

Bit 25: B1913.

B1914

Bit 26: B1914.

B1915

Bit 27: B1915.

B1916

Bit 28: B1916.

B1917

Bit 29: B1917.

B1918

Bit 30: B1918.

B1919

Bit 31: B1919.

MPCBB1_VCTR60

MPCBBx vector register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1951
rw 		B1950
rw 		B1949
rw 		B1948
rw 		B1947
rw 		B1946
rw 		B1945
rw 		B1944
rw 		B1943
rw 		B1942
rw 		B1941
rw 		B1940
rw 		B1939
rw 		B1938
rw 		B1937
rw 		B1936
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1935
rw 		B1934
rw 		B1933
rw 		B1932
rw 		B1931
rw 		B1930
rw 		B1929
rw 		B1928
rw 		B1927
rw 		B1926
rw 		B1925
rw 		B1924
rw 		B1923
rw 		B1922
rw 		B1921
rw 		B1920
rw
Toggle fields

B1920

Bit 0: B1920.

B1921

Bit 1: B1921.

B1922

Bit 2: B1922.

B1923

Bit 3: B1923.

B1924

Bit 4: B1924.

B1925

Bit 5: B1925.

B1926

Bit 6: B1926.

B1927

Bit 7: B1927.

B1928

Bit 8: B1928.

B1929

Bit 9: B1929.

B1930

Bit 10: B1930.

B1931

Bit 11: B1931.

B1932

Bit 12: B1932.

B1933

Bit 13: B1933.

B1934

Bit 14: B1934.

B1935

Bit 15: B1935.

B1936

Bit 16: B1936.

B1937

Bit 17: B1937.

B1938

Bit 18: B1938.

B1939

Bit 19: B1939.

B1940

Bit 20: B1940.

B1941

Bit 21: B1941.

B1942

Bit 22: B1942.

B1943

Bit 23: B1943.

B1944

Bit 24: B1944.

B1945

Bit 25: B1945.

B1946

Bit 26: B1946.

B1947

Bit 27: B1947.

B1948

Bit 28: B1948.

B1949

Bit 29: B1949.

B1950

Bit 30: B1950.

B1951

Bit 31: B1951.

MPCBB1_VCTR61

MPCBBx vector register

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1983
rw 		B1982
rw 		B1981
rw 		B1980
rw 		B1979
rw 		B1978
rw 		B1977
rw 		B1976
rw 		B1975
rw 		B1974
rw 		B1973
rw 		B1972
rw 		B1971
rw 		B1970
rw 		B1969
rw 		B1968
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1967
rw 		B1966
rw 		B1965
rw 		B1964
rw 		B1963
rw 		B1962
rw 		B1961
rw 		B1960
rw 		B1959
rw 		B1958
rw 		B1957
rw 		B1956
rw 		B1955
rw 		B1954
rw 		B1953
rw 		B1952
rw
Toggle fields

B1952

Bit 0: B1952.

B1953

Bit 1: B1953.

B1954

Bit 2: B1954.

B1955

Bit 3: B1955.

B1956

Bit 4: B1956.

B1957

Bit 5: B1957.

B1958

Bit 6: B1958.

B1959

Bit 7: B1959.

B1960

Bit 8: B1960.

B1961

Bit 9: B1961.

B1962

Bit 10: B1962.

B1963

Bit 11: B1963.

B1964

Bit 12: B1964.

B1965

Bit 13: B1965.

B1966

Bit 14: B1966.

B1967

Bit 15: B1967.

B1968

Bit 16: B1968.

B1969

Bit 17: B1969.

B1970

Bit 18: B1970.

B1971

Bit 19: B1971.

B1972

Bit 20: B1972.

B1973

Bit 21: B1973.

B1974

Bit 22: B1974.

B1975

Bit 23: B1975.

B1976

Bit 24: B1976.

B1977

Bit 25: B1977.

B1978

Bit 26: B1978.

B1979

Bit 27: B1979.

B1980

Bit 28: B1980.

B1981

Bit 29: B1981.

B1982

Bit 30: B1982.

B1983

Bit 31: B1983.

MPCBB1_VCTR62

MPCBBx vector register

Offset: 0x1f8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B2015
rw 		B2014
rw 		B2013
rw 		B2012
rw 		B2011
rw 		B2010
rw 		B2009
rw 		B2008
rw 		B2007
rw 		B2006
rw 		B2005
rw 		B2004
rw 		B2003
rw 		B2002
rw 		B2001
rw 		B2000
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1999
rw 		B1998
rw 		B1997
rw 		B1996
rw 		B1995
rw 		B1994
rw 		B1993
rw 		B1992
rw 		B1991
rw 		B1990
rw 		B1989
rw 		B1988
rw 		B1987
rw 		B1986
rw 		B1985
rw 		B1984
rw
Toggle fields

B1984

Bit 0: B1984.

B1985

Bit 1: B1985.

B1986

Bit 2: B1986.

B1987

Bit 3: B1987.

B1988

Bit 4: B1988.

B1989

Bit 5: B1989.

B1990

Bit 6: B1990.

B1991

Bit 7: B1991.

B1992

Bit 8: B1992.

B1993

Bit 9: B1993.

B1994

Bit 10: B1994.

B1995

Bit 11: B1995.

B1996

Bit 12: B1996.

B1997

Bit 13: B1997.

B1998

Bit 14: B1998.

B1999

Bit 15: B1999.

B2000

Bit 16: B2000.

B2001

Bit 17: B2001.

B2002

Bit 18: B2002.

B2003

Bit 19: B2003.

B2004

Bit 20: B2004.

B2005

Bit 21: B2005.

B2006

Bit 22: B2006.

B2007

Bit 23: B2007.

B2008

Bit 24: B2008.

B2009

Bit 25: B2009.

B2010

Bit 26: B2010.

B2011

Bit 27: B2011.

B2012

Bit 28: B2012.

B2013

Bit 29: B2013.

B2014

Bit 30: B2014.

B2015

Bit 31: B2015.

MPCBB1_VCTR63

MPCBBx vector register

Offset: 0x1fc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B2047
rw 		B2046
rw 		B2045
rw 		B2044
rw 		B2043
rw 		B2042
rw 		B2041
rw 		B2040
rw 		B2039
rw 		B2038
rw 		B2037
rw 		B2036
rw 		B2035
rw 		B2034
rw 		B2033
rw 		B2032
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2031
rw 		B2030
rw 		B2029
rw 		B2028
rw 		B2027
rw 		B2026
rw 		B2025
rw 		B2024
rw 		B2023
rw 		B2022
rw 		B2021
rw 		B2020
rw 		B2019
rw 		B2018
rw 		B2017
rw 		B2016
rw
Toggle fields

B2016

Bit 0: B2016.

B2017

Bit 1: B2017.

B2018

Bit 2: B2018.

B2019

Bit 3: B2019.

B2020

Bit 4: B2020.

B2021

Bit 5: B2021.

B2022

Bit 6: B2022.

B2023

Bit 7: B2023.

B2024

Bit 8: B2024.

B2025

Bit 9: B2025.

B2026

Bit 10: B2026.

B2027

Bit 11: B2027.

B2028

Bit 12: B2028.

B2029

Bit 13: B2029.

B2030

Bit 14: B2030.

B2031

Bit 15: B2031.

B2032

Bit 16: B2032.

B2033

Bit 17: B2033.

B2034

Bit 18: B2034.

B2035

Bit 19: B2035.

B2036

Bit 20: B2036.

B2037

Bit 21: B2037.

B2038

Bit 22: B2038.

B2039

Bit 23: B2039.

B2040

Bit 24: B2040.

B2041

Bit 25: B2041.

B2042

Bit 26: B2042.

B2043

Bit 27: B2043.

B2044

Bit 28: B2044.

B2045

Bit 29: B2045.

B2046

Bit 30: B2046.

B2047

Bit 31: B2047.

SEC_GTZC_MPCBB2

0x50033000: SEC_GTZC_MPCBB2

0/2115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MPCBB2_CR
0x10 MPCBB2_LCKVTR1
0x14 MPCBB2_LCKVTR2
0x100 MPCBB2_VCTR0
0x104 MPCBB2_VCTR1
0x108 MPCBB2_VCTR2
0x10c MPCBB2_VCTR3
0x110 MPCBB2_VCTR4
0x114 MPCBB2_VCTR5
0x118 MPCBB2_VCTR6
0x11c MPCBB2_VCTR7
0x120 MPCBB2_VCTR8
0x124 MPCBB2_VCTR9
0x128 MPCBB2_VCTR10
0x12c MPCBB2_VCTR11
0x130 MPCBB2_VCTR12
0x134 MPCBB2_VCTR13
0x138 MPCBB2_VCTR14
0x13c MPCBB2_VCTR15
0x140 MPCBB2_VCTR16
0x144 MPCBB2_VCTR17
0x148 MPCBB2_VCTR18
0x14c MPCBB2_VCTR19
0x150 MPCBB2_VCTR20
0x154 MPCBB2_VCTR21
0x158 MPCBB2_VCTR22
0x15c MPCBB2_VCTR23
0x160 MPCBB2_VCTR24
0x164 MPCBB2_VCTR25
0x168 MPCBB2_VCTR26
0x16c MPCBB2_VCTR27
0x170 MPCBB2_VCTR28
0x174 MPCBB2_VCTR29
0x178 MPCBB2_VCTR30
0x17c MPCBB2_VCTR31
0x180 MPCBB2_VCTR32
0x184 MPCBB2_VCTR33
0x188 MPCBB2_VCTR34
0x18c MPCBB2_VCTR35
0x190 MPCBB2_VCTR36
0x194 MPCBB2_VCTR37
0x198 MPCBB2_VCTR38
0x19c MPCBB2_VCTR39
0x1a0 MPCBB2_VCTR40
0x1a4 MPCBB2_VCTR41
0x1a8 MPCBB2_VCTR42
0x1ac MPCBB2_VCTR43
0x1b0 MPCBB2_VCTR44
0x1b4 MPCBB2_VCTR45
0x1b8 MPCBB2_VCTR46
0x1bc MPCBB2_VCTR47
0x1c0 MPCBB2_VCTR48
0x1c4 MPCBB2_VCTR49
0x1c8 MPCBB2_VCTR50
0x1cc MPCBB2_VCTR51
0x1d0 MPCBB2_VCTR52
0x1d4 MPCBB2_VCTR53
0x1d8 MPCBB2_VCTR54
0x1dc MPCBB2_VCTR55
0x1e0 MPCBB2_VCTR56
0x1e4 MPCBB2_VCTR57
0x1e8 MPCBB2_VCTR58
0x1ec MPCBB2_VCTR59
0x1f0 MPCBB2_VCTR60
0x1f4 MPCBB2_VCTR61
0x1f8 MPCBB2_VCTR62
0x1fc MPCBB2_VCTR63
Toggle registers

MPCBB2_CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRWILADIS
rw 		INVSECSTATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

INVSECSTATE

Bit 30: INVSECSTATE.

SRWILADIS

Bit 31: SRWILADIS.

MPCBB2_LCKVTR1

MPCBB control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKSB31
rw 		LCKSB30
rw 		LCKSB29
rw 		LCKSB28
rw 		LCKSB27
rw 		LCKSB26
rw 		LCKSB25
rw 		LCKSB24
rw 		LCKSB23
rw 		LCKSB22
rw 		LCKSB21
rw 		LCKSB20
rw 		LCKSB19
rw 		LCKSB18
rw 		LCKSB17
rw 		LCKSB16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB15
rw 		LCKSB14
rw 		LCKSB13
rw 		LCKSB12
rw 		LCKSB11
rw 		LCKSB10
rw 		LCKSB9
rw 		LCKSB8
rw 		LCKSB7
rw 		LCKSB6
rw 		LCKSB5
rw 		LCKSB4
rw 		LCKSB3
rw 		LCKSB2
rw 		LCKSB1
rw 		LCKSB0
rw
Toggle fields

LCKSB0

Bit 0: LCKSB0.

LCKSB1

Bit 1: LCKSB1.

LCKSB2

Bit 2: LCKSB2.

LCKSB3

Bit 3: LCKSB3.

LCKSB4

Bit 4: LCKSB4.

LCKSB5

Bit 5: LCKSB5.

LCKSB6

Bit 6: LCKSB6.

LCKSB7

Bit 7: LCKSB7.

LCKSB8

Bit 8: LCKSB8.

LCKSB9

Bit 9: LCKSB9.

LCKSB10

Bit 10: LCKSB10.

LCKSB11

Bit 11: LCKSB11.

LCKSB12

Bit 12: LCKSB12.

LCKSB13

Bit 13: LCKSB13.

LCKSB14

Bit 14: LCKSB14.

LCKSB15

Bit 15: LCKSB15.

LCKSB16

Bit 16: LCKSB16.

LCKSB17

Bit 17: LCKSB17.

LCKSB18

Bit 18: LCKSB18.

LCKSB19

Bit 19: LCKSB19.

LCKSB20

Bit 20: LCKSB20.

LCKSB21

Bit 21: LCKSB21.

LCKSB22

Bit 22: LCKSB22.

LCKSB23

Bit 23: LCKSB23.

LCKSB24

Bit 24: LCKSB24.

LCKSB25

Bit 25: LCKSB25.

LCKSB26

Bit 26: LCKSB26.

LCKSB27

Bit 27: LCKSB27.

LCKSB28

Bit 28: LCKSB28.

LCKSB29

Bit 29: LCKSB29.

LCKSB30

Bit 30: LCKSB30.

LCKSB31

Bit 31: LCKSB31.

MPCBB2_LCKVTR2

MPCBB control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKSB63
rw 		LCKSB62
rw 		LCKSB61
rw 		LCKSB60
rw 		LCKSB59
rw 		LCKSB58
rw 		LCKSB57
rw 		LCKSB56
rw 		LCKSB55
rw 		LCKSB54
rw 		LCKSB53
rw 		LCKSB52
rw 		LCKSB51
rw 		LCKSB50
rw 		LCKSB49
rw 		LCKSB48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB47
rw 		LCKSB46
rw 		LCKSB45
rw 		LCKSB44
rw 		LCKSB43
rw 		LCKSB42
rw 		LCKSB41
rw 		LCKSB40
rw 		LCKSB39
rw 		LCKSB38
rw 		LCKSB37
rw 		LCKSB36
rw 		LCKSB35
rw 		LCKSB34
rw 		LCKSB33
rw 		LCKSB32
rw
Toggle fields

LCKSB32

Bit 0: LCKSB32.

LCKSB33

Bit 1: LCKSB33.

LCKSB34

Bit 2: LCKSB34.

LCKSB35

Bit 3: LCKSB35.

LCKSB36

Bit 4: LCKSB36.

LCKSB37

Bit 5: LCKSB37.

LCKSB38

Bit 6: LCKSB38.

LCKSB39

Bit 7: LCKSB39.

LCKSB40

Bit 8: LCKSB40.

LCKSB41

Bit 9: LCKSB41.

LCKSB42

Bit 10: LCKSB42.

LCKSB43

Bit 11: LCKSB43.

LCKSB44

Bit 12: LCKSB44.

LCKSB45

Bit 13: LCKSB45.

LCKSB46

Bit 14: LCKSB46.

LCKSB47

Bit 15: LCKSB47.

LCKSB48

Bit 16: LCKSB48.

LCKSB49

Bit 17: LCKSB49.

LCKSB50

Bit 18: LCKSB50.

LCKSB51

Bit 19: LCKSB51.

LCKSB52

Bit 20: LCKSB52.

LCKSB53

Bit 21: LCKSB53.

LCKSB54

Bit 22: LCKSB54.

LCKSB55

Bit 23: LCKSB55.

LCKSB56

Bit 24: LCKSB56.

LCKSB57

Bit 25: LCKSB57.

LCKSB58

Bit 26: LCKSB58.

LCKSB59

Bit 27: LCKSB59.

LCKSB60

Bit 28: LCKSB60.

LCKSB61

Bit 29: LCKSB61.

LCKSB62

Bit 30: LCKSB62.

LCKSB63

Bit 31: LCKSB63.

MPCBB2_VCTR0

MPCBBx vector register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw 		B30
rw 		B29
rw 		B28
rw 		B27
rw 		B26
rw 		B25
rw 		B24
rw 		B23
rw 		B22
rw 		B21
rw 		B20
rw 		B19
rw 		B18
rw 		B17
rw 		B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw 		B14
rw 		B13
rw 		B12
rw 		B11
rw 		B10
rw 		B9
rw 		B8
rw 		B7
rw 		B6
rw 		B5
rw 		B4
rw 		B3
rw 		B2
rw 		B1
rw 		B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

MPCBB2_VCTR1

MPCBBx vector register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B63
rw 		B62
rw 		B61
rw 		B60
rw 		B59
rw 		B58
rw 		B57
rw 		B56
rw 		B55
rw 		B54
rw 		B53
rw 		B52
rw 		B51
rw 		B50
rw 		B49
rw 		B48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B47
rw 		B46
rw 		B45
rw 		B44
rw 		B43
rw 		B42
rw 		B41
rw 		B40
rw 		B39
rw 		B38
rw 		B37
rw 		B36
rw 		B35
rw 		B34
rw 		B33
rw 		B32
rw
Toggle fields

B32

Bit 0: B32.

B33

Bit 1: B33.

B34

Bit 2: B34.

B35

Bit 3: B35.

B36

Bit 4: B36.

B37

Bit 5: B37.

B38

Bit 6: B38.

B39

Bit 7: B39.

B40

Bit 8: B40.

B41

Bit 9: B41.

B42

Bit 10: B42.

B43

Bit 11: B43.

B44

Bit 12: B44.

B45

Bit 13: B45.

B46

Bit 14: B46.

B47

Bit 15: B47.

B48

Bit 16: B48.

B49

Bit 17: B49.

B50

Bit 18: B50.

B51

Bit 19: B51.

B52

Bit 20: B52.

B53

Bit 21: B53.

B54

Bit 22: B54.

B55

Bit 23: B55.

B56

Bit 24: B56.

B57

Bit 25: B57.

B58

Bit 26: B58.

B59

Bit 27: B59.

B60

Bit 28: B60.

B61

Bit 29: B61.

B62

Bit 30: B62.

B63

Bit 31: B63.

MPCBB2_VCTR2

MPCBBx vector register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B95
rw 		B94
rw 		B93
rw 		B92
rw 		B91
rw 		B90
rw 		B89
rw 		B88
rw 		B87
rw 		B86
rw 		B85
rw 		B84
rw 		B83
rw 		B82
rw 		B81
rw 		B80
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B79
rw 		B78
rw 		B77
rw 		B76
rw 		B75
rw 		B74
rw 		B73
rw 		B72
rw 		B71
rw 		B70
rw 		B69
rw 		B68
rw 		B67
rw 		B66
rw 		B65
rw 		B64
rw
Toggle fields

B64

Bit 0: B64.

B65

Bit 1: B65.

B66

Bit 2: B66.

B67

Bit 3: B67.

B68

Bit 4: B68.

B69

Bit 5: B69.

B70

Bit 6: B70.

B71

Bit 7: B71.

B72

Bit 8: B72.

B73

Bit 9: B73.

B74

Bit 10: B74.

B75

Bit 11: B75.

B76

Bit 12: B76.

B77

Bit 13: B77.

B78

Bit 14: B78.

B79

Bit 15: B79.

B80

Bit 16: B80.

B81

Bit 17: B81.

B82

Bit 18: B82.

B83

Bit 19: B83.

B84

Bit 20: B84.

B85

Bit 21: B85.

B86

Bit 22: B86.

B87

Bit 23: B87.

B88

Bit 24: B88.

B89

Bit 25: B89.

B90

Bit 26: B90.

B91

Bit 27: B91.

B92

Bit 28: B92.

B93

Bit 29: B93.

B94

Bit 30: B94.

B95

Bit 31: B95.

MPCBB2_VCTR3

MPCBBx vector register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B127
rw 		B126
rw 		B125
rw 		B124
rw 		B123
rw 		B122
rw 		B121
rw 		B120
rw 		B119
rw 		B118
rw 		B117
rw 		B116
rw 		B115
rw 		B114
rw 		B113
rw 		B112
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B111
rw 		B110
rw 		B109
rw 		B108
rw 		B107
rw 		B106
rw 		B105
rw 		B104
rw 		B103
rw 		B102
rw 		B101
rw 		B100
rw 		B99
rw 		B98
rw 		B97
rw 		B96
rw
Toggle fields

B96

Bit 0: B96.

B97

Bit 1: B97.

B98

Bit 2: B98.

B99

Bit 3: B99.

B100

Bit 4: B100.

B101

Bit 5: B101.

B102

Bit 6: B102.

B103

Bit 7: B103.

B104

Bit 8: B104.

B105

Bit 9: B105.

B106

Bit 10: B106.

B107

Bit 11: B107.

B108

Bit 12: B108.

B109

Bit 13: B109.

B110

Bit 14: B110.

B111

Bit 15: B111.

B112

Bit 16: B112.

B113

Bit 17: B113.

B114

Bit 18: B114.

B115

Bit 19: B115.

B116

Bit 20: B116.

B117

Bit 21: B117.

B118

Bit 22: B118.

B119

Bit 23: B119.

B120

Bit 24: B120.

B121

Bit 25: B121.

B122

Bit 26: B122.

B123

Bit 27: B123.

B124

Bit 28: B124.

B125

Bit 29: B125.

B126

Bit 30: B126.

B127

Bit 31: B127.

MPCBB2_VCTR4

MPCBBx vector register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B159
rw 		B158
rw 		B157
rw 		B156
rw 		B155
rw 		B154
rw 		B153
rw 		B152
rw 		B151
rw 		B150
rw 		B149
rw 		B148
rw 		B147
rw 		B146
rw 		B145
rw 		B144
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B143
rw 		B142
rw 		B141
rw 		B140
rw 		B139
rw 		B138
rw 		B137
rw 		B136
rw 		B135
rw 		B134
rw 		B133
rw 		B132
rw 		B131
rw 		B130
rw 		B129
rw 		B128
rw
Toggle fields

B128

Bit 0: B128.

B129

Bit 1: B129.

B130

Bit 2: B130.

B131

Bit 3: B131.

B132

Bit 4: B132.

B133

Bit 5: B133.

B134

Bit 6: B134.

B135

Bit 7: B135.

B136

Bit 8: B136.

B137

Bit 9: B137.

B138

Bit 10: B138.

B139

Bit 11: B139.

B140

Bit 12: B140.

B141

Bit 13: B141.

B142

Bit 14: B142.

B143

Bit 15: B143.

B144

Bit 16: B144.

B145

Bit 17: B145.

B146

Bit 18: B146.

B147

Bit 19: B147.

B148

Bit 20: B148.

B149

Bit 21: B149.

B150

Bit 22: B150.

B151

Bit 23: B151.

B152

Bit 24: B152.

B153

Bit 25: B153.

B154

Bit 26: B154.

B155

Bit 27: B155.

B156

Bit 28: B156.

B157

Bit 29: B157.

B158

Bit 30: B158.

B159

Bit 31: B159.

MPCBB2_VCTR5

MPCBBx vector register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B191
rw 		B190
rw 		B189
rw 		B188
rw 		B187
rw 		B186
rw 		B185
rw 		B184
rw 		B183
rw 		B182
rw 		B181
rw 		B180
rw 		B179
rw 		B178
rw 		B177
rw 		B176
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B175
rw 		B174
rw 		B173
rw 		B172
rw 		B171
rw 		B170
rw 		B169
rw 		B168
rw 		B167
rw 		B166
rw 		B165
rw 		B164
rw 		B163
rw 		B162
rw 		B161
rw 		B160
rw
Toggle fields

B160

Bit 0: B160.

B161

Bit 1: B161.

B162

Bit 2: B162.

B163

Bit 3: B163.

B164

Bit 4: B164.

B165

Bit 5: B165.

B166

Bit 6: B166.

B167

Bit 7: B167.

B168

Bit 8: B168.

B169

Bit 9: B169.

B170

Bit 10: B170.

B171

Bit 11: B171.

B172

Bit 12: B172.

B173

Bit 13: B173.

B174

Bit 14: B174.

B175

Bit 15: B175.

B176

Bit 16: B176.

B177

Bit 17: B177.

B178

Bit 18: B178.

B179

Bit 19: B179.

B180

Bit 20: B180.

B181

Bit 21: B181.

B182

Bit 22: B182.

B183

Bit 23: B183.

B184

Bit 24: B184.

B185

Bit 25: B185.

B186

Bit 26: B186.

B187

Bit 27: B187.

B188

Bit 28: B188.

B189

Bit 29: B189.

B190

Bit 30: B190.

B191

Bit 31: B191.

MPCBB2_VCTR6

MPCBBx vector register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B223
rw 		B222
rw 		B221
rw 		B220
rw 		B219
rw 		B218
rw 		B217
rw 		B216
rw 		B215
rw 		B214
rw 		B213
rw 		B212
rw 		B211
rw 		B210
rw 		B209
rw 		B208
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B207
rw 		B206
rw 		B205
rw 		B204
rw 		B203
rw 		B202
rw 		B201
rw 		B200
rw 		B199
rw 		B198
rw 		B197
rw 		B196
rw 		B195
rw 		B194
rw 		B193
rw 		B192
rw
Toggle fields

B192

Bit 0: B192.

B193

Bit 1: B193.

B194

Bit 2: B194.

B195

Bit 3: B195.

B196

Bit 4: B196.

B197

Bit 5: B197.

B198

Bit 6: B198.

B199

Bit 7: B199.

B200

Bit 8: B200.

B201

Bit 9: B201.

B202

Bit 10: B202.

B203

Bit 11: B203.

B204

Bit 12: B204.

B205

Bit 13: B205.

B206

Bit 14: B206.

B207

Bit 15: B207.

B208

Bit 16: B208.

B209

Bit 17: B209.

B210

Bit 18: B210.

B211

Bit 19: B211.

B212

Bit 20: B212.

B213

Bit 21: B213.

B214

Bit 22: B214.

B215

Bit 23: B215.

B216

Bit 24: B216.

B217

Bit 25: B217.

B218

Bit 26: B218.

B219

Bit 27: B219.

B220

Bit 28: B220.

B221

Bit 29: B221.

B222

Bit 30: B222.

B223

Bit 31: B223.

MPCBB2_VCTR7

MPCBBx vector register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B255
rw 		B254
rw 		B253
rw 		B252
rw 		B251
rw 		B250
rw 		B249
rw 		B248
rw 		B247
rw 		B246
rw 		B245
rw 		B244
rw 		B243
rw 		B242
rw 		B241
rw 		B240
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B239
rw 		B238
rw 		B237
rw 		B236
rw 		B235
rw 		B234
rw 		B233
rw 		B232
rw 		B231
rw 		B230
rw 		B229
rw 		B228
rw 		B227
rw 		B226
rw 		B225
rw 		B224
rw
Toggle fields

B224

Bit 0: B224.

B225

Bit 1: B225.

B226

Bit 2: B226.

B227

Bit 3: B227.

B228

Bit 4: B228.

B229

Bit 5: B229.

B230

Bit 6: B230.

B231

Bit 7: B231.

B232

Bit 8: B232.

B233

Bit 9: B233.

B234

Bit 10: B234.

B235

Bit 11: B235.

B236

Bit 12: B236.

B237

Bit 13: B237.

B238

Bit 14: B238.

B239

Bit 15: B239.

B240

Bit 16: B240.

B241

Bit 17: B241.

B242

Bit 18: B242.

B243

Bit 19: B243.

B244

Bit 20: B244.

B245

Bit 21: B245.

B246

Bit 22: B246.

B247

Bit 23: B247.

B248

Bit 24: B248.

B249

Bit 25: B249.

B250

Bit 26: B250.

B251

Bit 27: B251.

B252

Bit 28: B252.

B253

Bit 29: B253.

B254

Bit 30: B254.

B255

Bit 31: B255.

MPCBB2_VCTR8

MPCBBx vector register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B287
rw 		B286
rw 		B285
rw 		B284
rw 		B283
rw 		B282
rw 		B281
rw 		B280
rw 		B279
rw 		B278
rw 		B277
rw 		B276
rw 		B275
rw 		B274
rw 		B273
rw 		B272
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B271
rw 		B270
rw 		B269
rw 		B268
rw 		B267
rw 		B266
rw 		B265
rw 		B264
rw 		B263
rw 		B262
rw 		B261
rw 		B260
rw 		B259
rw 		B258
rw 		B257
rw 		B256
rw
Toggle fields

B256

Bit 0: B256.

B257

Bit 1: B257.

B258

Bit 2: B258.

B259

Bit 3: B259.

B260

Bit 4: B260.

B261

Bit 5: B261.

B262

Bit 6: B262.

B263

Bit 7: B263.

B264

Bit 8: B264.

B265

Bit 9: B265.

B266

Bit 10: B266.

B267

Bit 11: B267.

B268

Bit 12: B268.

B269

Bit 13: B269.

B270

Bit 14: B270.

B271

Bit 15: B271.

B272

Bit 16: B272.

B273

Bit 17: B273.

B274

Bit 18: B274.

B275

Bit 19: B275.

B276

Bit 20: B276.

B277

Bit 21: B277.

B278

Bit 22: B278.

B279

Bit 23: B279.

B280

Bit 24: B280.

B281

Bit 25: B281.

B282

Bit 26: B282.

B283

Bit 27: B283.

B284

Bit 28: B284.

B285

Bit 29: B285.

B286

Bit 30: B286.

B287

Bit 31: B287.

MPCBB2_VCTR9

MPCBBx vector register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B319
rw 		B318
rw 		B317
rw 		B316
rw 		B315
rw 		B314
rw 		B313
rw 		B312
rw 		B311
rw 		B310
rw 		B309
rw 		B308
rw 		B307
rw 		B306
rw 		B305
rw 		B304
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B303
rw 		B302
rw 		B301
rw 		B300
rw 		B299
rw 		B298
rw 		B297
rw 		B296
rw 		B295
rw 		B294
rw 		B293
rw 		B292
rw 		B291
rw 		B290
rw 		B289
rw 		B288
rw
Toggle fields

B288

Bit 0: B288.

B289

Bit 1: B289.

B290

Bit 2: B290.

B291

Bit 3: B291.

B292

Bit 4: B292.

B293

Bit 5: B293.

B294

Bit 6: B294.

B295

Bit 7: B295.

B296

Bit 8: B296.

B297

Bit 9: B297.

B298

Bit 10: B298.

B299

Bit 11: B299.

B300

Bit 12: B300.

B301

Bit 13: B301.

B302

Bit 14: B302.

B303

Bit 15: B303.

B304

Bit 16: B304.

B305

Bit 17: B305.

B306

Bit 18: B306.

B307

Bit 19: B307.

B308

Bit 20: B308.

B309

Bit 21: B309.

B310

Bit 22: B310.

B311

Bit 23: B311.

B312

Bit 24: B312.

B313

Bit 25: B313.

B314

Bit 26: B314.

B315

Bit 27: B315.

B316

Bit 28: B316.

B317

Bit 29: B317.

B318

Bit 30: B318.

B319

Bit 31: B319.

MPCBB2_VCTR10

MPCBBx vector register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B351
rw 		B350
rw 		B349
rw 		B348
rw 		B347
rw 		B346
rw 		B345
rw 		B344
rw 		B343
rw 		B342
rw 		B341
rw 		B340
rw 		B339
rw 		B338
rw 		B337
rw 		B336
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B335
rw 		B334
rw 		B333
rw 		B332
rw 		B331
rw 		B330
rw 		B329
rw 		B328
rw 		B327
rw 		B326
rw 		B325
rw 		B324
rw 		B323
rw 		B322
rw 		B321
rw 		B320
rw
Toggle fields

B320

Bit 0: B320.

B321

Bit 1: B321.

B322

Bit 2: B322.

B323

Bit 3: B323.

B324

Bit 4: B324.

B325

Bit 5: B325.

B326

Bit 6: B326.

B327

Bit 7: B327.

B328

Bit 8: B328.

B329

Bit 9: B329.

B330

Bit 10: B330.

B331

Bit 11: B331.

B332

Bit 12: B332.

B333

Bit 13: B333.

B334

Bit 14: B334.

B335

Bit 15: B335.

B336

Bit 16: B336.

B337

Bit 17: B337.

B338

Bit 18: B338.

B339

Bit 19: B339.

B340

Bit 20: B340.

B341

Bit 21: B341.

B342

Bit 22: B342.

B343

Bit 23: B343.

B344

Bit 24: B344.

B345

Bit 25: B345.

B346

Bit 26: B346.

B347

Bit 27: B347.

B348

Bit 28: B348.

B349

Bit 29: B349.

B350

Bit 30: B350.

B351

Bit 31: B351.

MPCBB2_VCTR11

MPCBBx vector register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B383
rw 		B382
rw 		B381
rw 		B380
rw 		B379
rw 		B378
rw 		B377
rw 		B376
rw 		B375
rw 		B374
rw 		B373
rw 		B372
rw 		B371
rw 		B370
rw 		B369
rw 		B368
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B367
rw 		B366
rw 		B365
rw 		B364
rw 		B363
rw 		B362
rw 		B361
rw 		B360
rw 		B359
rw 		B358
rw 		B357
rw 		B356
rw 		B355
rw 		B354
rw 		B353
rw 		B352
rw
Toggle fields

B352

Bit 0: B352.

B353

Bit 1: B353.

B354

Bit 2: B354.

B355

Bit 3: B355.

B356

Bit 4: B356.

B357

Bit 5: B357.

B358

Bit 6: B358.

B359

Bit 7: B359.

B360

Bit 8: B360.

B361

Bit 9: B361.

B362

Bit 10: B362.

B363

Bit 11: B363.

B364

Bit 12: B364.

B365

Bit 13: B365.

B366

Bit 14: B366.

B367

Bit 15: B367.

B368

Bit 16: B368.

B369

Bit 17: B369.

B370

Bit 18: B370.

B371

Bit 19: B371.

B372

Bit 20: B372.

B373

Bit 21: B373.

B374

Bit 22: B374.

B375

Bit 23: B375.

B376

Bit 24: B376.

B377

Bit 25: B377.

B378

Bit 26: B378.

B379

Bit 27: B379.

B380

Bit 28: B380.

B381

Bit 29: B381.

B382

Bit 30: B382.

B383

Bit 31: B383.

MPCBB2_VCTR12

MPCBBx vector register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B415
rw 		B414
rw 		B413
rw 		B412
rw 		B411
rw 		B410
rw 		B409
rw 		B408
rw 		B407
rw 		B406
rw 		B405
rw 		B404
rw 		B403
rw 		B402
rw 		B401
rw 		B400
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B399
rw 		B398
rw 		B397
rw 		B396
rw 		B395
rw 		B394
rw 		B393
rw 		B392
rw 		B391
rw 		B390
rw 		B389
rw 		B388
rw 		B387
rw 		B386
rw 		B385
rw 		B384
rw
Toggle fields

B384

Bit 0: B384.

B385

Bit 1: B385.

B386

Bit 2: B386.

B387

Bit 3: B387.

B388

Bit 4: B388.

B389

Bit 5: B389.

B390

Bit 6: B390.

B391

Bit 7: B391.

B392

Bit 8: B392.

B393

Bit 9: B393.

B394

Bit 10: B394.

B395

Bit 11: B395.

B396

Bit 12: B396.

B397

Bit 13: B397.

B398

Bit 14: B398.

B399

Bit 15: B399.

B400

Bit 16: B400.

B401

Bit 17: B401.

B402

Bit 18: B402.

B403

Bit 19: B403.

B404

Bit 20: B404.

B405

Bit 21: B405.

B406

Bit 22: B406.

B407

Bit 23: B407.

B408

Bit 24: B408.

B409

Bit 25: B409.

B410

Bit 26: B410.

B411

Bit 27: B411.

B412

Bit 28: B412.

B413

Bit 29: B413.

B414

Bit 30: B414.

B415

Bit 31: B415.

MPCBB2_VCTR13

MPCBBx vector register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B447
rw 		B446
rw 		B445
rw 		B444
rw 		B443
rw 		B442
rw 		B441
rw 		B440
rw 		B439
rw 		B438
rw 		B437
rw 		B436
rw 		B435
rw 		B434
rw 		B433
rw 		B432
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B431
rw 		B430
rw 		B429
rw 		B428
rw 		B427
rw 		B426
rw 		B425
rw 		B424
rw 		B423
rw 		B422
rw 		B421
rw 		B420
rw 		B419
rw 		B418
rw 		B417
rw 		B416
rw
Toggle fields

B416

Bit 0: B416.

B417

Bit 1: B417.

B418

Bit 2: B418.

B419

Bit 3: B419.

B420

Bit 4: B420.

B421

Bit 5: B421.

B422

Bit 6: B422.

B423

Bit 7: B423.

B424

Bit 8: B424.

B425

Bit 9: B425.

B426

Bit 10: B426.

B427

Bit 11: B427.

B428

Bit 12: B428.

B429

Bit 13: B429.

B430

Bit 14: B430.

B431

Bit 15: B431.

B432

Bit 16: B432.

B433

Bit 17: B433.

B434

Bit 18: B434.

B435

Bit 19: B435.

B436

Bit 20: B436.

B437

Bit 21: B437.

B438

Bit 22: B438.

B439

Bit 23: B439.

B440

Bit 24: B440.

B441

Bit 25: B441.

B442

Bit 26: B442.

B443

Bit 27: B443.

B444

Bit 28: B444.

B445

Bit 29: B445.

B446

Bit 30: B446.

B447

Bit 31: B447.

MPCBB2_VCTR14

MPCBBx vector register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B479
rw 		B478
rw 		B477
rw 		B476
rw 		B475
rw 		B474
rw 		B473
rw 		B472
rw 		B471
rw 		B470
rw 		B469
rw 		B468
rw 		B467
rw 		B466
rw 		B465
rw 		B464
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B463
rw 		B462
rw 		B461
rw 		B460
rw 		B459
rw 		B458
rw 		B457
rw 		B456
rw 		B455
rw 		B454
rw 		B453
rw 		B452
rw 		B451
rw 		B450
rw 		B449
rw 		B448
rw
Toggle fields

B448

Bit 0: B448.

B449

Bit 1: B449.

B450

Bit 2: B450.

B451

Bit 3: B451.

B452

Bit 4: B452.

B453

Bit 5: B453.

B454

Bit 6: B454.

B455

Bit 7: B455.

B456

Bit 8: B456.

B457

Bit 9: B457.

B458

Bit 10: B458.

B459

Bit 11: B459.

B460

Bit 12: B460.

B461

Bit 13: B461.

B462

Bit 14: B462.

B463

Bit 15: B463.

B464

Bit 16: B464.

B465

Bit 17: B465.

B466

Bit 18: B466.

B467

Bit 19: B467.

B468

Bit 20: B468.

B469

Bit 21: B469.

B470

Bit 22: B470.

B471

Bit 23: B471.

B472

Bit 24: B472.

B473

Bit 25: B473.

B474

Bit 26: B474.

B475

Bit 27: B475.

B476

Bit 28: B476.

B477

Bit 29: B477.

B478

Bit 30: B478.

B479

Bit 31: B479.

MPCBB2_VCTR15

MPCBBx vector register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B511
rw 		B510
rw 		B509
rw 		B508
rw 		B507
rw 		B506
rw 		B505
rw 		B504
rw 		B503
rw 		B502
rw 		B501
rw 		B500
rw 		B499
rw 		B498
rw 		B497
rw 		B496
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B495
rw 		B494
rw 		B493
rw 		B492
rw 		B491
rw 		B490
rw 		B489
rw 		B488
rw 		B487
rw 		B486
rw 		B485
rw 		B484
rw 		B483
rw 		B482
rw 		B481
rw 		B480
rw
Toggle fields

B480

Bit 0: B480.

B481

Bit 1: B481.

B482

Bit 2: B482.

B483

Bit 3: B483.

B484

Bit 4: B484.

B485

Bit 5: B485.

B486

Bit 6: B486.

B487

Bit 7: B487.

B488

Bit 8: B488.

B489

Bit 9: B489.

B490

Bit 10: B490.

B491

Bit 11: B491.

B492

Bit 12: B492.

B493

Bit 13: B493.

B494

Bit 14: B494.

B495

Bit 15: B495.

B496

Bit 16: B496.

B497

Bit 17: B497.

B498

Bit 18: B498.

B499

Bit 19: B499.

B500

Bit 20: B500.

B501

Bit 21: B501.

B502

Bit 22: B502.

B503

Bit 23: B503.

B504

Bit 24: B504.

B505

Bit 25: B505.

B506

Bit 26: B506.

B507

Bit 27: B507.

B508

Bit 28: B508.

B509

Bit 29: B509.

B510

Bit 30: B510.

B511

Bit 31: B511.

MPCBB2_VCTR16

MPCBBx vector register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B543
rw 		B542
rw 		B541
rw 		B540
rw 		B539
rw 		B538
rw 		B537
rw 		B536
rw 		B535
rw 		B534
rw 		B533
rw 		B532
rw 		B531
rw 		B530
rw 		B529
rw 		B528
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B527
rw 		B526
rw 		B525
rw 		B524
rw 		B523
rw 		B522
rw 		B521
rw 		B520
rw 		B519
rw 		B518
rw 		B517
rw 		B516
rw 		B515
rw 		B514
rw 		B513
rw 		B512
rw
Toggle fields

B512

Bit 0: B512.

B513

Bit 1: B513.

B514

Bit 2: B514.

B515

Bit 3: B515.

B516

Bit 4: B516.

B517

Bit 5: B517.

B518

Bit 6: B518.

B519

Bit 7: B519.

B520

Bit 8: B520.

B521

Bit 9: B521.

B522

Bit 10: B522.

B523

Bit 11: B523.

B524

Bit 12: B524.

B525

Bit 13: B525.

B526

Bit 14: B526.

B527

Bit 15: B527.

B528

Bit 16: B528.

B529

Bit 17: B529.

B530

Bit 18: B530.

B531

Bit 19: B531.

B532

Bit 20: B532.

B533

Bit 21: B533.

B534

Bit 22: B534.

B535

Bit 23: B535.

B536

Bit 24: B536.

B537

Bit 25: B537.

B538

Bit 26: B538.

B539

Bit 27: B539.

B540

Bit 28: B540.

B541

Bit 29: B541.

B542

Bit 30: B542.

B543

Bit 31: B543.

MPCBB2_VCTR17

MPCBBx vector register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B575
rw 		B574
rw 		B573
rw 		B572
rw 		B571
rw 		B570
rw 		B569
rw 		B568
rw 		B567
rw 		B566
rw 		B565
rw 		B564
rw 		B563
rw 		B562
rw 		B561
rw 		B560
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B559
rw 		B558
rw 		B557
rw 		B556
rw 		B555
rw 		B554
rw 		B553
rw 		B552
rw 		B551
rw 		B550
rw 		B549
rw 		B548
rw 		B547
rw 		B546
rw 		B545
rw 		B544
rw
Toggle fields

B544

Bit 0: B544.

B545

Bit 1: B545.

B546

Bit 2: B546.

B547

Bit 3: B547.

B548

Bit 4: B548.

B549

Bit 5: B549.

B550

Bit 6: B550.

B551

Bit 7: B551.

B552

Bit 8: B552.

B553

Bit 9: B553.

B554

Bit 10: B554.

B555

Bit 11: B555.

B556

Bit 12: B556.

B557

Bit 13: B557.

B558

Bit 14: B558.

B559

Bit 15: B559.

B560

Bit 16: B560.

B561

Bit 17: B561.

B562

Bit 18: B562.

B563

Bit 19: B563.

B564

Bit 20: B564.

B565

Bit 21: B565.

B566

Bit 22: B566.

B567

Bit 23: B567.

B568

Bit 24: B568.

B569

Bit 25: B569.

B570

Bit 26: B570.

B571

Bit 27: B571.

B572

Bit 28: B572.

B573

Bit 29: B573.

B574

Bit 30: B574.

B575

Bit 31: B575.

MPCBB2_VCTR18

MPCBBx vector register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B607
rw 		B606
rw 		B605
rw 		B604
rw 		B603
rw 		B602
rw 		B601
rw 		B600
rw 		B599
rw 		B598
rw 		B597
rw 		B596
rw 		B595
rw 		B594
rw 		B593
rw 		B592
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B591
rw 		B590
rw 		B589
rw 		B588
rw 		B587
rw 		B586
rw 		B585
rw 		B584
rw 		B583
rw 		B582
rw 		B581
rw 		B580
rw 		B579
rw 		B578
rw 		B577
rw 		B576
rw
Toggle fields

B576

Bit 0: B576.

B577

Bit 1: B577.

B578

Bit 2: B578.

B579

Bit 3: B579.

B580

Bit 4: B580.

B581

Bit 5: B581.

B582

Bit 6: B582.

B583

Bit 7: B583.

B584

Bit 8: B584.

B585

Bit 9: B585.

B586

Bit 10: B586.

B587

Bit 11: B587.

B588

Bit 12: B588.

B589

Bit 13: B589.

B590

Bit 14: B590.

B591

Bit 15: B591.

B592

Bit 16: B592.

B593

Bit 17: B593.

B594

Bit 18: B594.

B595

Bit 19: B595.

B596

Bit 20: B596.

B597

Bit 21: B597.

B598

Bit 22: B598.

B599

Bit 23: B599.

B600

Bit 24: B600.

B601

Bit 25: B601.

B602

Bit 26: B602.

B603

Bit 27: B603.

B604

Bit 28: B604.

B605

Bit 29: B605.

B606

Bit 30: B606.

B607

Bit 31: B607.

MPCBB2_VCTR19

MPCBBx vector register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B639
rw 		B638
rw 		B637
rw 		B636
rw 		B635
rw 		B634
rw 		B633
rw 		B632
rw 		B631
rw 		B630
rw 		B629
rw 		B628
rw 		B627
rw 		B626
rw 		B625
rw 		B624
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B623
rw 		B622
rw 		B621
rw 		B620
rw 		B619
rw 		B618
rw 		B617
rw 		B616
rw 		B615
rw 		B614
rw 		B613
rw 		B612
rw 		B611
rw 		B610
rw 		B609
rw 		B608
rw
Toggle fields

B608

Bit 0: B608.

B609

Bit 1: B609.

B610

Bit 2: B610.

B611

Bit 3: B611.

B612

Bit 4: B612.

B613

Bit 5: B613.

B614

Bit 6: B614.

B615

Bit 7: B615.

B616

Bit 8: B616.

B617

Bit 9: B617.

B618

Bit 10: B618.

B619

Bit 11: B619.

B620

Bit 12: B620.

B621

Bit 13: B621.

B622

Bit 14: B622.

B623

Bit 15: B623.

B624

Bit 16: B624.

B625

Bit 17: B625.

B626

Bit 18: B626.

B627

Bit 19: B627.

B628

Bit 20: B628.

B629

Bit 21: B629.

B630

Bit 22: B630.

B631

Bit 23: B631.

B632

Bit 24: B632.

B633

Bit 25: B633.

B634

Bit 26: B634.

B635

Bit 27: B635.

B636

Bit 28: B636.

B637

Bit 29: B637.

B638

Bit 30: B638.

B639

Bit 31: B639.

MPCBB2_VCTR20

MPCBBx vector register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B671
rw 		B670
rw 		B669
rw 		B668
rw 		B667
rw 		B666
rw 		B665
rw 		B664
rw 		B663
rw 		B662
rw 		B661
rw 		B660
rw 		B659
rw 		B658
rw 		B657
rw 		B656
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B655
rw 		B654
rw 		B653
rw 		B652
rw 		B651
rw 		B650
rw 		B649
rw 		B648
rw 		B647
rw 		B646
rw 		B645
rw 		B644
rw 		B643
rw 		B642
rw 		B641
rw 		B640
rw
Toggle fields

B640

Bit 0: B640.

B641

Bit 1: B641.

B642

Bit 2: B642.

B643

Bit 3: B643.

B644

Bit 4: B644.

B645

Bit 5: B645.

B646

Bit 6: B646.

B647

Bit 7: B647.

B648

Bit 8: B648.

B649

Bit 9: B649.

B650

Bit 10: B650.

B651

Bit 11: B651.

B652

Bit 12: B652.

B653

Bit 13: B653.

B654

Bit 14: B654.

B655

Bit 15: B655.

B656

Bit 16: B656.

B657

Bit 17: B657.

B658

Bit 18: B658.

B659

Bit 19: B659.

B660

Bit 20: B660.

B661

Bit 21: B661.

B662

Bit 22: B662.

B663

Bit 23: B663.

B664

Bit 24: B664.

B665

Bit 25: B665.

B666

Bit 26: B666.

B667

Bit 27: B667.

B668

Bit 28: B668.

B669

Bit 29: B669.

B670

Bit 30: B670.

B671

Bit 31: B671.

MPCBB2_VCTR21

MPCBBx vector register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B703
rw 		B702
rw 		B701
rw 		B700
rw 		B699
rw 		B698
rw 		B697
rw 		B696
rw 		B695
rw 		B694
rw 		B693
rw 		B692
rw 		B691
rw 		B690
rw 		B689
rw 		B688
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B687
rw 		B686
rw 		B685
rw 		B684
rw 		B683
rw 		B682
rw 		B681
rw 		B680
rw 		B679
rw 		B678
rw 		B677
rw 		B676
rw 		B675
rw 		B674
rw 		B673
rw 		B672
rw
Toggle fields

B672

Bit 0: B672.

B673

Bit 1: B673.

B674

Bit 2: B674.

B675

Bit 3: B675.

B676

Bit 4: B676.

B677

Bit 5: B677.

B678

Bit 6: B678.

B679

Bit 7: B679.

B680

Bit 8: B680.

B681

Bit 9: B681.

B682

Bit 10: B682.

B683

Bit 11: B683.

B684

Bit 12: B684.

B685

Bit 13: B685.

B686

Bit 14: B686.

B687

Bit 15: B687.

B688

Bit 16: B688.

B689

Bit 17: B689.

B690

Bit 18: B690.

B691

Bit 19: B691.

B692

Bit 20: B692.

B693

Bit 21: B693.

B694

Bit 22: B694.

B695

Bit 23: B695.

B696

Bit 24: B696.

B697

Bit 25: B697.

B698

Bit 26: B698.

B699

Bit 27: B699.

B700

Bit 28: B700.

B701

Bit 29: B701.

B702

Bit 30: B702.

B703

Bit 31: B703.

MPCBB2_VCTR22

MPCBBx vector register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B735
rw 		B734
rw 		B733
rw 		B732
rw 		B731
rw 		B730
rw 		B729
rw 		B728
rw 		B727
rw 		B726
rw 		B725
rw 		B724
rw 		B723
rw 		B722
rw 		B721
rw 		B720
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B719
rw 		B718
rw 		B717
rw 		B716
rw 		B715
rw 		B714
rw 		B713
rw 		B712
rw 		B711
rw 		B710
rw 		B709
rw 		B708
rw 		B707
rw 		B706
rw 		B705
rw 		B704
rw
Toggle fields

B704

Bit 0: B704.

B705

Bit 1: B705.

B706

Bit 2: B706.

B707

Bit 3: B707.

B708

Bit 4: B708.

B709

Bit 5: B709.

B710

Bit 6: B710.

B711

Bit 7: B711.

B712

Bit 8: B712.

B713

Bit 9: B713.

B714

Bit 10: B714.

B715

Bit 11: B715.

B716

Bit 12: B716.

B717

Bit 13: B717.

B718

Bit 14: B718.

B719

Bit 15: B719.

B720

Bit 16: B720.

B721

Bit 17: B721.

B722

Bit 18: B722.

B723

Bit 19: B723.

B724

Bit 20: B724.

B725

Bit 21: B725.

B726

Bit 22: B726.

B727

Bit 23: B727.

B728

Bit 24: B728.

B729

Bit 25: B729.

B730

Bit 26: B730.

B731

Bit 27: B731.

B732

Bit 28: B732.

B733

Bit 29: B733.

B734

Bit 30: B734.

B735

Bit 31: B735.

MPCBB2_VCTR23

MPCBBx vector register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B767
rw 		B766
rw 		B765
rw 		B764
rw 		B763
rw 		B762
rw 		B761
rw 		B760
rw 		B759
rw 		B758
rw 		B757
rw 		B756
rw 		B755
rw 		B754
rw 		B753
rw 		B752
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B751
rw 		B750
rw 		B749
rw 		B748
rw 		B747
rw 		B746
rw 		B745
rw 		B744
rw 		B743
rw 		B742
rw 		B741
rw 		B740
rw 		B739
rw 		B738
rw 		B737
rw 		B736
rw
Toggle fields

B736

Bit 0: B736.

B737

Bit 1: B737.

B738

Bit 2: B738.

B739

Bit 3: B739.

B740

Bit 4: B740.

B741

Bit 5: B741.

B742

Bit 6: B742.

B743

Bit 7: B743.

B744

Bit 8: B744.

B745

Bit 9: B745.

B746

Bit 10: B746.

B747

Bit 11: B747.

B748

Bit 12: B748.

B749

Bit 13: B749.

B750

Bit 14: B750.

B751

Bit 15: B751.

B752

Bit 16: B752.

B753

Bit 17: B753.

B754

Bit 18: B754.

B755

Bit 19: B755.

B756

Bit 20: B756.

B757

Bit 21: B757.

B758

Bit 22: B758.

B759

Bit 23: B759.

B760

Bit 24: B760.

B761

Bit 25: B761.

B762

Bit 26: B762.

B763

Bit 27: B763.

B764

Bit 28: B764.

B765

Bit 29: B765.

B766

Bit 30: B766.

B767

Bit 31: B767.

MPCBB2_VCTR24

MPCBBx vector register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B799
rw 		B798
rw 		B797
rw 		B796
rw 		B795
rw 		B794
rw 		B793
rw 		B792
rw 		B791
rw 		B790
rw 		B789
rw 		B788
rw 		B787
rw 		B786
rw 		B785
rw 		B784
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B783
rw 		B782
rw 		B781
rw 		B780
rw 		B779
rw 		B778
rw 		B777
rw 		B776
rw 		B775
rw 		B774
rw 		B773
rw 		B772
rw 		B771
rw 		B770
rw 		B769
rw 		B768
rw
Toggle fields

B768

Bit 0: B768.

B769

Bit 1: B769.

B770

Bit 2: B770.

B771

Bit 3: B771.

B772

Bit 4: B772.

B773

Bit 5: B773.

B774

Bit 6: B774.

B775

Bit 7: B775.

B776

Bit 8: B776.

B777

Bit 9: B777.

B778

Bit 10: B778.

B779

Bit 11: B779.

B780

Bit 12: B780.

B781

Bit 13: B781.

B782

Bit 14: B782.

B783

Bit 15: B783.

B784

Bit 16: B784.

B785

Bit 17: B785.

B786

Bit 18: B786.

B787

Bit 19: B787.

B788

Bit 20: B788.

B789

Bit 21: B789.

B790

Bit 22: B790.

B791

Bit 23: B791.

B792

Bit 24: B792.

B793

Bit 25: B793.

B794

Bit 26: B794.

B795

Bit 27: B795.

B796

Bit 28: B796.

B797

Bit 29: B797.

B798

Bit 30: B798.

B799

Bit 31: B799.

MPCBB2_VCTR25

MPCBBx vector register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B831
rw 		B830
rw 		B829
rw 		B828
rw 		B827
rw 		B826
rw 		B825
rw 		B824
rw 		B823
rw 		B822
rw 		B821
rw 		B820
rw 		B819
rw 		B818
rw 		B817
rw 		B816
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B815
rw 		B814
rw 		B813
rw 		B812
rw 		B811
rw 		B810
rw 		B809
rw 		B808
rw 		B807
rw 		B806
rw 		B805
rw 		B804
rw 		B803
rw 		B802
rw 		B801
rw 		B800
rw
Toggle fields

B800

Bit 0: B800.

B801

Bit 1: B801.

B802

Bit 2: B802.

B803

Bit 3: B803.

B804

Bit 4: B804.

B805

Bit 5: B805.

B806

Bit 6: B806.

B807

Bit 7: B807.

B808

Bit 8: B808.

B809

Bit 9: B809.

B810

Bit 10: B810.

B811

Bit 11: B811.

B812

Bit 12: B812.

B813

Bit 13: B813.

B814

Bit 14: B814.

B815

Bit 15: B815.

B816

Bit 16: B816.

B817

Bit 17: B817.

B818

Bit 18: B818.

B819

Bit 19: B819.

B820

Bit 20: B820.

B821

Bit 21: B821.

B822

Bit 22: B822.

B823

Bit 23: B823.

B824

Bit 24: B824.

B825

Bit 25: B825.

B826

Bit 26: B826.

B827

Bit 27: B827.

B828

Bit 28: B828.

B829

Bit 29: B829.

B830

Bit 30: B830.

B831

Bit 31: B831.

MPCBB2_VCTR26

MPCBBx vector register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B863
rw 		B862
rw 		B861
rw 		B860
rw 		B859
rw 		B858
rw 		B857
rw 		B856
rw 		B855
rw 		B854
rw 		B853
rw 		B852
rw 		B851
rw 		B850
rw 		B849
rw 		B848
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B847
rw 		B846
rw 		B845
rw 		B844
rw 		B843
rw 		B842
rw 		B841
rw 		B840
rw 		B839
rw 		B838
rw 		B837
rw 		B836
rw 		B835
rw 		B834
rw 		B833
rw 		B832
rw
Toggle fields

B832

Bit 0: B832.

B833

Bit 1: B833.

B834

Bit 2: B834.

B835

Bit 3: B835.

B836

Bit 4: B836.

B837

Bit 5: B837.

B838

Bit 6: B838.

B839

Bit 7: B839.

B840

Bit 8: B840.

B841

Bit 9: B841.

B842

Bit 10: B842.

B843

Bit 11: B843.

B844

Bit 12: B844.

B845

Bit 13: B845.

B846

Bit 14: B846.

B847

Bit 15: B847.

B848

Bit 16: B848.

B849

Bit 17: B849.

B850

Bit 18: B850.

B851

Bit 19: B851.

B852

Bit 20: B852.

B853

Bit 21: B853.

B854

Bit 22: B854.

B855

Bit 23: B855.

B856

Bit 24: B856.

B857

Bit 25: B857.

B858

Bit 26: B858.

B859

Bit 27: B859.

B860

Bit 28: B860.

B861

Bit 29: B861.

B862

Bit 30: B862.

B863

Bit 31: B863.

MPCBB2_VCTR27

MPCBBx vector register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B895
rw 		B894
rw 		B893
rw 		B892
rw 		B891
rw 		B890
rw 		B889
rw 		B888
rw 		B887
rw 		B886
rw 		B885
rw 		B884
rw 		B883
rw 		B882
rw 		B881
rw 		B880
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B879
rw 		B878
rw 		B877
rw 		B876
rw 		B875
rw 		B874
rw 		B873
rw 		B872
rw 		B871
rw 		B870
rw 		B869
rw 		B868
rw 		B867
rw 		B866
rw 		B865
rw 		B864
rw
Toggle fields

B864

Bit 0: B864.

B865

Bit 1: B865.

B866

Bit 2: B866.

B867

Bit 3: B867.

B868

Bit 4: B868.

B869

Bit 5: B869.

B870

Bit 6: B870.

B871

Bit 7: B871.

B872

Bit 8: B872.

B873

Bit 9: B873.

B874

Bit 10: B874.

B875

Bit 11: B875.

B876

Bit 12: B876.

B877

Bit 13: B877.

B878

Bit 14: B878.

B879

Bit 15: B879.

B880

Bit 16: B880.

B881

Bit 17: B881.

B882

Bit 18: B882.

B883

Bit 19: B883.

B884

Bit 20: B884.

B885

Bit 21: B885.

B886

Bit 22: B886.

B887

Bit 23: B887.

B888

Bit 24: B888.

B889

Bit 25: B889.

B890

Bit 26: B890.

B891

Bit 27: B891.

B892

Bit 28: B892.

B893

Bit 29: B893.

B894

Bit 30: B894.

B895

Bit 31: B895.

MPCBB2_VCTR28

MPCBBx vector register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B927
rw 		B926
rw 		B925
rw 		B924
rw 		B923
rw 		B922
rw 		B921
rw 		B920
rw 		B919
rw 		B918
rw 		B917
rw 		B916
rw 		B915
rw 		B914
rw 		B913
rw 		B912
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B911
rw 		B910
rw 		B909
rw 		B908
rw 		B907
rw 		B906
rw 		B905
rw 		B904
rw 		B903
rw 		B902
rw 		B901
rw 		B900
rw 		B899
rw 		B898
rw 		B897
rw 		B896
rw
Toggle fields

B896

Bit 0: B896.

B897

Bit 1: B897.

B898

Bit 2: B898.

B899

Bit 3: B899.

B900

Bit 4: B900.

B901

Bit 5: B901.

B902

Bit 6: B902.

B903

Bit 7: B903.

B904

Bit 8: B904.

B905

Bit 9: B905.

B906

Bit 10: B906.

B907

Bit 11: B907.

B908

Bit 12: B908.

B909

Bit 13: B909.

B910

Bit 14: B910.

B911

Bit 15: B911.

B912

Bit 16: B912.

B913

Bit 17: B913.

B914

Bit 18: B914.

B915

Bit 19: B915.

B916

Bit 20: B916.

B917

Bit 21: B917.

B918

Bit 22: B918.

B919

Bit 23: B919.

B920

Bit 24: B920.

B921

Bit 25: B921.

B922

Bit 26: B922.

B923

Bit 27: B923.

B924

Bit 28: B924.

B925

Bit 29: B925.

B926

Bit 30: B926.

B927

Bit 31: B927.

MPCBB2_VCTR29

MPCBBx vector register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B959
rw 		B958
rw 		B957
rw 		B956
rw 		B955
rw 		B954
rw 		B953
rw 		B952
rw 		B951
rw 		B950
rw 		B949
rw 		B948
rw 		B947
rw 		B946
rw 		B945
rw 		B944
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B943
rw 		B942
rw 		B941
rw 		B940
rw 		B939
rw 		B938
rw 		B937
rw 		B936
rw 		B935
rw 		B934
rw 		B933
rw 		B932
rw 		B931
rw 		B930
rw 		B929
rw 		B928
rw
Toggle fields

B928

Bit 0: B928.

B929

Bit 1: B929.

B930

Bit 2: B930.

B931

Bit 3: B931.

B932

Bit 4: B932.

B933

Bit 5: B933.

B934

Bit 6: B934.

B935

Bit 7: B935.

B936

Bit 8: B936.

B937

Bit 9: B937.

B938

Bit 10: B938.

B939

Bit 11: B939.

B940

Bit 12: B940.

B941

Bit 13: B941.

B942

Bit 14: B942.

B943

Bit 15: B943.

B944

Bit 16: B944.

B945

Bit 17: B945.

B946

Bit 18: B946.

B947

Bit 19: B947.

B948

Bit 20: B948.

B949

Bit 21: B949.

B950

Bit 22: B950.

B951

Bit 23: B951.

B952

Bit 24: B952.

B953

Bit 25: B953.

B954

Bit 26: B954.

B955

Bit 27: B955.

B956

Bit 28: B956.

B957

Bit 29: B957.

B958

Bit 30: B958.

B959

Bit 31: B959.

MPCBB2_VCTR30

MPCBBx vector register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B991
rw 		B990
rw 		B989
rw 		B988
rw 		B987
rw 		B986
rw 		B985
rw 		B984
rw 		B983
rw 		B982
rw 		B981
rw 		B980
rw 		B979
rw 		B978
rw 		B977
rw 		B976
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B975
rw 		B974
rw 		B973
rw 		B972
rw 		B971
rw 		B970
rw 		B969
rw 		B968
rw 		B967
rw 		B966
rw 		B965
rw 		B964
rw 		B963
rw 		B962
rw 		B961
rw 		B960
rw
Toggle fields

B960

Bit 0: B960.

B961

Bit 1: B961.

B962

Bit 2: B962.

B963

Bit 3: B963.

B964

Bit 4: B964.

B965

Bit 5: B965.

B966

Bit 6: B966.

B967

Bit 7: B967.

B968

Bit 8: B968.

B969

Bit 9: B969.

B970

Bit 10: B970.

B971

Bit 11: B971.

B972

Bit 12: B972.

B973

Bit 13: B973.

B974

Bit 14: B974.

B975

Bit 15: B975.

B976

Bit 16: B976.

B977

Bit 17: B977.

B978

Bit 18: B978.

B979

Bit 19: B979.

B980

Bit 20: B980.

B981

Bit 21: B981.

B982

Bit 22: B982.

B983

Bit 23: B983.

B984

Bit 24: B984.

B985

Bit 25: B985.

B986

Bit 26: B986.

B987

Bit 27: B987.

B988

Bit 28: B988.

B989

Bit 29: B989.

B990

Bit 30: B990.

B991

Bit 31: B991.

MPCBB2_VCTR31

MPCBBx vector register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1023
rw 		B1022
rw 		B1021
rw 		B1020
rw 		B1019
rw 		B1018
rw 		B1017
rw 		B1016
rw 		B1015
rw 		B1014
rw 		B1013
rw 		B1012
rw 		B1011
rw 		B1010
rw 		B1009
rw 		B1008
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1007
rw 		B1006
rw 		B1005
rw 		B1004
rw 		B1003
rw 		B1002
rw 		B1001
rw 		B1000
rw 		B999
rw 		B998
rw 		B997
rw 		B996
rw 		B995
rw 		B994
rw 		B993
rw 		B992
rw
Toggle fields

B992

Bit 0: B992.

B993

Bit 1: B993.

B994

Bit 2: B994.

B995

Bit 3: B995.

B996

Bit 4: B996.

B997

Bit 5: B997.

B998

Bit 6: B998.

B999

Bit 7: B999.

B1000

Bit 8: B1000.

B1001

Bit 9: B1001.

B1002

Bit 10: B1002.

B1003

Bit 11: B1003.

B1004

Bit 12: B1004.

B1005

Bit 13: B1005.

B1006

Bit 14: B1006.

B1007

Bit 15: B1007.

B1008

Bit 16: B1008.

B1009

Bit 17: B1009.

B1010

Bit 18: B1010.

B1011

Bit 19: B1011.

B1012

Bit 20: B1012.

B1013

Bit 21: B1013.

B1014

Bit 22: B1014.

B1015

Bit 23: B1015.

B1016

Bit 24: B1016.

B1017

Bit 25: B1017.

B1018

Bit 26: B1018.

B1019

Bit 27: B1019.

B1020

Bit 28: B1020.

B1021

Bit 29: B1021.

B1022

Bit 30: B1022.

B1023

Bit 31: B1023.

MPCBB2_VCTR32

MPCBBx vector register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1055
rw 		B1054
rw 		B1053
rw 		B1052
rw 		B1051
rw 		B1050
rw 		B1049
rw 		B1048
rw 		B1047
rw 		B1046
rw 		B1045
rw 		B1044
rw 		B1043
rw 		B1042
rw 		B1041
rw 		B1040
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1039
rw 		B1038
rw 		B1037
rw 		B1036
rw 		B1035
rw 		B1034
rw 		B1033
rw 		B1032
rw 		B1031
rw 		B1030
rw 		B1029
rw 		B1028
rw 		B1027
rw 		B1026
rw 		B1025
rw 		B1024
rw
Toggle fields

B1024

Bit 0: B1024.

B1025

Bit 1: B1025.

B1026

Bit 2: B1026.

B1027

Bit 3: B1027.

B1028

Bit 4: B1028.

B1029

Bit 5: B1029.

B1030

Bit 6: B1030.

B1031

Bit 7: B1031.

B1032

Bit 8: B1032.

B1033

Bit 9: B1033.

B1034

Bit 10: B1034.

B1035

Bit 11: B1035.

B1036

Bit 12: B1036.

B1037

Bit 13: B1037.

B1038

Bit 14: B1038.

B1039

Bit 15: B1039.

B1040

Bit 16: B1040.

B1041

Bit 17: B1041.

B1042

Bit 18: B1042.

B1043

Bit 19: B1043.

B1044

Bit 20: B1044.

B1045

Bit 21: B1045.

B1046

Bit 22: B1046.

B1047

Bit 23: B1047.

B1048

Bit 24: B1048.

B1049

Bit 25: B1049.

B1050

Bit 26: B1050.

B1051

Bit 27: B1051.

B1052

Bit 28: B1052.

B1053

Bit 29: B1053.

B1054

Bit 30: B1054.

B1055

Bit 31: B1055.

MPCBB2_VCTR33

MPCBBx vector register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1087
rw 		B1086
rw 		B1085
rw 		B1084
rw 		B1083
rw 		B1082
rw 		B1081
rw 		B1080
rw 		B1079
rw 		B1078
rw 		B1077
rw 		B1076
rw 		B1075
rw 		B1074
rw 		B1073
rw 		B1072
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1071
rw 		B1070
rw 		B1069
rw 		B1068
rw 		B1067
rw 		B1066
rw 		B1065
rw 		B1064
rw 		B1063
rw 		B1062
rw 		B1061
rw 		B1060
rw 		B1059
rw 		B1058
rw 		B1057
rw 		B1056
rw
Toggle fields

B1056

Bit 0: B1056.

B1057

Bit 1: B1057.

B1058

Bit 2: B1058.

B1059

Bit 3: B1059.

B1060

Bit 4: B1060.

B1061

Bit 5: B1061.

B1062

Bit 6: B1062.

B1063

Bit 7: B1063.

B1064

Bit 8: B1064.

B1065

Bit 9: B1065.

B1066

Bit 10: B1066.

B1067

Bit 11: B1067.

B1068

Bit 12: B1068.

B1069

Bit 13: B1069.

B1070

Bit 14: B1070.

B1071

Bit 15: B1071.

B1072

Bit 16: B1072.

B1073

Bit 17: B1073.

B1074

Bit 18: B1074.

B1075

Bit 19: B1075.

B1076

Bit 20: B1076.

B1077

Bit 21: B1077.

B1078

Bit 22: B1078.

B1079

Bit 23: B1079.

B1080

Bit 24: B1080.

B1081

Bit 25: B1081.

B1082

Bit 26: B1082.

B1083

Bit 27: B1083.

B1084

Bit 28: B1084.

B1085

Bit 29: B1085.

B1086

Bit 30: B1086.

B1087

Bit 31: B1087.

MPCBB2_VCTR34

MPCBBx vector register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1119
rw 		B1118
rw 		B1117
rw 		B1116
rw 		B1115
rw 		B1114
rw 		B1113
rw 		B1112
rw 		B1111
rw 		B1110
rw 		B1109
rw 		B1108
rw 		B1107
rw 		B1106
rw 		B1105
rw 		B1104
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1103
rw 		B1102
rw 		B1101
rw 		B1100
rw 		B1099
rw 		B1098
rw 		B1097
rw 		B1096
rw 		B1095
rw 		B1094
rw 		B1093
rw 		B1092
rw 		B1091
rw 		B1090
rw 		B1089
rw 		B1088
rw
Toggle fields

B1088

Bit 0: B1088.

B1089

Bit 1: B1089.

B1090

Bit 2: B1090.

B1091

Bit 3: B1091.

B1092

Bit 4: B1092.

B1093

Bit 5: B1093.

B1094

Bit 6: B1094.

B1095

Bit 7: B1095.

B1096

Bit 8: B1096.

B1097

Bit 9: B1097.

B1098

Bit 10: B1098.

B1099

Bit 11: B1099.

B1100

Bit 12: B1100.

B1101

Bit 13: B1101.

B1102

Bit 14: B1102.

B1103

Bit 15: B1103.

B1104

Bit 16: B1104.

B1105

Bit 17: B1105.

B1106

Bit 18: B1106.

B1107

Bit 19: B1107.

B1108

Bit 20: B1108.

B1109

Bit 21: B1109.

B1110

Bit 22: B1110.

B1111

Bit 23: B1111.

B1112

Bit 24: B1112.

B1113

Bit 25: B1113.

B1114

Bit 26: B1114.

B1115

Bit 27: B1115.

B1116

Bit 28: B1116.

B1117

Bit 29: B1117.

B1118

Bit 30: B1118.

B1119

Bit 31: B1119.

MPCBB2_VCTR35

MPCBBx vector register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1151
rw 		B1150
rw 		B1149
rw 		B1148
rw 		B1147
rw 		B1146
rw 		B1145
rw 		B1144
rw 		B1143
rw 		B1142
rw 		B1141
rw 		B1140
rw 		B1139
rw 		B1138
rw 		B1137
rw 		B1136
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1135
rw 		B1134
rw 		B1133
rw 		B1132
rw 		B1131
rw 		B1130
rw 		B1129
rw 		B1128
rw 		B1127
rw 		B1126
rw 		B1125
rw 		B1124
rw 		B1123
rw 		B1122
rw 		B1121
rw 		B1120
rw
Toggle fields

B1120

Bit 0: B1120.

B1121

Bit 1: B1121.

B1122

Bit 2: B1122.

B1123

Bit 3: B1123.

B1124

Bit 4: B1124.

B1125

Bit 5: B1125.

B1126

Bit 6: B1126.

B1127

Bit 7: B1127.

B1128

Bit 8: B1128.

B1129

Bit 9: B1129.

B1130

Bit 10: B1130.

B1131

Bit 11: B1131.

B1132

Bit 12: B1132.

B1133

Bit 13: B1133.

B1134

Bit 14: B1134.

B1135

Bit 15: B1135.

B1136

Bit 16: B1136.

B1137

Bit 17: B1137.

B1138

Bit 18: B1138.

B1139

Bit 19: B1139.

B1140

Bit 20: B1140.

B1141

Bit 21: B1141.

B1142

Bit 22: B1142.

B1143

Bit 23: B1143.

B1144

Bit 24: B1144.

B1145

Bit 25: B1145.

B1146

Bit 26: B1146.

B1147

Bit 27: B1147.

B1148

Bit 28: B1148.

B1149

Bit 29: B1149.

B1150

Bit 30: B1150.

B1151

Bit 31: B1151.

MPCBB2_VCTR36

MPCBBx vector register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1183
rw 		B1182
rw 		B1181
rw 		B1180
rw 		B1179
rw 		B1178
rw 		B1177
rw 		B1176
rw 		B1175
rw 		B1174
rw 		B1173
rw 		B1172
rw 		B1171
rw 		B1170
rw 		B1169
rw 		B1168
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1167
rw 		B1166
rw 		B1165
rw 		B1164
rw 		B1163
rw 		B1162
rw 		B1161
rw 		B1160
rw 		B1159
rw 		B1158
rw 		B1157
rw 		B1156
rw 		B1155
rw 		B1154
rw 		B1153
rw 		B1152
rw
Toggle fields

B1152

Bit 0: B1152.

B1153

Bit 1: B1153.

B1154

Bit 2: B1154.

B1155

Bit 3: B1155.

B1156

Bit 4: B1156.

B1157

Bit 5: B1157.

B1158

Bit 6: B1158.

B1159

Bit 7: B1159.

B1160

Bit 8: B1160.

B1161

Bit 9: B1161.

B1162

Bit 10: B1162.

B1163

Bit 11: B1163.

B1164

Bit 12: B1164.

B1165

Bit 13: B1165.

B1166

Bit 14: B1166.

B1167

Bit 15: B1167.

B1168

Bit 16: B1168.

B1169

Bit 17: B1169.

B1170

Bit 18: B1170.

B1171

Bit 19: B1171.

B1172

Bit 20: B1172.

B1173

Bit 21: B1173.

B1174

Bit 22: B1174.

B1175

Bit 23: B1175.

B1176

Bit 24: B1176.

B1177

Bit 25: B1177.

B1178

Bit 26: B1178.

B1179

Bit 27: B1179.

B1180

Bit 28: B1180.

B1181

Bit 29: B1181.

B1182

Bit 30: B1182.

B1183

Bit 31: B1183.

MPCBB2_VCTR37

MPCBBx vector register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1215
rw 		B1214
rw 		B1213
rw 		B1212
rw 		B1211
rw 		B1210
rw 		B1209
rw 		B1208
rw 		B1207
rw 		B1206
rw 		B1205
rw 		B1204
rw 		B1203
rw 		B1202
rw 		B1201
rw 		B1200
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1199
rw 		B1198
rw 		B1197
rw 		B1196
rw 		B1195
rw 		B1194
rw 		B1193
rw 		B1192
rw 		B1191
rw 		B1190
rw 		B1189
rw 		B1188
rw 		B1187
rw 		B1186
rw 		B1185
rw 		B1184
rw
Toggle fields

B1184

Bit 0: B1184.

B1185

Bit 1: B1185.

B1186

Bit 2: B1186.

B1187

Bit 3: B1187.

B1188

Bit 4: B1188.

B1189

Bit 5: B1189.

B1190

Bit 6: B1190.

B1191

Bit 7: B1191.

B1192

Bit 8: B1192.

B1193

Bit 9: B1193.

B1194

Bit 10: B1194.

B1195

Bit 11: B1195.

B1196

Bit 12: B1196.

B1197

Bit 13: B1197.

B1198

Bit 14: B1198.

B1199

Bit 15: B1199.

B1200

Bit 16: B1200.

B1201

Bit 17: B1201.

B1202

Bit 18: B1202.

B1203

Bit 19: B1203.

B1204

Bit 20: B1204.

B1205

Bit 21: B1205.

B1206

Bit 22: B1206.

B1207

Bit 23: B1207.

B1208

Bit 24: B1208.

B1209

Bit 25: B1209.

B1210

Bit 26: B1210.

B1211

Bit 27: B1211.

B1212

Bit 28: B1212.

B1213

Bit 29: B1213.

B1214

Bit 30: B1214.

B1215

Bit 31: B1215.

MPCBB2_VCTR38

MPCBBx vector register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1247
rw 		B1246
rw 		B1245
rw 		B1244
rw 		B1243
rw 		B1242
rw 		B1241
rw 		B1240
rw 		B1239
rw 		B1238
rw 		B1237
rw 		B1236
rw 		B1235
rw 		B1234
rw 		B1233
rw 		B1232
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1231
rw 		B1230
rw 		B1229
rw 		B1228
rw 		B1227
rw 		B1226
rw 		B1225
rw 		B1224
rw 		B1223
rw 		B1222
rw 		B1221
rw 		B1220
rw 		B1219
rw 		B1218
rw 		B1217
rw 		B1216
rw
Toggle fields

B1216

Bit 0: B1216.

B1217

Bit 1: B1217.

B1218

Bit 2: B1218.

B1219

Bit 3: B1219.

B1220

Bit 4: B1220.

B1221

Bit 5: B1221.

B1222

Bit 6: B1222.

B1223

Bit 7: B1223.

B1224

Bit 8: B1224.

B1225

Bit 9: B1225.

B1226

Bit 10: B1226.

B1227

Bit 11: B1227.

B1228

Bit 12: B1228.

B1229

Bit 13: B1229.

B1230

Bit 14: B1230.

B1231

Bit 15: B1231.

B1232

Bit 16: B1232.

B1233

Bit 17: B1233.

B1234

Bit 18: B1234.

B1235

Bit 19: B1235.

B1236

Bit 20: B1236.

B1237

Bit 21: B1237.

B1238

Bit 22: B1238.

B1239

Bit 23: B1239.

B1240

Bit 24: B1240.

B1241

Bit 25: B1241.

B1242

Bit 26: B1242.

B1243

Bit 27: B1243.

B1244

Bit 28: B1244.

B1245

Bit 29: B1245.

B1246

Bit 30: B1246.

B1247

Bit 31: B1247.

MPCBB2_VCTR39

MPCBBx vector register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1279
rw 		B1278
rw 		B1277
rw 		B1276
rw 		B1275
rw 		B1274
rw 		B1273
rw 		B1272
rw 		B1271
rw 		B1270
rw 		B1269
rw 		B1268
rw 		B1267
rw 		B1266
rw 		B1265
rw 		B1264
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1263
rw 		B1262
rw 		B1261
rw 		B1260
rw 		B1259
rw 		B1258
rw 		B1257
rw 		B1256
rw 		B1255
rw 		B1254
rw 		B1253
rw 		B1252
rw 		B1251
rw 		B1250
rw 		B1249
rw 		B1248
rw
Toggle fields

B1248

Bit 0: B1248.

B1249

Bit 1: B1249.

B1250

Bit 2: B1250.

B1251

Bit 3: B1251.

B1252

Bit 4: B1252.

B1253

Bit 5: B1253.

B1254

Bit 6: B1254.

B1255

Bit 7: B1255.

B1256

Bit 8: B1256.

B1257

Bit 9: B1257.

B1258

Bit 10: B1258.

B1259

Bit 11: B1259.

B1260

Bit 12: B1260.

B1261

Bit 13: B1261.

B1262

Bit 14: B1262.

B1263

Bit 15: B1263.

B1264

Bit 16: B1264.

B1265

Bit 17: B1265.

B1266

Bit 18: B1266.

B1267

Bit 19: B1267.

B1268

Bit 20: B1268.

B1269

Bit 21: B1269.

B1270

Bit 22: B1270.

B1271

Bit 23: B1271.

B1272

Bit 24: B1272.

B1273

Bit 25: B1273.

B1274

Bit 26: B1274.

B1275

Bit 27: B1275.

B1276

Bit 28: B1276.

B1277

Bit 29: B1277.

B1278

Bit 30: B1278.

B1279

Bit 31: B1279.

MPCBB2_VCTR40

MPCBBx vector register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1311
rw 		B1310
rw 		B1309
rw 		B1308
rw 		B1307
rw 		B1306
rw 		B1305
rw 		B1304
rw 		B1303
rw 		B1302
rw 		B1301
rw 		B1300
rw 		B1299
rw 		B1298
rw 		B1297
rw 		B1296
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1295
rw 		B1294
rw 		B1293
rw 		B1292
rw 		B1291
rw 		B1290
rw 		B1289
rw 		B1288
rw 		B1287
rw 		B1286
rw 		B1285
rw 		B1284
rw 		B1283
rw 		B1282
rw 		B1281
rw 		B1280
rw
Toggle fields

B1280

Bit 0: B1280.

B1281

Bit 1: B1281.

B1282

Bit 2: B1282.

B1283

Bit 3: B1283.

B1284

Bit 4: B1284.

B1285

Bit 5: B1285.

B1286

Bit 6: B1286.

B1287

Bit 7: B1287.

B1288

Bit 8: B1288.

B1289

Bit 9: B1289.

B1290

Bit 10: B1290.

B1291

Bit 11: B1291.

B1292

Bit 12: B1292.

B1293

Bit 13: B1293.

B1294

Bit 14: B1294.

B1295

Bit 15: B1295.

B1296

Bit 16: B1296.

B1297

Bit 17: B1297.

B1298

Bit 18: B1298.

B1299

Bit 19: B1299.

B1300

Bit 20: B1300.

B1301

Bit 21: B1301.

B1302

Bit 22: B1302.

B1303

Bit 23: B1303.

B1304

Bit 24: B1304.

B1305

Bit 25: B1305.

B1306

Bit 26: B1306.

B1307

Bit 27: B1307.

B1308

Bit 28: B1308.

B1309

Bit 29: B1309.

B1310

Bit 30: B1310.

B1311

Bit 31: B1311.

MPCBB2_VCTR41

MPCBBx vector register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1343
rw 		B1342
rw 		B1341
rw 		B1340
rw 		B1339
rw 		B1338
rw 		B1337
rw 		B1336
rw 		B1335
rw 		B1334
rw 		B1333
rw 		B1332
rw 		B1331
rw 		B1330
rw 		B1329
rw 		B1328
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1327
rw 		B1326
rw 		B1325
rw 		B1324
rw 		B1323
rw 		B1322
rw 		B1321
rw 		B1320
rw 		B1319
rw 		B1318
rw 		B1317
rw 		B1316
rw 		B1315
rw 		B1314
rw 		B1313
rw 		B1312
rw
Toggle fields

B1312

Bit 0: B1312.

B1313

Bit 1: B1313.

B1314

Bit 2: B1314.

B1315

Bit 3: B1315.

B1316

Bit 4: B1316.

B1317

Bit 5: B1317.

B1318

Bit 6: B1318.

B1319

Bit 7: B1319.

B1320

Bit 8: B1320.

B1321

Bit 9: B1321.

B1322

Bit 10: B1322.

B1323

Bit 11: B1323.

B1324

Bit 12: B1324.

B1325

Bit 13: B1325.

B1326

Bit 14: B1326.

B1327

Bit 15: B1327.

B1328

Bit 16: B1328.

B1329

Bit 17: B1329.

B1330

Bit 18: B1330.

B1331

Bit 19: B1331.

B1332

Bit 20: B1332.

B1333

Bit 21: B1333.

B1334

Bit 22: B1334.

B1335

Bit 23: B1335.

B1336

Bit 24: B1336.

B1337

Bit 25: B1337.

B1338

Bit 26: B1338.

B1339

Bit 27: B1339.

B1340

Bit 28: B1340.

B1341

Bit 29: B1341.

B1342

Bit 30: B1342.

B1343

Bit 31: B1343.

MPCBB2_VCTR42

MPCBBx vector register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1375
rw 		B1374
rw 		B1373
rw 		B1372
rw 		B1371
rw 		B1370
rw 		B1369
rw 		B1368
rw 		B1367
rw 		B1366
rw 		B1365
rw 		B1364
rw 		B1363
rw 		B1362
rw 		B1361
rw 		B1360
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1359
rw 		B1358
rw 		B1357
rw 		B1356
rw 		B1355
rw 		B1354
rw 		B1353
rw 		B1352
rw 		B1351
rw 		B1350
rw 		B1349
rw 		B1348
rw 		B1347
rw 		B1346
rw 		B1345
rw 		B1344
rw
Toggle fields

B1344

Bit 0: B1344.

B1345

Bit 1: B1345.

B1346

Bit 2: B1346.

B1347

Bit 3: B1347.

B1348

Bit 4: B1348.

B1349

Bit 5: B1349.

B1350

Bit 6: B1350.

B1351

Bit 7: B1351.

B1352

Bit 8: B1352.

B1353

Bit 9: B1353.

B1354

Bit 10: B1354.

B1355

Bit 11: B1355.

B1356

Bit 12: B1356.

B1357

Bit 13: B1357.

B1358

Bit 14: B1358.

B1359

Bit 15: B1359.

B1360

Bit 16: B1360.

B1361

Bit 17: B1361.

B1362

Bit 18: B1362.

B1363

Bit 19: B1363.

B1364

Bit 20: B1364.

B1365

Bit 21: B1365.

B1366

Bit 22: B1366.

B1367

Bit 23: B1367.

B1368

Bit 24: B1368.

B1369

Bit 25: B1369.

B1370

Bit 26: B1370.

B1371

Bit 27: B1371.

B1372

Bit 28: B1372.

B1373

Bit 29: B1373.

B1374

Bit 30: B1374.

B1375

Bit 31: B1375.

MPCBB2_VCTR43

MPCBBx vector register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1407
rw 		B1406
rw 		B1405
rw 		B1404
rw 		B1403
rw 		B1402
rw 		B1401
rw 		B1400
rw 		B1399
rw 		B1398
rw 		B1397
rw 		B1396
rw 		B1395
rw 		B1394
rw 		B1393
rw 		B1392
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1391
rw 		B1390
rw 		B1389
rw 		B1388
rw 		B1387
rw 		B1386
rw 		B1385
rw 		B1384
rw 		B1383
rw 		B1382
rw 		B1381
rw 		B1380
rw 		B1379
rw 		B1378
rw 		B1377
rw 		B1376
rw
Toggle fields

B1376

Bit 0: B1376.

B1377

Bit 1: B1377.

B1378

Bit 2: B1378.

B1379

Bit 3: B1379.

B1380

Bit 4: B1380.

B1381

Bit 5: B1381.

B1382

Bit 6: B1382.

B1383

Bit 7: B1383.

B1384

Bit 8: B1384.

B1385

Bit 9: B1385.

B1386

Bit 10: B1386.

B1387

Bit 11: B1387.

B1388

Bit 12: B1388.

B1389

Bit 13: B1389.

B1390

Bit 14: B1390.

B1391

Bit 15: B1391.

B1392

Bit 16: B1392.

B1393

Bit 17: B1393.

B1394

Bit 18: B1394.

B1395

Bit 19: B1395.

B1396

Bit 20: B1396.

B1397

Bit 21: B1397.

B1398

Bit 22: B1398.

B1399

Bit 23: B1399.

B1400

Bit 24: B1400.

B1401

Bit 25: B1401.

B1402

Bit 26: B1402.

B1403

Bit 27: B1403.

B1404

Bit 28: B1404.

B1405

Bit 29: B1405.

B1406

Bit 30: B1406.

B1407

Bit 31: B1407.

MPCBB2_VCTR44

MPCBBx vector register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1439
rw 		B1438
rw 		B1437
rw 		B1436
rw 		B1435
rw 		B1434
rw 		B1433
rw 		B1432
rw 		B1431
rw 		B1430
rw 		B1429
rw 		B1428
rw 		B1427
rw 		B1426
rw 		B1425
rw 		B1424
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1423
rw 		B1422
rw 		B1421
rw 		B1420
rw 		B1419
rw 		B1418
rw 		B1417
rw 		B1416
rw 		B1415
rw 		B1414
rw 		B1413
rw 		B1412
rw 		B1411
rw 		B1410
rw 		B1409
rw 		B1408
rw
Toggle fields

B1408

Bit 0: B1408.

B1409

Bit 1: B1409.

B1410

Bit 2: B1410.

B1411

Bit 3: B1411.

B1412

Bit 4: B1412.

B1413

Bit 5: B1413.

B1414

Bit 6: B1414.

B1415

Bit 7: B1415.

B1416

Bit 8: B1416.

B1417

Bit 9: B1417.

B1418

Bit 10: B1418.

B1419

Bit 11: B1419.

B1420

Bit 12: B1420.

B1421

Bit 13: B1421.

B1422

Bit 14: B1422.

B1423

Bit 15: B1423.

B1424

Bit 16: B1424.

B1425

Bit 17: B1425.

B1426

Bit 18: B1426.

B1427

Bit 19: B1427.

B1428

Bit 20: B1428.

B1429

Bit 21: B1429.

B1430

Bit 22: B1430.

B1431

Bit 23: B1431.

B1432

Bit 24: B1432.

B1433

Bit 25: B1433.

B1434

Bit 26: B1434.

B1435

Bit 27: B1435.

B1436

Bit 28: B1436.

B1437

Bit 29: B1437.

B1438

Bit 30: B1438.

B1439

Bit 31: B1439.

MPCBB2_VCTR45

MPCBBx vector register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1471
rw 		B1470
rw 		B1469
rw 		B1468
rw 		B1467
rw 		B1466
rw 		B1465
rw 		B1464
rw 		B1463
rw 		B1462
rw 		B1461
rw 		B1460
rw 		B1459
rw 		B1458
rw 		B1457
rw 		B1456
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1455
rw 		B1454
rw 		B1453
rw 		B1452
rw 		B1451
rw 		B1450
rw 		B1449
rw 		B1448
rw 		B1447
rw 		B1446
rw 		B1445
rw 		B1444
rw 		B1443
rw 		B1442
rw 		B1441
rw 		B1440
rw
Toggle fields

B1440

Bit 0: B1440.

B1441

Bit 1: B1441.

B1442

Bit 2: B1442.

B1443

Bit 3: B1443.

B1444

Bit 4: B1444.

B1445

Bit 5: B1445.

B1446

Bit 6: B1446.

B1447

Bit 7: B1447.

B1448

Bit 8: B1448.

B1449

Bit 9: B1449.

B1450

Bit 10: B1450.

B1451

Bit 11: B1451.

B1452

Bit 12: B1452.

B1453

Bit 13: B1453.

B1454

Bit 14: B1454.

B1455

Bit 15: B1455.

B1456

Bit 16: B1456.

B1457

Bit 17: B1457.

B1458

Bit 18: B1458.

B1459

Bit 19: B1459.

B1460

Bit 20: B1460.

B1461

Bit 21: B1461.

B1462

Bit 22: B1462.

B1463

Bit 23: B1463.

B1464

Bit 24: B1464.

B1465

Bit 25: B1465.

B1466

Bit 26: B1466.

B1467

Bit 27: B1467.

B1468

Bit 28: B1468.

B1469

Bit 29: B1469.

B1470

Bit 30: B1470.

B1471

Bit 31: B1471.

MPCBB2_VCTR46

MPCBBx vector register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1503
rw 		B1502
rw 		B1501
rw 		B1500
rw 		B1499
rw 		B1498
rw 		B1497
rw 		B1496
rw 		B1495
rw 		B1494
rw 		B1493
rw 		B1492
rw 		B1491
rw 		B1490
rw 		B1489
rw 		B1488
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1487
rw 		B1486
rw 		B1485
rw 		B1484
rw 		B1483
rw 		B1482
rw 		B1481
rw 		B1480
rw 		B1479
rw 		B1478
rw 		B1477
rw 		B1476
rw 		B1475
rw 		B1474
rw 		B1473
rw 		B1472
rw
Toggle fields

B1472

Bit 0: B1472.

B1473

Bit 1: B1473.

B1474

Bit 2: B1474.

B1475

Bit 3: B1475.

B1476

Bit 4: B1476.

B1477

Bit 5: B1477.

B1478

Bit 6: B1478.

B1479

Bit 7: B1479.

B1480

Bit 8: B1480.

B1481

Bit 9: B1481.

B1482

Bit 10: B1482.

B1483

Bit 11: B1483.

B1484

Bit 12: B1484.

B1485

Bit 13: B1485.

B1486

Bit 14: B1486.

B1487

Bit 15: B1487.

B1488

Bit 16: B1488.

B1489

Bit 17: B1489.

B1490

Bit 18: B1490.

B1491

Bit 19: B1491.

B1492

Bit 20: B1492.

B1493

Bit 21: B1493.

B1494

Bit 22: B1494.

B1495

Bit 23: B1495.

B1496

Bit 24: B1496.

B1497

Bit 25: B1497.

B1498

Bit 26: B1498.

B1499

Bit 27: B1499.

B1500

Bit 28: B1500.

B1501

Bit 29: B1501.

B1502

Bit 30: B1502.

B1503

Bit 31: B1503.

MPCBB2_VCTR47

MPCBBx vector register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1535
rw 		B1534
rw 		B1533
rw 		B1532
rw 		B1531
rw 		B1530
rw 		B1529
rw 		B1528
rw 		B1527
rw 		B1526
rw 		B1525
rw 		B1524
rw 		B1523
rw 		B1522
rw 		B1521
rw 		B1520
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1519
rw 		B1518
rw 		B1517
rw 		B1516
rw 		B1515
rw 		B1514
rw 		B1513
rw 		B1512
rw 		B1511
rw 		B1510
rw 		B1509
rw 		B1508
rw 		B1507
rw 		B1506
rw 		B1505
rw 		B1504
rw
Toggle fields

B1504

Bit 0: B1504.

B1505

Bit 1: B1505.

B1506

Bit 2: B1506.

B1507

Bit 3: B1507.

B1508

Bit 4: B1508.

B1509

Bit 5: B1509.

B1510

Bit 6: B1510.

B1511

Bit 7: B1511.

B1512

Bit 8: B1512.

B1513

Bit 9: B1513.

B1514

Bit 10: B1514.

B1515

Bit 11: B1515.

B1516

Bit 12: B1516.

B1517

Bit 13: B1517.

B1518

Bit 14: B1518.

B1519

Bit 15: B1519.

B1520

Bit 16: B1520.

B1521

Bit 17: B1521.

B1522

Bit 18: B1522.

B1523

Bit 19: B1523.

B1524

Bit 20: B1524.

B1525

Bit 21: B1525.

B1526

Bit 22: B1526.

B1527

Bit 23: B1527.

B1528

Bit 24: B1528.

B1529

Bit 25: B1529.

B1530

Bit 26: B1530.

B1531

Bit 27: B1531.

B1532

Bit 28: B1532.

B1533

Bit 29: B1533.

B1534

Bit 30: B1534.

B1535

Bit 31: B1535.

MPCBB2_VCTR48

MPCBBx vector register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1567
rw 		B1566
rw 		B1565
rw 		B1564
rw 		B1563
rw 		B1562
rw 		B1561
rw 		B1560
rw 		B1559
rw 		B1558
rw 		B1557
rw 		B1556
rw 		B1555
rw 		B1554
rw 		B1553
rw 		B1552
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1551
rw 		B1550
rw 		B1549
rw 		B1548
rw 		B1547
rw 		B1546
rw 		B1545
rw 		B1544
rw 		B1543
rw 		B1542
rw 		B1541
rw 		B1540
rw 		B1539
rw 		B1538
rw 		B1537
rw 		B1536
rw
Toggle fields

B1536

Bit 0: B1536.

B1537

Bit 1: B1537.

B1538

Bit 2: B1538.

B1539

Bit 3: B1539.

B1540

Bit 4: B1540.

B1541

Bit 5: B1541.

B1542

Bit 6: B1542.

B1543

Bit 7: B1543.

B1544

Bit 8: B1544.

B1545

Bit 9: B1545.

B1546

Bit 10: B1546.

B1547

Bit 11: B1547.

B1548

Bit 12: B1548.

B1549

Bit 13: B1549.

B1550

Bit 14: B1550.

B1551

Bit 15: B1551.

B1552

Bit 16: B1552.

B1553

Bit 17: B1553.

B1554

Bit 18: B1554.

B1555

Bit 19: B1555.

B1556

Bit 20: B1556.

B1557

Bit 21: B1557.

B1558

Bit 22: B1558.

B1559

Bit 23: B1559.

B1560

Bit 24: B1560.

B1561

Bit 25: B1561.

B1562

Bit 26: B1562.

B1563

Bit 27: B1563.

B1564

Bit 28: B1564.

B1565

Bit 29: B1565.

B1566

Bit 30: B1566.

B1567

Bit 31: B1567.

MPCBB2_VCTR49

MPCBBx vector register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1599
rw 		B1598
rw 		B1597
rw 		B1596
rw 		B1595
rw 		B1594
rw 		B1593
rw 		B1592
rw 		B1591
rw 		B1590
rw 		B1589
rw 		B1588
rw 		B1587
rw 		B1586
rw 		B1585
rw 		B1584
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1583
rw 		B1582
rw 		B1581
rw 		B1580
rw 		B1579
rw 		B1578
rw 		B1577
rw 		B1576
rw 		B1575
rw 		B1574
rw 		B1573
rw 		B1572
rw 		B1571
rw 		B1570
rw 		B1569
rw 		B1568
rw
Toggle fields

B1568

Bit 0: B1568.

B1569

Bit 1: B1569.

B1570

Bit 2: B1570.

B1571

Bit 3: B1571.

B1572

Bit 4: B1572.

B1573

Bit 5: B1573.

B1574

Bit 6: B1574.

B1575

Bit 7: B1575.

B1576

Bit 8: B1576.

B1577

Bit 9: B1577.

B1578

Bit 10: B1578.

B1579

Bit 11: B1579.

B1580

Bit 12: B1580.

B1581

Bit 13: B1581.

B1582

Bit 14: B1582.

B1583

Bit 15: B1583.

B1584

Bit 16: B1584.

B1585

Bit 17: B1585.

B1586

Bit 18: B1586.

B1587

Bit 19: B1587.

B1588

Bit 20: B1588.

B1589

Bit 21: B1589.

B1590

Bit 22: B1590.

B1591

Bit 23: B1591.

B1592

Bit 24: B1592.

B1593

Bit 25: B1593.

B1594

Bit 26: B1594.

B1595

Bit 27: B1595.

B1596

Bit 28: B1596.

B1597

Bit 29: B1597.

B1598

Bit 30: B1598.

B1599

Bit 31: B1599.

MPCBB2_VCTR50

MPCBBx vector register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1631
rw 		B1630
rw 		B1629
rw 		B1628
rw 		B1627
rw 		B1626
rw 		B1625
rw 		B1624
rw 		B1623
rw 		B1622
rw 		B1621
rw 		B1620
rw 		B1619
rw 		B1618
rw 		B1617
rw 		B1616
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1615
rw 		B1614
rw 		B1613
rw 		B1612
rw 		B1611
rw 		B1610
rw 		B1609
rw 		B1608
rw 		B1607
rw 		B1606
rw 		B1605
rw 		B1604
rw 		B1603
rw 		B1602
rw 		B1601
rw 		B1600
rw
Toggle fields

B1600

Bit 0: B1600.

B1601

Bit 1: B1601.

B1602

Bit 2: B1602.

B1603

Bit 3: B1603.

B1604

Bit 4: B1604.

B1605

Bit 5: B1605.

B1606

Bit 6: B1606.

B1607

Bit 7: B1607.

B1608

Bit 8: B1608.

B1609

Bit 9: B1609.

B1610

Bit 10: B1610.

B1611

Bit 11: B1611.

B1612

Bit 12: B1612.

B1613

Bit 13: B1613.

B1614

Bit 14: B1614.

B1615

Bit 15: B1615.

B1616

Bit 16: B1616.

B1617

Bit 17: B1617.

B1618

Bit 18: B1618.

B1619

Bit 19: B1619.

B1620

Bit 20: B1620.

B1621

Bit 21: B1621.

B1622

Bit 22: B1622.

B1623

Bit 23: B1623.

B1624

Bit 24: B1624.

B1625

Bit 25: B1625.

B1626

Bit 26: B1626.

B1627

Bit 27: B1627.

B1628

Bit 28: B1628.

B1629

Bit 29: B1629.

B1630

Bit 30: B1630.

B1631

Bit 31: B1631.

MPCBB2_VCTR51

MPCBBx vector register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1663
rw 		B1662
rw 		B1661
rw 		B1660
rw 		B1659
rw 		B1658
rw 		B1657
rw 		B1656
rw 		B1655
rw 		B1654
rw 		B1653
rw 		B1652
rw 		B1651
rw 		B1650
rw 		B1649
rw 		B1648
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1647
rw 		B1646
rw 		B1645
rw 		B1644
rw 		B1643
rw 		B1642
rw 		B1641
rw 		B1640
rw 		B1639
rw 		B1638
rw 		B1637
rw 		B1636
rw 		B1635
rw 		B1634
rw 		B1633
rw 		B1632
rw
Toggle fields

B1632

Bit 0: B1632.

B1633

Bit 1: B1633.

B1634

Bit 2: B1634.

B1635

Bit 3: B1635.

B1636

Bit 4: B1636.

B1637

Bit 5: B1637.

B1638

Bit 6: B1638.

B1639

Bit 7: B1639.

B1640

Bit 8: B1640.

B1641

Bit 9: B1641.

B1642

Bit 10: B1642.

B1643

Bit 11: B1643.

B1644

Bit 12: B1644.

B1645

Bit 13: B1645.

B1646

Bit 14: B1646.

B1647

Bit 15: B1647.

B1648

Bit 16: B1648.

B1649

Bit 17: B1649.

B1650

Bit 18: B1650.

B1651

Bit 19: B1651.

B1652

Bit 20: B1652.

B1653

Bit 21: B1653.

B1654

Bit 22: B1654.

B1655

Bit 23: B1655.

B1656

Bit 24: B1656.

B1657

Bit 25: B1657.

B1658

Bit 26: B1658.

B1659

Bit 27: B1659.

B1660

Bit 28: B1660.

B1661

Bit 29: B1661.

B1662

Bit 30: B1662.

B1663

Bit 31: B1663.

MPCBB2_VCTR52

MPCBBx vector register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1695
rw 		B1694
rw 		B1693
rw 		B1692
rw 		B1691
rw 		B1690
rw 		B1689
rw 		B1688
rw 		B1687
rw 		B1686
rw 		B1685
rw 		B1684
rw 		B1683
rw 		B1682
rw 		B1681
rw 		B1680
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1679
rw 		B1678
rw 		B1677
rw 		B1676
rw 		B1675
rw 		B1674
rw 		B1673
rw 		B1672
rw 		B1671
rw 		B1670
rw 		B1669
rw 		B1668
rw 		B1667
rw 		B1666
rw 		B1665
rw 		B1664
rw
Toggle fields

B1664

Bit 0: B1664.

B1665

Bit 1: B1665.

B1666

Bit 2: B1666.

B1667

Bit 3: B1667.

B1668

Bit 4: B1668.

B1669

Bit 5: B1669.

B1670

Bit 6: B1670.

B1671

Bit 7: B1671.

B1672

Bit 8: B1672.

B1673

Bit 9: B1673.

B1674

Bit 10: B1674.

B1675

Bit 11: B1675.

B1676

Bit 12: B1676.

B1677

Bit 13: B1677.

B1678

Bit 14: B1678.

B1679

Bit 15: B1679.

B1680

Bit 16: B1680.

B1681

Bit 17: B1681.

B1682

Bit 18: B1682.

B1683

Bit 19: B1683.

B1684

Bit 20: B1684.

B1685

Bit 21: B1685.

B1686

Bit 22: B1686.

B1687

Bit 23: B1687.

B1688

Bit 24: B1688.

B1689

Bit 25: B1689.

B1690

Bit 26: B1690.

B1691

Bit 27: B1691.

B1692

Bit 28: B1692.

B1693

Bit 29: B1693.

B1694

Bit 30: B1694.

B1695

Bit 31: B1695.

MPCBB2_VCTR53

MPCBBx vector register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1727
rw 		B1726
rw 		B1725
rw 		B1724
rw 		B1723
rw 		B1722
rw 		B1721
rw 		B1720
rw 		B1719
rw 		B1718
rw 		B1717
rw 		B1716
rw 		B1715
rw 		B1714
rw 		B1713
rw 		B1712
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1711
rw 		B1710
rw 		B1709
rw 		B1708
rw 		B1707
rw 		B1706
rw 		B1705
rw 		B1704
rw 		B1703
rw 		B1702
rw 		B1701
rw 		B1700
rw 		B1699
rw 		B1698
rw 		B1697
rw 		B1696
rw
Toggle fields

B1696

Bit 0: B1696.

B1697

Bit 1: B1697.

B1698

Bit 2: B1698.

B1699

Bit 3: B1699.

B1700

Bit 4: B1700.

B1701

Bit 5: B1701.

B1702

Bit 6: B1702.

B1703

Bit 7: B1703.

B1704

Bit 8: B1704.

B1705

Bit 9: B1705.

B1706

Bit 10: B1706.

B1707

Bit 11: B1707.

B1708

Bit 12: B1708.

B1709

Bit 13: B1709.

B1710

Bit 14: B1710.

B1711

Bit 15: B1711.

B1712

Bit 16: B1712.

B1713

Bit 17: B1713.

B1714

Bit 18: B1714.

B1715

Bit 19: B1715.

B1716

Bit 20: B1716.

B1717

Bit 21: B1717.

B1718

Bit 22: B1718.

B1719

Bit 23: B1719.

B1720

Bit 24: B1720.

B1721

Bit 25: B1721.

B1722

Bit 26: B1722.

B1723

Bit 27: B1723.

B1724

Bit 28: B1724.

B1725

Bit 29: B1725.

B1726

Bit 30: B1726.

B1727

Bit 31: B1727.

MPCBB2_VCTR54

MPCBBx vector register

Offset: 0x1d8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1759
rw 		B1758
rw 		B1757
rw 		B1756
rw 		B1755
rw 		B1754
rw 		B1753
rw 		B1752
rw 		B1751
rw 		B1750
rw 		B1749
rw 		B1748
rw 		B1747
rw 		B1746
rw 		B1745
rw 		B1744
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1743
rw 		B1742
rw 		B1741
rw 		B1740
rw 		B1739
rw 		B1738
rw 		B1737
rw 		B1736
rw 		B1735
rw 		B1734
rw 		B1733
rw 		B1732
rw 		B1731
rw 		B1730
rw 		B1729
rw 		B1728
rw
Toggle fields

B1728

Bit 0: B1728.

B1729

Bit 1: B1729.

B1730

Bit 2: B1730.

B1731

Bit 3: B1731.

B1732

Bit 4: B1732.

B1733

Bit 5: B1733.

B1734

Bit 6: B1734.

B1735

Bit 7: B1735.

B1736

Bit 8: B1736.

B1737

Bit 9: B1737.

B1738

Bit 10: B1738.

B1739

Bit 11: B1739.

B1740

Bit 12: B1740.

B1741

Bit 13: B1741.

B1742

Bit 14: B1742.

B1743

Bit 15: B1743.

B1744

Bit 16: B1744.

B1745

Bit 17: B1745.

B1746

Bit 18: B1746.

B1747

Bit 19: B1747.

B1748

Bit 20: B1748.

B1749

Bit 21: B1749.

B1750

Bit 22: B1750.

B1751

Bit 23: B1751.

B1752

Bit 24: B1752.

B1753

Bit 25: B1753.

B1754

Bit 26: B1754.

B1755

Bit 27: B1755.

B1756

Bit 28: B1756.

B1757

Bit 29: B1757.

B1758

Bit 30: B1758.

B1759

Bit 31: B1759.

MPCBB2_VCTR55

MPCBBx vector register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1791
rw 		B1790
rw 		B1789
rw 		B1788
rw 		B1787
rw 		B1786
rw 		B1785
rw 		B1784
rw 		B1783
rw 		B1782
rw 		B1781
rw 		B1780
rw 		B1779
rw 		B1778
rw 		B1777
rw 		B1776
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1775
rw 		B1774
rw 		B1773
rw 		B1772
rw 		B1771
rw 		B1770
rw 		B1769
rw 		B1768
rw 		B1767
rw 		B1766
rw 		B1765
rw 		B1764
rw 		B1763
rw 		B1762
rw 		B1761
rw 		B1760
rw
Toggle fields

B1760

Bit 0: B1760.

B1761

Bit 1: B1761.

B1762

Bit 2: B1762.

B1763

Bit 3: B1763.

B1764

Bit 4: B1764.

B1765

Bit 5: B1765.

B1766

Bit 6: B1766.

B1767

Bit 7: B1767.

B1768

Bit 8: B1768.

B1769

Bit 9: B1769.

B1770

Bit 10: B1770.

B1771

Bit 11: B1771.

B1772

Bit 12: B1772.

B1773

Bit 13: B1773.

B1774

Bit 14: B1774.

B1775

Bit 15: B1775.

B1776

Bit 16: B1776.

B1777

Bit 17: B1777.

B1778

Bit 18: B1778.

B1779

Bit 19: B1779.

B1780

Bit 20: B1780.

B1781

Bit 21: B1781.

B1782

Bit 22: B1782.

B1783

Bit 23: B1783.

B1784

Bit 24: B1784.

B1785

Bit 25: B1785.

B1786

Bit 26: B1786.

B1787

Bit 27: B1787.

B1788

Bit 28: B1788.

B1789

Bit 29: B1789.

B1790

Bit 30: B1790.

B1791

Bit 31: B1791.

MPCBB2_VCTR56

MPCBBx vector register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1823
rw 		B1822
rw 		B1821
rw 		B1820
rw 		B1819
rw 		B1818
rw 		B1817
rw 		B1816
rw 		B1815
rw 		B1814
rw 		B1813
rw 		B1812
rw 		B1811
rw 		B1810
rw 		B1809
rw 		B1808
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1807
rw 		B1806
rw 		B1805
rw 		B1804
rw 		B1803
rw 		B1802
rw 		B1801
rw 		B1800
rw 		B1799
rw 		B1798
rw 		B1797
rw 		B1796
rw 		B1795
rw 		B1794
rw 		B1793
rw 		B1792
rw
Toggle fields

B1792

Bit 0: B1792.

B1793

Bit 1: B1793.

B1794

Bit 2: B1794.

B1795

Bit 3: B1795.

B1796

Bit 4: B1796.

B1797

Bit 5: B1797.

B1798

Bit 6: B1798.

B1799

Bit 7: B1799.

B1800

Bit 8: B1800.

B1801

Bit 9: B1801.

B1802

Bit 10: B1802.

B1803

Bit 11: B1803.

B1804

Bit 12: B1804.

B1805

Bit 13: B1805.

B1806

Bit 14: B1806.

B1807

Bit 15: B1807.

B1808

Bit 16: B1808.

B1809

Bit 17: B1809.

B1810

Bit 18: B1810.

B1811

Bit 19: B1811.

B1812

Bit 20: B1812.

B1813

Bit 21: B1813.

B1814

Bit 22: B1814.

B1815

Bit 23: B1815.

B1816

Bit 24: B1816.

B1817

Bit 25: B1817.

B1818

Bit 26: B1818.

B1819

Bit 27: B1819.

B1820

Bit 28: B1820.

B1821

Bit 29: B1821.

B1822

Bit 30: B1822.

B1823

Bit 31: B1823.

MPCBB2_VCTR57

MPCBBx vector register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1855
rw 		B1854
rw 		B1853
rw 		B1852
rw 		B1851
rw 		B1850
rw 		B1849
rw 		B1848
rw 		B1847
rw 		B1846
rw 		B1845
rw 		B1844
rw 		B1843
rw 		B1842
rw 		B1841
rw 		B1840
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1839
rw 		B1838
rw 		B1837
rw 		B1836
rw 		B1835
rw 		B1834
rw 		B1833
rw 		B1832
rw 		B1831
rw 		B1830
rw 		B1829
rw 		B1828
rw 		B1827
rw 		B1826
rw 		B1825
rw 		B1824
rw
Toggle fields

B1824

Bit 0: B1824.

B1825

Bit 1: B1825.

B1826

Bit 2: B1826.

B1827

Bit 3: B1827.

B1828

Bit 4: B1828.

B1829

Bit 5: B1829.

B1830

Bit 6: B1830.

B1831

Bit 7: B1831.

B1832

Bit 8: B1832.

B1833

Bit 9: B1833.

B1834

Bit 10: B1834.

B1835

Bit 11: B1835.

B1836

Bit 12: B1836.

B1837

Bit 13: B1837.

B1838

Bit 14: B1838.

B1839

Bit 15: B1839.

B1840

Bit 16: B1840.

B1841

Bit 17: B1841.

B1842

Bit 18: B1842.

B1843

Bit 19: B1843.

B1844

Bit 20: B1844.

B1845

Bit 21: B1845.

B1846

Bit 22: B1846.

B1847

Bit 23: B1847.

B1848

Bit 24: B1848.

B1849

Bit 25: B1849.

B1850

Bit 26: B1850.

B1851

Bit 27: B1851.

B1852

Bit 28: B1852.

B1853

Bit 29: B1853.

B1854

Bit 30: B1854.

B1855

Bit 31: B1855.

MPCBB2_VCTR58

MPCBBx vector register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1887
rw 		B1886
rw 		B1885
rw 		B1884
rw 		B1883
rw 		B1882
rw 		B1881
rw 		B1880
rw 		B1879
rw 		B1878
rw 		B1877
rw 		B1876
rw 		B1875
rw 		B1874
rw 		B1873
rw 		B1872
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1871
rw 		B1870
rw 		B1869
rw 		B1868
rw 		B1867
rw 		B1866
rw 		B1865
rw 		B1864
rw 		B1863
rw 		B1862
rw 		B1861
rw 		B1860
rw 		B1859
rw 		B1858
rw 		B1857
rw 		B1856
rw
Toggle fields

B1856

Bit 0: B1856.

B1857

Bit 1: B1857.

B1858

Bit 2: B1858.

B1859

Bit 3: B1859.

B1860

Bit 4: B1860.

B1861

Bit 5: B1861.

B1862

Bit 6: B1862.

B1863

Bit 7: B1863.

B1864

Bit 8: B1864.

B1865

Bit 9: B1865.

B1866

Bit 10: B1866.

B1867

Bit 11: B1867.

B1868

Bit 12: B1868.

B1869

Bit 13: B1869.

B1870

Bit 14: B1870.

B1871

Bit 15: B1871.

B1872

Bit 16: B1872.

B1873

Bit 17: B1873.

B1874

Bit 18: B1874.

B1875

Bit 19: B1875.

B1876

Bit 20: B1876.

B1877

Bit 21: B1877.

B1878

Bit 22: B1878.

B1879

Bit 23: B1879.

B1880

Bit 24: B1880.

B1881

Bit 25: B1881.

B1882

Bit 26: B1882.

B1883

Bit 27: B1883.

B1884

Bit 28: B1884.

B1885

Bit 29: B1885.

B1886

Bit 30: B1886.

B1887

Bit 31: B1887.

MPCBB2_VCTR59

MPCBBx vector register

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1919
rw 		B1918
rw 		B1917
rw 		B1916
rw 		B1915
rw 		B1914
rw 		B1913
rw 		B1912
rw 		B1911
rw 		B1910
rw 		B1909
rw 		B1908
rw 		B1907
rw 		B1906
rw 		B1905
rw 		B1904
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1903
rw 		B1902
rw 		B1901
rw 		B1900
rw 		B1899
rw 		B1898
rw 		B1897
rw 		B1896
rw 		B1895
rw 		B1894
rw 		B1893
rw 		B1892
rw 		B1891
rw 		B1890
rw 		B1889
rw 		B1888
rw
Toggle fields

B1888

Bit 0: B1888.

B1889

Bit 1: B1889.

B1890

Bit 2: B1890.

B1891

Bit 3: B1891.

B1892

Bit 4: B1892.

B1893

Bit 5: B1893.

B1894

Bit 6: B1894.

B1895

Bit 7: B1895.

B1896

Bit 8: B1896.

B1897

Bit 9: B1897.

B1898

Bit 10: B1898.

B1899

Bit 11: B1899.

B1900

Bit 12: B1900.

B1901

Bit 13: B1901.

B1902

Bit 14: B1902.

B1903

Bit 15: B1903.

B1904

Bit 16: B1904.

B1905

Bit 17: B1905.

B1906

Bit 18: B1906.

B1907

Bit 19: B1907.

B1908

Bit 20: B1908.

B1909

Bit 21: B1909.

B1910

Bit 22: B1910.

B1911

Bit 23: B1911.

B1912

Bit 24: B1912.

B1913

Bit 25: B1913.

B1914

Bit 26: B1914.

B1915

Bit 27: B1915.

B1916

Bit 28: B1916.

B1917

Bit 29: B1917.

B1918

Bit 30: B1918.

B1919

Bit 31: B1919.

MPCBB2_VCTR60

MPCBBx vector register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1951
rw 		B1950
rw 		B1949
rw 		B1948
rw 		B1947
rw 		B1946
rw 		B1945
rw 		B1944
rw 		B1943
rw 		B1942
rw 		B1941
rw 		B1940
rw 		B1939
rw 		B1938
rw 		B1937
rw 		B1936
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1935
rw 		B1934
rw 		B1933
rw 		B1932
rw 		B1931
rw 		B1930
rw 		B1929
rw 		B1928
rw 		B1927
rw 		B1926
rw 		B1925
rw 		B1924
rw 		B1923
rw 		B1922
rw 		B1921
rw 		B1920
rw
Toggle fields

B1920

Bit 0: B1920.

B1921

Bit 1: B1921.

B1922

Bit 2: B1922.

B1923

Bit 3: B1923.

B1924

Bit 4: B1924.

B1925

Bit 5: B1925.

B1926

Bit 6: B1926.

B1927

Bit 7: B1927.

B1928

Bit 8: B1928.

B1929

Bit 9: B1929.

B1930

Bit 10: B1930.

B1931

Bit 11: B1931.

B1932

Bit 12: B1932.

B1933

Bit 13: B1933.

B1934

Bit 14: B1934.

B1935

Bit 15: B1935.

B1936

Bit 16: B1936.

B1937

Bit 17: B1937.

B1938

Bit 18: B1938.

B1939

Bit 19: B1939.

B1940

Bit 20: B1940.

B1941

Bit 21: B1941.

B1942

Bit 22: B1942.

B1943

Bit 23: B1943.

B1944

Bit 24: B1944.

B1945

Bit 25: B1945.

B1946

Bit 26: B1946.

B1947

Bit 27: B1947.

B1948

Bit 28: B1948.

B1949

Bit 29: B1949.

B1950

Bit 30: B1950.

B1951

Bit 31: B1951.

MPCBB2_VCTR61

MPCBBx vector register

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B1983
rw 		B1982
rw 		B1981
rw 		B1980
rw 		B1979
rw 		B1978
rw 		B1977
rw 		B1976
rw 		B1975
rw 		B1974
rw 		B1973
rw 		B1972
rw 		B1971
rw 		B1970
rw 		B1969
rw 		B1968
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1967
rw 		B1966
rw 		B1965
rw 		B1964
rw 		B1963
rw 		B1962
rw 		B1961
rw 		B1960
rw 		B1959
rw 		B1958
rw 		B1957
rw 		B1956
rw 		B1955
rw 		B1954
rw 		B1953
rw 		B1952
rw
Toggle fields

B1952

Bit 0: B1952.

B1953

Bit 1: B1953.

B1954

Bit 2: B1954.

B1955

Bit 3: B1955.

B1956

Bit 4: B1956.

B1957

Bit 5: B1957.

B1958

Bit 6: B1958.

B1959

Bit 7: B1959.

B1960

Bit 8: B1960.

B1961

Bit 9: B1961.

B1962

Bit 10: B1962.

B1963

Bit 11: B1963.

B1964

Bit 12: B1964.

B1965

Bit 13: B1965.

B1966

Bit 14: B1966.

B1967

Bit 15: B1967.

B1968

Bit 16: B1968.

B1969

Bit 17: B1969.

B1970

Bit 18: B1970.

B1971

Bit 19: B1971.

B1972

Bit 20: B1972.

B1973

Bit 21: B1973.

B1974

Bit 22: B1974.

B1975

Bit 23: B1975.

B1976

Bit 24: B1976.

B1977

Bit 25: B1977.

B1978

Bit 26: B1978.

B1979

Bit 27: B1979.

B1980

Bit 28: B1980.

B1981

Bit 29: B1981.

B1982

Bit 30: B1982.

B1983

Bit 31: B1983.

MPCBB2_VCTR62

MPCBBx vector register

Offset: 0x1f8, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B2015
rw 		B2014
rw 		B2013
rw 		B2012
rw 		B2011
rw 		B2010
rw 		B2009
rw 		B2008
rw 		B2007
rw 		B2006
rw 		B2005
rw 		B2004
rw 		B2003
rw 		B2002
rw 		B2001
rw 		B2000
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B1999
rw 		B1998
rw 		B1997
rw 		B1996
rw 		B1995
rw 		B1994
rw 		B1993
rw 		B1992
rw 		B1991
rw 		B1990
rw 		B1989
rw 		B1988
rw 		B1987
rw 		B1986
rw 		B1985
rw 		B1984
rw
Toggle fields

B1984

Bit 0: B1984.

B1985

Bit 1: B1985.

B1986

Bit 2: B1986.

B1987

Bit 3: B1987.

B1988

Bit 4: B1988.

B1989

Bit 5: B1989.

B1990

Bit 6: B1990.

B1991

Bit 7: B1991.

B1992

Bit 8: B1992.

B1993

Bit 9: B1993.

B1994

Bit 10: B1994.

B1995

Bit 11: B1995.

B1996

Bit 12: B1996.

B1997

Bit 13: B1997.

B1998

Bit 14: B1998.

B1999

Bit 15: B1999.

B2000

Bit 16: B2000.

B2001

Bit 17: B2001.

B2002

Bit 18: B2002.

B2003

Bit 19: B2003.

B2004

Bit 20: B2004.

B2005

Bit 21: B2005.

B2006

Bit 22: B2006.

B2007

Bit 23: B2007.

B2008

Bit 24: B2008.

B2009

Bit 25: B2009.

B2010

Bit 26: B2010.

B2011

Bit 27: B2011.

B2012

Bit 28: B2012.

B2013

Bit 29: B2013.

B2014

Bit 30: B2014.

B2015

Bit 31: B2015.

MPCBB2_VCTR63

MPCBBx vector register

Offset: 0x1fc, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B2047
rw 		B2046
rw 		B2045
rw 		B2044
rw 		B2043
rw 		B2042
rw 		B2041
rw 		B2040
rw 		B2039
rw 		B2038
rw 		B2037
rw 		B2036
rw 		B2035
rw 		B2034
rw 		B2033
rw 		B2032
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2031
rw 		B2030
rw 		B2029
rw 		B2028
rw 		B2027
rw 		B2026
rw 		B2025
rw 		B2024
rw 		B2023
rw 		B2022
rw 		B2021
rw 		B2020
rw 		B2019
rw 		B2018
rw 		B2017
rw 		B2016
rw
Toggle fields

B2016

Bit 0: B2016.

B2017

Bit 1: B2017.

B2018

Bit 2: B2018.

B2019

Bit 3: B2019.

B2020

Bit 4: B2020.

B2021

Bit 5: B2021.

B2022

Bit 6: B2022.

B2023

Bit 7: B2023.

B2024

Bit 8: B2024.

B2025

Bit 9: B2025.

B2026

Bit 10: B2026.

B2027

Bit 11: B2027.

B2028

Bit 12: B2028.

B2029

Bit 13: B2029.

B2030

Bit 14: B2030.

B2031

Bit 15: B2031.

B2032

Bit 16: B2032.

B2033

Bit 17: B2033.

B2034

Bit 18: B2034.

B2035

Bit 19: B2035.

B2036

Bit 20: B2036.

B2037

Bit 21: B2037.

B2038

Bit 22: B2038.

B2039

Bit 23: B2039.

B2040

Bit 24: B2040.

B2041

Bit 25: B2041.

B2042

Bit 26: B2042.

B2043

Bit 27: B2043.

B2044

Bit 28: B2044.

B2045

Bit 29: B2045.

B2046

Bit 30: B2046.

B2047

Bit 31: B2047.

SEC_GTZC_TZIC

0x50032800: GTZC_TZIC

32/210 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IER1
0x4 IER2
0x8 IER3
0x10 SR1
0x14 SR2
0x18 SR3
0x20 FCR1
0x24 FCR2
0x28 FCR3
Toggle registers

IER1

TZIC interrupt enable register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1IE
rw 		TIM1IE
rw 		COMPIE
rw 		VREFBUFIE
rw 		UCPD1IE
rw 		USBFSIE
rw 		FDCAN1IE
rw 		LPTIM3IE
rw 		LPTIM2IE
rw 		I2C4IE
rw 		LPUART1IE
rw 		LPTIM1IE
rw 		OPAMPIE
rw 		DACIE
rw 		CRSIE
rw 		I2C3IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2IE
rw 		I2C1IE
rw 		UART5IE
rw 		UART4IE
rw 		USART3IE
rw 		USART2IE
rw 		SPI3IE
rw 		SPI2IE
rw 		IWDGIE
rw 		WWDGIE
rw 		TIM7IE
rw 		TIM6IE
rw 		TIM5IE
rw 		TIM4IE
rw 		TIM3IE
rw 		TIM2IE
rw
Toggle fields

TIM2IE

Bit 0: TIM2IE.

TIM3IE

Bit 1: TIM3IE.

TIM4IE

Bit 2: TIM4IE.

TIM5IE

Bit 3: TIM5IE.

TIM6IE

Bit 4: TIM6IE.

TIM7IE

Bit 5: TIM7IE.

WWDGIE

Bit 6: WWDGIE.

IWDGIE

Bit 7: IWDGIE.

SPI2IE

Bit 8: SPI2IE.

SPI3IE

Bit 9: SPI3IE.

USART2IE

Bit 10: USART2IE.

USART3IE

Bit 11: USART3IE.

UART4IE

Bit 12: UART4IE.

UART5IE

Bit 13: UART5IE.

I2C1IE

Bit 14: I2C1IE.

I2C2IE

Bit 15: I2C2IE.

I2C3IE

Bit 16: I2C3IE.

CRSIE

Bit 17: CRSIE.

DACIE

Bit 18: DACIE.

OPAMPIE

Bit 19: OPAMPIE.

LPTIM1IE

Bit 20: LPTIM1IE.

LPUART1IE

Bit 21: LPUART1IE.

I2C4IE

Bit 22: I2C4IE.

LPTIM2IE

Bit 23: LPTIM2IE.

LPTIM3IE

Bit 24: LPTIM3IE.

FDCAN1IE

Bit 25: FDCAN1IE.

USBFSIE

Bit 26: USBFSIE.

UCPD1IE

Bit 27: UCPD1IE.

VREFBUFIE

Bit 28: VREFBUFIE.

COMPIE

Bit 29: COMPIE.

TIM1IE

Bit 30: TIM1IE.

SPI1IE

Bit 31: SPI1IE.

IER2

TZIC interrupt enable register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTFDEC1IE
rw 		EXTIIE
rw 		FLASH_REGIE
rw 		FLASHIE
rw 		RCCIE
rw 		DMAMUX1IE
rw 		DMA2IE
rw 		DMA1IE
rw 		SYSCFGIE
rw 		PWRIE
rw 		RTCIE
rw 		OCTOSPI1_REGIE
rw 		FMC_REGIE
rw 		SDMMC1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAIE
rw 		RNGIE
rw 		HASHIE
rw 		AESIE
rw 		ADCIE
rw 		ICACHEIE
rw 		TSCIE
rw 		CRCIE
rw 		DFSDM1IE
rw 		SAI2IE
rw 		SAI1IE
rw 		TIM17IE
rw 		TIM16IE
rw 		TIM15IE
rw 		USART1IE
rw 		TIM8IE
rw
Toggle fields

TIM8IE

Bit 0: TIM8IE.

USART1IE

Bit 1: USART1IE.

TIM15IE

Bit 2: TIM15IE.

TIM16IE

Bit 3: TIM16IE.

TIM17IE

Bit 4: TIM17IE.

SAI1IE

Bit 5: SAI1IE.

SAI2IE

Bit 6: SAI2IE.

DFSDM1IE

Bit 7: DFSDM1IE.

CRCIE

Bit 8: CRCIE.

TSCIE

Bit 9: TSCIE.

ICACHEIE

Bit 10: ICACHEIE.

ADCIE

Bit 11: ADCIE.

AESIE

Bit 12: AESIE.

HASHIE

Bit 13: HASHIE.

RNGIE

Bit 14: RNGIE.

PKAIE

Bit 15: PKAIE.

SDMMC1IE

Bit 16: SDMMC1IE.

FMC_REGIE

Bit 17: FMC_REGIE.

OCTOSPI1_REGIE

Bit 18: OCTOSPI1_REGIE.

RTCIE

Bit 19: RTCIE.

PWRIE

Bit 20: PWRIE.

SYSCFGIE

Bit 21: SYSCFGIE.

DMA1IE

Bit 22: DMA1IE.

DMA2IE

Bit 23: DMA2IE.

DMAMUX1IE

Bit 24: DMAMUX1IE.

RCCIE

Bit 25: RCCIE.

FLASHIE

Bit 26: FLASHIE.

FLASH_REGIE

Bit 27: FLASH_REGIE.

EXTIIE

Bit 28: EXTIIE.

OTFDEC1IE

Bit 29: OTFDEC1IE.

IER3

TZIC interrupt enable register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPCBB2_REGIE
rw 		MPCBB2IE
rw 		MPCBB1_REGIE
rw 		MPCBB1IE
rw 		MPCWM2IE
rw 		MPCWM1IE
rw 		TZICIE
rw 		TZSCIE
rw
Toggle fields

TZSCIE

Bit 0: TZSCIE.

TZICIE

Bit 1: TZICIE.

MPCWM1IE

Bit 2: MPCWM1IE.

MPCWM2IE

Bit 3: MPCWM2IE.

MPCBB1IE

Bit 4: MPCBB1IE.

MPCBB1_REGIE

Bit 5: MPCBB1_REGIE.

MPCBB2IE

Bit 6: MPCBB2IE.

MPCBB2_REGIE

Bit 7: MPCBB2_REGIE.

SR1

TZIC interrupt status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1F
r 		TIM1F
r 		COMPF
r 		VREFBUFF
r 		UCPD1F
r 		USBFSF
r 		FDCAN1F
r 		LPTIM3F
r 		LPTIM2F
r 		I2C4F
r 		LPUART1F
r 		LPTIM1F
r 		OPAMPF
r 		DACF
r 		CRSF
r 		I2C3F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2F
r 		I2C1F
r 		UART5F
r 		UART4F
r 		USART3F
r 		USART2F
r 		SPI3F
r 		SPI2F
r 		IWDGF
r 		WWDGF
r 		TIM7F
r 		TIM6F
r 		TIM5F
r 		TIM4F
r 		TIM3F
r 		TIM2F
r
Toggle fields

TIM2F

Bit 0: TIM2F.

TIM3F

Bit 1: TIM3F.

TIM4F

Bit 2: TIM4F.

TIM5F

Bit 3: TIM5F.

TIM6F

Bit 4: TIM6F.

TIM7F

Bit 5: TIM7F.

WWDGF

Bit 6: WWDGF.

IWDGF

Bit 7: IWDGF.

SPI2F

Bit 8: SPI2F.

SPI3F

Bit 9: SPI3F.

USART2F

Bit 10: USART2F.

USART3F

Bit 11: USART3F.

UART4F

Bit 12: UART4F.

UART5F

Bit 13: UART5F.

I2C1F

Bit 14: I2C1F.

I2C2F

Bit 15: I2C2F.

I2C3F

Bit 16: I2C3F.

CRSF

Bit 17: CRSF.

DACF

Bit 18: DACF.

OPAMPF

Bit 19: OPAMPF.

LPTIM1F

Bit 20: LPTIM1F.

LPUART1F

Bit 21: LPUART1F.

I2C4F

Bit 22: I2C4F.

LPTIM2F

Bit 23: LPTIM2F.

LPTIM3F

Bit 24: LPTIM3F.

FDCAN1F

Bit 25: FDCAN1F.

USBFSF

Bit 26: USBFSF.

UCPD1F

Bit 27: UCPD1F.

VREFBUFF

Bit 28: VREFBUFF.

COMPF

Bit 29: COMPF.

TIM1F

Bit 30: TIM1F.

SPI1F

Bit 31: SPI1F.

SR2

TZIC interrupt status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTFDEC1F
rw 		EXTIF
rw 		FLASH_REGF
rw 		FLASHF
rw 		RCCF
rw 		DMAMUX1F
rw 		DMA2F
rw 		DMA1F
rw 		SYSCFGF
rw 		PWRF
rw 		RTCF
rw 		OCTOSPI1_REGF
rw 		FMC_REGF
rw 		SDMMC1F
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAF
rw 		RNGF
rw 		HASHF
rw 		AESF
rw 		ADCF
rw 		ICACHEF
rw 		TSCF
rw 		CRCF
rw 		DFSDM1F
rw 		SAI2F
rw 		SAI1F
rw 		TIM17F
rw 		TIM16F
rw 		TIM15F
rw 		USART1F
rw 		TIM8F
rw
Toggle fields

TIM8F

Bit 0: TIM8F.

USART1F

Bit 1: USART1F.

TIM15F

Bit 2: TIM15F.

TIM16F

Bit 3: TIM16F.

TIM17F

Bit 4: TIM17F.

SAI1F

Bit 5: SAI1F.

SAI2F

Bit 6: SAI2F.

DFSDM1F

Bit 7: DFSDM1F.

CRCF

Bit 8: CRCF.

TSCF

Bit 9: TSCF.

ICACHEF

Bit 10: ICACHEF.

ADCF

Bit 11: ADCF.

AESF

Bit 12: AESF.

HASHF

Bit 13: HASHF.

RNGF

Bit 14: RNGF.

PKAF

Bit 15: PKAF.

SDMMC1F

Bit 16: SDMMC1F.

FMC_REGF

Bit 17: FMC_REGF.

OCTOSPI1_REGF

Bit 18: OCTOSPI1_REGF.

RTCF

Bit 19: RTCF.

PWRF

Bit 20: PWRF.

SYSCFGF

Bit 21: SYSCFGF.

DMA1F

Bit 22: DMA1F.

DMA2F

Bit 23: DMA2F.

DMAMUX1F

Bit 24: DMAMUX1F.

RCCF

Bit 25: RCCF.

FLASHF

Bit 26: FLASHF.

FLASH_REGF

Bit 27: FLASH_REGF.

EXTIF

Bit 28: EXTIF.

OTFDEC1F

Bit 29: OTFDEC1F.

SR3

TZIC interrupt status register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPCBB2_REGF
rw 		MPCBB2F
rw 		MPCBB1_REGF
rw 		MPCBB1F
rw 		MPCWM2F
rw 		MPCWM1F
rw 		TZICF
rw 		TZSCF
rw
Toggle fields

TZSCF

Bit 0: TZSCF.

TZICF

Bit 1: TZICF.

MPCWM1F

Bit 2: MPCWM1F.

MPCWM2F

Bit 3: MPCWM2F.

MPCBB1F

Bit 4: MPCBB1F.

MPCBB1_REGF

Bit 5: MPCBB1_REGF.

MPCBB2F

Bit 6: MPCBB2F.

MPCBB2_REGF

Bit 7: MPCBB2_REGF.

FCR1

TZIC interrupt clear register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1FC
w 		TIM1FC
w 		COMPFC
w 		VREFBUFFC
w 		UCPD1FC
w 		USBFSFC
w 		FDCAN1FC
w 		LPTIM3FC
w 		LPTIM2FC
w 		I2C4FC
w 		LPUART1FC
w 		LPTIM1FC
w 		OPAMPFC
w 		DACFC
w 		CRSFC
w 		I2C3FC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2FC
w 		I2C1FC
w 		UART5FC
w 		UART4FC
w 		USART3FC
w 		USART2FC
w 		SPI3FC
w 		SPI2FC
w 		IWDGFC
w 		WWDGFC
w 		TIM7FC
w 		TIM6FC
w 		TIM5FC
w 		TIM4FC
w 		TIM3FC
w 		TIM2FC
w
Toggle fields

TIM2FC

Bit 0: TIM2FC.

TIM3FC

Bit 1: TIM3FC.

TIM4FC

Bit 2: TIM4FC.

TIM5FC

Bit 3: TIM5FC.

TIM6FC

Bit 4: TIM6FC.

TIM7FC

Bit 5: TIM7FC.

WWDGFC

Bit 6: WWDGFC.

IWDGFC

Bit 7: IWDGFC.

SPI2FC

Bit 8: SPI2FC.

SPI3FC

Bit 9: SPI3FC.

USART2FC

Bit 10: USART2FC.

USART3FC

Bit 11: USART3FC.

UART4FC

Bit 12: UART4FC.

UART5FC

Bit 13: UART5FC.

I2C1FC

Bit 14: I2C1FC.

I2C2FC

Bit 15: I2C2FC.

I2C3FC

Bit 16: I2C3FC.

CRSFC

Bit 17: CRSFC.

DACFC

Bit 18: DACFC.

OPAMPFC

Bit 19: OPAMPFC.

LPTIM1FC

Bit 20: LPTIM1FC.

LPUART1FC

Bit 21: LPUART1FC.

I2C4FC

Bit 22: I2C4FC.

LPTIM2FC

Bit 23: LPTIM2FC.

LPTIM3FC

Bit 24: LPTIM3FC.

FDCAN1FC

Bit 25: FDCAN1FC.

USBFSFC

Bit 26: USBFSFC.

UCPD1FC

Bit 27: UCPD1FC.

VREFBUFFC

Bit 28: VREFBUFFC.

COMPFC

Bit 29: COMPFC.

TIM1FC

Bit 30: TIM1FC.

SPI1FC

Bit 31: SPI1FC.

FCR2

TZIC interrupt clear register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTFDEC1FC
rw 		EXTIFC
rw 		FLASH_REGFC
rw 		FLASHFC
rw 		RCCFC
rw 		DMAMUX1FC
rw 		DMA2FC
rw 		DMA1FC
rw 		SYSCFGFC
rw 		PWRFC
rw 		RTCFC
rw 		OCTOSPI1_REGFC
rw 		FMC_REGFC
rw 		SDMMC1FC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAFC
rw 		RNGFC
rw 		HASHFC
rw 		AESFC
rw 		ADCFC
rw 		ICACHEFC
rw 		TSCFC
rw 		CRCFC
rw 		DFSDM1FC
rw 		SAI2FC
rw 		SAI1FC
rw 		TIM17FC
rw 		TIM16FC
rw 		TIM15FC
rw 		USART1FC
rw 		TIM8FC
rw
Toggle fields

TIM8FC

Bit 0: TIM8FC.

USART1FC

Bit 1: USART1FC.

TIM15FC

Bit 2: TIM15FC.

TIM16FC

Bit 3: TIM16FC.

TIM17FC

Bit 4: TIM17FC.

SAI1FC

Bit 5: SAI1FC.

SAI2FC

Bit 6: SAI2FC.

DFSDM1FC

Bit 7: DFSDM1FC.

CRCFC

Bit 8: CRCFC.

TSCFC

Bit 9: TSCFC.

ICACHEFC

Bit 10: ICACHEFC.

ADCFC

Bit 11: ADCFC.

AESFC

Bit 12: AESFC.

HASHFC

Bit 13: HASHFC.

RNGFC

Bit 14: RNGFC.

PKAFC

Bit 15: PKAFC.

SDMMC1FC

Bit 16: SDMMC1FC.

FMC_REGFC

Bit 17: FMC_REGFC.

OCTOSPI1_REGFC

Bit 18: OCTOSPI1_REGFC.

RTCFC

Bit 19: RTCFC.

PWRFC

Bit 20: PWRFC.

SYSCFGFC

Bit 21: SYSCFGFC.

DMA1FC

Bit 22: DMA1FC.

DMA2FC

Bit 23: DMA2FC.

DMAMUX1FC

Bit 24: DMAMUX1FC.

RCCFC

Bit 25: RCCFC.

FLASHFC

Bit 26: FLASHFC.

FLASH_REGFC

Bit 27: FLASH_REGFC.

EXTIFC

Bit 28: EXTIFC.

OTFDEC1FC

Bit 29: OTFDEC1FC.

FCR3

TZIC interrupt clear register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPCBB2_REGFC
rw 		MPCBB2FC
rw 		MPCBB1_REGFC
rw 		MPCBB1FC
rw 		MPCWM2FC
rw 		MPCWM1FC
rw 		TZICFC
rw 		TZSCFC
rw
Toggle fields

TZSCFC

Bit 0: TZSCFC.

TZICFC

Bit 1: TZICFC.

MPCWM1FC

Bit 2: MPCWM1FC.

MPCWM2FC

Bit 3: MPCWM2FC.

MPCBB1FC

Bit 4: MPCBB1FC.

MPCBB1_REGFC

Bit 5: MPCBB1_REGFC.

MPCBB2FC

Bit 6: MPCBB2FC.

MPCBB2_REGFC

Bit 7: MPCBB2_REGFC.

SEC_GTZC_TZSC

0x50032400: GTZC_TZSC

0/113 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 SECCFGR1
0x14 SECCFGR2
0x20 PRIVCFGR1
0x24 PRIVCFGR2
0x30 MPCWM1_NSWMR1
0x34 MPCWM1_NSWMR2
0x38 MPCWM2_NSWMR1
0x3c MPCWM2_NSWMR2
0x40 MPCWM3_NSWMR1
Toggle registers

CR

TZSC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

SECCFGR1

TZSC secure configuration register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1SEC
rw 		TIM1SEC
rw 		COMPSEC
rw 		VREFBUFSEC
rw 		UCPD1SEC
rw 		USBFSSEC
rw 		FDCAN1SEC
rw 		LPTIM3SEC
rw 		LPTIM2SEC
rw 		I2C4SEC
rw 		LPUART1SEC
rw 		LPTIM1SEC
rw 		OPAMPSEC
rw 		DACSEC
rw 		CRSSEC
rw 		I2C3SEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEC
rw 		I2C1SEC
rw 		UART5SEC
rw 		UART4SEC
rw 		USART3SEC
rw 		USART2SEC
rw 		SPI3SEC
rw 		SPI2SEC
rw 		IWDGSEC
rw 		WWDGSEC
rw 		TIM7SEC
rw 		TIM6SEC
rw 		TIM5SEC
rw 		TIM4SEC
rw 		TIM3SEC
rw 		TIM2SEC
rw
Toggle fields

TIM2SEC

Bit 0: TIM2SEC.

TIM3SEC

Bit 1: TIM3SEC.

TIM4SEC

Bit 2: TIM4SEC.

TIM5SEC

Bit 3: TIM5SEC.

TIM6SEC

Bit 4: TIM6SEC.

TIM7SEC

Bit 5: TIM7SEC.

WWDGSEC

Bit 6: WWDGSEC.

IWDGSEC

Bit 7: IWDGSEC.

SPI2SEC

Bit 8: SPI2SEC.

SPI3SEC

Bit 9: SPI3SEC.

USART2SEC

Bit 10: USART2SEC.

USART3SEC

Bit 11: USART3SEC.

UART4SEC

Bit 12: UART4SEC.

UART5SEC

Bit 13: UART5SEC.

I2C1SEC

Bit 14: I2C1SEC.

I2C2SEC

Bit 15: I2C2SEC.

I2C3SEC

Bit 16: I2C3SEC.

CRSSEC

Bit 17: CRSSEC.

DACSEC

Bit 18: DACSEC.

OPAMPSEC

Bit 19: OPAMPSEC.

LPTIM1SEC

Bit 20: LPTIM1SEC.

LPUART1SEC

Bit 21: LPUART1SEC.

I2C4SEC

Bit 22: I2C4SEC.

LPTIM2SEC

Bit 23: LPTIM2SEC.

LPTIM3SEC

Bit 24: LPTIM3SEC.

FDCAN1SEC

Bit 25: FDCAN1SEC.

USBFSSEC

Bit 26: USBFSSEC.

UCPD1SEC

Bit 27: UCPD1SEC.

VREFBUFSEC

Bit 28: VREFBUFSEC.

COMPSEC

Bit 29: COMPSEC.

TIM1SEC

Bit 30: TIM1SEC.

SPI1SEC

Bit 31: SPI1SEC.

SECCFGR2

TZSC secure configuration register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OCTOSPI1_REGSEC
rw 		FSMC_REGSEC
rw 		SDMMC1SEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKASEC
rw 		RNGSEC
rw 		HASHSEC
rw 		AESSEC
rw 		ADCSEC
rw 		ICACHESEC
rw 		TSCSEC
rw 		CRCSEC
rw 		DFSDM1SEC
rw 		SAI2SEC
rw 		SAI1SEC
rw 		TIM17SEC
rw 		TIM16SEC
rw 		TIM15SEC
rw 		USART1SEC
rw 		TIM8SEC
rw
Toggle fields

TIM8SEC

Bit 0: TIM8SEC.

USART1SEC

Bit 1: USART1SEC.

TIM15SEC

Bit 2: TIM15SEC.

TIM16SEC

Bit 3: TIM16SEC.

TIM17SEC

Bit 4: TIM17SEC.

SAI1SEC

Bit 5: SAI1SEC.

SAI2SEC

Bit 6: SAI2SEC.

DFSDM1SEC

Bit 7: DFSDM1SEC.

CRCSEC

Bit 8: CRCSEC.

TSCSEC

Bit 9: TSCSEC.

ICACHESEC

Bit 10: ICACHESEC.

ADCSEC

Bit 11: ADCSEC.

AESSEC

Bit 12: AESSEC.

HASHSEC

Bit 13: HASHSEC.

RNGSEC

Bit 14: RNGSEC.

PKASEC

Bit 15: PKASEC.

SDMMC1SEC

Bit 16: SDMMC1SEC.

FSMC_REGSEC

Bit 17: FSMC_REGSEC.

OCTOSPI1_REGSEC

Bit 18: OCTOSPI1_REGSEC.

PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1PRIV
rw 		TIM1PRIV
rw 		COMPPRIV
rw 		VREFBUFPRIV
rw 		UCPD1PRIV
rw 		USBFSPRIV
rw 		FDCAN1PRIV
rw 		LPTIM3PRIV
rw 		LPTIM2PRIV
rw 		I2C4PRIV
rw 		LPUART1PRIV
rw 		LPTIM1PRIV
rw 		OPAMPPRIV
rw 		DACPRIV
rw 		CRSPRIV
rw 		I2C3PRIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2PRIV
rw 		I2C1PRIV
rw 		UART5PRIV
rw 		UART4PRIV
rw 		USART3PRIV
rw 		USART2PRIV
rw 		SPI3PRIV
rw 		SPI2PRIV
rw 		IWDGPRIV
rw 		WWDGPRIV
rw 		TIM7PRIV
rw 		TIM6PRIV
rw 		TIM5PRIV
rw 		TIM4PRIV
rw 		TIM3PRIV
rw 		TIM2PRIV
rw
Toggle fields

TIM2PRIV

Bit 0: TIM2PRIV.

TIM3PRIV

Bit 1: TIM3PRIV.

TIM4PRIV

Bit 2: TIM4PRIV.

TIM5PRIV

Bit 3: TIM5PRIV.

TIM6PRIV

Bit 4: TIM6PRIV.

TIM7PRIV

Bit 5: TIM7PRIV.

WWDGPRIV

Bit 6: WWDGPRIV.

IWDGPRIV

Bit 7: IWDGPRIV.

SPI2PRIV

Bit 8: SPI2PRIV.

SPI3PRIV

Bit 9: SPI3PRIV.

USART2PRIV

Bit 10: USART2PRIV.

USART3PRIV

Bit 11: USART3PRIV.

UART4PRIV

Bit 12: UART4PRIV.

UART5PRIV

Bit 13: UART5PRIV.

I2C1PRIV

Bit 14: I2C1PRIV.

I2C2PRIV

Bit 15: I2C2PRIV.

I2C3PRIV

Bit 16: I2C3PRIV.

CRSPRIV

Bit 17: CRSPRIV.

DACPRIV

Bit 18: DACPRIV.

OPAMPPRIV

Bit 19: OPAMPPRIV.

LPTIM1PRIV

Bit 20: LPTIM1PRIV.

LPUART1PRIV

Bit 21: LPUART1PRIV.

I2C4PRIV

Bit 22: I2C4PRIV.

LPTIM2PRIV

Bit 23: LPTIM2PRIV.

LPTIM3PRIV

Bit 24: LPTIM3PRIV.

FDCAN1PRIV

Bit 25: FDCAN1PRIV.

USBFSPRIV

Bit 26: USBFSPRIV.

UCPD1PRIV

Bit 27: UCPD1PRIV.

VREFBUFPRIV

Bit 28: VREFBUFPRIV.

COMPPRIV

Bit 29: COMPPRIV.

TIM1PRIV

Bit 30: TIM1PRIV.

SPI1PRIV

Bit 31: SPI1PRIV.

PRIVCFGR2

TZSC privilege configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OCTOSPI1_REGPRIV
rw 		FSMC_REGPRIV
rw 		SDMMC1PRIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PKAPRIV
rw 		RNGPRIV
rw 		HASHPRIV
rw 		AESPRIV
rw 		ADCPRIV
rw 		ICACHEPRIV
rw 		TSCPRIV
rw 		CRCPRIV
rw 		DFSDM1PRIV
rw 		SAI2PRIV
rw 		SAI1PRIV
rw 		TIM17PRIV
rw 		TIM16PRIV
rw 		TIM15PRIV
rw 		USART1PRIV
rw 		TIM8PRIV
rw
Toggle fields

TIM8PRIV

Bit 0: TIM8PRIV.

USART1PRIV

Bit 1: USART1PRIV.

TIM15PRIV

Bit 2: TIM15PRIV.

TIM16PRIV

Bit 3: TIM16PRIV.

TIM17PRIV

Bit 4: TIM17PRIV.

SAI1PRIV

Bit 5: SAI1PRIV.

SAI2PRIV

Bit 6: SAI2PRIV.

DFSDM1PRIV

Bit 7: DFSDM1PRIV.

CRCPRIV

Bit 8: CRCPRIV.

TSCPRIV

Bit 9: TSCPRIV.

ICACHEPRIV

Bit 10: ICACHEPRIV.

ADCPRIV

Bit 11: ADCPRIV.

AESPRIV

Bit 12: AESPRIV.

HASHPRIV

Bit 13: HASHPRIV.

RNGPRIV

Bit 14: RNGPRIV.

PKAPRIV

Bit 15: PKAPRIV.

SDMMC1PRIV

Bit 16: SDMMC1PRIV.

FSMC_REGPRIV

Bit 17: FSMC_REGPRIV.

OCTOSPI1_REGPRIV

Bit 18: OCTOSPI1_REGRIV.

MPCWM1_NSWMR1

TZSC external memory non-secure watermark register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM1LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM1STRT
rw
Toggle fields

NSWM1STRT

Bits 0-10: NSWM1STRT.

NSWM1LGTH

Bits 16-27: NSWM1LGTH.

MPCWM1_NSWMR2

TZSC external memory non-secure watermark register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

MPCWM2_NSWMR1

TZSC external memory non-secure watermark register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM1LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM1STRT
rw
Toggle fields

NSWM1STRT

Bits 0-10: NSWM1STRT.

NSWM1LGTH

Bits 16-27: NSWM1LGTH.

MPCWM2_NSWMR2

TZSC external memory non-secure watermark register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

MPCWM3_NSWMR1

TZSC external memory non-secure watermark register 2

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

SEC_HASH

0x520c0400: Hash processor

17/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HRA0
0x10 HRA1
0x14 HRA2
0x18 HRA3
0x1c HRA4
0x20 IMR
0x24 SR
0xf8 CSR0
0xfc CSR1
0x100 CSR2
0x104 CSR3
0x108 CSR4
0x10c CSR5
0x110 CSR6
0x114 CSR7
0x118 CSR8
0x11c CSR9
0x120 CSR10
0x124 CSR11
0x128 CSR12
0x12c CSR13
0x130 CSR14
0x134 CSR15
0x138 CSR16
0x13c CSR17
0x140 CSR18
0x144 CSR19
0x148 CSR20
0x14c CSR21
0x150 CSR22
0x154 CSR23
0x158 CSR24
0x15c CSR25
0x160 CSR26
0x164 CSR27
0x168 CSR28
0x16c CSR29
0x170 CSR30
0x174 CSR31
0x178 CSR32
0x17c CSR33
0x180 CSR34
0x184 CSR35
0x188 CSR36
0x18c CSR37
0x190 CSR38
0x194 CSR39
0x198 CSR40
0x19c CSR41
0x1a0 CSR42
0x1a4 CSR43
0x1a8 CSR44
0x1ac CSR45
0x1b0 CSR46
0x1b4 CSR47
0x1b8 CSR48
0x1bc CSR49
0x1c0 CSR50
0x1c4 CSR51
0x1c8 CSR52
0x1cc CSR53
0x310 HR0
0x314 HR1
0x318 HR2
0x31c HR3
0x320 HR4
0x324 HR5
0x328 HR6
0x32c HR7
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw 		LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAT
rw 		DINNE
r 		NBW
r 		ALGO0
rw 		MODE
rw 		DATATYPE
rw 		DMAE
rw 		INIT
w
Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

ALGO0

Bit 7: Algorithm selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO1

Bit 18: Algorithm selection.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
rw 		NBLW
rw
Toggle fields

NBLW

Bits 0-4: Number of valid bits in the last word of the message.

DCAL

Bit 8: Digest calculation.

HRA0

HASH aliased digest register 0

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HRA1

HASH aliased digest register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HRA2

HASH aliased digest register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HRA3

HASH aliased digest register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HRA4

HASH aliased digest register 4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

IMR

interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw 		DINIE
rw
Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		DMAS
r 		DCIS
rw 		DINIS
rw
Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

CSR0

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR0
rw
Toggle fields

CSR0

Bits 0-31: CSR0.

CSR1

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR1
rw
Toggle fields

CSR1

Bits 0-31: CSR1.

CSR2

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR2
rw
Toggle fields

CSR2

Bits 0-31: CSR2.

CSR3

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR3
rw
Toggle fields

CSR3

Bits 0-31: CSR3.

CSR4

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR4
rw
Toggle fields

CSR4

Bits 0-31: CSR4.

CSR5

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR5
rw
Toggle fields

CSR5

Bits 0-31: CSR5.

CSR6

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR6
rw
Toggle fields

CSR6

Bits 0-31: CSR6.

CSR7

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR7
rw
Toggle fields

CSR7

Bits 0-31: CSR7.

CSR8

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR8
rw
Toggle fields

CSR8

Bits 0-31: CSR8.

CSR9

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR9
rw
Toggle fields

CSR9

Bits 0-31: CSR9.

CSR10

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR10
rw
Toggle fields

CSR10

Bits 0-31: CSR10.

CSR11

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR11
rw
Toggle fields

CSR11

Bits 0-31: CSR11.

CSR12

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR12
rw
Toggle fields

CSR12

Bits 0-31: CSR12.

CSR13

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR13
rw
Toggle fields

CSR13

Bits 0-31: CSR13.

CSR14

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR14
rw
Toggle fields

CSR14

Bits 0-31: CSR14.

CSR15

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR15
rw
Toggle fields

CSR15

Bits 0-31: CSR15.

CSR16

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR16
rw
Toggle fields

CSR16

Bits 0-31: CSR16.

CSR17

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR17
rw
Toggle fields

CSR17

Bits 0-31: CSR17.

CSR18

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR18
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR18
rw
Toggle fields

CSR18

Bits 0-31: CSR18.

CSR19

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR19
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR19
rw
Toggle fields

CSR19

Bits 0-31: CSR19.

CSR20

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR20
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR20
rw
Toggle fields

CSR20

Bits 0-31: CSR20.

CSR21

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR21
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR21
rw
Toggle fields

CSR21

Bits 0-31: CSR21.

CSR22

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR22
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR22
rw
Toggle fields

CSR22

Bits 0-31: CSR22.

CSR23

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR23
rw
Toggle fields

CSR23

Bits 0-31: CSR23.

CSR24

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR24
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR24
rw
Toggle fields

CSR24

Bits 0-31: CSR24.

CSR25

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR25
rw
Toggle fields

CSR25

Bits 0-31: CSR25.

CSR26

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR26
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR26
rw
Toggle fields

CSR26

Bits 0-31: CSR26.

CSR27

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR27
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR27
rw
Toggle fields

CSR27

Bits 0-31: CSR27.

CSR28

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR28
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR28
rw
Toggle fields

CSR28

Bits 0-31: CSR28.

CSR29

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR29
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR29
rw
Toggle fields

CSR29

Bits 0-31: CSR29.

CSR30

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR30
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR30
rw
Toggle fields

CSR30

Bits 0-31: CSR30.

CSR31

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR31
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR31
rw
Toggle fields

CSR31

Bits 0-31: CSR31.

CSR32

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR32
rw
Toggle fields

CSR32

Bits 0-31: CSR32.

CSR33

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR33
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR33
rw
Toggle fields

CSR33

Bits 0-31: CSR33.

CSR34

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR34
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR34
rw
Toggle fields

CSR34

Bits 0-31: CSR34.

CSR35

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR35
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR35
rw
Toggle fields

CSR35

Bits 0-31: CSR35.

CSR36

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR36
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR36
rw
Toggle fields

CSR36

Bits 0-31: CSR36.

CSR37

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR37
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR37
rw
Toggle fields

CSR37

Bits 0-31: CSR37.

CSR38

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR38
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR38
rw
Toggle fields

CSR38

Bits 0-31: CSR38.

CSR39

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR39
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR39
rw
Toggle fields

CSR39

Bits 0-31: CSR39.

CSR40

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR40
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR40
rw
Toggle fields

CSR40

Bits 0-31: CSR40.

CSR41

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR41
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR41
rw
Toggle fields

CSR41

Bits 0-31: CSR41.

CSR42

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR42
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR42
rw
Toggle fields

CSR42

Bits 0-31: CSR42.

CSR43

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR43
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR43
rw
Toggle fields

CSR43

Bits 0-31: CSR43.

CSR44

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR44
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR44
rw
Toggle fields

CSR44

Bits 0-31: CSR44.

CSR45

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR45
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR45
rw
Toggle fields

CSR45

Bits 0-31: CSR45.

CSR46

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR46
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR46
rw
Toggle fields

CSR46

Bits 0-31: CSR46.

CSR47

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR47
rw
Toggle fields

CSR47

Bits 0-31: CSR47.

CSR48

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR48
rw
Toggle fields

CSR48

Bits 0-31: CSR48.

CSR49

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR49
rw
Toggle fields

CSR49

Bits 0-31: CSR49.

CSR50

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR50
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR50
rw
Toggle fields

CSR50

Bits 0-31: CSR50.

CSR51

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR51
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR51
rw
Toggle fields

CSR51

Bits 0-31: CSR51.

CSR52

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR52
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR52
rw
Toggle fields

CSR52

Bits 0-31: CSR52.

CSR53

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR53
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR53
rw
Toggle fields

CSR53

Bits 0-31: CSR53.

HR0

digest register 0

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HR1

digest register 1

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HR2

digest register 4

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HR3

digest register 3

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HR4

digest register 4

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

HR5

supplementary digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H5
r
Toggle fields

H5

Bits 0-31: H5.

HR6

supplementary digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H6
r
Toggle fields

H6

Bits 0-31: H6.

HR7

supplementary digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H7
r
Toggle fields

H7

Bits 0-31: H7.

SEC_I2C1

0x50005400: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

SEC_I2C2

0x50005800: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

SEC_I2C3

0x50005c00: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

SEC_I2C4

0x50008400: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

SEC_ICache

0x50030400: ICache

5/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 IER
0xc FCR
0x10 HMONR
0x14 MMONR
0x20 CRR[0]
0x24 CRR[1]
0x28 CRR[2]
0x2c CRR[3]
Toggle registers

CR

ICACHE control register

Offset: 0x0, size: 32, reset: 0x00000004, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISSMRST
rw 		HITMRST
rw 		MISSMEN
rw 		HITMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAYSEL
rw 		CACHEINV
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

CACHEINV

Bit 1: CACHEINV.

WAYSEL

Bit 2: WAYSEL.

HITMEN

Bit 16: HITMEN.

MISSMEN

Bit 17: MISSMEN.

HITMRST

Bit 18: HITMRST.

MISSMRST

Bit 19: MISSMRST.

SR

ICACHE status register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRF
r 		BSYENDF
r 		BUSYF
r
Toggle fields

BUSYF

Bit 0: BUSYF.

BSYENDF

Bit 1: BSYENDF.

ERRF

Bit 2: ERRF.

IER

ICACHE interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		BSYENDIE
rw
Toggle fields

BSYENDIE

Bit 1: BSYENDIE.

ERRIE

Bit 2: ERRIE.

FCR

ICACHE flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CERRF
w 		CBSYENDF
w
Toggle fields

CBSYENDF

Bit 1: CBSYENDF.

CERRF

Bit 2: CERRF.

HMONR

ICACHE hit monitor register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HITMON
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HITMON
r
Toggle fields

HITMON

Bits 0-31: HITMON.

MMONR

ICACHE miss monitor register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISSMON
r
Toggle fields

MISSMON

Bits 0-15: MISSMON.

CRR[0]

ICACHE region configuration register

Offset: 0x20, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw 		MSTSEL
rw 		REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw 		RSIZE
rw 		BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[1]

ICACHE region configuration register

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw 		MSTSEL
rw 		REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw 		RSIZE
rw 		BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[2]

ICACHE region configuration register

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw 		MSTSEL
rw 		REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw 		RSIZE
rw 		BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[3]

ICACHE region configuration register

Offset: 0x2c, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw 		MSTSEL
rw 		REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw 		RSIZE
rw 		BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

SEC_IWDG

0x50003000: Independent watchdog

3/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 KR
0x4 PR
0x8 RLR
0xc SR
0x10 WINR
Toggle registers

KR

Key register

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

SEC_LPTIM1

0x50007c00: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw 		RSTARE
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

SEC_LPTIM2

0x50009400: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw 		RSTARE
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

SEC_LPTIM3

0x50009800: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r 		UE
r 		DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKCF
w 		UECF
w 		DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw 		UEIE
rw 		DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw 		RSTARE
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw 		OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

SEC_LPUART1

0x50008000: Universal synchronous asynchronous receiver transmitter

22/85 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		STOP
rw 		ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

STOP

Bits 12-13: STOP bits.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		HDSEL
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

HDSEL

Bit 3: Half-duplex selection.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-19: BRR.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w
Toggle fields

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: TXFRQ.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r 		CTSIF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w 		TCCF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TCCF

Bit 6: Transmission complete clear flag.

CTSCF

Bit 9: CTS clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

SEC_OCTOSPI1

0x54021000: OctoSPI

0/96 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x8 DCR1
0xc DCR2
0x10 DCR3
0x14 DCR4
0x20 SR
0x24 FCR
0x40 DLR
0x48 AR
0x50 DR
0x80 PSMKR
0x88 PSMAR
0x90 PIR
0x100 CCR
0x108 TCR
0x110 IR
0x120 ABR
0x130 LPTR
0x140 WPCCR
0x148 WPTCR
0x150 WPIR
0x160 WPABR
0x180 WCCR
0x188 WTCR
0x190 WIR
0x1a0 WABR
0x200 HLCR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMODE
rw 		PMM
rw 		APMS
rw 		TOIE
rw 		SMIE
rw 		FTIE
rw 		TCIE
rw 		TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw 		FSEL
rw 		DQM
rw 		TCEN
rw 		DMAEN
rw 		ABORT
rw 		EN
rw
Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTYP
rw 		DEVSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw 		FRCK
rw 		CKMODE
rw
Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

CSHT

Bits 8-10: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-25: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRAPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSBOUND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CSBOUND

Bits 16-20: CS boundary.

DCR4

DCR4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
rw 		BUSY
rw 		TOF
rw 		SMF
rw 		FTF
rw 		TCF
rw 		TEF
rw
Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-13: FIFO level.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w 		CSMF
w 		CTCF
w 		CTEF
w
Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: Data length.

DLR

data length register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: ADDRESS.

AR

address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

DR

data register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: Status mask.

PSMKR

polling status mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: Status match.

PSMAR

polling status match register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: Polling interval.

PIR

polling interval register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw 		DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

CCR

communication configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw 		DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

TCR

timing configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

IR

instruction register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

ABR

alternate bytes register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

LPTR

low-power timeout register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WPCCR

write communication configuration register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw 		DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

WPTCR

write timing configuration register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WPIR

write instruction register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

WPABR

write alternate bytes register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACC
rw 		WZL
rw 		LM
rw
Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

WCCR

WCCR

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH
rw
Toggle fields

REFRESH

Bits 0-15: REFRESH.

WTCR

WTCR

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw 		DDTR
rw 		DMODE
rw 		ABSIZE
rw 		ABDTR
rw 		ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw 		ADDTR
rw 		ADMODE
rw 		ISIZE
rw 		IDTR
rw 		IMODE
rw
Toggle fields

IMODE

Bits 0-2: IMODE.

IDTR

Bit 3: IDTR.

ISIZE

Bits 4-5: ISIZE.

ADMODE

Bits 8-10: ADMODE.

ADDTR

Bit 11: ADDTR.

ADSIZE

Bits 12-13: ADSIZE.

ABMODE

Bits 16-18: ABMODE.

ABDTR

Bit 19: ABDTR.

ABSIZE

Bits 20-21: ABSIZE.

DMODE

Bits 24-26: DMODE.

DDTR

Bit 27: DDTR.

DQSE

Bit 29: DQSE.

WIR

WIR

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: DCYC.

WABR

WABR

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

HLCR

HyperBusTM latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

SEC_OPAMP

0x50007800: Operational amplifiers

0/29 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OPAMP1_CSR
0x4 OPAMP1_OTR
0x8 OPAMP1_LPOTR
0x10 OPAMP2_CRS
0x14 OPAMP2_OTR
0x18 OPAMP2_LPOTR
Toggle registers

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_RANGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw 		USERTRIM
rw 		CALSEL
rw 		CALON
rw 		VP_SEL
rw 		VM_SEL
rw 		PGA_GAIN
rw 		OPAMODE
rw 		OPALPM
rw 		OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: inverting input selection.

VP_SEL

Bit 10: non inverted input selection.

CALON

Bit 12: calibration mode enable.

CALSEL

Bit 13: calibration selection.

USERTRIM

Bit 14: User trimming enable.

CALOUT

Bit 15: Operational amplifier calibration output.

OPA_RANGE

Bit 31: Operational amplifier power supply range for stability.

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw 		TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_LPOTR

OPAMP1 offset trimming register in low-powe mode

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw 		TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_CRS

OPAMP2 control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw 		USERTRIM
rw 		CALSEL
rw 		CALON
rw 		VP_SEL
rw 		VM_SEL
rw 		PGA_GAIN
rw 		OPAMODE
rw 		OPALPM
rw 		OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: inverting input selection.

VP_SEL

Bit 10: non inverted input selection.

CALON

Bit 12: calibration mode enable.

CALSEL

Bit 13: calibration selection.

USERTRIM

Bit 14: User trimming enable.

CALOUT

Bit 15: Operational amplifier calibration output.

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw 		TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_LPOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw 		TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

SEC_PWR

0x50007000: Power control

17/322 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc CR4
0x10 SR1
0x14 SR2
0x18 SCR
0x20 PUCRA
0x24 PDCRA
0x28 PUCRB
0x2c PDCRB
0x30 PUCRC
0x34 PDCRC
0x38 PUCRD
0x3c PDCRD
0x40 PUCRE
0x44 PDCRE
0x48 PUCRF
0x4c PDCRF
0x50 PUCRG
0x54 PDCRG
0x58 PUCRH
0x5c PDCRH
0x78 SECCFGR
0x80 PRIVCFGR
Toggle registers

CR1

Power control register 1

Offset: 0x0, size: 32, reset: 0x00000400, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR
rw 		VOS
rw 		DBP
rw 		LPMS
rw
Toggle fields

LPMS

Bits 0-2: Low-power mode selection.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USV
rw 		IOSV
rw 		PVME4
rw 		PVME3
rw 		PVME2
rw 		PVME1
rw 		PLS
rw 		PVDE
rw
Toggle fields

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection.

PVME1

Bit 4: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V.

PVME2

Bit 5: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V.

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

PVME4

Bit 7: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V.

IOSV

Bit 9: VDDIO2 Independent I/Os supply valid.

USV

Bit 10: VDDUSB USB supply valid.

CR3

Power control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCPD_DBDIS
rw 		UCPD_STDBY
rw 		ULPMEN
rw 		APC
rw 		RRS
rw 		EWUP5
rw 		EWUP4
rw 		EWUP3
rw 		EWUP2
rw 		EWUP1
rw
Toggle fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable Wakeup pin WKUP5.

RRS

Bits 8-9: SRAM2 retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration.

ULPMEN

Bit 11: ULPMEN.

UCPD_STDBY

Bit 13: UCPD_STDBY.

UCPD_DBDIS

Bit 14: UCPD_DBDIS.

CR4

Power control register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSLPEN
rw 		SMPSFSTEN
rw 		EXTSMPSEN
rw 		SMPSBYP
rw 		VBRS
rw 		VBE
rw 		WUPP5
rw 		WUPP4
rw 		WUPP3
rw 		WUPP2
rw 		WUPP1
rw
Toggle fields

WUPP1

Bit 0: Wakeup pin WKUP1 polarity.

WUPP2

Bit 1: Wakeup pin WKUP2 polarity.

WUPP3

Bit 2: Wakeup pin WKUP3 polarity.

WUPP4

Bit 3: Wakeup pin WKUP4 polarity.

WUPP5

Bit 4: Wakeup pin WKUP5 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

SMPSBYP

Bit 12: SMPSBYP.

EXTSMPSEN

Bit 13: EXTSMPSEN.

SMPSFSTEN

Bit 14: SMPSFSTEN.

SMPSLPEN

Bit 15: SMPSLPEN.

SR1

Power status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSHPRDY
r 		EXTSMPSRDY
r 		SMPSBYPRDY
r 		SBF
r 		WUF5
r 		WUF4
r 		WUF3
r 		WUF2
r 		WUF1
r
Toggle fields

WUF1

Bit 0: Wakeup flag 1.

WUF2

Bit 1: Wakeup flag 2.

WUF3

Bit 2: Wakeup flag 3.

WUF4

Bit 3: Wakeup flag 4.

WUF5

Bit 4: Wakeup flag 5.

SBF

Bit 8: Standby flag.

SMPSBYPRDY

Bit 12: SMPSBYPRDY.

EXTSMPSRDY

Bit 13: EXTSMPSRDY.

SMPSHPRDY

Bit 15: SMPSHPRDY.

SR2

Power status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO4
r 		PVMO3
r 		PVMO2
r 		PVMO1
r 		PVDO
r 		VOSF
r 		REGLPF
r 		REGLPS
r
Toggle fields

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO1

Bit 12: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V.

PVMO2

Bit 13: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

PVMO4

Bit 15: Peripheral voltage monitoring output: VDDA vs. 2.2 V.

SCR

Power status clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSBF
w 		CWUF5
w 		CWUF4
w 		CWUF3
w 		CWUF2
w 		CWUF1
w
Toggle fields

CWUF1

Bit 0: Clear wakeup flag 1.

CWUF2

Bit 1: Clear wakeup flag 2.

CWUF3

Bit 2: Clear wakeup flag 3.

CWUF4

Bit 3: Clear wakeup flag 4.

CWUF5

Bit 4: Clear wakeup flag 5.

CSBF

Bit 8: Clear standby flag.

PUCRA

Power Port A pull-up control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU14

Bit 14: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD13

Bit 13: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PD15

Bit 15: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD4

Bit 4: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU7

Bit 7: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PU10

Bit 10: Port D pull-up bit y (y=0..15).

PU11

Bit 11: Port D pull-up bit y (y=0..15).

PU12

Bit 12: Port D pull-up bit y (y=0..15).

PU13

Bit 13: Port D pull-up bit y (y=0..15).

PU14

Bit 14: Port D pull-up bit y (y=0..15).

PU15

Bit 15: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD7

Bit 7: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PD10

Bit 10: Port D pull-down bit y (y=0..15).

PD11

Bit 11: Port D pull-down bit y (y=0..15).

PD12

Bit 12: Port D pull-down bit y (y=0..15).

PD13

Bit 13: Port D pull-down bit y (y=0..15).

PD14

Bit 14: Port D pull-down bit y (y=0..15).

PD15

Bit 15: Port D pull-down bit y (y=0..15).

PUCRE

Power Port E pull-up control register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port E pull-up bit y (y=0..15).

PU1

Bit 1: Port E pull-up bit y (y=0..15).

PU2

Bit 2: Port E pull-up bit y (y=0..15).

PU3

Bit 3: Port E pull-up bit y (y=0..15).

PU4

Bit 4: Port E pull-up bit y (y=0..15).

PU5

Bit 5: Port E pull-up bit y (y=0..15).

PU6

Bit 6: Port E pull-up bit y (y=0..15).

PU7

Bit 7: Port E pull-up bit y (y=0..15).

PU8

Bit 8: Port E pull-up bit y (y=0..15).

PU9

Bit 9: Port E pull-up bit y (y=0..15).

PU10

Bit 10: Port E pull-up bit y (y=0..15).

PU11

Bit 11: Port E pull-up bit y (y=0..15).

PU12

Bit 12: Port E pull-up bit y (y=0..15).

PU13

Bit 13: Port E pull-up bit y (y=0..15).

PU14

Bit 14: Port E pull-up bit y (y=0..15).

PU15

Bit 15: Port E pull-up bit y (y=0..15).

PDCRE

Power Port E pull-down control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port E pull-down bit y (y=0..15).

PD1

Bit 1: Port E pull-down bit y (y=0..15).

PD2

Bit 2: Port E pull-down bit y (y=0..15).

PD3

Bit 3: Port E pull-down bit y (y=0..15).

PD4

Bit 4: Port E pull-down bit y (y=0..15).

PD5

Bit 5: Port E pull-down bit y (y=0..15).

PD6

Bit 6: Port E pull-down bit y (y=0..15).

PD7

Bit 7: Port E pull-down bit y (y=0..15).

PD8

Bit 8: Port E pull-down bit y (y=0..15).

PD9

Bit 9: Port E pull-down bit y (y=0..15).

PD10

Bit 10: Port E pull-down bit y (y=0..15).

PD11

Bit 11: Port E pull-down bit y (y=0..15).

PD12

Bit 12: Port E pull-down bit y (y=0..15).

PD13

Bit 13: Port E pull-down bit y (y=0..15).

PD14

Bit 14: Port E pull-down bit y (y=0..15).

PD15

Bit 15: Port E pull-down bit y (y=0..15).

PUCRF

Power Port F pull-up control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port F pull-up bit y (y=0..15).

PU1

Bit 1: Port F pull-up bit y (y=0..15).

PU2

Bit 2: Port F pull-up bit y (y=0..15).

PU3

Bit 3: Port F pull-up bit y (y=0..15).

PU4

Bit 4: Port F pull-up bit y (y=0..15).

PU5

Bit 5: Port F pull-up bit y (y=0..15).

PU6

Bit 6: Port F pull-up bit y (y=0..15).

PU7

Bit 7: Port F pull-up bit y (y=0..15).

PU8

Bit 8: Port F pull-up bit y (y=0..15).

PU9

Bit 9: Port F pull-up bit y (y=0..15).

PU10

Bit 10: Port F pull-up bit y (y=0..15).

PU11

Bit 11: Port F pull-up bit y (y=0..15).

PU12

Bit 12: Port F pull-up bit y (y=0..15).

PU13

Bit 13: Port F pull-up bit y (y=0..15).

PU14

Bit 14: Port F pull-up bit y (y=0..15).

PU15

Bit 15: Port F pull-up bit y (y=0..15).

PDCRF

Power Port F pull-down control register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port F pull-down bit y (y=0..15).

PD1

Bit 1: Port F pull-down bit y (y=0..15).

PD2

Bit 2: Port F pull-down bit y (y=0..15).

PD3

Bit 3: Port F pull-down bit y (y=0..15).

PD4

Bit 4: Port F pull-down bit y (y=0..15).

PD5

Bit 5: Port F pull-down bit y (y=0..15).

PD6

Bit 6: Port F pull-down bit y (y=0..15).

PD7

Bit 7: Port F pull-down bit y (y=0..15).

PD8

Bit 8: Port F pull-down bit y (y=0..15).

PD9

Bit 9: Port F pull-down bit y (y=0..15).

PD10

Bit 10: Port F pull-down bit y (y=0..15).

PD11

Bit 11: Port F pull-down bit y (y=0..15).

PD12

Bit 12: Port F pull-down bit y (y=0..15).

PD13

Bit 13: Port F pull-down bit y (y=0..15).

PD14

Bit 14: Port F pull-down bit y (y=0..15).

PD15

Bit 15: Port F pull-down bit y (y=0..15).

PUCRG

Power Port G pull-up control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRG

Power Port G pull-down control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw 		PU14
rw 		PU13
rw 		PU12
rw 		PU11
rw 		PU10
rw 		PU9
rw 		PU8
rw 		PU7
rw 		PU6
rw 		PU5
rw 		PU4
rw 		PU3
rw 		PU2
rw 		PU1
rw 		PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRH

Power Port H pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

SECCFGR

Power secure configuration register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APCSEC
rw 		VBSEC
rw 		VDMSEC
rw 		LPMSEC
rw 		WUP5SEC
rw 		WUP4SEC
rw 		WUP3SEC
rw 		WUP2SEC
rw 		WUP1SEC
rw
Toggle fields

WUP1SEC

Bit 0: WKUP1 pin security.

WUP2SEC

Bit 1: WKUP2 pin security.

WUP3SEC

Bit 2: WKUP3 pin security.

WUP4SEC

Bit 3: WKUP4 pin security.

WUP5SEC

Bit 4: WKUP5 pin security.

LPMSEC

Bit 8: LPMSEC.

VDMSEC

Bit 9: VDMSEC.

VBSEC

Bit 10: VBSEC.

APCSEC

Bit 11: APCSEC.

PRIVCFGR

Power privilege configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
Toggle fields

PRIV

Bit 0: PRIV.

SEC_RCC

0x50021000: Reset and clock control

245/421 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ICSCR
0x8 CFGR
0xc PLLCFGR
0x10 PLLSAI1CFGR
0x14 PLLSAI2CFGR
0x18 CIER
0x1c CIFR
0x20 CICR
0x28 AHB1RSTR
0x2c AHB2RSTR
0x30 AHB3RSTR
0x38 APB1RSTR1
0x3c APB1RSTR2
0x40 APB2RSTR
0x48 AHB1ENR
0x4c AHB2ENR
0x50 AHB3ENR
0x58 APB1ENR1
0x5c APB1ENR2
0x60 APB2ENR
0x68 AHB1SMENR
0x6c AHB2SMENR
0x70 AHB3SMENR
0x78 APB1SMENR1
0x7c APB1SMENR2
0x80 APB2SMENR
0x88 CCIPR1
0x90 BDCR
0x94 CSR
0x98 CRRCR
0x9c CCIPR2
0xb8 SECCFGR
0xbc SECSR
0xe8 AHB1SECSR
0xec AHB2SECSR
0xf0 AHB3SECSR
0xf8 APB1SECSR1
0xfc APB1SECSR2
0x100 APB2SECSR
Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000063, access: Unspecified

11/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw 		PLLSAI2RDY
r 		PLLSAI2ON
rw 		PLLSAI1RDY
r 		PLLSAI1ON
rw 		PLLRDY
r 		PLLON
rw 		CSSON
w 		HSEBYP
rw 		HSERDY
r 		HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIASFS
rw 		HSIRDY
r 		HSIKERON
rw 		HSION
rw 		MSIRANGE
rw 		MSIRGSEL
w 		MSIPLLEN
rw 		MSIRDY
r 		MSION
rw
Toggle fields

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRGSEL

Bit 3: MSI clock range selection.

MSIRANGE

Bits 4-7: MSI clock ranges.

HSION

Bit 8: HSI clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIKERON

Bit 9: HSI always enable for peripheral kernels.

HSIRDY

Bit 10: HSI clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSIASFS

Bit 11: HSI automatic start from Stop.

HSEON

Bit 16: HSE clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: HSE clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: HSE crystal oscillator bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock security system enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: Main PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: Main PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLSAI1ON

Bit 26: SAI1 PLL enable.

PLLSAI1RDY

Bit 27: SAI1 PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLSAI2ON

Bit 28: SAI2 PLL enable.

PLLSAI2RDY

Bit 29: SAI2 PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PRIV

Bit 31: PRIV.

ICSCR

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x40000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw 		HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM
rw 		MSICAL
r
Toggle fields

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI clock calibration.

HSITRIM

Bits 24-30: HSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
r 		MCOSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK
rw 		PPRE2
rw 		PPRE1
rw 		HPRE
rw 		SWS
r 		SW
rw
Toggle fields

SW

Bits 0-1: System clock switch.

Allowed values:
0: MSI: MSI selected as system clock
1: HSI: HSI selected as system clock
2: HSE: HSE selected as system clock
3: PLL: PLL selected as system clock

SWS

Bits 2-3: System clock switch status.

Allowed values:
0: MSI: MSI oscillator used as system clock
1: HSI: HSI oscillator used as system clock
2: HSE: HSE used as system clock
3: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
0: Div1: SYSCLK not divided
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512

PPRE1

Bits 8-10: PB low-speed prescaler (APB1).

Allowed values:
0: Div1: HCLK not divided
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

Allowed values:
0: Div1: HCLK not divided
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

Allowed values:
0: MSI: MSI oscillator selected as wakeup from stop clock and CSS backup clock
1: HSI: HSI oscillator selected as wakeup from stop clock and CSS backup clock

MCOSEL

Bits 24-27: Microcontroller clock output.

Allowed values:
0: None: MCO output disabled, no clock on MCO
1: SYSCLK: SYSCLK system clock selected
2: MSI: MSI clock selected
3: HSI: HSI clock selected
4: HSE: HSE clock selected
5: PLL: Main PLL clock selected
6: LSI: LSI clock selected
7: LSE: LSE clock selected
8: HSI48: Internal HSI48 clock selected

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

Allowed values:
0: Div1: MCO divided by 1
1: Div2: MCO divided by 2
2: Div4: MCO divided by 4
3: Div8: MCO divided by 8
4: Div16: MCO divided by 16

PLLCFGR

PLL configuration register

Offset: 0xc, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPDIV
rw 		PLLR
rw 		PLLREN
rw 		PLLQ
rw 		PLLQEN
rw 		PLLP
rw 		PLLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw 		PLLM
rw 		PLLSRC
rw
Toggle fields

PLLSRC

Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.

PLLM

Bits 4-7: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.

PLLN

Bits 8-14: Main PLL multiplication factor for VCO.

PLLPEN

Bit 16: Main PLL PLLSAI3CLK output enable.

PLLP

Bit 17: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).

PLLQEN

Bit 20: Main PLL PLLUSB1CLK output enable.

PLLQ

Bits 21-22: Main PLL division factor for PLLUSB1CLK(48 MHz clock).

PLLREN

Bit 24: Main PLL PLLCLK output enable.

PLLR

Bits 25-26: Main PLL division factor for PLLCLK (system clock).

PLLPDIV

Bits 27-31: Main PLL division factor for PLLSAI2CLK.

PLLSAI1CFGR

PLLSAI1 configuration register

Offset: 0x10, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI1PDIV
rw 		PLLSAI1R
rw 		PLLSAI1REN
rw 		PLLSAI1Q
rw 		PLLSAI1QEN
rw 		PLLSAI1P
rw 		PLLSAI1PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI1N
rw 		PLLSAI1M
rw 		PLLSAI1SRC
rw
Toggle fields

PLLSAI1SRC

Bits 0-1: PLLSAI1SRC.

PLLSAI1M

Bits 4-7: Division factor for PLLSAI1 input clock.

PLLSAI1N

Bits 8-14: SAI1PLL multiplication factor for VCO.

PLLSAI1PEN

Bit 16: SAI1PLL PLLSAI1CLK output enable.

PLLSAI1P

Bit 17: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).

PLLSAI1QEN

Bit 20: SAI1PLL PLLUSB2CLK output enable.

PLLSAI1Q

Bits 21-22: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock).

PLLSAI1REN

Bit 24: PLLSAI1 PLLADC1CLK output enable.

PLLSAI1R

Bits 25-26: PLLSAI1 division factor for PLLADC1CLK (ADC clock).

PLLSAI1PDIV

Bits 27-31: PLLSAI1 division factor for PLLSAI1CLK.

PLLSAI2CFGR

PLLSAI2 configuration register

Offset: 0x14, size: 32, reset: 0x00001000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI2PDIV
rw 		PLLSAI2P
rw 		PLLSAI2PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI2N
rw 		PLLSAI2M
rw 		PLLSAI2SRC
rw
Toggle fields

PLLSAI2SRC

Bits 0-1: PLLSAI2SRC.

PLLSAI2M

Bits 4-7: Division factor for PLLSAI2 input clock.

PLLSAI2N

Bits 8-14: SAI2PLL multiplication factor for VCO.

PLLSAI2PEN

Bit 16: SAI2PLL PLLSAI2CLK output enable.

PLLSAI2P

Bit 17: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock).

PLLSAI2PDIV

Bits 27-31: PLLSAI2 division factor for PLLSAI2CLK.

CIER

Clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYIE
rw 		LSECSSIE
rw 		PLLSAI2RDYIE
rw 		PLLSAI1RDYIE
rw 		PLLRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		MSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw
Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLRDYIE

Bit 5: PLL ready interrupt enable.

PLLSAI1RDYIE

Bit 6: PLLSAI1 ready interrupt enable.

PLLSAI2RDYIE

Bit 7: PLLSAI2 ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

HSI48RDYIE

Bit 10: HSI48 ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYF
r 		LSECSSF
r 		CSSF
r 		PLLSAI2RDYF
r 		PLLSAI1RDYF
r 		PLLRDYF
r 		HSERDYF
r 		HSIRDYF
r 		MSIRDYF
r 		LSERDYF
r 		LSIRDYF
r
Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

PLLSAI1RDYF

Bit 6: PLLSAI1 ready interrupt flag.

PLLSAI2RDYF

Bit 7: PLLSAI2 ready interrupt flag.

CSSF

Bit 8: Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

HSI48RDYF

Bit 10: HSI48 ready interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYC
w 		LSECSSC
w 		CSSC
w 		PLLSAI2RDYC
w 		PLLSAI1RDYC
w 		PLLRDYC
w 		HSERDYC
w 		HSIRDYC
w 		MSIRDYC
w 		LSERDYC
w 		LSIRDYC
w
Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

PLLSAI1RDYC

Bit 6: PLLSAI1 ready interrupt clear.

PLLSAI2RDYC

Bit 7: PLLSAI2 ready interrupt clear.

CSSC

Bit 8: Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

HSI48RDYC

Bit 10: HSI48 oscillator ready interrupt clear.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GTZCRST
rw 		TSCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw 		FLASHRST
rw 		DMAMUX1RST
rw 		DMA2RST
rw 		DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1 reset.

Allowed values:
1: Reset: Reset the selected module

DMA2RST

Bit 1: DMA2 reset.

Allowed values:
1: Reset: Reset the selected module

DMAMUX1RST

Bit 2: DMAMUXRST.

Allowed values:
1: Reset: Reset the selected module

FLASHRST

Bit 8: Flash memory interface reset.

Allowed values:
1: Reset: Reset the selected module

CRCRST

Bit 12: CRC reset.

Allowed values:
1: Reset: Reset the selected module

TSCRST

Bit 16: Touch Sensing Controller reset.

Allowed values:
1: Reset: Reset the selected module

GTZCRST

Bit 22: GTZC reset.

Allowed values:
1: Reset: Reset the selected module

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1RST
rw 		OTFDEC1RST
rw 		PKARST
rw 		RNGRST
rw 		HASHRST
rw 		AESRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCRST
rw 		GPIOHRST
rw 		GPIOGRST
rw 		GPIOFRST
rw 		GPIOERST
rw 		GPIODRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: IO port A reset.

Allowed values:
1: Reset: Reset the selected module

GPIOBRST

Bit 1: IO port B reset.

Allowed values:
1: Reset: Reset the selected module

GPIOCRST

Bit 2: IO port C reset.

Allowed values:
1: Reset: Reset the selected module

GPIODRST

Bit 3: IO port D reset.

Allowed values:
1: Reset: Reset the selected module

GPIOERST

Bit 4: IO port E reset.

Allowed values:
1: Reset: Reset the selected module

GPIOFRST

Bit 5: IO port F reset.

Allowed values:
1: Reset: Reset the selected module

GPIOGRST

Bit 6: IO port G reset.

Allowed values:
1: Reset: Reset the selected module

GPIOHRST

Bit 7: IO port H reset.

Allowed values:
1: Reset: Reset the selected module

ADCRST

Bit 13: ADC reset.

Allowed values:
1: Reset: Reset the selected module

AESRST

Bit 16: AES hardware accelerator reset.

Allowed values:
1: Reset: Reset the selected module

HASHRST

Bit 17: Hash reset.

Allowed values:
1: Reset: Reset the selected module

RNGRST

Bit 18: Random number generator reset.

Allowed values:
1: Reset: Reset the selected module

PKARST

Bit 19: PKARST.

Allowed values:
1: Reset: Reset the selected module

OTFDEC1RST

Bit 21: OTFDEC1RST.

Allowed values:
1: Reset: Reset the selected module

SDMMC1RST

Bit 22: SDMMC1 reset.

Allowed values:
1: Reset: Reset the selected module

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1RST
rw 		FMCRST
rw
Toggle fields

FMCRST

Bit 0: Flexible memory controller reset.

Allowed values:
1: Reset: Reset the selected module

OSPI1RST

Bit 8: OSPI1RST.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1RST
rw 		OPAMPRST
rw 		DAC1RST
rw 		PWRRST
rw 		CRSRST
rw 		I2C3RST
rw 		I2C2RST
rw 		I2C1RST
rw 		UART5RST
rw 		UART4RST
rw 		USART3RST
rw 		USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw 		SPI2RST
rw 		TIM7RST
rw 		TIM6RST
rw 		TIM5RST
rw 		TIM4RST
rw 		TIM3RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: TIM3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: TIM3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: TIM5 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: TIM6 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: TIM7 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI2 reset.

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI3 reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART2 reset.

Allowed values:
1: Reset: Reset the selected module

USART3RST

Bit 18: USART3 reset.

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 19: UART4 reset.

Allowed values:
1: Reset: Reset the selected module

UART5RST

Bit 20: UART5 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C2 reset.

Allowed values:
1: Reset: Reset the selected module

I2C3RST

Bit 23: I2C3 reset.

Allowed values:
1: Reset: Reset the selected module

CRSRST

Bit 24: CRS reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

DAC1RST

Bit 29: DAC1 interface reset.

Allowed values:
1: Reset: Reset the selected module

OPAMPRST

Bit 30: OPAMP interface reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1RST
rw 		USBFSRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1RST
rw 		LPTIM3RST
rw 		LPTIM2RST
rw 		I2C4RST
rw 		LPUART1RST
rw
Toggle fields

LPUART1RST

Bit 0: Low-power UART 1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C4RST

Bit 1: I2C4 reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM2RST

Bit 5: Low-power timer 2 reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM3RST

Bit 6: LPTIM3RST.

Allowed values:
1: Reset: Reset the selected module

FDCAN1RST

Bit 9: FDCAN1RST.

Allowed values:
1: Reset: Reset the selected module

USBFSRST

Bit 21: USBFSRST.

Allowed values:
1: Reset: Reset the selected module

UCPD1RST

Bit 23: UCPD1RST.

Allowed values:
1: Reset: Reset the selected module

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1RST
rw 		SAI2RST
rw 		SAI1RST
rw 		TIM17RST
rw 		TIM16RST
rw 		TIM15RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		TIM8RST
rw 		SPI1RST
rw 		TIM1RST
rw 		SYSCFGRST
rw
Toggle fields

SYSCFGRST

Bit 0: System configuration (SYSCFG) reset.

Allowed values:
1: Reset: Reset the selected module

TIM1RST

Bit 11: TIM1 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM8RST

Bit 13: TIM8 timer reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 14: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM15RST

Bit 16: TIM15 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM16RST

Bit 17: TIM16 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM17RST

Bit 18: TIM17 timer reset.

Allowed values:
1: Reset: Reset the selected module

SAI1RST

Bit 21: Serial audio interface 1 (SAI1) reset.

Allowed values:
1: Reset: Reset the selected module

SAI2RST

Bit 22: Serial audio interface 2 (SAI2) reset.

Allowed values:
1: Reset: Reset the selected module

DFSDM1RST

Bit 24: Digital filters for sigma-delata modulators (DFSDM) reset.

Allowed values:
1: Reset: Reset the selected module

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, size: 32, reset: 0x00000100, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GTZCEN
rw 		TSCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		FLASHEN
rw 		DMAMUX1EN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 1: DMA2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMAMUX1EN

Bit 2: DMAMUX clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FLASHEN

Bit 8: Flash memory interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 12: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TSCEN

Bit 16: Touch Sensing Controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GTZCEN

Bit 22: GTZCEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1EN
rw 		OTFDEC1EN
rw 		PKAEN
rw 		RNGEN
rw 		HASHEN
rw 		AESEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCEN
rw 		GPIOHEN
rw 		GPIOGEN
rw 		GPIOFEN
rw 		GPIOEEN
rw 		GPIODEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: IO port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOBEN

Bit 1: IO port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOCEN

Bit 2: IO port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIODEN

Bit 3: IO port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOEEN

Bit 4: IO port E clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOFEN

Bit 5: IO port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOGEN

Bit 6: IO port G clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOHEN

Bit 7: IO port H clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADCEN

Bit 13: ADC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AESEN

Bit 16: AES accelerator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

HASHEN

Bit 17: HASH clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RNGEN

Bit 18: Random Number Generator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PKAEN

Bit 19: PKAEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTFDEC1EN

Bit 21: OTFDEC1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDMMC1EN

Bit 22: SDMMC1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1EN
rw 		FMCEN
rw
Toggle fields

FMCEN

Bit 0: Flexible memory controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OSPI1EN

Bit 8: OSPI1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR1

APB1ENR1

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw 		OPAMPEN
rw 		DAC1EN
rw 		PWREN
rw 		CRSEN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		UART5EN
rw 		UART4EN
rw 		USART3EN
rw 		USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP3EN
rw 		SPI2EN
rw 		WWDGEN
rw 		RTCAPBEN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: TIM3 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: TIM4 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: TIM5 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: TIM6 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: TIM7 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RTCAPBEN

Bit 10: RTC APB clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SP3EN

Bit 15: SPI3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 19: UART4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART5EN

Bit 20: UART5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C3EN

Bit 23: I2C3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRSEN

Bit 24: Clock Recovery System clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DAC1EN

Bit 29: DAC1 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OPAMPEN

Bit 30: OPAMP interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM1EN

Bit 31: Low power timer 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1EN
rw 		USBFSEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1EN
rw 		LPTIM3EN
rw 		LPTIM2EN
rw 		I2C4EN
rw 		LPUART1EN
rw
Toggle fields

LPUART1EN

Bit 0: Low power UART 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C4EN

Bit 1: I2C4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM2EN

Bit 5: LPTIM2EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM3EN

Bit 6: LPTIM3EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FDCAN1EN

Bit 9: FDCAN1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USBFSEN

Bit 21: USBFSEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UCPD1EN

Bit 23: UCPD1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2ENR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1EN
rw 		SAI2EN
rw 		SAI1EN
rw 		TIM17EN
rw 		TIM16EN
rw 		TIM15EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw 		TIM8EN
rw 		SPI1EN
rw 		TIM1EN
rw 		SYSCFGEN
rw
Toggle fields

SYSCFGEN

Bit 0: SYSCFG clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM1EN

Bit 11: TIM1 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM8EN

Bit 13: TIM8 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 14: USART1clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM15EN

Bit 16: TIM15 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM16EN

Bit 17: TIM16 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM17EN

Bit 18: TIM17 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI1EN

Bit 21: SAI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI2EN

Bit 22: SAI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DFSDM1EN

Bit 24: DFSDM timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x68, size: 32, reset: 0x00C11307, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESMEN
rw 		GTZCSMEN
rw 		TSCSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw 		SRAM1SMEN
rw 		FLASHSMEN
rw 		DMAMUX1SMEN
rw 		DMA2SMEN
rw 		DMA1SMEN
rw
Toggle fields

DMA1SMEN

Bit 0: DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: DMA2 clocks enable during Sleep and Stop modes.

DMAMUX1SMEN

Bit 2: DMAMUX clock enable during Sleep and Stop modes.

FLASHSMEN

Bit 8: Flash memory interface clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: SRAM1 interface clocks enable during Sleep and Stop modes.

CRCSMEN

Bit 12: CRCSMEN.

TSCSMEN

Bit 16: Touch Sensing Controller clocks enable during Sleep and Stop modes.

GTZCSMEN

Bit 22: GTZCSMEN.

ICACHESMEN

Bit 23: ICACHESMEN.

AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x6c, size: 32, reset: 0x006F22FF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SMEN
rw 		OTFDEC1SMEN
rw 		PKASMEN
rw 		RNGSMEN
rw 		HASHSMEN
rw 		AESSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCFSSMEN
rw 		SRAM2SMEN
rw 		GPIOHSMEN
rw 		GPIOGSMEN
rw 		GPIOFSMEN
rw 		GPIOESMEN
rw 		GPIODSMEN
rw 		GPIOCSMEN
rw 		GPIOBSMEN
rw 		GPIOASMEN
rw
Toggle fields

GPIOASMEN

Bit 0: IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: IO port E clocks enable during Sleep and Stop modes.

GPIOFSMEN

Bit 5: IO port F clocks enable during Sleep and Stop modes.

GPIOGSMEN

Bit 6: IO port G clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: IO port H clocks enable during Sleep and Stop modes.

SRAM2SMEN

Bit 9: SRAM2 interface clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: ADC clocks enable during Sleep and Stop modes.

AESSMEN

Bit 16: AES accelerator clocks enable during Sleep and Stop modes.

HASHSMEN

Bit 17: HASH clock enable during Sleep and Stop modes.

RNGSMEN

Bit 18: Random Number Generator clocks enable during Sleep and Stop modes.

PKASMEN

Bit 19: PKASMEN.

OTFDEC1SMEN

Bit 21: OTFDEC1SMEN.

SDMMC1SMEN

Bit 22: SDMMC1 clocks enable during Sleep and Stop modes.

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, size: 32, reset: 0x00000101, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SMEN
rw 		FMCSMEN
rw
Toggle fields

FMCSMEN

Bit 0: Flexible memory controller clocks enable during Sleep and Stop modes.

OSPI1SMEN

Bit 8: OSPI1SMEN.

APB1SMENR1

APB1SMENR1

Offset: 0x78, size: 32, reset: 0xF1FECC3F, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SMEN
rw 		OPAMPSMEN
rw 		DAC1SMEN
rw 		PWRSMEN
rw 		CRSSMEN
rw 		I2C3SMEN
rw 		I2C2SMEN
rw 		I2C1SMEN
rw 		UART5SMEN
rw 		UART4SMEN
rw 		USART3SMEN
rw 		USART2SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP3SMEN
rw 		SPI2SMEN
rw 		WWDGSMEN
rw 		RTCAPBSMEN
rw 		TIM7SMEN
rw 		TIM6SMEN
rw 		TIM5SMEN
rw 		TIM4SMEN
rw 		TIM3SMEN
rw 		TIM2SMEN
rw
Toggle fields

TIM2SMEN

Bit 0: TIM2 timer clocks enable during Sleep and Stop modes.

TIM3SMEN

Bit 1: TIM3 timer clocks enable during Sleep and Stop modes.

TIM4SMEN

Bit 2: TIM4 timer clocks enable during Sleep and Stop modes.

TIM5SMEN

Bit 3: TIM5 timer clocks enable during Sleep and Stop modes.

TIM6SMEN

Bit 4: TIM6 timer clocks enable during Sleep and Stop modes.

TIM7SMEN

Bit 5: TIM7 timer clocks enable during Sleep and Stop modes.

RTCAPBSMEN

Bit 10: RTC APB clock enable during Sleep and Stop modes.

WWDGSMEN

Bit 11: Window watchdog clocks enable during Sleep and Stop modes.

SPI2SMEN

Bit 14: SPI2 clocks enable during Sleep and Stop modes.

SP3SMEN

Bit 15: SPI3 clocks enable during Sleep and Stop modes.

USART2SMEN

Bit 17: USART2 clocks enable during Sleep and Stop modes.

USART3SMEN

Bit 18: USART3 clocks enable during Sleep and Stop modes.

UART4SMEN

Bit 19: UART4 clocks enable during Sleep and Stop modes.

UART5SMEN

Bit 20: UART5 clocks enable during Sleep and Stop modes.

I2C1SMEN

Bit 21: I2C1 clocks enable during Sleep and Stop modes.

I2C2SMEN

Bit 22: I2C2 clocks enable during Sleep and Stop modes.

I2C3SMEN

Bit 23: I2C3 clocks enable during Sleep and Stop modes.

CRSSMEN

Bit 24: CRS clock enable during Sleep and Stop modes.

PWRSMEN

Bit 28: Power interface clocks enable during Sleep and Stop modes.

DAC1SMEN

Bit 29: DAC1 interface clocks enable during Sleep and Stop modes.

OPAMPSMEN

Bit 30: OPAMP interface clocks enable during Sleep and Stop modes.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during Sleep and Stop modes.

APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x7c, size: 32, reset: 0x00A00223, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1SMEN
rw 		USBFSSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1SMEN
rw 		LPTIM3SMEN
rw 		LPTIM2SMEN
rw 		I2C4SMEN
rw 		LPUART1SMEN
rw
Toggle fields

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during Sleep and Stop modes.

I2C4SMEN

Bit 1: I2C4 clocks enable during Sleep and Stop modes.

LPTIM2SMEN

Bit 5: LPTIM2SMEN.

LPTIM3SMEN

Bit 6: LPTIM3SMEN.

FDCAN1SMEN

Bit 9: FDCAN1SMEN.

USBFSSMEN

Bit 21: USBFSSMEN.

UCPD1SMEN

Bit 23: UCPD1SMEN.

APB2SMENR

APB2SMENR

Offset: 0x80, size: 32, reset: 0x01677801, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SMEN
rw 		SAI2SMEN
rw 		SAI1SMEN
rw 		TIM17SMEN
rw 		TIM16SMEN
rw 		TIM15SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw 		TIM8SMEN
rw 		SPI1SMEN
rw 		TIM1SMEN
rw 		SYSCFGSMEN
rw
Toggle fields

SYSCFGSMEN

Bit 0: SYSCFG clocks enable during Sleep and Stop modes.

TIM1SMEN

Bit 11: TIM1 timer clocks enable during Sleep and Stop modes.

SPI1SMEN

Bit 12: SPI1 clocks enable during Sleep and Stop modes.

TIM8SMEN

Bit 13: TIM8 timer clocks enable during Sleep and Stop modes.

USART1SMEN

Bit 14: USART1clocks enable during Sleep and Stop modes.

TIM15SMEN

Bit 16: TIM15 timer clocks enable during Sleep and Stop modes.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during Sleep and Stop modes.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during Sleep and Stop modes.

SAI1SMEN

Bit 21: SAI1 clocks enable during Sleep and Stop modes.

SAI2SMEN

Bit 22: SAI2 clocks enable during Sleep and Stop modes.

DFSDM1SMEN

Bit 24: DFSDM timer clocks enable during Sleep and Stop modes.

CCIPR1

CCIPR1

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCSEL
rw 		CLK48MSEL
rw 		FDCANSEL
rw 		LPTIM3SEL
rw 		LPTIM2SEL
rw 		LPTIM1SEL
rw 		I2C3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw 		I2C1SEL
rw 		LPUART1SEL
rw 		UART5SEL
rw 		UART4SEL
rw 		USART3SEL
rw 		USART2SEL
rw 		USART1SEL
rw
Toggle fields

USART1SEL

Bits 0-1: USART1 clock source selection.

USART2SEL

Bits 2-3: USART2 clock source selection.

USART3SEL

Bits 4-5: USART3 clock source selection.

UART4SEL

Bits 6-7: UART4 clock source selection.

UART5SEL

Bits 8-9: UART5 clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2C2SEL

Bits 14-15: I2C2 clock source selection.

I2C3SEL

Bits 16-17: I2C3 clock source selection.

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

LPTIM3SEL

Bits 22-23: Low-power timer 3 clock source selection.

FDCANSEL

Bits 24-25: FDCAN clock source selection.

CLK48MSEL

Bits 26-27: 48 MHz clock source selection.

ADCSEL

Bits 28-29: ADCs clock source selection.

BDCR

BDCR

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOSEL
rw 		LSCOEN
rw 		BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		LSESYSRDY
rw 		RTCSEL
rw 		LSESYSEN
rw 		LSECSSD
r 		LSECSSON
rw 		LSEDRV
rw 		LSEBYP
rw 		LSERDY
r 		LSEON
rw
Toggle fields

LSEON

Bit 0: LSE oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: LSE oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: LSE oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

LSEDRV

Bits 3-4: SE oscillator drive capability.

Allowed values:
0: Lower: 'Xtal mode' lower driving capability
1: MediumLow: 'Xtal mode' medium low driving capability
2: MediumHigh: 'Xtal mode' medium high driving capability
3: Higher: 'Xtal mode' higher driving capability

LSECSSON

Bit 5: LSECSSON.

Allowed values:
0: Off: CSS on LSE (32 kHz external oscillator) OFF
1: On: CSS on LSE (32 kHz external oscillator) ON

LSECSSD

Bit 6: LSECSSD.

Allowed values:
0: NoFailure: No failure detected on LSE (32 kHz oscillator)
1: Failure: Failure detected on LSE (32 kHz oscillator)

LSESYSEN

Bit 7: LSESYSEN.

Allowed values:
0: Disabled: LSESYS only enabled when requested by a peripheral or system function
1: Enabled: LSESYS enabled always generated by RCC

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

LSESYSRDY

Bit 11: LSESYSRDY.

Allowed values:
0: NotReady: LSESYS clock not ready
1: Ready: LSESYS clock ready

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

LSCOEN

Bit 24: Low speed clock output enable.

Allowed values:
0: Disabled: LSCO disabled
1: Enabled: LSCO enabled

LSCOSEL

Bit 25: Low speed clock output selection.

Allowed values:
0: LSI: LSI clock selected"
1: LSE: LSE clock selected

CSR

CSR

Offset: 0x94, size: 32, reset: 0x0C000600, access: Unspecified

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRSTF
r 		WWDGRSTF
r 		IWWDGRSTF
r 		SFTRSTF
r 		BORRSTF
r 		PINRSTF
r 		OBLRSTF
r 		RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSISRANGE
rw 		LSIPREDIV
rw 		LSIRDY
r 		LSION
rw
Toggle fields

LSION

Bit 0: LSI oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: LSI oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

LSIPREDIV

Bit 4: LSIPREDIV.

MSISRANGE

Bits 8-11: SI range after Standby mode.

RMVF

Bit 23: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

OBLRSTF

Bit 25: Option byte loader reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PINRSTF

Bit 26: Pin reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

BORRSTF

Bit 27: BOR flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

IWWDGRSTF

Bit 29: Independent window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

CRRCR

Clock recovery RC register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48CAL
r 		HSI48RDY
r 		HSI48ON
rw
Toggle fields

HSI48ON

Bit 0: HSI48 clock enable.

HSI48RDY

Bit 1: HSI48 clock ready flag.

HSI48CAL

Bits 7-15: HSI48 clock calibration.

CCIPR2

Peripherals independent clock configuration register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPISEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMCSEL
rw 		SAI2SEL
rw 		SAI1SEL
rw 		ADFSDMSEL
rw 		DFSDMSEL
rw 		I2C4SEL
rw
Toggle fields

I2C4SEL

Bits 0-1: I2C4 clock source selection.

DFSDMSEL

Bit 2: Digital filter for sigma delta modulator kernel clock source selection.

ADFSDMSEL

Bits 3-4: Digital filter for sigma delta modulator audio clock source selection.

SAI1SEL

Bits 5-7: SAI1 clock source selection.

SAI2SEL

Bits 8-10: SAI2 clock source selection.

SDMMCSEL

Bit 14: SDMMC clock selection.

OSPISEL

Bits 20-21: Octospi clock source selection.

SECCFGR

RCC secure configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMVFSEC
rw 		HSI48SEC
rw 		CLK48MSEC
rw 		PLLSAI2SEC
rw 		PLLSAI1SEC
rw 		PLLSEC
rw 		PRESCSEC
rw 		SYSCLKSEC
rw 		LSESEC
rw 		LSISEC
rw 		MSISEC
rw 		HSESEC
rw 		HSISEC
rw
Toggle fields

HSISEC

Bit 0: HSISEC.

HSESEC

Bit 1: HSESEC.

MSISEC

Bit 2: MSISEC.

LSISEC

Bit 3: LSISEC.

LSESEC

Bit 4: LSESEC.

SYSCLKSEC

Bit 5: SYSCLKSEC.

PRESCSEC

Bit 6: PRESCSEC.

PLLSEC

Bit 7: PLLSEC.

PLLSAI1SEC

Bit 8: PLLSAI1SEC.

PLLSAI2SEC

Bit 9: PLLSAI2SEC.

CLK48MSEC

Bit 10: CLK48MSEC.

HSI48SEC

Bit 11: HSI48SEC.

RMVFSEC

Bit 12: RMVFSEC.

SECSR

RCC secure status register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMVFSECF
rw 		HSI48SECF
rw 		CLK48MSECF
rw 		PLLSAI2SECF
rw 		PLLSAI1SECF
rw 		PLLSECF
rw 		PRESCSECF
rw 		SYSCLKSECF
rw 		LSESECF
rw 		LSISECF
rw 		MSISECF
rw 		HSESECF
rw 		HSISECF
rw
Toggle fields

HSISECF

Bit 0: HSISECF.

HSESECF

Bit 1: HSESECF.

MSISECF

Bit 2: MSISECF.

LSISECF

Bit 3: LSISECF.

LSESECF

Bit 4: LSESECF.

SYSCLKSECF

Bit 5: SYSCLKSECF.

PRESCSECF

Bit 6: PRESCSECF.

PLLSECF

Bit 7: PLLSECF.

PLLSAI1SECF

Bit 8: PLLSAI1SECF.

PLLSAI2SECF

Bit 9: PLLSAI2SECF.

CLK48MSECF

Bit 10: CLK48MSECF.

HSI48SECF

Bit 11: HSI48SECF.

RMVFSECF

Bit 12: RMVFSECF.

AHB1SECSR

RCC AHB1 security status register

Offset: 0xe8, size: 32, reset: 0x00400300, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESECF
r 		GTZCSECF
r 		TSCSECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSECF
r 		SRAM1SECF
r 		FLASHSECF
r 		DMAMUX1SECF
r 		DMA2SECF
r 		DMA1SECF
r
Toggle fields

DMA1SECF

Bit 0: DMA1SECF.

DMA2SECF

Bit 1: DMA2SECF.

DMAMUX1SECF

Bit 2: DMAMUX1SECF.

FLASHSECF

Bit 8: FLASHSECF.

SRAM1SECF

Bit 9: SRAM1SECF.

CRCSECF

Bit 12: CRCSECF.

TSCSECF

Bit 16: TSCSECF.

GTZCSECF

Bit 22: GTZCSECF.

ICACHESECF

Bit 23: ICACHESECF.

AHB2SECSR

RCC AHB2 security status register

Offset: 0xec, size: 32, reset: 0x002002FF, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SECF
r 		OTFDEC1SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2SECF
r 		GPIOHSECF
r 		GPIOGSECF
r 		GPIOFSECF
r 		GPIOESECF
r 		GPIODSECF
r 		GPIOCSECF
r 		GPIOBSECF
r 		GPIOASECF
r
Toggle fields

GPIOASECF

Bit 0: GPIOASECF.

GPIOBSECF

Bit 1: GPIOBSECF.

GPIOCSECF

Bit 2: GPIOCSECF.

GPIODSECF

Bit 3: GPIODSECF.

GPIOESECF

Bit 4: GPIOESECF.

GPIOFSECF

Bit 5: GPIOFSECF.

GPIOGSECF

Bit 6: GPIOGSECF.

GPIOHSECF

Bit 7: GPIOHSECF.

SRAM2SECF

Bit 9: SRAM2SECF.

OTFDEC1SECF

Bit 21: OTFDEC1SECF.

SDMMC1SECF

Bit 22: SDMMC1SECF.

AHB3SECSR

RCC AHB3 security status register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SECF
r 		FSMCSECF
r
Toggle fields

FSMCSECF

Bit 0: FSMCSECF.

OSPI1SECF

Bit 8: OSPI1SECF.

APB1SECSR1

RCC APB1 security status register 1

Offset: 0xf8, size: 32, reset: 0x00000400, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SECF
r 		OPAMPSECF
r 		DACSECF
r 		PWRSECF
r 		CRSSECF
r 		I2C3SECF
r 		I2C2SECF
r 		I2C1SECF
r 		UART5SECF
r 		UART4SECF
r 		UART3SECF
r 		UART2SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3SECF
r 		SPI2SECF
r 		WWDGSECF
r 		RTCAPBSECF
r 		TIM7SECF
r 		TIM6SECF
r 		TIM5SECF
r 		TIM4SECF
r 		TIM3SECF
r 		TIM2SECF
r
Toggle fields

TIM2SECF

Bit 0: TIM2SECF.

TIM3SECF

Bit 1: TIM3SECF.

TIM4SECF

Bit 2: TIM4SECF.

TIM5SECF

Bit 3: TIM5SECF.

TIM6SECF

Bit 4: TIM6SECF.

TIM7SECF

Bit 5: TIM7SECF.

RTCAPBSECF

Bit 10: RTCAPBSECF.

WWDGSECF

Bit 11: WWDGSECF.

SPI2SECF

Bit 14: SPI2SECF.

SPI3SECF

Bit 15: SPI3SECF.

UART2SECF

Bit 17: UART2SECF.

UART3SECF

Bit 18: UART3SECF.

UART4SECF

Bit 19: UART4SECF.

UART5SECF

Bit 20: UART5SECF.

I2C1SECF

Bit 21: I2C1SECF.

I2C2SECF

Bit 22: I2C2SECF.

I2C3SECF

Bit 23: I2C3SECF.

CRSSECF

Bit 24: CRSSECF.

PWRSECF

Bit 28: PWRSECF.

DACSECF

Bit 29: DACSECF.

OPAMPSECF

Bit 30: OPAMPSECF.

LPTIM1SECF

Bit 31: LPTIM1SECF.

APB1SECSR2

RCC APB1 security status register 2

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1SECF
r 		USBFSSECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1SECF
r 		LPTIM3SECF
r 		LPTIM2SECF
r 		I2C4SECF
r 		LPUART1SECF
r
Toggle fields

LPUART1SECF

Bit 0: LPUART1SECF.

I2C4SECF

Bit 1: I2C4SECF.

LPTIM2SECF

Bit 5: LPTIM2SECF.

LPTIM3SECF

Bit 6: LPTIM3SECF.

FDCAN1SECF

Bit 9: FDCAN1SECF.

USBFSSECF

Bit 21: USBFSSECF.

UCPD1SECF

Bit 23: UCPD1SECF.

APB2SECSR

RCC APB2 security status register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SECF
r 		SAI2SECF
r 		SAI1SECF
r 		TIM17SECF
r 		TIM16SECF
r 		TIM15SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SECF
r 		TIM8SECF
r 		SPI1SECF
r 		TIM1SECF
r 		SYSCFGSECF
r
Toggle fields

SYSCFGSECF

Bit 0: SYSCFGSECF.

TIM1SECF

Bit 11: TIM1SECF.

SPI1SECF

Bit 12: SPI1SECF.

TIM8SECF

Bit 13: TIM8SECF.

USART1SECF

Bit 14: USART1SECF.

TIM15SECF

Bit 16: TIM15SECF.

TIM16SECF

Bit 17: TIM16SECF.

TIM17SECF

Bit 18: TIM17SECF.

SAI1SECF

Bit 21: SAI1SECF.

SAI2SECF

Bit 22: SAI2SECF.

DFSDM1SECF

Bit 24: DFSDM1SECF.

SEC_RNG

0x520c0800: RNG

4/17 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
0x10 HTCR
Toggle registers

CR

RNG control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONFIGLOCK
rw 		CONDRST
rw 		RNG_CONFIG1
rw 		CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG_CONFIG2
rw 		NISTC
rw 		RNG_CONFIG3
rw 		CED
rw 		IE
rw 		RNGEN
rw
Toggle fields

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

CED

Bit 5: Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled..

RNG_CONFIG3

Bits 8-11: RNG configuration 3.

NISTC

Bit 12: Non NIST compliant.

RNG_CONFIG2

Bits 13-15: RNG configuration 2.

CLKDIV

Bits 16-19: Clock divider factor.

RNG_CONFIG1

Bits 20-25: RNG configuration 1.

CONDRST

Bit 30: Conditioning soft reset.

CONFIGLOCK

Bit 31: RNG Config Lock.

SR

RNG status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw 		CEIS
rw 		SECS
r 		CECS
r 		DRDY
r
Toggle fields

DRDY

Bit 0: Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated..

CECS

Bit 1: Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SECS

Bit 2: Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01).

CEIS

Bit 5: Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SEIS

Bit 6: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register..

DR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: Random data 32-bit random data which are valid when DRDY=1..

HTCR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x10, size: 32, reset: 0x000CAA74, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTCFG
rw
Toggle fields

HTCFG

Bits 0-31: health test configuration.

SEC_RTC

0x50002800: Real-time clock

26/147 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 SSR
0xc ICSR
0x10 PRER
0x14 WUTR
0x18 CR
0x1c PRIVCR
0x20 SMCR
0x24 WPR
0x28 CALR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x40 ALRM[A]R
0x44 ALRM[A]SSR
0x48 ALRM[B]R
0x4c ALRM[B]SSR
0x50 SR
0x54 MISR
0x58 SMISR
0x5c SCR
Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

ICSR

RTC initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw 		INITF
r 		RSF
rw 		INITS
r 		SHPF
rw 		WUTWF
r 		ALRBWF
r 		ALRAWF
r
Toggle fields

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUTOCLR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

WUTOCLR

Bits 16-31: WUTOCLR.

CR

RTC control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2EN
rw 		TAMPALRM_TYPE
rw 		TAMPALRM_PU
rw 		TAMPOE
rw 		TAMPTS
rw 		ITSE
rw 		COE
rw 		OSEL
rw 		POL
rw 		COSEL
rw 		BKP
rw 		SUB1H
rw 		ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALRBIE
rw 		ALRAIE
rw 		TSE
rw 		WUTE
rw 		ALRBE
rw 		ALRAE
rw 		FMT
rw 		BYPSHAD
rw 		REFCKON
rw 		TSEDGE
rw 		WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: WUCKSEL.

TSEDGE

Bit 3: TSEDGE.

REFCKON

Bit 4: REFCKON.

BYPSHAD

Bit 5: BYPSHAD.

FMT

Bit 6: FMT.

ALRAE

Bit 8: ALRAE.

ALRBE

Bit 9: ALRBE.

WUTE

Bit 10: WUTE.

TSE

Bit 11: TSE.

ALRAIE

Bit 12: ALRAIE.

ALRBIE

Bit 13: ALRBIE.

WUTIE

Bit 14: WUTIE.

TSIE

Bit 15: TSIE.

ADD1H

Bit 16: ADD1H.

SUB1H

Bit 17: SUB1H.

BKP

Bit 18: BKP.

COSEL

Bit 19: COSEL.

POL

Bit 20: POL.

OSEL

Bits 21-22: OSEL.

COE

Bit 23: COE.

ITSE

Bit 24: ITSE.

TAMPTS

Bit 25: TAMPTS.

TAMPOE

Bit 26: TAMPOE.

TAMPALRM_PU

Bit 29: TAMPALRM_PU.

TAMPALRM_TYPE

Bit 30: TAMPALRM_TYPE.

OUT2EN

Bit 31: OUT2EN.

PRIVCR

RTC privilege mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw 		INITPRIV
rw 		CALPRIV
rw 		TSPRIV
rw 		WUTPRIV
rw 		ALRBPRIV
rw 		ALRAPRIV
rw
Toggle fields

ALRAPRIV

Bit 0: ALRAPRIV.

ALRBPRIV

Bit 1: ALRBPRIV.

WUTPRIV

Bit 2: WUTPRIV.

TSPRIV

Bit 3: TSPRIV.

CALPRIV

Bit 13: CALPRIV.

INITPRIV

Bit 14: INITPRIV.

PRIV

Bit 15: PRIV.

SMCR

RTC secure mode control register

Offset: 0x20, size: 32, reset: 0x0000E00F, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT
rw 		INITDPROT
rw 		CALDPROT
rw 		TSDPROT
rw 		WUTDPROT
rw 		ALRBDPROT
rw 		ALRADPROT
rw
Toggle fields

ALRADPROT

Bit 0: ALRADPROT.

ALRBDPROT

Bit 1: ALRBDPROT.

WUTDPROT

Bit 2: WUTDPROT.

TSDPROT

Bit 3: TSDPROT.

CALDPROT

Bit 13: CALDPROT.

INITDPROT

Bit 14: INITDPROT.

DECPROT

Bit 15: DECPROT.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

CALR

calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		LPCAL
rw 		CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

LPCAL

Bit 12: LPCAL.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

ALRM[A]R

Alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRM[B]R

Alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm date mask.

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

SR

RTC status register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSF
r 		TSOVF
r 		TSF
r 		WUTF
r 		ALRBF
r 		ALRAF
r
Toggle fields

ALRAF

Bit 0: ALRAF.

ALRBF

Bit 1: ALRBF.

WUTF

Bit 2: WUTF.

TSF

Bit 3: TSF.

TSOVF

Bit 4: TSOVF.

ITSF

Bit 5: ITSF.

MISR

RTC non-secure masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r 		TSOVMF
r 		TSMF
r 		WUTMF
r 		ALRBMF
r 		ALRAMF
r
Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SMISR

RTC secure masked interrupt status register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r 		TSOVMF
r 		TSMF
r 		WUTMF
r 		ALRBMF
r 		ALRAMF
r
Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SCR

RTC status clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CITSF
w 		CTSOVF
w 		CTSF
w 		CWUTF
w 		CALRBF
w 		CALRAF
w
Toggle fields

CALRAF

Bit 0: CALRAF.

CALRBF

Bit 1: CALRBF.

CWUTF

Bit 2: CWUTF.

CTSF

Bit 3: CTSF.

CTSOVF

Bit 4: CTSOVF.

CITSF

Bit 5: CITSF.

SEC_SAI1

0x50015400: Serial audio interface

84/118 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw 		SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN2
rw 		CKEN1
rw 		MICNBR
rw 		PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw 		DLYM[4]L
rw 		DLYM[3]R
rw 		DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw 		DLYM[2]L
rw 		DLYM[1]R
rw 		DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SEC_SAI2

0x50015800: Serial audio interface

84/118 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw 		SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN2
rw 		CKEN1
rw 		MICNBR
rw 		PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw 		DLYM[4]L
rw 		DLYM[3]R
rw 		DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw 		DLYM[2]L
rw 		DLYM[1]R
rw 		DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SEC_SDMMC1

0x520c8000: SDMMC1

38/125 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SDMMC_POWER
0x4 SDMMC_CLKCR
0x8 SDMMC_ARGR
0xc SDMMC_CMDR
0x10 SDMMC_RESPCMDR
0x14 SDMMC_RESP1R
0x18 SDMMC_RESP2R
0x1c SDMMC_RESP3R
0x20 SDMMC_RESP4R
0x24 SDMMC_DTIMER
0x28 SDMMC_DLENR
0x2c SDMMC_DCTRL
0x30 SDMMC_DCNTR
0x34 SDMMC_STAR
0x38 SDMMC_ICR
0x3c SDMMC_MASKR
0x40 SDMMC_ACKTIMER
0x50 SDMMC_IDMACTRLR
0x54 SDMMC_IDMABSIZER
0x58 SDMMC_IDMABASE0R
0x5c SDMMC_IDMABASE1R
0x80 SDMMC_FIFOR
0x3f4 SDMMC_VER
0x3f8 SDMMC_ID
Toggle registers

SDMMC_POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw 		VSWITCHEN
rw 		VSWITCH
rw 		PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11..

VSWITCH

Bit 2: Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:.

VSWITCHEN

Bit 3: Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:.

DIRPOL

Bit 4: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)..

SDMMC_CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw 		BUSSPEED
rw 		DDR
rw 		HWFC_EN
rw 		NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw 		PWRSAV
rw 		CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc...

PWRSAV

Bit 12: Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:.

WIDBUS

Bits 14-15: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

NEGEDGE

Bit 16: SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge..

HWFC_EN

Bit 17: Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11..

DDR

Bit 18: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0).

BUSSPEED

Bit 19: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

SELCLKRX

Bits 20-21: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

SDMMC_ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register..

SDMMC_CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw 		BOOTMODE
rw 		DTHOLD
rw 		CPSMEN
rw 		WAITPEND
rw 		WAITINT
rw 		WAITRESP
rw 		CMDSTOP
rw 		CMDTRANS
rw 		CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message..

CMDTRANS

Bit 6: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent..

CMDSTOP

Bit 7: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent..

WAITRESP

Bits 8-9: Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response..

WAITINT

Bit 10: CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode..

WAITPEND

Bit 11: CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card..

CPSMEN

Bit 12: Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0..

DTHOLD

Bit 13: Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state..

BOOTMODE

Bit 14: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0).

BOOTEN

Bit 15: Enable boot mode procedure..

CMDSUSPEND

Bit 16: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1..

SDMMC_RESPCMDR

SDMMC command response register

Offset: 0x10, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

SDMMC_RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: see Table 432.

SDMMC_RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: see Table404..

SDMMC_RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: see Table404..

SDMMC_RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: see Table404..

SDMMC_DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods..

SDMMC_DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0..

SDMMC_DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw 		BOOTACKEN
rw 		SDIOEN
rw 		RWMOD
rw 		RWSTOP
rw 		RWSTART
rw 		DBLOCKSIZE
rw 		DTMODE
rw 		DTDIR
rw 		DTEN
rw
Toggle fields

DTEN

Bit 0: Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards..

DTDIR

Bit 1: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DTMODE

Bits 2-3: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DBLOCKSIZE

Bits 4-7: Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered).

RWSTART

Bit 8: Read wait start. If this bit is set, read wait operation starts..

RWSTOP

Bit 9: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state..

RWMOD

Bit 10: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

SDIOEN

Bit 11: SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation..

BOOTACKEN

Bit 12: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

FIFORST

Bit 13: FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs..

SDMMC_DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect..

SDMMC_STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTC
r 		IDMATE
r 		CKSTOP
r 		VSWEND
r 		ACKTIMEOUT
r 		ACKFAIL
r 		SDIOIT
r 		BUSYD0END
r 		BUSYD0
r 		RXFIFOE
r 		TXFIFOE
r 		RXFIFOF
r 		TXFIFOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHF
r 		TXFIFOHE
r 		CPSMACT
r 		DPSMACT
r 		DABORT
r 		DBCKEND
r 		DHOLD
r 		DATAEND
r 		CMDSENT
r 		CMDREND
r 		RXOVERR
r 		TXUNDERR
r 		DTIMEOUT
r 		CTIMEOUT
r 		DCRCFAIL
r 		CCRCFAIL
r
Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CTIMEOUT

Bit 2: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods..

DTIMEOUT

Bit 3: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

TXUNDERR

Bit 4: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

RXOVERR

Bit 5: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDREND

Bit 6: Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDSENT

Bit 7: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DATAEND

Bit 8: Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DHOLD

Bit 9: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DBCKEND

Bit 10: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DABORT

Bit 11: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DPSMACT

Bit 12: Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

CPSMACT

Bit 13: Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

TXFIFOHE

Bit 14: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full..

RXFIFOHF

Bit 15: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty..

TXFIFOF

Bit 16: Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty..

RXFIFOF

Bit 17: Receive FIFO full This bit is cleared when one FIFO location becomes empty..

TXFIFOE

Bit 18: Transmit FIFO empty This bit is cleared when one FIFO location becomes full..

RXFIFOE

Bit 19: Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full..

BUSYD0

Bit 20: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt..

BUSYD0END

Bit 21: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

SDIOIT

Bit 22: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKFAIL

Bit 23: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKTIMEOUT

Bit 24: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

VSWEND

Bit 25: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CKSTOP

Bit 26: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMATE

Bit 27: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMABTC

Bit 28: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

SDMMC_ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCC
rw 		IDMATEC
rw 		CKSTOPC
rw 		VSWENDC
rw 		ACKTIMEOUTC
rw 		ACKFAILC
rw 		SDIOITC
rw 		BUSYD0ENDC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DABORTC
rw 		DBCKENDC
rw 		DHOLDC
rw 		DATAENDC
rw 		CMDSENTC
rw 		CMDRENDC
rw 		RXOVERRC
rw 		TXUNDERRC
rw 		DTIMEOUTC
rw 		CTIMEOUTC
rw 		DCRCFAILC
rw 		CCRCFAILC
rw
Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag..

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag..

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag..

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag..

TXUNDERRC

Bit 4: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag..

RXOVERRC

Bit 5: RXOVERR flag clear bit Set by software to clear the RXOVERR flag..

CMDRENDC

Bit 6: CMDREND flag clear bit Set by software to clear the CMDREND flag..

CMDSENTC

Bit 7: CMDSENT flag clear bit Set by software to clear the CMDSENT flag..

DATAENDC

Bit 8: DATAEND flag clear bit Set by software to clear the DATAEND flag..

DHOLDC

Bit 9: DHOLD flag clear bit Set by software to clear the DHOLD flag..

DBCKENDC

Bit 10: DBCKEND flag clear bit Set by software to clear the DBCKEND flag..

DABORTC

Bit 11: DABORT flag clear bit Set by software to clear the DABORT flag..

BUSYD0ENDC

Bit 21: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag..

SDIOITC

Bit 22: SDIOIT flag clear bit Set by software to clear the SDIOIT flag..

ACKFAILC

Bit 23: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag..

ACKTIMEOUTC

Bit 24: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag..

VSWENDC

Bit 25: VSWEND flag clear bit Set by software to clear the VSWEND flag..

CKSTOPC

Bit 26: CKSTOP flag clear bit Set by software to clear the CKSTOP flag..

IDMATEC

Bit 27: IDMA transfer error clear bit Set by software to clear the IDMATE flag..

IDMABTCC

Bit 28: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag..

SDMMC_MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCIE
rw 		CKSTOPIE
rw 		VSWENDIE
rw 		ACKTIMEOUTIE
rw 		ACKFAILIE
rw 		SDIOITIE
rw 		BUSYD0ENDIE
rw 		TXFIFOEIE
rw 		RXFIFOFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHFIE
rw 		TXFIFOHEIE
rw 		DABORTIE
rw 		DBCKENDIE
rw 		DHOLDIE
rw 		DATAENDIE
rw 		CMDSENTIE
rw 		CMDRENDIE
rw 		RXOVERRIE
rw 		TXUNDERRIE
rw 		DTIMEOUTIE
rw 		CTIMEOUTIE
rw 		DCRCFAILIE
rw 		CCRCFAILIE
rw
Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure..

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure..

CTIMEOUTIE

Bit 2: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout..

DTIMEOUTIE

Bit 3: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout..

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error..

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error..

CMDRENDIE

Bit 6: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response..

CMDSENTIE

Bit 7: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command..

DATAENDIE

Bit 8: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end..

DHOLDIE

Bit 9: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state..

DBCKENDIE

Bit 10: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end..

DABORTIE

Bit 11: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted..

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty..

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full..

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full..

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty..

BUSYD0ENDIE

Bit 21: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response..

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt..

ACKFAILIE

Bit 23: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail..

ACKTIMEOUTIE

Bit 24: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout..

VSWENDIE

Bit 25: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion..

CKSTOPIE

Bit 26: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped..

IDMABTCIE

Bit 28: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer..

SDMMC_ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods..

SDMMC_IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABACT
rw 		IDMABMODE
rw 		IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABMODE

Bit 1: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABACT

Bit 2: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware..

SDMMC_IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
Toggle fields

IDMABNDT

Bits 5-12: Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

SDMMC_IDMABASE0R

The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE0
rw
Toggle fields

IDMABASE0

Bits 0-31: Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)..

SDMMC_IDMABASE1R

The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE1
rw
Toggle fields

IDMABASE1

Bits 0-31: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)..

SDMMC_FIFOR

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words..

SDMMC_VER

SDMMC IP version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: IP minor revision number..

MAJREV

Bits 4-7: IP major revision number..

SDMMC_ID

SDMMC IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: SDMMC IP identification..

SEC_SPI1

0x50013000: Serial peripheral interface

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SEC_SPI2

0x50003800: Serial peripheral interface

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SEC_SPI3

0x50003c00: Serial peripheral interface

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SEC_SYSCFG

0x50010000: System configuration controller

1/93 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SECCFGR
0x4 CFGR1
0x8 FPUIMR
0xc CNSLCKR
0x10 CSLOCKR
0x14 CFGR2
0x18 SCSR
0x1c SKR
0x20 SWPR
0x24 SWPR2
0x2c RSSCMDR
Toggle registers

SECCFGR

SYSCFG secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPUSEC
rw 		SRAM2SEC
rw 		CLASSBSEC
rw 		SYSCFGSEC
rw
Toggle fields

SYSCFGSEC

Bit 0: SYSCFG clock control security.

CLASSBSEC

Bit 1: ClassB security.

SRAM2SEC

Bit 2: SRAM2 security.

FPUSEC

Bit 3: FPUSEC.

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C4_FMP
rw 		I2C3_FMP
rw 		I2C2_FMP
rw 		I2C1_FMP
rw 		I2C_PB9_FMP
rw 		I2C_PB8_FMP
rw 		I2C_PB7_FMP
rw 		I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANASWVDD
rw 		BOOSTEN
rw
Toggle fields

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

ANASWVDD

Bit 9: GPIO analog switch control voltage selection.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C2_FMP

Bit 21: I2C2 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

I2C4_FMP

Bit 23: I2C4_FMP.

FPUIMR

FPU interrupt mask register

Offset: 0x8, size: 32, reset: 0x0000001F, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPU_IE
rw
Toggle fields

FPU_IE

Bits 0-5: Floating point unit interrupts enable bits.

CNSLCKR

SYSCFG CPU non-secure lock register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKNSMPU
rw 		LOCKNSVTOR
rw
Toggle fields

LOCKNSVTOR

Bit 0: VTOR_NS register lock.

LOCKNSMPU

Bit 1: Non-secure MPU registers lock.

CSLOCKR

SYSCFG CPU secure lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKSAU
rw 		LOCKSMPU
rw 		LOCKSVTAIRCR
rw
Toggle fields

LOCKSVTAIRCR

Bit 0: LOCKSVTAIRCR.

LOCKSMPU

Bit 1: LOCKSMPU.

LOCKSAU

Bit 2: LOCKSAU.

CFGR2

CFGR2

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPF
rw 		ECCL
w 		PVDL
w 		SPL
w 		CLL
w
Toggle fields

CLL

Bit 0: LOCKUP (hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SCSR

SCSR

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2BSY
r 		SRAM2ER
rw
Toggle fields

SRAM2ER

Bit 0: SRAM2 Erase.

SRAM2BSY

Bit 1: SRAM2 busy by erase operation.

SKR

SKR

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: SRAM2 write protection key for software erase.

SWPR

SWPR

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31WP
w 		P30WP
w 		P29WP
w 		P28WP
w 		P27WP
w 		P26WP
w 		P25WP
w 		P24WP
w 		P23WP
w 		P22WP
w 		P21WP
w 		P20WP
w 		P19WP
w 		P18WP
w 		P17WP
w 		P16WP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15WP
w 		P14WP
w 		P13WP
w 		P12WP
w 		P11WP
w 		P10WP
w 		P9WP
w 		P8WP
w 		P7WP
w 		P6WP
w 		P5WP
w 		P4WP
w 		P3WP
w 		P2WP
w 		P1WP
w 		P0WP
w
Toggle fields

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: SRAM2 page 31 write protection.

SWPR2

SWPR2

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P63WP
w 		P62WP
w 		P61WP
w 		P60WP
w 		P59WP
w 		P58WP
w 		P57WP
w 		P56WP
w 		P55WP
w 		P54WP
w 		P53WP
w 		P52WP
w 		P51WP
w 		P50WP
w 		P49WP
w 		P48WP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P47WP
w 		P46WP
w 		P45WP
w 		P44WP
w 		P43WP
w 		P42WP
w 		P41WP
w 		P40WP
w 		P39WP
w 		P38WP
w 		P37WP
w 		P36WP
w 		P35WP
w 		P34WP
w 		P33WP
w 		P32WP
w
Toggle fields

P32WP

Bit 0: P32WP.

P33WP

Bit 1: P33WP.

P34WP

Bit 2: P34WP.

P35WP

Bit 3: P35WP.

P36WP

Bit 4: P36WP.

P37WP

Bit 5: P37WP.

P38WP

Bit 6: P38WP.

P39WP

Bit 7: P39WP.

P40WP

Bit 8: P40WP.

P41WP

Bit 9: P41WP.

P42WP

Bit 10: P42WP.

P43WP

Bit 11: P43WP.

P44WP

Bit 12: P44WP.

P45WP

Bit 13: P45WP.

P46WP

Bit 14: P46WP.

P47WP

Bit 15: P47WP.

P48WP

Bit 16: P48WP.

P49WP

Bit 17: P49WP.

P50WP

Bit 18: P50WP.

P51WP

Bit 19: P51WP.

P52WP

Bit 20: P52WP.

P53WP

Bit 21: P53WP.

P54WP

Bit 22: P54WP.

P55WP

Bit 23: P55WP.

P56WP

Bit 24: P56WP.

P57WP

Bit 25: P57WP.

P58WP

Bit 26: P58WP.

P59WP

Bit 27: P59WP.

P60WP

Bit 28: P60WP.

P61WP

Bit 29: P61WP.

P62WP

Bit 30: P62WP.

P63WP

Bit 31: P63WP.

RSSCMDR

RSSCMDR

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSSCMD
rw
Toggle fields

RSSCMD

Bits 0-7: RSS commands.

SEC_TAMP

0x50003400: Tamper and backup registers

43/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc FLTCR
0x10 ATCR1
0x14 ATSEEDR
0x18 ATOR
0x1c ATCR2
0x20 SMCR
0x24 PRIVCR
0x2c IER
0x30 SR
0x34 MISR
0x38 SMISR
0x3c SCR
0x40 COUNTR
0x50 CFGR
0x100 BKP[0]R
0x104 BKP[1]R
0x108 BKP[2]R
0x10c BKP[3]R
0x110 BKP[4]R
0x114 BKP[5]R
0x118 BKP[6]R
0x11c BKP[7]R
0x120 BKP[8]R
0x124 BKP[9]R
0x128 BKP[10]R
0x12c BKP[11]R
0x130 BKP[12]R
0x134 BKP[13]R
0x138 BKP[14]R
0x13c BKP[15]R
0x140 BKP[16]R
0x144 BKP[17]R
0x148 BKP[18]R
0x14c BKP[19]R
0x150 BKP[20]R
0x154 BKP[21]R
0x158 BKP[22]R
0x15c BKP[23]R
0x160 BKP[24]R
0x164 BKP[25]R
0x168 BKP[26]R
0x16c BKP[27]R
0x170 BKP[28]R
0x174 BKP[29]R
0x178 BKP[30]R
0x17c BKP[31]R
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0xFFFF0000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8E
rw 		ITAMP5E
rw 		ITAMP3E
rw 		ITAMP2E
rw 		ITAMP1E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8E
rw 		TAMP7E
rw 		TAMP6E
rw 		TAMP5E
rw 		TAMP4E
rw 		TAMP3E
rw 		TAMP2E
rw 		TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

TAMP3E

Bit 2: TAMP3E.

TAMP4E

Bit 3: TAMP4E.

TAMP5E

Bit 4: TAMP5E.

TAMP6E

Bit 5: TAMP6E.

TAMP7E

Bit 6: TAMP7E.

TAMP8E

Bit 7: TAMP8E.

ITAMP1E

Bit 16: ITAMP1E.

ITAMP2E

Bit 17: ITAMP2E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP8E

Bit 23: ITAMP5E.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP8TRG
rw 		TAMP7TRG
rw 		TAMP6TRG
rw 		TAMP5TRG
rw 		TAMP4TRG
rw 		TAMP3TRG
rw 		TAMP2TRG
rw 		TAMP1TRG
rw 		BKERASE
rw 		TAMP3MSK
rw 		TAMP2MSK
rw 		TAMP1MSK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8NOER
rw 		TAMP7NOER
rw 		TAMP6NOER
rw 		TAMP5NOER
rw 		TAMP4NOER
rw 		TAMP3NOER
rw 		TAMP2NOER
rw 		TAMP1NOER
rw
Toggle fields

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP3NOER

Bit 2: TAMP3NOER.

TAMP4NOER

Bit 3: TAMP4NOER.

TAMP5NOER

Bit 4: TAMP5NOER.

TAMP6NOER

Bit 5: TAMP6NOER.

TAMP7NOER

Bit 6: TAMP7NOER.

TAMP8NOER

Bit 7: TAMP8NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP3MSK

Bit 18: TAMP3MSK.

BKERASE

Bit 23: BKERASE.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

TAMP3TRG

Bit 26: TAMP3TRG.

TAMP4TRG

Bit 27: TAMP4TRG.

TAMP5TRG

Bit 28: TAMP5TRG.

TAMP6TRG

Bit 29: TAMP6TRG.

TAMP7TRG

Bit 30: TAMP7TRG.

TAMP8TRG

Bit 31: TAMP8TRG.

CR3

control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITAMP8NOER
rw 		ITAMP5NOER
rw 		ITAMP3NOER
rw 		ITAMP2NOER
rw 		ITAMP1NOER
rw
Toggle fields

ITAMP1NOER

Bit 0: ITAMP1NOER.

ITAMP2NOER

Bit 1: ITAMP2NOER.

ITAMP3NOER

Bit 2: ITAMP3NOER.

ITAMP5NOER

Bit 4: ITAMP5NOER.

ITAMP8NOER

Bit 7: ITAMP8NOER.

FLTCR

TAMP filter control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw
Toggle fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

ATCR1

TAMP active tamper control register 1

Offset: 0x10, size: 32, reset: 0x00070000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTEN
rw 		ATOSHARE
rw 		ATPER
rw 		ATCKSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL4
rw 		ATOSEL3
rw 		ATOSEL2
rw 		ATOSEL1
rw 		TAMP8AM
rw 		TAMP7AM
rw 		TAMP6AM
rw 		TAMP5AM
rw 		TAMP4AM
rw 		TAMP3AM
rw 		TAMP2AM
rw 		TAMP1AM
rw
Toggle fields

TAMP1AM

Bit 0: TAMP1AM.

TAMP2AM

Bit 1: TAMP2AM.

TAMP3AM

Bit 2: TAMP3AM.

TAMP4AM

Bit 3: TAMP4AM.

TAMP5AM

Bit 4: TAMP5AM.

TAMP6AM

Bit 5: TAMP6AM.

TAMP7AM

Bit 6: TAMP7AM.

TAMP8AM

Bit 7: TAMP8AM.

ATOSEL1

Bits 8-9: ATOSEL1.

ATOSEL2

Bits 10-11: ATOSEL2.

ATOSEL3

Bits 12-13: ATOSEL3.

ATOSEL4

Bits 14-15: ATOSEL4.

ATCKSEL

Bits 16-17: ATCKSEL.

ATPER

Bits 24-25: ATPER.

ATOSHARE

Bit 30: ATOSHARE.

FLTEN

Bit 31: FLTEN.

ATSEEDR

TAMP active tamper seed register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
w
Toggle fields

SEED

Bits 0-31: Pseudo-random generator seed value.

ATOR

TAMP active tamper output register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INITS
r 		SEEDF
r 		PRNG
r
Toggle fields

PRNG

Bits 0-7: Pseudo-random generator value.

SEEDF

Bit 14: Seed running flag.

INITS

Bit 15: Active tamper initialization status.

ATCR2

TAMP active tamper control register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATOSEL8
rw 		ATOSEL7
rw 		ATOSEL6
rw 		ATOSEL5
rw 		ATOSEL4
rw 		ATOSEL3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL3
rw 		ATOSEL2
rw 		ATOSEL1
rw
Toggle fields

ATOSEL1

Bits 8-10: ATOSEL1.

ATOSEL2

Bits 11-13: ATOSEL2.

ATOSEL3

Bits 14-16: ATOSEL3.

ATOSEL4

Bits 17-19: ATOSEL4.

ATOSEL5

Bits 20-22: ATOSEL5.

ATOSEL6

Bits 23-25: ATOSEL6.

ATOSEL7

Bits 26-28: ATOSEL7.

ATOSEL8

Bits 29-31: ATOSEL8.

SMCR

TAMP secure mode register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPDPROT
rw 		BKPWDPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPRWDPROT
rw
Toggle fields

BKPRWDPROT

Bits 0-7: Backup registers read/write protection offset.

BKPWDPROT

Bits 16-23: Backup registers write protection offset.

TAMPDPROT

Bit 31: Tamper protection.

PRIVCR

TAMP privilege mode control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPPRIV
rw 		BKPWPRIV
rw 		BKPRWPRIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

BKPRWPRIV

Bit 29: Backup registers zone 1 privilege protection.

BKPWPRIV

Bit 30: Backup registers zone 2 privilege protection.

TAMPPRIV

Bit 31: Tamper privilege protection.

IER

TAMP interrupt enable register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8IE
rw 		ITAMP5IE
rw 		ITAMP3IE
rw 		ITAMP2IE
rw 		ITAMP1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8IE
rw 		TAMP7IE
rw 		TAMP6IE
rw 		TAMP5IE
rw 		TAMP4IE
rw 		TAMP3IE
rw 		TAMP2IE
rw 		TAMP1IE
rw
Toggle fields

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

TAMP3IE

Bit 2: TAMP3IE.

TAMP4IE

Bit 3: TAMP4IE.

TAMP5IE

Bit 4: TAMP5IE.

TAMP6IE

Bit 5: TAMP6IE.

TAMP7IE

Bit 6: TAMP7IE.

TAMP8IE

Bit 7: TAMP8IE.

ITAMP1IE

Bit 16: ITAMP1IE.

ITAMP2IE

Bit 17: ITAMP2IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP8IE

Bit 23: ITAMP8IE.

SR

TAMP status register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8F
r 		ITAMP5F
r 		ITAMP3F
r 		ITAMP2F
r 		ITAMP1F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8F
r 		TAMP7F
r 		TAMP6F
r 		TAMP5F
r 		TAMP4F
r 		TAMP3F
r 		TAMP2F
r 		TAMP1F
r
Toggle fields

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

TAMP3F

Bit 2: TAMP3F.

TAMP4F

Bit 3: TAMP4F.

TAMP5F

Bit 4: TAMP5F.

TAMP6F

Bit 5: TAMP6F.

TAMP7F

Bit 6: TAMP7F.

TAMP8F

Bit 7: TAMP8F.

ITAMP1F

Bit 16: ITAMP1F.

ITAMP2F

Bit 17: ITAMP2F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP8F

Bit 23: ITAMP8F.

MISR

TAMP masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r 		ITAMP5MF
r 		ITAMP3MF
r 		ITAMP2MF
r 		ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8MF
r 		TAMP7MF
r 		TAMP6MF
r 		TAMP5MF
r 		TAMP4MF
r 		TAMP3MF
r 		TAMP2MF
r 		TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF:.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SMISR

TAMP secure masked interrupt status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r 		ITAMP5MF
r 		ITAMP3MF
r 		ITAMP2MF
r 		ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8MF
r 		TAMP7MF
r 		TAMP6MF
r 		TAMP5MF
r 		TAMP4MF
r 		TAMP3MF
r 		TAMP2MF
r 		TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF:.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CITAMP8F
w 		CITAMP5F
w 		CITAMP3F
w 		CITAMP2F
w 		CITAMP1F
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP8F
w 		CTAMP7F
w 		CTAMP6F
w 		CTAMP5F
w 		CTAMP4F
w 		CTAMP3F
w 		CTAMP2F
w 		CTAMP1F
w
Toggle fields

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CTAMP3F

Bit 2: CTAMP3F.

CTAMP4F

Bit 3: CTAMP4F.

CTAMP5F

Bit 4: CTAMP5F.

CTAMP6F

Bit 5: CTAMP6F.

CTAMP7F

Bit 6: CTAMP7F.

CTAMP8F

Bit 7: CTAMP8F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP8F

Bit 23: CITAMP8F.

COUNTR

TAMP monotonic counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle fields

COUNT

Bits 0-31: COUNT.

CFGR

TAMP configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUTMONEN
rw 		VMONEN
rw 		TMONEN
rw
Toggle fields

TMONEN

Bit 1: TMONEN.

VMONEN

Bit 2: VMONEN.

WUTMONEN

Bit 3: WUTMONEN.

BKP[0]R

TAMP backup register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[1]R

TAMP backup register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[2]R

TAMP backup register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[3]R

TAMP backup register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[4]R

TAMP backup register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[5]R

TAMP backup register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[6]R

TAMP backup register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[7]R

TAMP backup register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[8]R

TAMP backup register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[9]R

TAMP backup register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[10]R

TAMP backup register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[11]R

TAMP backup register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[12]R

TAMP backup register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[13]R

TAMP backup register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[14]R

TAMP backup register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[15]R

TAMP backup register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[16]R

TAMP backup register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[17]R

TAMP backup register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[18]R

TAMP backup register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[19]R

TAMP backup register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[20]R

TAMP backup register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[21]R

TAMP backup register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[22]R

TAMP backup register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[23]R

TAMP backup register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[24]R

TAMP backup register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[25]R

TAMP backup register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[26]R

TAMP backup register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[27]R

TAMP backup register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[28]R

TAMP backup register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[29]R

TAMP backup register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[30]R

TAMP backup register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[31]R

TAMP backup register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

SEC_TIM1

0x50012c00: Advanced-timers

13/186 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS5
rw 		OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS5

Bit 15: Output Idle state 5 (OC5 output).

OIS6

Bit 16: Output Idle state 6.

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw 		ETR_ADC1_RMP
rw
Toggle fields

ETR_ADC1_RMP

Bits 0-1: External trigger remap on ADC1 analog watchdog.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M_3
rw 		OC5M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_3

Bit 16: Output Compare 5 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC6M_3

Bit 24: Output Compare 6 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register 4

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 4

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: Capture/Compare value.

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDFBK0E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK0E

Bit 8: BRK DFSDM_BREAK0 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2DFBK0E
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

SEC_TIM15

0x50014000: General purpose timers

4/95 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 CCR2
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-5: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output idle state 2 (OC2 output).

SMCR

TIM15 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/slave mode.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/Compare 2 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_bit3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2M
rw 		OC2PE
rw 		CC2S
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC1M_3

Bit 16: Output Compare 1 mode.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output polarity.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

CCR2

TIM15 capture/compare register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM15 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENCODER_MODE
rw 		TI1_RMP
rw
Toggle fields

TI1_RMP

Bit 0: Input capture 1 remap.

ENCODER_MODE

Bits 1-2: Encoder mode.

OR2

TIM15 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDF1BK0E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK0E

Bit 8: BRK dfsdm1_break[0] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

SEC_TIM16

0x50014400: General purpose timers

2/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDF1BK1E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK1E

Bit 8: BRK dfsdm1_break[1] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

SEC_TIM17

0x50014800: General purpose timers

2/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDF1BK2E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK2E

Bit 8: BRK dfsdm1_break[2] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

SEC_TIM2

0x50000000: General-purpose-timers

8/117 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_bit31
rw 		CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw 		ETR1_RMP
rw 		ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

ETR1_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input Capture 4 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

SEC_TIM3

0x50000400: General-purpose-timers

8/115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_bit31
rw 		CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

SEC_TIM4

0x50000800: General-purpose-timers

8/113 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_bit31
rw 		CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

SEC_TIM5

0x50000c00: General-purpose-timers

8/113 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_bit31
rw 		CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

SEC_TIM6

0x50001000: General-purpose-timers

0/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMA
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMA

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

UDE

Bit 8: Update DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_bit0
rw
Toggle fields

CNT_bit0

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY or Res.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_bit0
rw
Toggle fields

ARR_bit0

Bits 0-15: ARR_bit0.

SEC_TIM7

0x50001400: General-purpose-timers

0/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMA
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMA

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

UDE

Bit 8: Update DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_bit0
rw
Toggle fields

CNT_bit0

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY or Res.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_bit0
rw
Toggle fields

ARR_bit0

Bits 0-15: ARR_bit0.

SEC_TIM8

0x50013400: Advanced-timers

13/185 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS5
rw 		OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS5

Bit 15: Output Idle state 5 (OC5 output).

OIS6

Bit 16: Output Idle state 6.

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M_3
rw 		OC5M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_3

Bit 16: Output Compare 5 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC6M_3

Bit 24: Output Compare 6 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register 4

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 4

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: Capture/Compare value.

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDF1BK2E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK2E

Bit 8: BRK dfsdm1_break[2] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2DFBK3E
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK3E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

SEC_TSC

0x50024000: Touch sensing controller

16/170 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 IER
0x8 ICR
0xc ISR
0x10 IOHCR
0x18 IOASCR
0x20 IOSCR
0x28 IOCCR
0x30 IOGCSR
0x34 IOG1CR
0x38 IOG2CR
0x3c IOG3CR
0x40 IOG4CR
0x44 IOG5CR
0x48 IOG6CR
0x4c IOG7CR
0x50 IOG8CR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTPH
rw 		CTPL
rw 		SSD
rw 		SSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSPSC
rw 		PGPSC
rw 		MCV
rw 		IODEF
rw 		SYNCPOL
rw 		AM
rw 		START
rw 		TSCE
rw
Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIE
rw 		EOAIE
rw
Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIC
rw 		EOAIC
rw
Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEF
rw 		EOAF
rw
Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

8/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8S
r 		G7S
r 		G6S
r 		G5S
r 		G4S
r 		G3S
r 		G2S
r 		G1S
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G8E
rw 		G7E
rw 		G6E
rw 		G5E
rw 		G4E
rw 		G3E
rw 		G2E
rw 		G1E
rw
Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

G8S

Bit 23: Analog I/O group x status.

IOG1CR

I/O group x counter register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG2CR

I/O group x counter register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG3CR

I/O group x counter register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG4CR

I/O group x counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG5CR

I/O group x counter register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG6CR

I/O group x counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG7CR

I/O group x counter register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG8CR

I/O group x counter register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

SEC_UART4

0x50004c00: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

SEC_UART5

0x50005000: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

SEC_UCPD1

0x5000dc00: USB Power Delivery interface

23/88 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFG1
0x4 CFG2
0x8 CFG3
0xc CR
0x10 IMR
0x14 SR
0x18 ICR
0x1c TX_ORDSET
0x20 TX_PAYSZ
0x24 TXDR
0x28 RX_ORDSET
0x2c RX_PAYSZ
0x30 RXDR
0x34 RX_ORDEXT1
0x38 RX_ORDEXT2
Toggle registers

CFG1

UCPD configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPDEN
rw 		RXDMAEN
rw 		TXDMAEN
rw 		RXORDSETEN
rw 		PSC_USBPDCLK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRANSWIN
rw 		IFRGAP
rw 		HBITCLKDIV
rw
Toggle fields

HBITCLKDIV

Bits 0-5: HBITCLKDIV.

IFRGAP

Bits 6-10: IFRGAP.

TRANSWIN

Bits 11-15: TRANSWIN.

PSC_USBPDCLK

Bits 17-19: PSC_USBPDCLK.

RXORDSETEN

Bits 20-28: RXORDSETEN.

TXDMAEN

Bit 29: TXDMAEN.

RXDMAEN

Bit 30: RXDMAEN:.

UCPDEN

Bit 31: UCPDEN.

CFG2

UCPD configuration register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUPEN
rw 		FORCECLK
rw 		RXFILT2N3
rw 		RXFILTDIS
rw
Toggle fields

RXFILTDIS

Bit 0: RXFILTDIS.

RXFILT2N3

Bit 1: RXFILT2N3.

FORCECLK

Bit 2: FORCECLK.

WUPEN

Bit 3: WUPEN.

CFG3

UCPD configuration register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRIM2_NG_CC3A0
rw 		TRIM2_NG_CC1A5
rw 		TRIM2_NG_CCRPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM1_NG_CC3A0
rw 		TRIM1_NG_CC1A5
rw 		TRIM1_NG_CCRPD
rw
Toggle fields

TRIM1_NG_CCRPD

Bits 0-3: TRIM1_NG_CCRPD.

TRIM1_NG_CC1A5

Bits 4-8: TRIM1_NG_CC1A5.

TRIM1_NG_CC3A0

Bits 9-12: TRIM1_NG_CC3A0.

TRIM2_NG_CCRPD

Bits 16-19: TRIM2_NG_CCRPD.

TRIM2_NG_CC1A5

Bits 20-24: TRIM2_NG_CC1A5.

TRIM2_NG_CC3A0

Bits 25-28: TRIM2_NG_CC3A0.

CR

UCPD control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC2TCDIS
rw 		CC1TCDIS
rw 		RDCH
rw 		FRSTX
rw 		FRSRXEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCENABLE
rw 		ANAMODE
rw 		ANASUBMODE
rw 		PHYCCSEL
rw 		PHYRXEN
rw 		RXMODE
rw 		TXHRST
rw 		TXSEND
rw 		TXMODE
rw
Toggle fields

TXMODE

Bits 0-1: TXMODE.

TXSEND

Bit 2: TXSEND.

TXHRST

Bit 3: TXHRST.

RXMODE

Bit 4: RXMODE.

PHYRXEN

Bit 5: PHYRXEN.

PHYCCSEL

Bit 6: PHYCCSEL.

ANASUBMODE

Bits 7-8: ANASUBMODE.

ANAMODE

Bit 9: ANAMODE.

CCENABLE

Bits 10-11: CCENABLE.

FRSRXEN

Bit 16: FRSRXEN.

FRSTX

Bit 17: FRSTX.

RDCH

Bit 18: RDCH.

CC1TCDIS

Bit 20: CC1TCDIS.

CC2TCDIS

Bit 21: CC2TCDIS.

IMR

UCPD Interrupt Mask Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVTIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2IE
rw 		TYPECEVT1IE
rw 		RXMSGENDIE
rw 		RXOVRIE
rw 		RXHRSTDETIE
rw 		RXORDDETIE
rw 		RXNEIE
rw 		TXUNDIE
rw 		HRSTSENTIE
rw 		HRSTDISCIE
rw 		TXMSGABTIE
rw 		TXMSGSENTIE
rw 		TXMSGDISCIE
rw 		TXISIE
rw
Toggle fields

TXISIE

Bit 0: TXISIE.

TXMSGDISCIE

Bit 1: TXMSGDISCIE.

TXMSGSENTIE

Bit 2: TXMSGSENTIE.

TXMSGABTIE

Bit 3: TXMSGABTIE.

HRSTDISCIE

Bit 4: HRSTDISCIE.

HRSTSENTIE

Bit 5: HRSTSENTIE.

TXUNDIE

Bit 6: TXUNDIE.

RXNEIE

Bit 8: RXNEIE.

RXORDDETIE

Bit 9: RXORDDETIE.

RXHRSTDETIE

Bit 10: RXHRSTDETIE.

RXOVRIE

Bit 11: RXOVRIE.

RXMSGENDIE

Bit 12: RXMSGENDIE.

TYPECEVT1IE

Bit 14: TYPECEVT1IE.

TYPECEVT2IE

Bit 15: TYPECEVT2IE.

FRSEVTIE

Bit 20: FRSEVTIE.

SR

UCPD Status Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVT
r 		TYPEC_VSTATE_CC2
r 		TYPEC_VSTATE_CC1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2
r 		TYPECEVT1
r 		RXERR
r 		RXMSGEND
r 		RXOVR
r 		RXHRSTDET
r 		RXORDDET
r 		RXNE
r 		TXUND
r 		HRSTSENT
r 		HRSTDISC
r 		TXMSGABT
r 		TXMSGSENT
r 		TXMSGDISC
r 		TXIS
r
Toggle fields

TXIS

Bit 0: TXIS.

TXMSGDISC

Bit 1: TXMSGDISC.

TXMSGSENT

Bit 2: TXMSGSENT.

TXMSGABT

Bit 3: TXMSGABT.

HRSTDISC

Bit 4: HRSTDISC.

HRSTSENT

Bit 5: HRSTSENT.

TXUND

Bit 6: TXUND.

RXNE

Bit 8: RXNE.

RXORDDET

Bit 9: RXORDDET.

RXHRSTDET

Bit 10: RXHRSTDET.

RXOVR

Bit 11: RXOVR.

RXMSGEND

Bit 12: RXMSGEND.

RXERR

Bit 13: RXERR.

TYPECEVT1

Bit 14: TYPECEVT1.

TYPECEVT2

Bit 15: TYPECEVT2.

TYPEC_VSTATE_CC1

Bits 16-17: TYPEC_VSTATE_CC1.

TYPEC_VSTATE_CC2

Bits 18-19: TYPEC_VSTATE_CC2.

FRSEVT

Bit 20: FRSEVT.

ICR

UCPD Interrupt Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVTCF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2CF
rw 		TYPECEVT1CF
rw 		RXMSGENDCF
rw 		RXOVRCF
rw 		RXHRSTDETCF
rw 		RXORDDETCF
rw 		TXUNDCF
rw 		HRSTSENTCF
rw 		HRSTDISCCF
rw 		TXMSGABTCF
rw 		TXMSGSENTCF
rw 		TXMSGDISCCF
rw
Toggle fields

TXMSGDISCCF

Bit 1: TXMSGDISCCF.

TXMSGSENTCF

Bit 2: TXMSGSENTCF.

TXMSGABTCF

Bit 3: TXMSGABTCF.

HRSTDISCCF

Bit 4: HRSTDISCCF.

HRSTSENTCF

Bit 5: HRSTSENTCF.

TXUNDCF

Bit 6: TXUNDCF.

RXORDDETCF

Bit 9: RXORDDETCF.

RXHRSTDETCF

Bit 10: RXHRSTDETCF.

RXOVRCF

Bit 11: RXOVRCF.

RXMSGENDCF

Bit 12: RXMSGENDCF.

TYPECEVT1CF

Bit 14: TYPECEVT1CF.

TYPECEVT2CF

Bit 15: TYPECEVT2CF.

FRSEVTCF

Bit 20: FRSEVTCF.

TX_ORDSET

UCPD Tx Ordered Set Type Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXORDSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXORDSET
rw
Toggle fields

TXORDSET

Bits 0-19: TXORDSET.

TX_PAYSZ

UCPD Tx Paysize Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPAYSZ
rw
Toggle fields

TXPAYSZ

Bits 0-9: TXPAYSZ.

TXDR

UCPD Tx Data Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

RX_ORDSET

UCPD Rx Ordered Set Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPKINVALID
r 		RXSOP3OF4
r 		RXORDSET
r
Toggle fields

RXORDSET

Bits 0-2: RXORDSET.

RXSOP3OF4

Bit 3: RXSOP3OF4.

RXSOPKINVALID

Bits 4-6: RXSOPKINVALID.

RX_PAYSZ

UCPD Rx Paysize Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPAYSZ
r
Toggle fields

RXPAYSZ

Bits 0-9: RXPAYSZ.

RXDR

UCPD Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

RX_ORDEXT1

UCPD Rx Ordered Set Extension Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSOPX1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPX1
rw
Toggle fields

RXSOPX1

Bits 0-19: RXSOPX1.

RX_ORDEXT2

UCPD Rx Ordered Set Extension Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSOPX2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPX2
rw
Toggle fields

RXSOPX2

Bits 0-19: RXSOPX2.

SEC_USART1

0x50013800: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

SEC_USART2

0x50004400: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

SEC_USART3

0x50004800: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

SEC_USB

0x5000d400: Universal serial bus full-speed device interface

8/127 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) EP0R
0x4 (16-bit) EP1R
0x8 (16-bit) EP2R
0xc (16-bit) EP3R
0x10 (16-bit) EP4R
0x14 (16-bit) EP5R
0x18 (16-bit) EP6R
0x1c (16-bit) EP7R
0x40 (16-bit) CNTR
0x44 (16-bit) ISTR
0x48 (16-bit) FNR
0x4c (16-bit) DADDR
0x50 (16-bit) BTABLE
0x54 (16-bit) LPMCSR
0x58 (16-bit) BCDR
Toggle registers

EP0R

endpoint 0 register

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP1R

endpoint 1 register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP2R

endpoint 2 register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP3R

endpoint 3 register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP4R

endpoint 4 register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP5R

endpoint 5 register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP6R

endpoint 6 register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP7R

endpoint 7 register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, size: 16, reset: 0x00000003, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRM
rw 		PMAOVRM
rw 		ERRM
rw 		WKUPM
rw 		SUSPM
rw 		RESETM
rw 		SOFM
rw 		ESOFM
rw 		L1REQM
rw 		L1RESUME
rw 		RESUME
rw 		FSUSP
rw 		LPMODE
rw 		PDWN
rw 		FRES
rw
Toggle fields

FRES

Bit 0: Force USB Reset.

PDWN

Bit 1: Power down.

LPMODE

Bit 2: Low-power mode.

FSUSP

Bit 3: Force suspend.

RESUME

Bit 4: Resume request.

L1RESUME

Bit 5: LPM L1 Resume request.

L1REQM

Bit 7: LPM L1 state request interrupt mask.

ESOFM

Bit 8: Expected start of frame interrupt mask.

SOFM

Bit 9: Start of frame interrupt mask.

RESETM

Bit 10: USB reset interrupt mask.

SUSPM

Bit 11: Suspend mode interrupt mask.

WKUPM

Bit 12: Wakeup interrupt mask.

ERRM

Bit 13: Error interrupt mask.

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

CTRM

Bit 15: Correct transfer interrupt mask.

ISTR

interrupt status register

Offset: 0x44, size: 16, reset: 0x00000000, access: Unspecified

3/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR
r 		PMAOVR
rw 		ERR
rw 		WKUP
rw 		SUSP
rw 		RESET
rw 		SOF
rw 		ESOF
rw 		L1REQ
rw 		DIR
r 		EP_ID
r
Toggle fields

EP_ID

Bits 0-3: Endpoint Identifier.

DIR

Bit 4: Direction of transaction.

L1REQ

Bit 7: LPM L1 state request.

ESOF

Bit 8: Expected start frame.

SOF

Bit 9: start of frame.

RESET

Bit 10: reset request.

SUSP

Bit 11: Suspend mode request.

WKUP

Bit 12: Wakeup.

ERR

Bit 13: Error.

PMAOVR

Bit 14: Packet memory area over / underrun.

CTR

Bit 15: Correct transfer.

FNR

frame number register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP
r 		RXDM
r 		LCK
r 		LSOF
r 		FN
r
Toggle fields

FN

Bits 0-10: Frame number.

LSOF

Bits 11-12: Lost SOF.

LCK

Bit 13: Locked.

RXDM

Bit 14: Receive data - line status.

RXDP

Bit 15: Receive data + line status.

DADDR

device address

Offset: 0x4c, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
rw 		ADD
rw
Toggle fields

ADD

Bits 0-6: Device address.

EF

Bit 7: Enable function.

BTABLE

Buffer table address

Offset: 0x50, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTABLE
rw
Toggle fields

BTABLE

Bits 3-15: Buffer table.

LPMCSR

LPM control and status register

Offset: 0x54, size: 16, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BESL
rw 		REMWAKE
rw 		LPMACK
rw 		LPMEN
rw
Toggle fields

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM Token acknowledge enable.

REMWAKE

Bit 3: RemoteWake value.

BESL

Bits 4-7: BESL value.

BCDR

Battery charging detector

Offset: 0x58, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPPU
rw 		PS2DET
rw 		SDET
rw 		PDET
rw 		DCDET
rw 		SDEN
rw 		PDEN
rw 		DCDEN
rw 		BCDEN
rw
Toggle fields

BCDEN

Bit 0: Battery charging detector (BCD) enable.

DCDEN

Bit 1: Data contact detection (DCD) mode enable.

PDEN

Bit 2: Primary detection (PD) mode enable.

SDEN

Bit 3: Secondary detection (SD) mode enable.

DCDET

Bit 4: Data contact detection (DCD) status.

PDET

Bit 5: Primary detection (PD) status.

SDET

Bit 6: Secondary detection (SD) status.

PS2DET

Bit 7: DM pull-up detection status.

DPPU

Bit 15: DP pull-up control.

SEC_VREFBUF

0x50010030: Voltage reference buffer

1/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
Toggle registers

CSR

VREF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r 		VRS
rw 		HIZ
rw 		ENVR
rw
Toggle fields

ENVR

Bit 0: Voltage reference buffer enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle fields

TRIM

Bits 0-5: Trimming code.

SEC_WWDG

0x50002c00: System window watchdog

0/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFR
0x8 SR
Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw 		WDGTB
rw 		W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

WDGTB

Bits 7-8: Timer base.

EWI

Bit 9: Early wakeup interrupt.

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.

SPI1

0x40013000: Serial peripheral interface

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SPI2

0x40003800: Serial peripheral interface

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SPI3

0x40003c00: Serial peripheral interface

10/39 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SR
0xc DR
0x10 CRCPR
0x14 RXCRCR
0x18 TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw 		BIDIOE
rw 		CRCEN
rw 		CRCNEXT
rw 		CRCL
rw 		RXONLY
rw 		SSM
rw 		SSI
rw 		LSBFIRST
rw 		SPE
rw 		BR
rw 		MSTR
rw 		CPOL
rw 		CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw 		LDMA_RX
rw 		FRXTH
rw 		DS
rw 		TXEIE
rw 		RXNEIE
rw 		ERRIE
rw 		FRF
rw 		NSSP
rw 		SSOE
rw 		TXDMAEN
rw 		RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 32, reset: 0x00000002, access: Unspecified

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r 		FRLVL
r 		TIFRFE
r 		BSY
r 		OVR
r 		MODF
r 		CRCERR
rw 		TXE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

SYSCFG

0x40010000: System configuration controller

1/93 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SECCFGR
0x4 CFGR1
0x8 FPUIMR
0xc CNSLCKR
0x10 CSLOCKR
0x14 CFGR2
0x18 SCSR
0x1c SKR
0x20 SWPR
0x24 SWPR2
0x2c RSSCMDR
Toggle registers

SECCFGR

SYSCFG secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPUSEC
rw 		SRAM2SEC
rw 		CLASSBSEC
rw 		SYSCFGSEC
rw
Toggle fields

SYSCFGSEC

Bit 0: SYSCFG clock control security.

CLASSBSEC

Bit 1: ClassB security.

SRAM2SEC

Bit 2: SRAM2 security.

FPUSEC

Bit 3: FPUSEC.

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C4_FMP
rw 		I2C3_FMP
rw 		I2C2_FMP
rw 		I2C1_FMP
rw 		I2C_PB9_FMP
rw 		I2C_PB8_FMP
rw 		I2C_PB7_FMP
rw 		I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANASWVDD
rw 		BOOSTEN
rw
Toggle fields

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

ANASWVDD

Bit 9: GPIO analog switch control voltage selection.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C2_FMP

Bit 21: I2C2 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

I2C4_FMP

Bit 23: I2C4_FMP.

FPUIMR

FPU interrupt mask register

Offset: 0x8, size: 32, reset: 0x0000001F, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPU_IE
rw
Toggle fields

FPU_IE

Bits 0-5: Floating point unit interrupts enable bits.

CNSLCKR

SYSCFG CPU non-secure lock register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKNSMPU
rw 		LOCKNSVTOR
rw
Toggle fields

LOCKNSVTOR

Bit 0: VTOR_NS register lock.

LOCKNSMPU

Bit 1: Non-secure MPU registers lock.

CSLOCKR

SYSCFG CPU secure lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKSAU
rw 		LOCKSMPU
rw 		LOCKSVTAIRCR
rw
Toggle fields

LOCKSVTAIRCR

Bit 0: LOCKSVTAIRCR.

LOCKSMPU

Bit 1: LOCKSMPU.

LOCKSAU

Bit 2: LOCKSAU.

CFGR2

CFGR2

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPF
rw 		ECCL
w 		PVDL
w 		SPL
w 		CLL
w
Toggle fields

CLL

Bit 0: LOCKUP (hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SCSR

SCSR

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2BSY
r 		SRAM2ER
rw
Toggle fields

SRAM2ER

Bit 0: SRAM2 Erase.

SRAM2BSY

Bit 1: SRAM2 busy by erase operation.

SKR

SKR

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: SRAM2 write protection key for software erase.

SWPR

SWPR

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31WP
w 		P30WP
w 		P29WP
w 		P28WP
w 		P27WP
w 		P26WP
w 		P25WP
w 		P24WP
w 		P23WP
w 		P22WP
w 		P21WP
w 		P20WP
w 		P19WP
w 		P18WP
w 		P17WP
w 		P16WP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15WP
w 		P14WP
w 		P13WP
w 		P12WP
w 		P11WP
w 		P10WP
w 		P9WP
w 		P8WP
w 		P7WP
w 		P6WP
w 		P5WP
w 		P4WP
w 		P3WP
w 		P2WP
w 		P1WP
w 		P0WP
w
Toggle fields

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: SRAM2 page 31 write protection.

SWPR2

SWPR2

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P63WP
w 		P62WP
w 		P61WP
w 		P60WP
w 		P59WP
w 		P58WP
w 		P57WP
w 		P56WP
w 		P55WP
w 		P54WP
w 		P53WP
w 		P52WP
w 		P51WP
w 		P50WP
w 		P49WP
w 		P48WP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P47WP
w 		P46WP
w 		P45WP
w 		P44WP
w 		P43WP
w 		P42WP
w 		P41WP
w 		P40WP
w 		P39WP
w 		P38WP
w 		P37WP
w 		P36WP
w 		P35WP
w 		P34WP
w 		P33WP
w 		P32WP
w
Toggle fields

P32WP

Bit 0: P32WP.

P33WP

Bit 1: P33WP.

P34WP

Bit 2: P34WP.

P35WP

Bit 3: P35WP.

P36WP

Bit 4: P36WP.

P37WP

Bit 5: P37WP.

P38WP

Bit 6: P38WP.

P39WP

Bit 7: P39WP.

P40WP

Bit 8: P40WP.

P41WP

Bit 9: P41WP.

P42WP

Bit 10: P42WP.

P43WP

Bit 11: P43WP.

P44WP

Bit 12: P44WP.

P45WP

Bit 13: P45WP.

P46WP

Bit 14: P46WP.

P47WP

Bit 15: P47WP.

P48WP

Bit 16: P48WP.

P49WP

Bit 17: P49WP.

P50WP

Bit 18: P50WP.

P51WP

Bit 19: P51WP.

P52WP

Bit 20: P52WP.

P53WP

Bit 21: P53WP.

P54WP

Bit 22: P54WP.

P55WP

Bit 23: P55WP.

P56WP

Bit 24: P56WP.

P57WP

Bit 25: P57WP.

P58WP

Bit 26: P58WP.

P59WP

Bit 27: P59WP.

P60WP

Bit 28: P60WP.

P61WP

Bit 29: P61WP.

P62WP

Bit 30: P62WP.

P63WP

Bit 31: P63WP.

RSSCMDR

RSSCMDR

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSSCMD
rw
Toggle fields

RSSCMD

Bits 0-7: RSS commands.

TAMP

0x40003400: Tamper and backup registers

43/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc FLTCR
0x10 ATCR1
0x14 ATSEEDR
0x18 ATOR
0x1c ATCR2
0x20 SMCR
0x24 PRIVCR
0x2c IER
0x30 SR
0x34 MISR
0x38 SMISR
0x3c SCR
0x40 COUNTR
0x50 CFGR
0x100 BKP[0]R
0x104 BKP[1]R
0x108 BKP[2]R
0x10c BKP[3]R
0x110 BKP[4]R
0x114 BKP[5]R
0x118 BKP[6]R
0x11c BKP[7]R
0x120 BKP[8]R
0x124 BKP[9]R
0x128 BKP[10]R
0x12c BKP[11]R
0x130 BKP[12]R
0x134 BKP[13]R
0x138 BKP[14]R
0x13c BKP[15]R
0x140 BKP[16]R
0x144 BKP[17]R
0x148 BKP[18]R
0x14c BKP[19]R
0x150 BKP[20]R
0x154 BKP[21]R
0x158 BKP[22]R
0x15c BKP[23]R
0x160 BKP[24]R
0x164 BKP[25]R
0x168 BKP[26]R
0x16c BKP[27]R
0x170 BKP[28]R
0x174 BKP[29]R
0x178 BKP[30]R
0x17c BKP[31]R
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0xFFFF0000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8E
rw 		ITAMP5E
rw 		ITAMP3E
rw 		ITAMP2E
rw 		ITAMP1E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8E
rw 		TAMP7E
rw 		TAMP6E
rw 		TAMP5E
rw 		TAMP4E
rw 		TAMP3E
rw 		TAMP2E
rw 		TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

TAMP3E

Bit 2: TAMP3E.

TAMP4E

Bit 3: TAMP4E.

TAMP5E

Bit 4: TAMP5E.

TAMP6E

Bit 5: TAMP6E.

TAMP7E

Bit 6: TAMP7E.

TAMP8E

Bit 7: TAMP8E.

ITAMP1E

Bit 16: ITAMP1E.

ITAMP2E

Bit 17: ITAMP2E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP8E

Bit 23: ITAMP5E.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP8TRG
rw 		TAMP7TRG
rw 		TAMP6TRG
rw 		TAMP5TRG
rw 		TAMP4TRG
rw 		TAMP3TRG
rw 		TAMP2TRG
rw 		TAMP1TRG
rw 		BKERASE
rw 		TAMP3MSK
rw 		TAMP2MSK
rw 		TAMP1MSK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8NOER
rw 		TAMP7NOER
rw 		TAMP6NOER
rw 		TAMP5NOER
rw 		TAMP4NOER
rw 		TAMP3NOER
rw 		TAMP2NOER
rw 		TAMP1NOER
rw
Toggle fields

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP3NOER

Bit 2: TAMP3NOER.

TAMP4NOER

Bit 3: TAMP4NOER.

TAMP5NOER

Bit 4: TAMP5NOER.

TAMP6NOER

Bit 5: TAMP6NOER.

TAMP7NOER

Bit 6: TAMP7NOER.

TAMP8NOER

Bit 7: TAMP8NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP3MSK

Bit 18: TAMP3MSK.

BKERASE

Bit 23: BKERASE.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

TAMP3TRG

Bit 26: TAMP3TRG.

TAMP4TRG

Bit 27: TAMP4TRG.

TAMP5TRG

Bit 28: TAMP5TRG.

TAMP6TRG

Bit 29: TAMP6TRG.

TAMP7TRG

Bit 30: TAMP7TRG.

TAMP8TRG

Bit 31: TAMP8TRG.

CR3

control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITAMP8NOER
rw 		ITAMP5NOER
rw 		ITAMP3NOER
rw 		ITAMP2NOER
rw 		ITAMP1NOER
rw
Toggle fields

ITAMP1NOER

Bit 0: ITAMP1NOER.

ITAMP2NOER

Bit 1: ITAMP2NOER.

ITAMP3NOER

Bit 2: ITAMP3NOER.

ITAMP5NOER

Bit 4: ITAMP5NOER.

ITAMP8NOER

Bit 7: ITAMP8NOER.

FLTCR

TAMP filter control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw
Toggle fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

ATCR1

TAMP active tamper control register 1

Offset: 0x10, size: 32, reset: 0x00070000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTEN
rw 		ATOSHARE
rw 		ATPER
rw 		ATCKSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL4
rw 		ATOSEL3
rw 		ATOSEL2
rw 		ATOSEL1
rw 		TAMP8AM
rw 		TAMP7AM
rw 		TAMP6AM
rw 		TAMP5AM
rw 		TAMP4AM
rw 		TAMP3AM
rw 		TAMP2AM
rw 		TAMP1AM
rw
Toggle fields

TAMP1AM

Bit 0: TAMP1AM.

TAMP2AM

Bit 1: TAMP2AM.

TAMP3AM

Bit 2: TAMP3AM.

TAMP4AM

Bit 3: TAMP4AM.

TAMP5AM

Bit 4: TAMP5AM.

TAMP6AM

Bit 5: TAMP6AM.

TAMP7AM

Bit 6: TAMP7AM.

TAMP8AM

Bit 7: TAMP8AM.

ATOSEL1

Bits 8-9: ATOSEL1.

ATOSEL2

Bits 10-11: ATOSEL2.

ATOSEL3

Bits 12-13: ATOSEL3.

ATOSEL4

Bits 14-15: ATOSEL4.

ATCKSEL

Bits 16-17: ATCKSEL.

ATPER

Bits 24-25: ATPER.

ATOSHARE

Bit 30: ATOSHARE.

FLTEN

Bit 31: FLTEN.

ATSEEDR

TAMP active tamper seed register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
w
Toggle fields

SEED

Bits 0-31: Pseudo-random generator seed value.

ATOR

TAMP active tamper output register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INITS
r 		SEEDF
r 		PRNG
r
Toggle fields

PRNG

Bits 0-7: Pseudo-random generator value.

SEEDF

Bit 14: Seed running flag.

INITS

Bit 15: Active tamper initialization status.

ATCR2

TAMP active tamper control register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATOSEL8
rw 		ATOSEL7
rw 		ATOSEL6
rw 		ATOSEL5
rw 		ATOSEL4
rw 		ATOSEL3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL3
rw 		ATOSEL2
rw 		ATOSEL1
rw
Toggle fields

ATOSEL1

Bits 8-10: ATOSEL1.

ATOSEL2

Bits 11-13: ATOSEL2.

ATOSEL3

Bits 14-16: ATOSEL3.

ATOSEL4

Bits 17-19: ATOSEL4.

ATOSEL5

Bits 20-22: ATOSEL5.

ATOSEL6

Bits 23-25: ATOSEL6.

ATOSEL7

Bits 26-28: ATOSEL7.

ATOSEL8

Bits 29-31: ATOSEL8.

SMCR

TAMP secure mode register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPDPROT
rw 		BKPWDPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPRWDPROT
rw
Toggle fields

BKPRWDPROT

Bits 0-7: Backup registers read/write protection offset.

BKPWDPROT

Bits 16-23: Backup registers write protection offset.

TAMPDPROT

Bit 31: Tamper protection.

PRIVCR

TAMP privilege mode control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPPRIV
rw 		BKPWPRIV
rw 		BKPRWPRIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

BKPRWPRIV

Bit 29: Backup registers zone 1 privilege protection.

BKPWPRIV

Bit 30: Backup registers zone 2 privilege protection.

TAMPPRIV

Bit 31: Tamper privilege protection.

IER

TAMP interrupt enable register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8IE
rw 		ITAMP5IE
rw 		ITAMP3IE
rw 		ITAMP2IE
rw 		ITAMP1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8IE
rw 		TAMP7IE
rw 		TAMP6IE
rw 		TAMP5IE
rw 		TAMP4IE
rw 		TAMP3IE
rw 		TAMP2IE
rw 		TAMP1IE
rw
Toggle fields

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

TAMP3IE

Bit 2: TAMP3IE.

TAMP4IE

Bit 3: TAMP4IE.

TAMP5IE

Bit 4: TAMP5IE.

TAMP6IE

Bit 5: TAMP6IE.

TAMP7IE

Bit 6: TAMP7IE.

TAMP8IE

Bit 7: TAMP8IE.

ITAMP1IE

Bit 16: ITAMP1IE.

ITAMP2IE

Bit 17: ITAMP2IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP8IE

Bit 23: ITAMP8IE.

SR

TAMP status register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8F
r 		ITAMP5F
r 		ITAMP3F
r 		ITAMP2F
r 		ITAMP1F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8F
r 		TAMP7F
r 		TAMP6F
r 		TAMP5F
r 		TAMP4F
r 		TAMP3F
r 		TAMP2F
r 		TAMP1F
r
Toggle fields

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

TAMP3F

Bit 2: TAMP3F.

TAMP4F

Bit 3: TAMP4F.

TAMP5F

Bit 4: TAMP5F.

TAMP6F

Bit 5: TAMP6F.

TAMP7F

Bit 6: TAMP7F.

TAMP8F

Bit 7: TAMP8F.

ITAMP1F

Bit 16: ITAMP1F.

ITAMP2F

Bit 17: ITAMP2F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP8F

Bit 23: ITAMP8F.

MISR

TAMP masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r 		ITAMP5MF
r 		ITAMP3MF
r 		ITAMP2MF
r 		ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8MF
r 		TAMP7MF
r 		TAMP6MF
r 		TAMP5MF
r 		TAMP4MF
r 		TAMP3MF
r 		TAMP2MF
r 		TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF:.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SMISR

TAMP secure masked interrupt status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r 		ITAMP5MF
r 		ITAMP3MF
r 		ITAMP2MF
r 		ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8MF
r 		TAMP7MF
r 		TAMP6MF
r 		TAMP5MF
r 		TAMP4MF
r 		TAMP3MF
r 		TAMP2MF
r 		TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF:.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CITAMP8F
w 		CITAMP5F
w 		CITAMP3F
w 		CITAMP2F
w 		CITAMP1F
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP8F
w 		CTAMP7F
w 		CTAMP6F
w 		CTAMP5F
w 		CTAMP4F
w 		CTAMP3F
w 		CTAMP2F
w 		CTAMP1F
w
Toggle fields

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CTAMP3F

Bit 2: CTAMP3F.

CTAMP4F

Bit 3: CTAMP4F.

CTAMP5F

Bit 4: CTAMP5F.

CTAMP6F

Bit 5: CTAMP6F.

CTAMP7F

Bit 6: CTAMP7F.

CTAMP8F

Bit 7: CTAMP8F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP8F

Bit 23: CITAMP8F.

COUNTR

TAMP monotonic counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle fields

COUNT

Bits 0-31: COUNT.

CFGR

TAMP configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUTMONEN
rw 		VMONEN
rw 		TMONEN
rw
Toggle fields

TMONEN

Bit 1: TMONEN.

VMONEN

Bit 2: VMONEN.

WUTMONEN

Bit 3: WUTMONEN.

BKP[0]R

TAMP backup register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[1]R

TAMP backup register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[2]R

TAMP backup register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[3]R

TAMP backup register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[4]R

TAMP backup register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[5]R

TAMP backup register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[6]R

TAMP backup register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[7]R

TAMP backup register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[8]R

TAMP backup register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[9]R

TAMP backup register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[10]R

TAMP backup register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[11]R

TAMP backup register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[12]R

TAMP backup register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[13]R

TAMP backup register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[14]R

TAMP backup register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[15]R

TAMP backup register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[16]R

TAMP backup register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[17]R

TAMP backup register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[18]R

TAMP backup register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[19]R

TAMP backup register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[20]R

TAMP backup register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[21]R

TAMP backup register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[22]R

TAMP backup register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[23]R

TAMP backup register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[24]R

TAMP backup register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[25]R

TAMP backup register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[26]R

TAMP backup register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[27]R

TAMP backup register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[28]R

TAMP backup register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[29]R

TAMP backup register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[30]R

TAMP backup register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[31]R

TAMP backup register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

TIM1

0x40012c00: Advanced-timers

13/186 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS5
rw 		OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS5

Bit 15: Output Idle state 5 (OC5 output).

OIS6

Bit 16: Output Idle state 6.

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw 		ETR_ADC1_RMP
rw
Toggle fields

ETR_ADC1_RMP

Bits 0-1: External trigger remap on ADC1 analog watchdog.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M_3
rw 		OC5M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_3

Bit 16: Output Compare 5 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC6M_3

Bit 24: Output Compare 6 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register 4

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 4

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: Capture/Compare value.

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDFBK0E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK0E

Bit 8: BRK DFSDM_BREAK0 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2DFBK0E
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TIM15

0x40014000: General purpose timers

4/95 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 CCR2
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-5: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output idle state 2 (OC2 output).

SMCR

TIM15 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/slave mode.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/Compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/Compare 2 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_bit3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2M
rw 		OC2PE
rw 		CC2S
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC1M_3

Bit 16: Output Compare 1 mode.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_bit3

Bit 24: Output Compare 2 mode - bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output polarity.

CC2NP

Bit 7: Capture/Compare 2 complementary output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

CCR2

TIM15 capture/compare register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM15 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENCODER_MODE
rw 		TI1_RMP
rw
Toggle fields

TI1_RMP

Bit 0: Input capture 1 remap.

ENCODER_MODE

Bits 1-2: Encoder mode.

OR2

TIM15 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDF1BK0E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK0E

Bit 8: BRK dfsdm1_break[0] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

TIM16

0x40014400: General purpose timers

2/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDF1BK1E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK1E

Bit 8: BRK dfsdm1_break[1] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM17

0x40014800: General purpose timers

2/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		COMG
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M_2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC1M_2

Bit 16: Output Compare 1 mode.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDF1BK2E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK2E

Bit 8: BRK dfsdm1_break[2] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM2

0x40000000: General-purpose-timers

8/117 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_bit31
rw 		CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw 		ETR1_RMP
rw 		ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

ETR1_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input Capture 4 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

TIM3

0x40000400: General-purpose-timers

8/115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_bit31
rw 		CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

TIM4

0x40000800: General-purpose-timers

8/113 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_bit31
rw 		CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

TIM5

0x40000c00: General-purpose-timers

8/113 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x48 DCR
0x4c DMAR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw 		CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		TIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_bit31
rw 		CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_L
rw
Toggle fields

CNT_L

Bits 0-15: Least significant part of counter value.

CNT_H

Bits 16-30: Most significant part counter value (on TIM2 and TIM5).

CNT_bit31

Bit 31: Most significant bit of counter value (on TIM2 and TIM5).

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_L
rw
Toggle fields

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1_L
rw
Toggle fields

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR2_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2_L
rw
Toggle fields

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR3_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3_L
rw
Toggle fields

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR4_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4_L
rw
Toggle fields

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

TIM6

0x40001000: General-purpose-timers

0/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMA
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMA

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

UDE

Bit 8: Update DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_bit0
rw
Toggle fields

CNT_bit0

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY or Res.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_bit0
rw
Toggle fields

ARR_bit0

Bits 0-15: ARR_bit0.

TIM7

0x40001400: General-purpose-timers

0/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMA
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

UIFREMA

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

UDE

Bit 8: Update DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT_bit0
rw
Toggle fields

CNT_bit0

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY or Res.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR_bit0
rw
Toggle fields

ARR_bit0

Bits 0-15: ARR_bit0.

TIM8

0x40013400: Advanced-timers

13/185 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR1
0x38 CCR2
0x3c CCR3
0x40 CCR4
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS5
rw 		OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS5

Bit 15: Output Idle state 5 (OC5 output).

OIS6

Bit 16: Output Idle state 6.

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_bit3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC4M_3
rw 		OC3M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE
rw 		OC4M
rw 		OC4PE
rw 		OC4FE
rw 		CC4S
rw 		OC3CE
rw 		OC3M
rw 		OC3PE
rw 		OC3FE
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

OC3FE

Bit 2: Output compare 3 fast enable.

OC3PE

Bit 3: Output compare 3 preload enable.

OC3M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC3CE

Bit 7: Output compare 3 clear enable.

CC4S

Bits 8-9: Capture/Compare 4 selection.

OC4FE

Bit 10: Output compare 4 fast enable.

OC4PE

Bit 11: Output compare 4 preload enable.

OC4M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC4CE

Bit 15: Output compare 4 clear enable.

OC3M_3

Bit 16: Output Compare 3 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC4M_3

Bit 24: Output Compare 4 mode - bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M_3
rw 		OC5M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_3

Bit 16: Output Compare 5 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC6M_3

Bit 24: Output Compare 6 mode bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register 4

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 4

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: Capture/Compare value.

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKCMP2P
rw 		BKCMP1P
rw 		BKINP
rw 		BKDF1BK2E
rw 		BKCMP2E
rw 		BKCMP1E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK2E

Bit 8: BRK dfsdm1_break[2] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw 		BK2CMP1P
rw 		BK2INP
rw 		BK2DFBK3E
rw 		BK2CMP2E
rw 		BK2CMP1E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK3E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TSC

0x40024000: Touch sensing controller

16/170 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 IER
0x8 ICR
0xc ISR
0x10 IOHCR
0x18 IOASCR
0x20 IOSCR
0x28 IOCCR
0x30 IOGCSR
0x34 IOG1CR
0x38 IOG2CR
0x3c IOG3CR
0x40 IOG4CR
0x44 IOG5CR
0x48 IOG6CR
0x4c IOG7CR
0x50 IOG8CR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTPH
rw 		CTPL
rw 		SSD
rw 		SSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSPSC
rw 		PGPSC
rw 		MCV
rw 		IODEF
rw 		SYNCPOL
rw 		AM
rw 		START
rw 		TSCE
rw
Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIE
rw 		EOAIE
rw
Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIC
rw 		EOAIC
rw
Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEF
rw 		EOAF
rw
Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw 		G8_IO3
rw 		G8_IO2
rw 		G8_IO1
rw 		G7_IO4
rw 		G7_IO3
rw 		G7_IO2
rw 		G7_IO1
rw 		G6_IO4
rw 		G6_IO3
rw 		G6_IO2
rw 		G6_IO1
rw 		G5_IO4
rw 		G5_IO3
rw 		G5_IO2
rw 		G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw 		G4_IO3
rw 		G4_IO2
rw 		G4_IO1
rw 		G3_IO4
rw 		G3_IO3
rw 		G3_IO2
rw 		G3_IO1
rw 		G2_IO4
rw 		G2_IO3
rw 		G2_IO2
rw 		G2_IO1
rw 		G1_IO4
rw 		G1_IO3
rw 		G1_IO2
rw 		G1_IO1
rw
Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

8/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8S
r 		G7S
r 		G6S
r 		G5S
r 		G4S
r 		G3S
r 		G2S
r 		G1S
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G8E
rw 		G7E
rw 		G6E
rw 		G5E
rw 		G4E
rw 		G3E
rw 		G2E
rw 		G1E
rw
Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

G8S

Bit 23: Analog I/O group x status.

IOG1CR

I/O group x counter register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG2CR

I/O group x counter register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG3CR

I/O group x counter register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG4CR

I/O group x counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG5CR

I/O group x counter register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG6CR

I/O group x counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG7CR

I/O group x counter register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG8CR

I/O group x counter register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

UART4

0x40004c00: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

UART5

0x40005000: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

UCPD1

0x4000dc00: USB Power Delivery interface

23/88 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFG1
0x4 CFG2
0x8 CFG3
0xc CR
0x10 IMR
0x14 SR
0x18 ICR
0x1c TX_ORDSET
0x20 TX_PAYSZ
0x24 TXDR
0x28 RX_ORDSET
0x2c RX_PAYSZ
0x30 RXDR
0x34 RX_ORDEXT1
0x38 RX_ORDEXT2
Toggle registers

CFG1

UCPD configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPDEN
rw 		RXDMAEN
rw 		TXDMAEN
rw 		RXORDSETEN
rw 		PSC_USBPDCLK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRANSWIN
rw 		IFRGAP
rw 		HBITCLKDIV
rw
Toggle fields

HBITCLKDIV

Bits 0-5: HBITCLKDIV.

IFRGAP

Bits 6-10: IFRGAP.

TRANSWIN

Bits 11-15: TRANSWIN.

PSC_USBPDCLK

Bits 17-19: PSC_USBPDCLK.

RXORDSETEN

Bits 20-28: RXORDSETEN.

TXDMAEN

Bit 29: TXDMAEN.

RXDMAEN

Bit 30: RXDMAEN:.

UCPDEN

Bit 31: UCPDEN.

CFG2

UCPD configuration register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUPEN
rw 		FORCECLK
rw 		RXFILT2N3
rw 		RXFILTDIS
rw
Toggle fields

RXFILTDIS

Bit 0: RXFILTDIS.

RXFILT2N3

Bit 1: RXFILT2N3.

FORCECLK

Bit 2: FORCECLK.

WUPEN

Bit 3: WUPEN.

CFG3

UCPD configuration register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRIM2_NG_CC3A0
rw 		TRIM2_NG_CC1A5
rw 		TRIM2_NG_CCRPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM1_NG_CC3A0
rw 		TRIM1_NG_CC1A5
rw 		TRIM1_NG_CCRPD
rw
Toggle fields

TRIM1_NG_CCRPD

Bits 0-3: TRIM1_NG_CCRPD.

TRIM1_NG_CC1A5

Bits 4-8: TRIM1_NG_CC1A5.

TRIM1_NG_CC3A0

Bits 9-12: TRIM1_NG_CC3A0.

TRIM2_NG_CCRPD

Bits 16-19: TRIM2_NG_CCRPD.

TRIM2_NG_CC1A5

Bits 20-24: TRIM2_NG_CC1A5.

TRIM2_NG_CC3A0

Bits 25-28: TRIM2_NG_CC3A0.

CR

UCPD control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC2TCDIS
rw 		CC1TCDIS
rw 		RDCH
rw 		FRSTX
rw 		FRSRXEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCENABLE
rw 		ANAMODE
rw 		ANASUBMODE
rw 		PHYCCSEL
rw 		PHYRXEN
rw 		RXMODE
rw 		TXHRST
rw 		TXSEND
rw 		TXMODE
rw
Toggle fields

TXMODE

Bits 0-1: TXMODE.

TXSEND

Bit 2: TXSEND.

TXHRST

Bit 3: TXHRST.

RXMODE

Bit 4: RXMODE.

PHYRXEN

Bit 5: PHYRXEN.

PHYCCSEL

Bit 6: PHYCCSEL.

ANASUBMODE

Bits 7-8: ANASUBMODE.

ANAMODE

Bit 9: ANAMODE.

CCENABLE

Bits 10-11: CCENABLE.

FRSRXEN

Bit 16: FRSRXEN.

FRSTX

Bit 17: FRSTX.

RDCH

Bit 18: RDCH.

CC1TCDIS

Bit 20: CC1TCDIS.

CC2TCDIS

Bit 21: CC2TCDIS.

IMR

UCPD Interrupt Mask Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVTIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2IE
rw 		TYPECEVT1IE
rw 		RXMSGENDIE
rw 		RXOVRIE
rw 		RXHRSTDETIE
rw 		RXORDDETIE
rw 		RXNEIE
rw 		TXUNDIE
rw 		HRSTSENTIE
rw 		HRSTDISCIE
rw 		TXMSGABTIE
rw 		TXMSGSENTIE
rw 		TXMSGDISCIE
rw 		TXISIE
rw
Toggle fields

TXISIE

Bit 0: TXISIE.

TXMSGDISCIE

Bit 1: TXMSGDISCIE.

TXMSGSENTIE

Bit 2: TXMSGSENTIE.

TXMSGABTIE

Bit 3: TXMSGABTIE.

HRSTDISCIE

Bit 4: HRSTDISCIE.

HRSTSENTIE

Bit 5: HRSTSENTIE.

TXUNDIE

Bit 6: TXUNDIE.

RXNEIE

Bit 8: RXNEIE.

RXORDDETIE

Bit 9: RXORDDETIE.

RXHRSTDETIE

Bit 10: RXHRSTDETIE.

RXOVRIE

Bit 11: RXOVRIE.

RXMSGENDIE

Bit 12: RXMSGENDIE.

TYPECEVT1IE

Bit 14: TYPECEVT1IE.

TYPECEVT2IE

Bit 15: TYPECEVT2IE.

FRSEVTIE

Bit 20: FRSEVTIE.

SR

UCPD Status Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVT
r 		TYPEC_VSTATE_CC2
r 		TYPEC_VSTATE_CC1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2
r 		TYPECEVT1
r 		RXERR
r 		RXMSGEND
r 		RXOVR
r 		RXHRSTDET
r 		RXORDDET
r 		RXNE
r 		TXUND
r 		HRSTSENT
r 		HRSTDISC
r 		TXMSGABT
r 		TXMSGSENT
r 		TXMSGDISC
r 		TXIS
r
Toggle fields

TXIS

Bit 0: TXIS.

TXMSGDISC

Bit 1: TXMSGDISC.

TXMSGSENT

Bit 2: TXMSGSENT.

TXMSGABT

Bit 3: TXMSGABT.

HRSTDISC

Bit 4: HRSTDISC.

HRSTSENT

Bit 5: HRSTSENT.

TXUND

Bit 6: TXUND.

RXNE

Bit 8: RXNE.

RXORDDET

Bit 9: RXORDDET.

RXHRSTDET

Bit 10: RXHRSTDET.

RXOVR

Bit 11: RXOVR.

RXMSGEND

Bit 12: RXMSGEND.

RXERR

Bit 13: RXERR.

TYPECEVT1

Bit 14: TYPECEVT1.

TYPECEVT2

Bit 15: TYPECEVT2.

TYPEC_VSTATE_CC1

Bits 16-17: TYPEC_VSTATE_CC1.

TYPEC_VSTATE_CC2

Bits 18-19: TYPEC_VSTATE_CC2.

FRSEVT

Bit 20: FRSEVT.

ICR

UCPD Interrupt Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVTCF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2CF
rw 		TYPECEVT1CF
rw 		RXMSGENDCF
rw 		RXOVRCF
rw 		RXHRSTDETCF
rw 		RXORDDETCF
rw 		TXUNDCF
rw 		HRSTSENTCF
rw 		HRSTDISCCF
rw 		TXMSGABTCF
rw 		TXMSGSENTCF
rw 		TXMSGDISCCF
rw
Toggle fields

TXMSGDISCCF

Bit 1: TXMSGDISCCF.

TXMSGSENTCF

Bit 2: TXMSGSENTCF.

TXMSGABTCF

Bit 3: TXMSGABTCF.

HRSTDISCCF

Bit 4: HRSTDISCCF.

HRSTSENTCF

Bit 5: HRSTSENTCF.

TXUNDCF

Bit 6: TXUNDCF.

RXORDDETCF

Bit 9: RXORDDETCF.

RXHRSTDETCF

Bit 10: RXHRSTDETCF.

RXOVRCF

Bit 11: RXOVRCF.

RXMSGENDCF

Bit 12: RXMSGENDCF.

TYPECEVT1CF

Bit 14: TYPECEVT1CF.

TYPECEVT2CF

Bit 15: TYPECEVT2CF.

FRSEVTCF

Bit 20: FRSEVTCF.

TX_ORDSET

UCPD Tx Ordered Set Type Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXORDSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXORDSET
rw
Toggle fields

TXORDSET

Bits 0-19: TXORDSET.

TX_PAYSZ

UCPD Tx Paysize Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPAYSZ
rw
Toggle fields

TXPAYSZ

Bits 0-9: TXPAYSZ.

TXDR

UCPD Tx Data Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

RX_ORDSET

UCPD Rx Ordered Set Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPKINVALID
r 		RXSOP3OF4
r 		RXORDSET
r
Toggle fields

RXORDSET

Bits 0-2: RXORDSET.

RXSOP3OF4

Bit 3: RXSOP3OF4.

RXSOPKINVALID

Bits 4-6: RXSOPKINVALID.

RX_PAYSZ

UCPD Rx Paysize Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPAYSZ
r
Toggle fields

RXPAYSZ

Bits 0-9: RXPAYSZ.

RXDR

UCPD Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

RX_ORDEXT1

UCPD Rx Ordered Set Extension Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSOPX1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPX1
rw
Toggle fields

RXSOPX1

Bits 0-19: RXSOPX1.

RX_ORDEXT2

UCPD Rx Ordered Set Extension Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSOPX2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPX2
rw
Toggle fields

RXSOPX2

Bits 0-19: RXSOPX2.

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

28/133 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT4
rw 		DEAT3
rw 		DEAT2
rw 		DEAT1
rw 		DEAT0
rw 		DEDT4
rw 		DEDT3
rw 		DEDT2
rw 		DEDT1
rw 		DEDT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFOEN.

TXFEIE

Bit 30: TXFEIE.

RXFFIE

Bit 31: RXFFIE.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD1
rw 		ABRMOD0
rw 		ABREN
rw 		MSBFIRST
rw 		DATAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

DIS_NSS

Bit 3: DIS_NSS.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

DATAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: TXFTIE.

TCBGTIE

Bit 24: TCBGTIE.

RXFTCFG

Bits 25-27: RXFTCFG.

RXFTIE

Bit 28: RXFTIE.

TXFTCFG

Bits 29-31: TXFTCFG.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

27/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

RXFF

Bit 24: RXFF.

TCBGT

Bit 25: TCBGT.

RXFT

Bit 26: RXFT.

TXFT

Bit 27: TXFT.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFECF.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: TCBGTCF.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: UDRCF.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

USB

0x4000d400: Universal serial bus full-speed device interface

8/127 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) EP0R
0x4 (16-bit) EP1R
0x8 (16-bit) EP2R
0xc (16-bit) EP3R
0x10 (16-bit) EP4R
0x14 (16-bit) EP5R
0x18 (16-bit) EP6R
0x1c (16-bit) EP7R
0x40 (16-bit) CNTR
0x44 (16-bit) ISTR
0x48 (16-bit) FNR
0x4c (16-bit) DADDR
0x50 (16-bit) BTABLE
0x54 (16-bit) LPMCSR
0x58 (16-bit) BCDR
Toggle registers

EP0R

endpoint 0 register

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP1R

endpoint 1 register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP2R

endpoint 2 register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP3R

endpoint 3 register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP4R

endpoint 4 register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP5R

endpoint 5 register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP6R

endpoint 6 register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP7R

endpoint 7 register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw 		DTOG_RX
rw 		STAT_RX
rw 		SETUP
rw 		EP_TYPE
rw 		EP_KIND
rw 		CTR_TX
rw 		DTOG_TX
rw 		STAT_TX
rw 		EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, size: 16, reset: 0x00000003, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRM
rw 		PMAOVRM
rw 		ERRM
rw 		WKUPM
rw 		SUSPM
rw 		RESETM
rw 		SOFM
rw 		ESOFM
rw 		L1REQM
rw 		L1RESUME
rw 		RESUME
rw 		FSUSP
rw 		LPMODE
rw 		PDWN
rw 		FRES
rw
Toggle fields

FRES

Bit 0: Force USB Reset.

PDWN

Bit 1: Power down.

LPMODE

Bit 2: Low-power mode.

FSUSP

Bit 3: Force suspend.

RESUME

Bit 4: Resume request.

L1RESUME

Bit 5: LPM L1 Resume request.

L1REQM

Bit 7: LPM L1 state request interrupt mask.

ESOFM

Bit 8: Expected start of frame interrupt mask.

SOFM

Bit 9: Start of frame interrupt mask.

RESETM

Bit 10: USB reset interrupt mask.

SUSPM

Bit 11: Suspend mode interrupt mask.

WKUPM

Bit 12: Wakeup interrupt mask.

ERRM

Bit 13: Error interrupt mask.

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

CTRM

Bit 15: Correct transfer interrupt mask.

ISTR

interrupt status register

Offset: 0x44, size: 16, reset: 0x00000000, access: Unspecified

3/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR
r 		PMAOVR
rw 		ERR
rw 		WKUP
rw 		SUSP
rw 		RESET
rw 		SOF
rw 		ESOF
rw 		L1REQ
rw 		DIR
r 		EP_ID
r
Toggle fields

EP_ID

Bits 0-3: Endpoint Identifier.

DIR

Bit 4: Direction of transaction.

L1REQ

Bit 7: LPM L1 state request.

ESOF

Bit 8: Expected start frame.

SOF

Bit 9: start of frame.

RESET

Bit 10: reset request.

SUSP

Bit 11: Suspend mode request.

WKUP

Bit 12: Wakeup.

ERR

Bit 13: Error.

PMAOVR

Bit 14: Packet memory area over / underrun.

CTR

Bit 15: Correct transfer.

FNR

frame number register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP
r 		RXDM
r 		LCK
r 		LSOF
r 		FN
r
Toggle fields

FN

Bits 0-10: Frame number.

LSOF

Bits 11-12: Lost SOF.

LCK

Bit 13: Locked.

RXDM

Bit 14: Receive data - line status.

RXDP

Bit 15: Receive data + line status.

DADDR

device address

Offset: 0x4c, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
rw 		ADD
rw
Toggle fields

ADD

Bits 0-6: Device address.

EF

Bit 7: Enable function.

BTABLE

Buffer table address

Offset: 0x50, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTABLE
rw
Toggle fields

BTABLE

Bits 3-15: Buffer table.

LPMCSR

LPM control and status register

Offset: 0x54, size: 16, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BESL
rw 		REMWAKE
rw 		LPMACK
rw 		LPMEN
rw
Toggle fields

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM Token acknowledge enable.

REMWAKE

Bit 3: RemoteWake value.

BESL

Bits 4-7: BESL value.

BCDR

Battery charging detector

Offset: 0x58, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPPU
rw 		PS2DET
rw 		SDET
rw 		PDET
rw 		DCDET
rw 		SDEN
rw 		PDEN
rw 		DCDEN
rw 		BCDEN
rw
Toggle fields

BCDEN

Bit 0: Battery charging detector (BCD) enable.

DCDEN

Bit 1: Data contact detection (DCD) mode enable.

PDEN

Bit 2: Primary detection (PD) mode enable.

SDEN

Bit 3: Secondary detection (SD) mode enable.

DCDET

Bit 4: Data contact detection (DCD) status.

PDET

Bit 5: Primary detection (PD) status.

SDET

Bit 6: Secondary detection (SD) status.

PS2DET

Bit 7: DM pull-up detection status.

DPPU

Bit 15: DP pull-up control.

VREFBUF

0x40010030: Voltage reference buffer

1/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
Toggle registers

CSR

VREF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r 		VRS
rw 		HIZ
rw 		ENVR
rw
Toggle fields

ENVR

Bit 0: Voltage reference buffer enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle fields

TRIM

Bits 0-5: Trimming code.

WWDG

0x40002c00: System window watchdog

0/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFR
0x8 SR
Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x0000007F, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, size: 32, reset: 0x0000007F, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw 		WDGTB
rw 		W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

WDGTB

Bits 7-8: Timer base.

EWI

Bit 9: Early wakeup interrupt.

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.